Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 2 | /* |
ramneek mehresh | 3d33963 | 2012-04-18 19:39:53 +0000 | [diff] [blame] | 3 | * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | /* |
| 7 | * mpc8536ds board configuration file |
| 8 | * |
| 9 | */ |
| 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H |
| 12 | |
Kumar Gala | a1c0a46 | 2010-05-21 04:14:49 -0500 | [diff] [blame] | 13 | #include "../board/freescale/common/ics307_clk.h" |
| 14 | |
Wolfgang Denk | dc25d15 | 2010-10-04 19:58:00 +0200 | [diff] [blame] | 15 | #ifdef CONFIG_SDCARD |
Mingkai Hu | a74e395 | 2009-09-23 15:20:38 +0800 | [diff] [blame] | 16 | #define CONFIG_RAMBOOT_SDCARD 1 |
Kumar Gala | e727a36 | 2011-01-12 02:48:53 -0600 | [diff] [blame] | 17 | #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc |
Mingkai Hu | a74e395 | 2009-09-23 15:20:38 +0800 | [diff] [blame] | 18 | #endif |
| 19 | |
Wolfgang Denk | dc25d15 | 2010-10-04 19:58:00 +0200 | [diff] [blame] | 20 | #ifdef CONFIG_SPIFLASH |
Mingkai Hu | a74e395 | 2009-09-23 15:20:38 +0800 | [diff] [blame] | 21 | #define CONFIG_RAMBOOT_SPIFLASH 1 |
Kumar Gala | e727a36 | 2011-01-12 02:48:53 -0600 | [diff] [blame] | 22 | #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 23 | #endif |
| 24 | |
Kumar Gala | e727a36 | 2011-01-12 02:48:53 -0600 | [diff] [blame] | 25 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 26 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
| 27 | #endif |
| 28 | |
Haiying Wang | 31b9012 | 2010-11-10 15:37:13 -0500 | [diff] [blame] | 29 | #ifndef CONFIG_SYS_MONITOR_BASE |
| 30 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 31 | #endif |
| 32 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 33 | #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ |
Robert P. J. Day | a809981 | 2016-05-03 19:52:49 -0400 | [diff] [blame] | 34 | #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ |
| 35 | #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ |
| 36 | #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 37 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 38 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 39 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
Kumar Gala | 7738d5c | 2008-10-21 11:33:58 -0500 | [diff] [blame] | 40 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 41 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 42 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 43 | #define CONFIG_ENV_OVERWRITE |
| 44 | |
Kumar Gala | a1c0a46 | 2010-05-21 04:14:49 -0500 | [diff] [blame] | 45 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ |
| 46 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 47 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 48 | |
| 49 | /* |
| 50 | * These can be toggled for performance analysis, otherwise use default. |
| 51 | */ |
| 52 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 53 | #define CONFIG_BTB /* toggle branch predition */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 54 | |
| 55 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 56 | |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 57 | #ifdef CONFIG_PHYS_64BIT |
| 58 | #define CONFIG_ADDR_MAP 1 |
| 59 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ |
| 60 | #endif |
| 61 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 62 | #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ |
| 63 | #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 64 | |
| 65 | /* |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 66 | * Config the L2 Cache as L2 SRAM |
| 67 | */ |
| 68 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| 69 | #ifdef CONFIG_PHYS_64BIT |
| 70 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull |
| 71 | #else |
| 72 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| 73 | #endif |
| 74 | #define CONFIG_SYS_L2_SIZE (512 << 10) |
| 75 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
| 76 | |
Timur Tabi | d8f341c | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 77 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
| 78 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 79 | |
Kumar Gala | 842aa5b | 2011-11-09 09:10:49 -0600 | [diff] [blame] | 80 | #if defined(CONFIG_NAND_SPL) |
Timur Tabi | d8f341c | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 81 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 82 | #endif |
| 83 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 84 | /* DDR Setup */ |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 85 | #define CONFIG_VERY_BIG_RAM |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 86 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 87 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
| 88 | #define CONFIG_DDR_SPD |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 89 | |
Dave Liu | d3ca124 | 2008-10-28 17:53:38 +0800 | [diff] [blame] | 90 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 91 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 92 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 93 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 94 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 95 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 96 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 97 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 |
| 98 | |
| 99 | /* I2C addresses of SPD EEPROMs */ |
| 100 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 101 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 102 | |
| 103 | /* These are used when DDR doesn't use SPD. */ |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 104 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 105 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 106 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 107 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
| 108 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 |
| 109 | #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 |
| 110 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 |
| 111 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 |
| 112 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
| 113 | #define CONFIG_SYS_DDR_INTERVAL 0x06180100 |
| 114 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| 115 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 |
| 116 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 |
| 117 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 118 | #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 119 | #define CONFIG_SYS_DDR_CONTROL2 0x04400010 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 120 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 121 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d |
| 122 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 |
| 123 | #define CONFIG_SYS_DDR_SBE 0x00010000 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 124 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 125 | /* Make sure required options are set */ |
| 126 | #ifndef CONFIG_SPD_EEPROM |
| 127 | #error ("CONFIG_SPD_EEPROM is required") |
| 128 | #endif |
| 129 | |
| 130 | #undef CONFIG_CLOCKS_IN_MHZ |
| 131 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 132 | /* |
| 133 | * Memory map -- xxx -this is wrong, needs updating |
| 134 | * |
| 135 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable |
| 136 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable |
| 137 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable |
| 138 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable |
| 139 | * |
| 140 | * Localbus cacheable (TBD) |
| 141 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable |
| 142 | * |
| 143 | * Localbus non-cacheable |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 144 | * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 145 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 146 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 147 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
| 148 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 |
| 149 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable |
| 150 | */ |
| 151 | |
| 152 | /* |
| 153 | * Local Bus Definitions |
| 154 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 155 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 156 | #ifdef CONFIG_PHYS_64BIT |
| 157 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull |
| 158 | #else |
Kumar Gala | 4be8b57 | 2008-12-02 14:19:34 -0600 | [diff] [blame] | 159 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 160 | #endif |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 161 | |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 162 | #define CONFIG_FLASH_BR_PRELIM \ |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 163 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 164 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 165 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 166 | #define CONFIG_SYS_BR1_PRELIM \ |
| 167 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
| 168 | | BR_PS_16 | BR_V) |
Kumar Gala | 4be8b57 | 2008-12-02 14:19:34 -0600 | [diff] [blame] | 169 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 170 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 171 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ |
| 172 | CONFIG_SYS_FLASH_BASE_PHYS } |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 173 | #define CONFIG_SYS_FLASH_QUIET_TEST |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 174 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 175 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 176 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 177 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 178 | #undef CONFIG_SYS_FLASH_CHECKSUM |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 179 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 180 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 181 | |
Masahiro Yamada | 0c5b8eb | 2014-06-04 10:26:50 +0900 | [diff] [blame] | 182 | #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 183 | #define CONFIG_SYS_RAMBOOT |
Kumar Gala | b1dd51f | 2010-11-29 14:32:11 -0600 | [diff] [blame] | 184 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 185 | #else |
| 186 | #undef CONFIG_SYS_RAMBOOT |
| 187 | #endif |
| 188 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 189 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 190 | #define CONFIG_SYS_FLASH_CFI |
| 191 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 192 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 193 | |
Ramneek Mehresh | a0cce27 | 2011-06-07 10:10:43 +0000 | [diff] [blame] | 194 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 195 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
| 196 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 197 | #ifdef CONFIG_PHYS_64BIT |
| 198 | #define PIXIS_BASE_PHYS 0xfffdf0000ull |
| 199 | #else |
Kumar Gala | 0f492b4 | 2008-12-02 14:19:33 -0600 | [diff] [blame] | 200 | #define PIXIS_BASE_PHYS PIXIS_BASE |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 201 | #endif |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 202 | |
Kumar Gala | 0f492b4 | 2008-12-02 14:19:33 -0600 | [diff] [blame] | 203 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 204 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 205 | |
| 206 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
| 207 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ |
| 208 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ |
| 209 | #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ |
| 210 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ |
| 211 | #define PIXIS_PWR 0x5 /* PIXIS Power status register */ |
| 212 | #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ |
| 213 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ |
| 214 | #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ |
| 215 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ |
| 216 | #define PIXIS_VSTAT 0x11 /* VELA Status Register */ |
| 217 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ |
| 218 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ |
| 219 | #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ |
| 220 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ |
Kumar Gala | e21db03 | 2009-07-14 22:42:01 -0500 | [diff] [blame] | 221 | #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ |
| 222 | #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ |
| 223 | #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ |
| 224 | #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ |
| 225 | #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ |
| 226 | #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ |
| 227 | #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 228 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
| 229 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ |
| 230 | #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ |
| 231 | #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ |
| 232 | #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ |
| 233 | #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ |
| 234 | #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ |
| 235 | #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ |
| 236 | #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ |
| 237 | #define PIXIS_VWATCH 0x24 /* Watchdog Register */ |
| 238 | #define PIXIS_LED 0x25 /* LED Register */ |
| 239 | |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 240 | #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ |
| 241 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 242 | /* old pixis referenced names */ |
| 243 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ |
| 244 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ |
Matthew McClintock | 3cde72b | 2011-02-25 16:20:11 -0600 | [diff] [blame] | 245 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 246 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 247 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 248 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 249 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 250 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 251 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 252 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 253 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 254 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 255 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 256 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 257 | |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 258 | #ifndef CONFIG_NAND_SPL |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 259 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
| 260 | #ifdef CONFIG_PHYS_64BIT |
| 261 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull |
| 262 | #else |
| 263 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 264 | #endif |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 265 | #else |
| 266 | #define CONFIG_SYS_NAND_BASE 0xfff00000 |
| 267 | #ifdef CONFIG_PHYS_64BIT |
| 268 | #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull |
| 269 | #else |
| 270 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 271 | #endif |
| 272 | #endif |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 273 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ |
| 274 | CONFIG_SYS_NAND_BASE + 0x40000, \ |
| 275 | CONFIG_SYS_NAND_BASE + 0x80000, \ |
| 276 | CONFIG_SYS_NAND_BASE + 0xC0000} |
| 277 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 278 | #define CONFIG_NAND_FSL_ELBC 1 |
| 279 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| 280 | |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 281 | /* NAND boot: 4K NAND loader config */ |
| 282 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 |
Haijun.Zhang | afdc3f5 | 2014-02-13 09:03:02 +0800 | [diff] [blame] | 283 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 284 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) |
| 285 | #define CONFIG_SYS_NAND_U_BOOT_START \ |
| 286 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) |
| 287 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) |
| 288 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) |
| 289 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) |
| 290 | |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 291 | /* NAND flash config */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 292 | #define CONFIG_SYS_NAND_BR_PRELIM \ |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 293 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 294 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 295 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| 296 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 297 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 298 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 299 | | OR_FCM_PGS /* Large Page*/ \ |
| 300 | | OR_FCM_CSCT \ |
| 301 | | OR_FCM_CST \ |
| 302 | | OR_FCM_CHT \ |
| 303 | | OR_FCM_SCY_1 \ |
| 304 | | OR_FCM_TRLX \ |
| 305 | | OR_FCM_EHTR) |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 306 | |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 307 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 308 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 309 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| 310 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 311 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 312 | #define CONFIG_SYS_BR4_PRELIM \ |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 313 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 314 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 315 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| 316 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 317 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 318 | #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 319 | #define CONFIG_SYS_BR5_PRELIM \ |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 320 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 321 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 322 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| 323 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 324 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 325 | #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 326 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 327 | #define CONFIG_SYS_BR6_PRELIM \ |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 328 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 329 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 330 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| 331 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 332 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 333 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 334 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 335 | /* Serial Port - controlled on board with jumper J8 |
| 336 | * open - index 2 |
| 337 | * shorted - index 1 |
| 338 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 339 | #define CONFIG_SYS_NS16550_SERIAL |
| 340 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 341 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
Kumar Gala | f273623 | 2010-04-07 01:34:11 -0500 | [diff] [blame] | 342 | #ifdef CONFIG_NAND_SPL |
| 343 | #define CONFIG_NS16550_MIN_FUNCTIONS |
| 344 | #endif |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 345 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 346 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 347 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 348 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 349 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) |
| 350 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 351 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 352 | /* |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 353 | * I2C |
| 354 | */ |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 355 | #define CONFIG_SYS_I2C |
| 356 | #define CONFIG_SYS_I2C_FSL |
| 357 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 358 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 359 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| 360 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
| 361 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| 362 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 |
| 363 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 364 | |
| 365 | /* |
| 366 | * I2C2 EEPROM |
| 367 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 8349c72 | 2008-08-30 23:54:58 +0200 | [diff] [blame] | 368 | #define CONFIG_ID_EEPROM |
| 369 | #ifdef CONFIG_ID_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 370 | #define CONFIG_SYS_I2C_EEPROM_NXID |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 371 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 372 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 373 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 374 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 375 | |
| 376 | /* |
Xie Xiaobo | 8f3933e | 2011-10-03 12:18:39 -0700 | [diff] [blame] | 377 | * eSPI - Enhanced SPI |
| 378 | */ |
| 379 | #define CONFIG_HARD_SPI |
Xie Xiaobo | 8f3933e | 2011-10-03 12:18:39 -0700 | [diff] [blame] | 380 | |
| 381 | #if defined(CONFIG_SPI_FLASH) |
Xie Xiaobo | 8f3933e | 2011-10-03 12:18:39 -0700 | [diff] [blame] | 382 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
| 383 | #define CONFIG_SF_DEFAULT_MODE 0 |
| 384 | #endif |
| 385 | |
| 386 | /* |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 387 | * General PCI |
| 388 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 389 | */ |
| 390 | |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 391 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 392 | #ifdef CONFIG_PHYS_64BIT |
| 393 | #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 |
| 394 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull |
| 395 | #else |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 396 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
| 397 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 398 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 399 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 400 | #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 |
| 401 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
| 402 | #ifdef CONFIG_PHYS_64BIT |
| 403 | #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull |
| 404 | #else |
| 405 | #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 |
| 406 | #endif |
| 407 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 408 | |
| 409 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ |
Kumar Gala | 06bea37 | 2010-12-17 15:14:54 -0600 | [diff] [blame] | 410 | #define CONFIG_SYS_PCIE1_NAME "Slot 1" |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 411 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 412 | #ifdef CONFIG_PHYS_64BIT |
| 413 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 |
| 414 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull |
| 415 | #else |
Kumar Gala | 3fe8087 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 416 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 417 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 418 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 419 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 420 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 421 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 422 | #ifdef CONFIG_PHYS_64BIT |
| 423 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull |
| 424 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 425 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 426 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 427 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 428 | |
| 429 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ |
Kumar Gala | 06bea37 | 2010-12-17 15:14:54 -0600 | [diff] [blame] | 430 | #define CONFIG_SYS_PCIE2_NAME "Slot 2" |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 431 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 432 | #ifdef CONFIG_PHYS_64BIT |
| 433 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 |
| 434 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull |
| 435 | #else |
Kumar Gala | 3fe8087 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 436 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 437 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 438 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 439 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 440 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 441 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| 442 | #ifdef CONFIG_PHYS_64BIT |
| 443 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull |
| 444 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 445 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 446 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 447 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 448 | |
| 449 | /* controller 3, direct to uli, tgtid 3, Base address 8000 */ |
Kumar Gala | 06bea37 | 2010-12-17 15:14:54 -0600 | [diff] [blame] | 450 | #define CONFIG_SYS_PCIE3_NAME "Slot 3" |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 451 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 452 | #ifdef CONFIG_PHYS_64BIT |
| 453 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
| 454 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull |
| 455 | #else |
Kumar Gala | 3fe8087 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 456 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 457 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 458 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 459 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 460 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 461 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
| 462 | #ifdef CONFIG_PHYS_64BIT |
| 463 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull |
| 464 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 465 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 466 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 467 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 468 | |
| 469 | #if defined(CONFIG_PCI) |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 470 | /*PCIE video card used*/ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 471 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 472 | |
| 473 | /*PCI video card used*/ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 474 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 475 | |
| 476 | /* video */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 477 | |
| 478 | #if defined(CONFIG_VIDEO) |
| 479 | #define CONFIG_BIOSEMU |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 480 | #define CONFIG_ATI_RADEON_FB |
| 481 | #define CONFIG_VIDEO_LOGO |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 482 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 483 | #endif |
| 484 | |
| 485 | #undef CONFIG_EEPRO100 |
| 486 | #undef CONFIG_TULIP |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 487 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 488 | #ifndef CONFIG_PCI_PNP |
Kumar Gala | 64bb6d1 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 489 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS |
| 490 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 491 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
| 492 | #endif |
| 493 | |
| 494 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 495 | |
| 496 | #endif /* CONFIG_PCI */ |
| 497 | |
| 498 | /* SATA */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 499 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 500 | #define CONFIG_SATA1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 501 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
| 502 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 503 | #define CONFIG_SATA2 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 504 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR |
| 505 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 506 | |
| 507 | #ifdef CONFIG_FSL_SATA |
| 508 | #define CONFIG_LBA48 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 509 | #endif |
| 510 | |
| 511 | #if defined(CONFIG_TSEC_ENET) |
| 512 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 513 | #define CONFIG_MII 1 /* MII PHY management */ |
| 514 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
| 515 | #define CONFIG_TSEC1 1 |
| 516 | #define CONFIG_TSEC1_NAME "eTSEC1" |
| 517 | #define CONFIG_TSEC3 1 |
| 518 | #define CONFIG_TSEC3_NAME "eTSEC3" |
| 519 | |
Jason Jin | 21181fd | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 520 | #define CONFIG_FSL_SGMII_RISER 1 |
| 521 | #define SGMII_RISER_PHY_OFFSET 0x1c |
| 522 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 523 | #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ |
| 524 | #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ |
| 525 | |
| 526 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 527 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 528 | |
| 529 | #define TSEC1_PHYIDX 0 |
| 530 | #define TSEC3_PHYIDX 0 |
| 531 | |
| 532 | #define CONFIG_ETHPRIME "eTSEC1" |
| 533 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 534 | #endif /* CONFIG_TSEC_ENET */ |
| 535 | |
| 536 | /* |
| 537 | * Environment |
| 538 | */ |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 539 | |
| 540 | #if defined(CONFIG_SYS_RAMBOOT) |
Masahiro Yamada | 0c5b8eb | 2014-06-04 10:26:50 +0900 | [diff] [blame] | 541 | #if defined(CONFIG_RAMBOOT_SPIFLASH) |
Xie Xiaobo | 93c08de | 2011-10-03 12:54:21 -0700 | [diff] [blame] | 542 | #define CONFIG_ENV_SPI_BUS 0 |
| 543 | #define CONFIG_ENV_SPI_CS 0 |
| 544 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 |
| 545 | #define CONFIG_ENV_SPI_MODE 0 |
| 546 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
| 547 | #define CONFIG_ENV_OFFSET 0xF0000 |
| 548 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
| 549 | #elif defined(CONFIG_RAMBOOT_SDCARD) |
Fabio Estevam | ae8c45e | 2012-01-11 09:20:50 +0000 | [diff] [blame] | 550 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
Xie Xiaobo | 93c08de | 2011-10-03 12:54:21 -0700 | [diff] [blame] | 551 | #define CONFIG_ENV_SIZE 0x2000 |
| 552 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 553 | #else |
Mingkai Hu | a74e395 | 2009-09-23 15:20:38 +0800 | [diff] [blame] | 554 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| 555 | #define CONFIG_ENV_SIZE 0x2000 |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 556 | #endif |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 557 | #else |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 558 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 559 | #define CONFIG_ENV_SIZE 0x2000 |
| 560 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 561 | #endif |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 562 | |
| 563 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 564 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 565 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 566 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 567 | |
Andy Fleming | 6843a6e | 2008-10-30 16:51:33 -0500 | [diff] [blame] | 568 | #ifdef CONFIG_MMC |
Andy Fleming | 6843a6e | 2008-10-30 16:51:33 -0500 | [diff] [blame] | 569 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
Fanzc | 6f976fe | 2011-10-03 12:18:42 -0700 | [diff] [blame] | 570 | #endif |
| 571 | |
| 572 | /* |
| 573 | * USB |
| 574 | */ |
ramneek mehresh | 3d33963 | 2012-04-18 19:39:53 +0000 | [diff] [blame] | 575 | #define CONFIG_HAS_FSL_MPH_USB |
| 576 | #ifdef CONFIG_HAS_FSL_MPH_USB |
Tom Rini | ceed5d2 | 2017-05-12 22:33:27 -0400 | [diff] [blame] | 577 | #ifdef CONFIG_USB_EHCI_HCD |
Fanzc | 6f976fe | 2011-10-03 12:18:42 -0700 | [diff] [blame] | 578 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 579 | #define CONFIG_USB_EHCI_FSL |
Fanzc | 6f976fe | 2011-10-03 12:18:42 -0700 | [diff] [blame] | 580 | #endif |
ramneek mehresh | 3d33963 | 2012-04-18 19:39:53 +0000 | [diff] [blame] | 581 | #endif |
Fanzc | 6f976fe | 2011-10-03 12:18:42 -0700 | [diff] [blame] | 582 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 583 | /* |
| 584 | * Miscellaneous configurable options |
| 585 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 586 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 587 | |
| 588 | /* |
| 589 | * For booting Linux, the board info and command line data |
Kumar Gala | 39ffcc1 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 590 | * have to be in the first 64 MB of memory, since this is |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 591 | * the maximum mapped by the Linux kernel during initialization. |
| 592 | */ |
Kumar Gala | 39ffcc1 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 593 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ |
| 594 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 595 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 596 | #if defined(CONFIG_CMD_KGDB) |
| 597 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 598 | #endif |
| 599 | |
| 600 | /* |
| 601 | * Environment Configuration |
| 602 | */ |
| 603 | |
| 604 | /* The mac addresses for all ethernet interface */ |
| 605 | #if defined(CONFIG_TSEC_ENET) |
| 606 | #define CONFIG_HAS_ETH0 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 607 | #define CONFIG_HAS_ETH1 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 608 | #define CONFIG_HAS_ETH2 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 609 | #define CONFIG_HAS_ETH3 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 610 | #endif |
| 611 | |
| 612 | #define CONFIG_IPADDR 192.168.1.254 |
| 613 | |
Mario Six | 790d844 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 614 | #define CONFIG_HOSTNAME "unknown" |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 615 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 616 | #define CONFIG_BOOTFILE "uImage" |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 617 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 618 | |
| 619 | #define CONFIG_SERVERIP 192.168.1.1 |
| 620 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 621 | #define CONFIG_NETMASK 255.255.255.0 |
| 622 | |
| 623 | /* default location for tftp and bootm */ |
| 624 | #define CONFIG_LOADADDR 1000000 |
| 625 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 626 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 627 | "netdev=eth0\0" \ |
| 628 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 629 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| 630 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 631 | " +$filesize; " \ |
| 632 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 633 | " +$filesize; " \ |
| 634 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 635 | " $filesize; " \ |
| 636 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 637 | " +$filesize; " \ |
| 638 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 639 | " $filesize\0" \ |
| 640 | "consoledev=ttyS0\0" \ |
| 641 | "ramdiskaddr=2000000\0" \ |
| 642 | "ramdiskfile=8536ds/ramdisk.uboot\0" \ |
Scott Wood | b7f4b85 | 2016-07-19 17:52:06 -0500 | [diff] [blame] | 643 | "fdtaddr=1e00000\0" \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 644 | "fdtfile=8536ds/mpc8536ds.dtb\0" \ |
| 645 | "bdev=sda3\0" \ |
| 646 | "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 647 | |
| 648 | #define CONFIG_HDBOOT \ |
| 649 | "setenv bootargs root=/dev/$bdev rw " \ |
| 650 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 651 | "tftp $loadaddr $bootfile;" \ |
| 652 | "tftp $fdtaddr $fdtfile;" \ |
| 653 | "bootm $loadaddr - $fdtaddr" |
| 654 | |
| 655 | #define CONFIG_NFSBOOTCOMMAND \ |
| 656 | "setenv bootargs root=/dev/nfs rw " \ |
| 657 | "nfsroot=$serverip:$rootpath " \ |
| 658 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 659 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 660 | "tftp $loadaddr $bootfile;" \ |
| 661 | "tftp $fdtaddr $fdtfile;" \ |
| 662 | "bootm $loadaddr - $fdtaddr" |
| 663 | |
| 664 | #define CONFIG_RAMBOOTCOMMAND \ |
| 665 | "setenv bootargs root=/dev/ram rw " \ |
| 666 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 667 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 668 | "tftp $loadaddr $bootfile;" \ |
| 669 | "tftp $fdtaddr $fdtfile;" \ |
| 670 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| 671 | |
| 672 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT |
| 673 | |
| 674 | #endif /* __CONFIG_H */ |