Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Configuration for Versatile Express. Parts were derived from other ARM |
| 4 | * configurations. |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 7 | #ifndef __VEXPRESS_AEMV8_H |
| 8 | #define __VEXPRESS_AEMV8_H |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 9 | |
Peter Hoyes | 16fff30 | 2021-11-11 09:26:01 +0000 | [diff] [blame] | 10 | #include <linux/stringify.h> |
| 11 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 12 | /* Link Definitions */ |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 13 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 14 | #else |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 15 | /* ATF loads u-boot here for BASE_FVP model */ |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 16 | #endif |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 17 | |
Ryan Harkin | 642aa2c | 2015-10-09 17:18:01 +0100 | [diff] [blame] | 18 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| 19 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 20 | /* CS register bases for the original memory map. */ |
Peter Hoyes | 3ca0ea0 | 2022-03-04 16:30:18 +0000 | [diff] [blame] | 21 | #ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP |
| 22 | #define V2M_DRAM_BASE 0x00000000 |
| 23 | #define V2M_PA_BASE 0x80000000 |
| 24 | #else |
Andre Przywara | 87de4b7 | 2022-03-04 16:30:16 +0000 | [diff] [blame] | 25 | #define V2M_DRAM_BASE 0x80000000 |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 26 | #define V2M_PA_BASE 0x00000000 |
Peter Hoyes | 3ca0ea0 | 2022-03-04 16:30:18 +0000 | [diff] [blame] | 27 | #endif |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 28 | |
| 29 | #define V2M_PA_CS0 (V2M_PA_BASE + 0x00000000) |
| 30 | #define V2M_PA_CS1 (V2M_PA_BASE + 0x14000000) |
| 31 | #define V2M_PA_CS2 (V2M_PA_BASE + 0x18000000) |
| 32 | #define V2M_PA_CS3 (V2M_PA_BASE + 0x1c000000) |
| 33 | #define V2M_PA_CS4 (V2M_PA_BASE + 0x0c000000) |
| 34 | #define V2M_PA_CS5 (V2M_PA_BASE + 0x10000000) |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 35 | |
| 36 | #define V2M_PERIPH_OFFSET(x) (x << 16) |
| 37 | #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) |
| 38 | #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) |
| 39 | #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) |
| 40 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 41 | /* Common peripherals relative to CS7. */ |
| 42 | #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) |
| 43 | #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) |
| 44 | #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) |
| 45 | #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) |
| 46 | |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 47 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
| 48 | #define V2M_UART0 0x7ff80000 |
| 49 | #define V2M_UART1 0x7ff70000 |
| 50 | #else /* Not Juno */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 51 | #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) |
| 52 | #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) |
| 53 | #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) |
| 54 | #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 55 | #endif |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 56 | |
| 57 | #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) |
| 58 | |
| 59 | #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) |
| 60 | #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) |
| 61 | |
| 62 | #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) |
| 63 | #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) |
| 64 | |
| 65 | #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) |
| 66 | |
| 67 | #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) |
| 68 | |
| 69 | /* System register offsets. */ |
| 70 | #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) |
| 71 | #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) |
| 72 | #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) |
| 73 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 74 | /* Generic Interrupt Controller Definitions */ |
David Feng | 79bbde0 | 2014-03-14 14:26:27 +0800 | [diff] [blame] | 75 | #ifdef CONFIG_GICV3 |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 76 | #define GICD_BASE (V2M_PA_BASE + 0x2f000000) |
| 77 | #define GICR_BASE (V2M_PA_BASE + 0x2f100000) |
David Feng | 79bbde0 | 2014-03-14 14:26:27 +0800 | [diff] [blame] | 78 | #else |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 79 | |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 80 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 81 | #define GICD_BASE (0x2C010000) |
| 82 | #define GICC_BASE (0x2C02f000) |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 83 | #else |
| 84 | #define GICD_BASE (V2M_PA_BASE + 0x2f000000) |
| 85 | #define GICC_BASE (V2M_PA_BASE + 0x2c000000) |
David Feng | 79bbde0 | 2014-03-14 14:26:27 +0800 | [diff] [blame] | 86 | #endif |
Linus Walleij | a90caa3 | 2015-03-23 11:06:14 +0100 | [diff] [blame] | 87 | #endif /* !CONFIG_GICV3 */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 88 | |
Peter Hoyes | 8194cda | 2021-11-11 09:26:03 +0000 | [diff] [blame] | 89 | #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && !defined(CONFIG_DM_ETH) |
| 90 | /* The Vexpress64 BASE_FVP simulator uses SMSC91C111 */ |
Bhupesh Sharma | e997f35 | 2014-01-16 09:47:40 -0600 | [diff] [blame] | 91 | #define CONFIG_SMC91111 1 |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 92 | #define CONFIG_SMC91111_BASE (V2M_PA_BASE + 0x01A000000) |
Linus Walleij | 48b4755 | 2015-02-17 11:35:25 +0100 | [diff] [blame] | 93 | #endif |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 94 | |
| 95 | /* PL011 Serial Configuration */ |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 96 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
Andre Przywara | d345718 | 2020-04-27 19:18:00 +0100 | [diff] [blame] | 97 | #define CONFIG_PL011_CLOCK 7372800 |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 98 | #else |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 99 | #define CONFIG_PL011_CLOCK 24000000 |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 100 | #endif |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 101 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 102 | /* Physical Memory Map */ |
Andre Przywara | 87de4b7 | 2022-03-04 16:30:16 +0000 | [diff] [blame] | 103 | #define PHYS_SDRAM_1 (V2M_DRAM_BASE) /* SDRAM Bank #1 */ |
Linus Walleij | 0a38bfe | 2015-05-11 10:03:57 +0200 | [diff] [blame] | 104 | /* Top 16MB reserved for secure world use */ |
| 105 | #define DRAM_SEC_SIZE 0x01000000 |
| 106 | #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE |
| 107 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 108 | |
Ryan Harkin | 98d2fff | 2015-11-18 10:39:07 +0000 | [diff] [blame] | 109 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
Ryan Harkin | 98d2fff | 2015-11-18 10:39:07 +0000 | [diff] [blame] | 110 | #define PHYS_SDRAM_2 (0x880000000) |
| 111 | #define PHYS_SDRAM_2_SIZE 0x180000000 |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 112 | #elif CONFIG_NR_DRAM_BANKS == 2 |
Diego Sueiro | 7a02a1b | 2021-02-15 07:27:57 +0000 | [diff] [blame] | 113 | #define PHYS_SDRAM_2 (0x880000000) |
| 114 | #define PHYS_SDRAM_2_SIZE 0x80000000 |
Ryan Harkin | 98d2fff | 2015-11-18 10:39:07 +0000 | [diff] [blame] | 115 | #endif |
| 116 | |
Andre Przywara | ec41c7f | 2022-03-04 16:30:12 +0000 | [diff] [blame] | 117 | /* Copy the kernel, initrd and FDT from NOR flash to DRAM memory and boot. */ |
Andre Przywara | be03531 | 2021-07-12 00:25:15 +0100 | [diff] [blame] | 118 | #define BOOTENV_DEV_AFS(devtypeu, devtypel, instance) \ |
| 119 | "bootcmd_afs=" \ |
| 120 | "afs load ${kernel_name} ${kernel_addr_r} ;"\ |
| 121 | "if test $? -eq 1; then "\ |
| 122 | " echo Loading ${kernel_alt_name} instead of ${kernel_name}; "\ |
| 123 | " afs load ${kernel_alt_name} ${kernel_addr_r};"\ |
| 124 | "fi ; "\ |
| 125 | "afs load ${fdtfile} ${fdt_addr_r} ;"\ |
| 126 | "if test $? -eq 1; then "\ |
| 127 | " echo Loading ${fdt_alt_name} instead of ${fdtfile}; "\ |
| 128 | " afs load ${fdt_alt_name} ${fdt_addr_r}; "\ |
| 129 | "fi ; "\ |
| 130 | "fdt addr ${fdt_addr_r}; fdt resize; " \ |
| 131 | "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\ |
| 132 | "then "\ |
| 133 | " setenv ramdisk_param ${ramdisk_addr_r}; "\ |
| 134 | "else "\ |
| 135 | " setenv ramdisk_param -; "\ |
| 136 | "fi ; " \ |
| 137 | "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}\0" |
| 138 | #define BOOTENV_DEV_NAME_AFS(devtypeu, devtypel, instance) "afs " |
| 139 | |
Andre Przywara | 019753a | 2022-03-04 16:30:14 +0000 | [diff] [blame] | 140 | /* Boot by executing a U-Boot script pre-loaded into DRAM. */ |
| 141 | #define BOOTENV_DEV_MEM(devtypeu, devtypel, instance) \ |
| 142 | "bootcmd_mem= " \ |
| 143 | "source ${scriptaddr}; " \ |
| 144 | "if test $? -eq 1; then " \ |
| 145 | " env import -t ${scriptaddr}; " \ |
| 146 | " if test -n $uenvcmd; then " \ |
| 147 | " echo Running uenvcmd ...; " \ |
| 148 | " run uenvcmd; " \ |
| 149 | " fi; " \ |
| 150 | "fi\0" |
| 151 | #define BOOTENV_DEV_NAME_MEM(devtypeu, devtypel, instance) "mem " |
| 152 | |
| 153 | #ifdef CONFIG_CMD_VIRTIO |
| 154 | #define FUNC_VIRTIO(func) func(VIRTIO, virtio, 0) |
| 155 | #else |
| 156 | #define FUNC_VIRTIO(func) |
| 157 | #endif |
| 158 | |
| 159 | /* |
| 160 | * Boot by loading an Android image, or kernel, initrd and FDT through |
| 161 | * semihosting into DRAM. |
| 162 | */ |
| 163 | #define BOOTENV_DEV_SMH(devtypeu, devtypel, instance) \ |
| 164 | "bootcmd_smh= " \ |
Sean Anderson | 3e056ba | 2022-03-22 16:59:22 -0400 | [diff] [blame] | 165 | "if load hostfs - ${boot_addr_r} ${boot_name}; then" \ |
Andre Przywara | 019753a | 2022-03-04 16:30:14 +0000 | [diff] [blame] | 166 | " setenv bootargs;" \ |
| 167 | " abootimg addr ${boot_addr_r};" \ |
| 168 | " abootimg get dtb --index=0 fdt_addr_r;" \ |
| 169 | " bootm ${boot_addr_r} ${boot_addr_r} ${fdt_addr_r};" \ |
| 170 | "else" \ |
Sean Anderson | 3e056ba | 2022-03-22 16:59:22 -0400 | [diff] [blame] | 171 | " if load hostfs - ${kernel_addr_r} ${kernel_name}; then" \ |
Andre Przywara | 019753a | 2022-03-04 16:30:14 +0000 | [diff] [blame] | 172 | " setenv fdt_high 0xffffffffffffffff;" \ |
| 173 | " setenv initrd_high 0xffffffffffffffff;" \ |
Sean Anderson | 3e056ba | 2022-03-22 16:59:22 -0400 | [diff] [blame] | 174 | " load hostfs - ${fdt_addr_r} ${fdtfile};" \ |
| 175 | " load hostfs - ${ramdisk_addr_r} ${ramdisk_name};" \ |
Andre Przywara | 019753a | 2022-03-04 16:30:14 +0000 | [diff] [blame] | 176 | " fdt addr ${fdt_addr_r};" \ |
| 177 | " fdt resize;" \ |
Sean Anderson | 3e056ba | 2022-03-22 16:59:22 -0400 | [diff] [blame] | 178 | " fdt chosen ${ramdisk_addr_r} ${filesize};" \ |
Andre Przywara | 019753a | 2022-03-04 16:30:14 +0000 | [diff] [blame] | 179 | " booti $kernel_addr_r - $fdt_addr_r;" \ |
| 180 | " fi;" \ |
| 181 | "fi\0" |
| 182 | #define BOOTENV_DEV_NAME_SMH(devtypeu, devtypel, instance) "smh " |
| 183 | |
Andre Przywara | ec41c7f | 2022-03-04 16:30:12 +0000 | [diff] [blame] | 184 | /* Boot sources for distro boot and load addresses, per board */ |
| 185 | |
| 186 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO /* Arm Juno board */ |
| 187 | |
Andre Przywara | be03531 | 2021-07-12 00:25:15 +0100 | [diff] [blame] | 188 | #define BOOT_TARGET_DEVICES(func) \ |
| 189 | func(USB, usb, 0) \ |
| 190 | func(SATA, sata, 0) \ |
| 191 | func(SATA, sata, 1) \ |
| 192 | func(PXE, pxe, na) \ |
| 193 | func(DHCP, dhcp, na) \ |
| 194 | func(AFS, afs, na) |
| 195 | |
Andre Przywara | ec41c7f | 2022-03-04 16:30:12 +0000 | [diff] [blame] | 196 | #define VEXPRESS_KERNEL_ADDR 0x80080000 |
| 197 | #define VEXPRESS_PXEFILE_ADDR 0x8fb00000 |
| 198 | #define VEXPRESS_FDT_ADDR 0x8fc00000 |
| 199 | #define VEXPRESS_SCRIPT_ADDR 0x8fd00000 |
| 200 | #define VEXPRESS_RAMDISK_ADDR 0x8fe00000 |
Linus Walleij | c39566a | 2015-04-05 01:48:32 +0200 | [diff] [blame] | 201 | |
Andre Przywara | ec41c7f | 2022-03-04 16:30:12 +0000 | [diff] [blame] | 202 | #define EXTRA_ENV_NAMES \ |
| 203 | "kernel_name=norkern\0" \ |
| 204 | "kernel_alt_name=Image\0" \ |
| 205 | "ramdisk_name=ramdisk.img\0" \ |
| 206 | "fdtfile=board.dtb\0" \ |
| 207 | "fdt_alt_name=juno\0" |
Peter Hoyes | 16fff30 | 2021-11-11 09:26:01 +0000 | [diff] [blame] | 208 | |
Andre Przywara | ec41c7f | 2022-03-04 16:30:12 +0000 | [diff] [blame] | 209 | #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP /* ARMv8-A base model */ |
Peter Hoyes | 16fff30 | 2021-11-11 09:26:01 +0000 | [diff] [blame] | 210 | |
Andre Przywara | 019753a | 2022-03-04 16:30:14 +0000 | [diff] [blame] | 211 | #define BOOT_TARGET_DEVICES(func) \ |
| 212 | func(SMH, smh, na) \ |
| 213 | func(MEM, mem, na) \ |
| 214 | FUNC_VIRTIO(func) \ |
| 215 | func(PXE, pxe, na) \ |
| 216 | func(DHCP, dhcp, na) |
| 217 | |
Andre Przywara | ec41c7f | 2022-03-04 16:30:12 +0000 | [diff] [blame] | 218 | #define VEXPRESS_KERNEL_ADDR 0x80080000 |
| 219 | #define VEXPRESS_PXEFILE_ADDR 0x8fa00000 |
| 220 | #define VEXPRESS_SCRIPT_ADDR 0x8fb00000 |
| 221 | #define VEXPRESS_FDT_ADDR 0x8fc00000 |
| 222 | #define VEXPRESS_BOOT_ADDR 0x8fd00000 |
| 223 | #define VEXPRESS_RAMDISK_ADDR 0x8fe00000 |
| 224 | |
| 225 | #define EXTRA_ENV_NAMES \ |
| 226 | "kernel_name=Image\0" \ |
| 227 | "ramdisk_name=ramdisk.img\0" \ |
| 228 | "fdtfile=devtree.dtb\0" \ |
| 229 | "boot_name=boot.img\0" \ |
| 230 | "boot_addr_r=" __stringify(VEXPRESS_BOOT_ADDR) "\0" |
| 231 | |
Peter Hoyes | 3ca0ea0 | 2022-03-04 16:30:18 +0000 | [diff] [blame] | 232 | #elif CONFIG_TARGET_VEXPRESS64_BASER_FVP /* ARMv8-R base model */ |
| 233 | |
| 234 | #define BOOT_TARGET_DEVICES(func) \ |
| 235 | func(MEM, mem, na) \ |
| 236 | FUNC_VIRTIO(func) \ |
| 237 | func(PXE, pxe, na) \ |
| 238 | func(DHCP, dhcp, na) |
| 239 | |
| 240 | #define VEXPRESS_KERNEL_ADDR 0x00200000 |
| 241 | #define VEXPRESS_PXEFILE_ADDR 0x0fb00000 |
| 242 | #define VEXPRESS_FDT_ADDR 0x0fc00000 |
| 243 | #define VEXPRESS_SCRIPT_ADDR 0x0fd00000 |
| 244 | #define VEXPRESS_RAMDISK_ADDR 0x0fe00000 |
| 245 | |
| 246 | #define EXTRA_ENV_NAMES \ |
| 247 | "kernel_name=Image\0" \ |
| 248 | "ramdisk_name=ramdisk.img\0" \ |
| 249 | "fdtfile=board.dtb\0" |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 250 | #endif |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 251 | |
Andre Przywara | 019753a | 2022-03-04 16:30:14 +0000 | [diff] [blame] | 252 | #include <config_distro_bootcmd.h> |
| 253 | |
Andre Przywara | ec41c7f | 2022-03-04 16:30:12 +0000 | [diff] [blame] | 254 | /* Default load addresses and names for the different payloads. */ |
| 255 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 256 | "kernel_addr_r=" __stringify(VEXPRESS_KERNEL_ADDR) "\0" \ |
| 257 | "ramdisk_addr_r=" __stringify(VEXPRESS_RAMDISK_ADDR) "\0" \ |
| 258 | "pxefile_addr_r=" __stringify(VEXPRESS_PXEFILE_ADDR) "\0" \ |
| 259 | "fdt_addr_r=" __stringify(VEXPRESS_FDT_ADDR) "\0" \ |
| 260 | "scriptaddr=" __stringify(VEXPRESS_SCRIPT_ADDR) "\0" \ |
| 261 | EXTRA_ENV_NAMES \ |
| 262 | BOOTENV |
| 263 | |
Ryan Harkin | ad5b2a2 | 2015-11-18 10:39:09 +0000 | [diff] [blame] | 264 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
| 265 | #define CONFIG_SYS_FLASH_BASE 0x08000000 |
| 266 | /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ |
| 267 | #define CONFIG_SYS_MAX_FLASH_SECT 259 |
| 268 | /* Store environment at top of flash in the same location as blank.img */ |
| 269 | /* in the Juno firmware. */ |
Linus Walleij | 6ba4b6a | 2015-02-19 17:19:37 +0100 | [diff] [blame] | 270 | #else |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 271 | #define CONFIG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000) |
Ryan Harkin | ad5b2a2 | 2015-11-18 10:39:09 +0000 | [diff] [blame] | 272 | /* 256 x 256KiB sectors */ |
| 273 | #define CONFIG_SYS_MAX_FLASH_SECT 256 |
| 274 | /* Store environment at top of flash */ |
Ryan Harkin | ad5b2a2 | 2015-11-18 10:39:09 +0000 | [diff] [blame] | 275 | #endif |
| 276 | |
Andre Przywara | e3e8121 | 2020-04-27 19:18:03 +0100 | [diff] [blame] | 277 | #ifdef CONFIG_USB_EHCI_HCD |
| 278 | #define CONFIG_USB_OHCI_NEW |
| 279 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 |
| 280 | #endif |
| 281 | |
Linus Walleij | 6ba4b6a | 2015-02-19 17:19:37 +0100 | [diff] [blame] | 282 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ |
Ryan Harkin | ad5b2a2 | 2015-11-18 10:39:09 +0000 | [diff] [blame] | 283 | #define FLASH_MAX_SECTOR_SIZE 0x00040000 |
Linus Walleij | 6ba4b6a | 2015-02-19 17:19:37 +0100 | [diff] [blame] | 284 | |
Peter Hoyes | 3286037 | 2021-11-11 09:26:00 +0000 | [diff] [blame] | 285 | #endif /* __VEXPRESS_AEMV8_H */ |