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git01.mediatek.com / filogic / uboot / bebd282446306e3adfea2144af472e87856955d8 / . / arch / arm / mach-omap2 / omap5 / Kconfig
blob: 4c2f990b28782ef1628a99f66392cb19e61f8b92 [file] [log] [blame]
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]1if OMAP54XX
2
Uri Mashiache47ae872017-02-23 15:39:35 +0200[diff] [blame]3config DRA7XX
4 bool
5 help
6 DRA7xx is an OMAP based SOC with Dual Core A-15s.
7
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]8choice
9 prompt "OMAP5 board select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500[diff] [blame]10 optional
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]11
12config TARGET_CM_T54
13 bool "CompuLab CM-T54"
14
15config TARGET_OMAP5_UEVM
16 bool "TI OMAP5 uEVM board"
17
18config TARGET_DRA7XX_EVM
19 bool "TI DRA7XX"
Tom Rini22d567e2017-01-22 19:43:11 -0500[diff] [blame]20 select BOARD_LATE_INIT
Uri Mashiache47ae872017-02-23 15:39:35 +0200[diff] [blame]21 select DRA7XX
Masahiro Yamada653e9fe2016-07-25 19:56:03 +0900[diff] [blame]22 select PHYS_64BIT
Michal Simek7e7ba3b2018-07-23 15:55:15 +0200[diff] [blame]23 select TI_I2C_BOARD_DETECT
Lokesh Vutla68ad5062017-08-21 12:50:51 +0530[diff] [blame]24 imply DM_PMIC
Lokesh Vutla68ad5062017-08-21 12:50:51 +0530[diff] [blame]25 imply DM_REGULATOR
26 imply DM_REGULATOR_LP87565
Faiz Abbas6c198d72017-11-14 16:12:33 +0530[diff] [blame]27 imply DM_THERMAL
Michal Simek7e7ba3b2018-07-23 15:55:15 +0200[diff] [blame]28 imply PMIC_LP87565
29 imply SCSI
30 imply SPL_THERMAL
Faiz Abbas6c198d72017-11-14 16:12:33 +0530[diff] [blame]31 imply TI_DRA7_THERMAL
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]32
Lokesh Vutla6c2cfdd2016-06-10 09:35:42 +0530[diff] [blame]33config TARGET_AM57XX_EVM
34 bool "AM57XX"
Tom Rini22d567e2017-01-22 19:43:11 -0500[diff] [blame]35 select BOARD_LATE_INIT
Michal Simek7e7ba3b2018-07-23 15:55:15 +0200[diff] [blame]36 select CMD_DDR3
Uri Mashiache47ae872017-02-23 15:39:35 +0200[diff] [blame]37 select DRA7XX
Kipisz, Steven161f1382016-02-24 12:30:58 -0600[diff] [blame]38 select TI_I2C_BOARD_DETECT
Kory Maincent66fd9ec2021-05-04 19:31:25 +0200[diff] [blame]39 select SUPPORT_EXTENSION_SCAN
Michal Simek7e7ba3b2018-07-23 15:55:15 +0200[diff] [blame]40 imply DM_THERMAL
Simon Glass0e5faf02017-06-14 21:28:21 -0600[diff] [blame]41 imply SCSI
Faiz Abbas6c198d72017-11-14 16:12:33 +0530[diff] [blame]42 imply SPL_THERMAL
Faiz Abbas6c198d72017-11-14 16:12:33 +0530[diff] [blame]43 imply TI_DRA7_THERMAL
Felipe Balbi4750eb62014-11-10 14:02:44 -0600[diff] [blame]44
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]45endchoice
46
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]47config SYS_SOC
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]48 default "omap5"
49
Tom Rini50e221a2017-05-12 22:33:17 -0400[diff] [blame]50config OMAP_PLATFORM_RESET_TIME_MAX_USEC
51 int "Something"
52 range 0 31219
53 default 31219
54 help
55 Most OMAPs' provide a way to specify the time for which the reset
56 should be held low while the voltages and Oscillator outputs
57 stabilize.
58 This time is mostly board and PMIC dependent. Hence the boards are
59 expected to specify a pre-computed time using the above option.
60 This value can be computed using a summation of the below 3
61 parameters
62 1: Time taken by the Osciallator to stop and restart
63 2: PMIC OTP time
64 3: Voltage ramp time, which can be derived using the PMIC slew rate
65 and value of voltage ramp needed.
66
Suman Annaf28b26c2016-11-23 12:54:40 +0530[diff] [blame]67if TARGET_DRA7XX_EVM || TARGET_AM57XX_EVM
68menu "Voltage Domain OPP selections"
69
70choice
71 prompt "MPU Voltage Domain"
72 default DRA7_MPU_OPP_NOM
73 help
74 Select the Operating Performance Point(OPP) for the MPU voltage
75 domain on DRA7xx & AM57xx SoCs.
76
77config DRA7_MPU_OPP_NOM
78 bool "OPP NOM"
79 help
80 This config option enables Normal OPP for MPU. This is the safest
81 option for booting.
82
83endchoice
84
85choice
86 prompt "DSPEVE Voltage Domain"
87 help
88 Select the Operating Performance Point(OPP) for the DSPEVE voltage
89 domain on DRA7xx & AM57xx SoCs.
90
91config DRA7_DSPEVE_OPP_NOM
92 bool "OPP NOM"
93 help
94 This config option enables Normal OPP for DSPEVE. This is the safest
95 option for booting and choose this when unsure about other OPPs .
96
97config DRA7_DSPEVE_OPP_OD
98 bool "OPP OD"
99 help
100 This config option enables Over drive OPP for DSPEVE.
101
102config DRA7_DSPEVE_OPP_HIGH
103 bool "OPP HIGH"
104 help
105 This config option enables High OPP for DSPEVE.
106
107endchoice
108
109choice
110 prompt "IVA Voltage Domain"
111 help
112 Select the Operating Performance Point(OPP) for the IVA voltage
113 domain on DRA7xx & AM57xx SoCs.
114
115config DRA7_IVA_OPP_NOM
116 bool "OPP NOM"
117 help
118 This config option enables Normal OPP for IVA. This is the safest
119 option for booting and choose this when unsure about other OPPs .
120
121config DRA7_IVA_OPP_OD
122 bool "OPP OD"
123 help
124 This config option enables Over drive OPP for IVA.
125
126config DRA7_IVA_OPP_HIGH
127 bool "OPP HIGH"
128 help
129 This config option enables High OPP for IVA.
130
131endchoice
132
133choice
134 prompt "GPU Voltage Domain"
135 help
136 Select the Operating Performance Point(OPP) for the GPU voltage
137 domain on DRA7xx & AM57xx SoCs.
138
139config DRA7_GPU_OPP_NOM
140 bool "OPP NOM"
141 help
142 This config option enables Normal OPP for GPU. This is the safest
143 option for booting and choose this when unsure about other OPPs .
144
145config DRA7_GPU_OPP_OD
146 bool "OPP OD"
147 help
148 This config option enables Over drive OPP for GPU.
149
150config DRA7_GPU_OPP_HIGH
151 bool "OPP HIGH"
152 help
153 This config option enables High OPP for GPU.
154
155endchoice
156
157endmenu
158endif
159
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]160source "board/ti/omap5_uevm/Kconfig"
161source "board/ti/dra7xx/Kconfig"
Kipisz, Steven1dacd0d2015-10-29 16:50:43 -0500[diff] [blame]162source "board/ti/am57xx/Kconfig"
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]163
164endif