blob: 8c0592767029fa63927bda49fbd466226e738875 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060040 mmc2 = "/mmc2";
41 mmc3 = "/mmc3";
Bin Meng408e5902018-08-03 01:14:41 -070042 pci0 = &pci0;
43 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070044 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020045 remoteproc0 = &rproc_1;
46 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060047 rtc0 = &rtc_0;
48 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060049 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020050 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070051 testbus3 = "/some-bus";
52 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070053 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070054 testfdt3 = "/b-test";
55 testfdt5 = "/some-bus/c-test@5";
56 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070057 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020058 fdt-dummy0 = "/translation-test@8000/dev@0,0";
59 fdt-dummy1 = "/translation-test@8000/dev@1,100";
60 fdt-dummy2 = "/translation-test@8000/dev@2,200";
61 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060062 usb0 = &usb_0;
63 usb1 = &usb_1;
64 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020065 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020066 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060067 };
68
Simon Glass5e135d32022-10-20 18:23:15 -060069 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020070 };
71
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020072 config {
Simon Glass0034d962021-08-07 07:24:01 -060073 testing-bool;
74 testing-int = <123>;
75 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020076 environment {
77 from_fdt = "yes";
78 fdt_env_path = "";
79 };
80 };
81
Simon Glassb255efc2022-04-24 23:31:24 -060082 bootstd {
Simon Glassa9289612022-10-20 18:23:14 -060083 u-boot,dm-vpl;
Simon Glassb255efc2022-04-24 23:31:24 -060084 compatible = "u-boot,boot-std";
85
86 filename-prefixes = "/", "/boot/";
87 bootdev-order = "mmc2", "mmc1";
88
89 syslinux {
90 compatible = "u-boot,distro-syslinux";
91 };
92
93 efi {
94 compatible = "u-boot,distro-efi";
95 };
Simon Glassa9289612022-10-20 18:23:14 -060096
Simon Glassd2bc33ed2023-01-06 08:52:41 -060097 theme {
98 font-size = <30>;
99 };
100
Simon Glassf1eba352022-10-20 18:23:20 -0600101 /*
102 * This is used for the VBE OS-request tests. A FAT filesystem
103 * created in a partition with the VBE information appearing
104 * before the parititon starts
105 */
Simon Glassa9289612022-10-20 18:23:14 -0600106 firmware0 {
107 u-boot,dm-vpl;
108 compatible = "fwupd,vbe-simple";
109 storage = "mmc1";
110 skip-offset = <0x200>;
111 area-start = <0x400>;
112 area-size = <0x1000>;
113 state-offset = <0x400>;
114 state-size = <0x40>;
115 version-offset = <0x800>;
116 version-size = <0x100>;
117 };
Simon Glassf1eba352022-10-20 18:23:20 -0600118
119 /*
120 * This is used for the VBE VPL tests. The MMC device holds the
121 * binman image.bin file. The test progresses through each phase
122 * of U-Boot, loading each in turn from MMC.
123 *
124 * Note that the test enables this node (and mmc3) before
125 * running U-Boot
126 */
127 firmware1 {
128 u-boot,dm-vpl;
129 status = "disabled";
130 compatible = "fwupd,vbe-simple";
131 storage = "mmc3";
132 skip-offset = <0x400000>;
133 area-start = <0>;
134 area-size = <0xe00000>;
135 state-offset = <0xdffc00>;
136 state-size = <0x40>;
137 version-offset = <0xdffe00>;
138 version-size = <0x100>;
139 };
Simon Glassb255efc2022-04-24 23:31:24 -0600140 };
141
Andrew Scull451b8b12022-05-30 10:00:12 +0000142 fuzzing-engine {
143 compatible = "sandbox,fuzzing-engine";
144 };
145
Nandor Han6521e5d2021-06-10 16:56:44 +0300146 reboot-mode0 {
147 compatible = "reboot-mode-gpio";
148 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
149 u-boot,env-variable = "bootstatus";
150 mode-test = <0x01>;
151 mode-download = <0x03>;
152 };
153
Nandor Han7e4067a2021-06-10 16:56:45 +0300154 reboot_mode1: reboot-mode@14 {
155 compatible = "reboot-mode-rtc";
156 rtc = <&rtc_0>;
157 reg = <0x30 4>;
158 u-boot,env-variable = "bootstatus";
159 big-endian;
160 mode-test = <0x21969147>;
161 mode-download = <0x51939147>;
162 };
163
Simon Glassed96cde2018-12-10 10:37:33 -0700164 audio: audio-codec {
165 compatible = "sandbox,audio-codec";
166 #sound-dai-cells = <1>;
167 };
168
Philippe Reynes1ee26482020-07-24 18:19:51 +0200169 buttons {
170 compatible = "gpio-keys";
171
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200172 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200173 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200174 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200175 };
176
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200177 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200178 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200179 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200180 };
181 };
182
Marek Szyprowskiad398592021-02-18 11:33:18 +0100183 buttons2 {
184 compatible = "adc-keys";
185 io-channels = <&adc 3>;
186 keyup-threshold-microvolt = <3000000>;
187
188 button-up {
189 label = "button3";
190 linux,code = <KEY_F3>;
191 press-threshold-microvolt = <1500000>;
192 };
193
194 button-down {
195 label = "button4";
196 linux,code = <KEY_F4>;
197 press-threshold-microvolt = <1000000>;
198 };
199
200 button-enter {
201 label = "button5";
202 linux,code = <KEY_F5>;
203 press-threshold-microvolt = <500000>;
204 };
205 };
206
Simon Glassc953aaf2018-12-10 10:37:34 -0700207 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600208 reg = <0 0>;
209 compatible = "google,cros-ec-sandbox";
210
211 /*
212 * This describes the flash memory within the EC. Note
213 * that the STM32L flash erases to 0, not 0xff.
214 */
215 flash {
216 image-pos = <0x08000000>;
217 size = <0x20000>;
218 erase-value = <0>;
219
220 /* Information for sandbox */
221 ro {
222 image-pos = <0>;
223 size = <0xf000>;
224 };
225 wp-ro {
226 image-pos = <0xf000>;
227 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700228 used = <0x884>;
229 compress = "lz4";
230 uncomp-size = <0xcf8>;
231 hash {
232 algo = "sha256";
233 value = [00 01 02 03 04 05 06 07
234 08 09 0a 0b 0c 0d 0e 0f
235 10 11 12 13 14 15 16 17
236 18 19 1a 1b 1c 1d 1e 1f];
237 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600238 };
239 rw {
240 image-pos = <0x10000>;
241 size = <0x10000>;
242 };
243 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300244
245 cros_ec_pwm: cros-ec-pwm {
246 compatible = "google,cros-ec-pwm";
247 #pwm-cells = <1>;
248 };
249
Simon Glass699c9ca2018-10-01 12:22:08 -0600250 };
251
Yannick Fertré9712c822019-10-07 15:29:05 +0200252 dsi_host: dsi_host {
253 compatible = "sandbox,dsi-host";
254 };
255
Simon Glassb2c1cac2014-02-26 15:59:21 -0700256 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600257 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700258 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600259 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700260 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600261 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100262 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
263 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700264 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100265 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
266 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
267 <&gpio_b 7 GPIO_IN 3 2 1>,
268 <&gpio_b 8 GPIO_OUT 3 2 1>,
269 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100270 test3-gpios =
271 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
272 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
273 <&gpio_c 2 GPIO_OUT>,
274 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
275 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200276 <&gpio_c 5 GPIO_IN>,
277 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
278 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530279 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
280 test5-gpios = <&gpio_a 19>;
281
Simon Glass73025392021-10-23 17:26:04 -0600282 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200283 int8-value = /bits/ 8 <0x12>;
284 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700285 int-value = <1234>;
286 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200287 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200288 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600289 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700290 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600291 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200292 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530293
294 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
295 <&muxcontroller0 2>, <&muxcontroller0 3>,
296 <&muxcontroller1>;
297 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
298 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100299 display-timings {
300 timing0: 240x320 {
301 clock-frequency = <6500000>;
302 hactive = <240>;
303 vactive = <320>;
304 hfront-porch = <6>;
305 hback-porch = <7>;
306 hsync-len = <1>;
307 vback-porch = <5>;
308 vfront-porch = <8>;
309 vsync-len = <2>;
310 hsync-active = <1>;
311 vsync-active = <0>;
312 de-active = <1>;
313 pixelclk-active = <1>;
314 interlaced;
315 doublescan;
316 doubleclk;
317 };
318 timing1: 480x800 {
319 clock-frequency = <9000000>;
320 hactive = <480>;
321 vactive = <800>;
322 hfront-porch = <10>;
323 hback-porch = <59>;
324 hsync-len = <12>;
325 vback-porch = <15>;
326 vfront-porch = <17>;
327 vsync-len = <16>;
328 hsync-active = <0>;
329 vsync-active = <1>;
330 de-active = <0>;
331 pixelclk-active = <0>;
332 };
333 timing2: 800x480 {
334 clock-frequency = <33500000>;
335 hactive = <800>;
336 vactive = <480>;
337 hback-porch = <89>;
338 hfront-porch = <164>;
339 vback-porch = <23>;
340 vfront-porch = <10>;
341 hsync-len = <11>;
342 vsync-len = <13>;
343 };
344 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700345 };
346
347 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600348 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700349 compatible = "not,compatible";
350 };
351
352 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600353 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700354 };
355
Simon Glass5620cf82018-10-01 12:22:40 -0600356 backlight: backlight {
357 compatible = "pwm-backlight";
358 enable-gpios = <&gpio_a 1>;
359 power-supply = <&ldo_1>;
360 pwms = <&pwm 0 1000>;
361 default-brightness-level = <5>;
362 brightness-levels = <0 16 32 64 128 170 202 234 255>;
363 };
364
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200365 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200366 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200367 bind-test-child1 {
368 compatible = "sandbox,phy";
369 #phy-cells = <1>;
370 };
371
372 bind-test-child2 {
373 compatible = "simple-bus";
374 };
375 };
376
Simon Glassb2c1cac2014-02-26 15:59:21 -0700377 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600378 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700379 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600380 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700381 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530382
383 mux-controls = <&muxcontroller0 0>;
384 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700385 };
386
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200387 phy_provider0: gen_phy@0 {
388 compatible = "sandbox,phy";
389 #phy-cells = <1>;
390 };
391
392 phy_provider1: gen_phy@1 {
393 compatible = "sandbox,phy";
394 #phy-cells = <0>;
395 broken;
396 };
397
developer71092972020-05-02 11:35:12 +0200398 phy_provider2: gen_phy@2 {
399 compatible = "sandbox,phy";
400 #phy-cells = <0>;
401 };
402
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200403 gen_phy_user: gen_phy_user {
404 compatible = "simple-bus";
405 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
406 phy-names = "phy1", "phy2", "phy3";
407 };
408
developer71092972020-05-02 11:35:12 +0200409 gen_phy_user1: gen_phy_user1 {
410 compatible = "simple-bus";
411 phys = <&phy_provider0 0>, <&phy_provider2>;
412 phy-names = "phy1", "phy2";
413 };
414
Simon Glassb2c1cac2014-02-26 15:59:21 -0700415 some-bus {
416 #address-cells = <1>;
417 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600418 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600419 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600420 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700421 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600422 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700423 compatible = "denx,u-boot-fdt-test";
424 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600425 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700426 ping-add = <5>;
427 };
Simon Glass40717422014-07-23 06:55:18 -0600428 c-test@0 {
429 compatible = "denx,u-boot-fdt-test";
430 reg = <0>;
431 ping-expect = <6>;
432 ping-add = <6>;
433 };
434 c-test@1 {
435 compatible = "denx,u-boot-fdt-test";
436 reg = <1>;
437 ping-expect = <7>;
438 ping-add = <7>;
439 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700440 };
441
442 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600443 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600444 ping-expect = <6>;
445 ping-add = <6>;
446 compatible = "google,another-fdt-test";
447 };
448
449 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600450 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600451 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700452 ping-add = <6>;
453 compatible = "google,another-fdt-test";
454 };
455
Simon Glass0ccb0972015-01-25 08:27:05 -0700456 f-test {
457 compatible = "denx,u-boot-fdt-test";
458 };
459
460 g-test {
461 compatible = "denx,u-boot-fdt-test";
462 };
463
Bin Mengd9d24782018-10-10 22:07:01 -0700464 h-test {
465 compatible = "denx,u-boot-fdt-test1";
466 };
467
developercf8bc132020-05-02 11:35:10 +0200468 i-test {
469 compatible = "mediatek,u-boot-fdt-test";
470 #address-cells = <1>;
471 #size-cells = <0>;
472
473 subnode@0 {
474 reg = <0>;
475 };
476
477 subnode@1 {
478 reg = <1>;
479 };
480
481 subnode@2 {
482 reg = <2>;
483 };
484 };
485
Simon Glass204675c2019-12-29 21:19:25 -0700486 devres-test {
487 compatible = "denx,u-boot-devres-test";
488 };
489
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530490 another-test {
491 reg = <0 2>;
492 compatible = "denx,u-boot-fdt-test";
493 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
494 test5-gpios = <&gpio_a 19>;
495 };
496
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100497 mmio-bus@0 {
498 #address-cells = <1>;
499 #size-cells = <1>;
500 compatible = "denx,u-boot-test-bus";
501 dma-ranges = <0x10000000 0x00000000 0x00040000>;
502
503 subnode@0 {
504 compatible = "denx,u-boot-fdt-test";
505 };
506 };
507
508 mmio-bus@1 {
509 #address-cells = <1>;
510 #size-cells = <1>;
511 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100512
513 subnode@0 {
514 compatible = "denx,u-boot-fdt-test";
515 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100516 };
517
Simon Glass3c601b12020-07-07 13:12:06 -0600518 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600519 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600520 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600521 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600522 child {
523 compatible = "denx,u-boot-acpi-test";
524 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600525 };
526
Simon Glass3c601b12020-07-07 13:12:06 -0600527 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600528 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600529 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600530 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600531 };
532
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200533 clocks {
534 clk_fixed: clk-fixed {
535 compatible = "fixed-clock";
536 #clock-cells = <0>;
537 clock-frequency = <1234>;
538 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000539
540 clk_fixed_factor: clk-fixed-factor {
541 compatible = "fixed-factor-clock";
542 #clock-cells = <0>;
543 clock-div = <3>;
544 clock-mult = <2>;
545 clocks = <&clk_fixed>;
546 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200547
548 osc {
549 compatible = "fixed-clock";
550 #clock-cells = <0>;
551 clock-frequency = <20000000>;
552 };
Stephen Warrena9622432016-06-17 09:44:00 -0600553 };
554
555 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600556 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600557 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200558 assigned-clocks = <&clk_sandbox 3>;
559 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600560 };
561
562 clk-test {
563 compatible = "sandbox,clk-test";
564 clocks = <&clk_fixed>,
565 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200566 <&clk_sandbox 0>,
567 <&clk_sandbox 3>,
568 <&clk_sandbox 2>;
569 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600570 };
571
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200572 ccf: clk-ccf {
573 compatible = "sandbox,clk-ccf";
574 };
575
Simon Glass507ab962021-12-04 08:56:31 -0700576 efi-media {
577 compatible = "sandbox,efi-media";
578 };
579
Simon Glass5b968632015-05-22 15:42:15 -0600580 eth@10002000 {
581 compatible = "sandbox,eth";
582 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600583 };
584
585 eth_5: eth@10003000 {
586 compatible = "sandbox,eth";
587 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400588 nvmem-cells = <&eth5_addr>;
589 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600590 };
591
Bin Meng04a11cb2015-08-27 22:25:53 -0700592 eth_3: sbe5 {
593 compatible = "sandbox,eth";
594 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400595 nvmem-cells = <&eth3_addr>;
596 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700597 };
598
Simon Glass5b968632015-05-22 15:42:15 -0600599 eth@10004000 {
600 compatible = "sandbox,eth";
601 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600602 };
603
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200604 phy_eth0: phy-test-eth {
605 compatible = "sandbox,eth";
606 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400607 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200608 phy-handle = <&ethphy1>;
Marek BehĂșnbc194772022-04-07 00:33:01 +0200609 phy-mode = "2500base-x";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200610 };
611
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800612 dsa_eth0: dsa-test-eth {
613 compatible = "sandbox,eth";
614 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400615 nvmem-cells = <&eth4_addr>;
616 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800617 };
618
619 dsa-test {
620 compatible = "sandbox,dsa";
621
622 ports {
623 #address-cells = <1>;
624 #size-cells = <0>;
625 swp_0: port@0 {
626 reg = <0>;
627 label = "lan0";
628 phy-mode = "rgmii-rxid";
629
630 fixed-link {
631 speed = <100>;
632 full-duplex;
633 };
634 };
635
636 swp_1: port@1 {
637 reg = <1>;
638 label = "lan1";
639 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800640 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800641 };
642
643 port@2 {
644 reg = <2>;
645 ethernet = <&dsa_eth0>;
646
647 fixed-link {
648 speed = <1000>;
649 full-duplex;
650 };
651 };
652 };
653 };
654
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700655 firmware {
656 sandbox_firmware: sandbox-firmware {
657 compatible = "sandbox,firmware";
658 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200659
Etienne Carriere09665cb2022-02-21 09:22:39 +0100660 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200661 compatible = "sandbox,scmi-agent";
662 #address-cells = <1>;
663 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200664
Etienne Carriere09665cb2022-02-21 09:22:39 +0100665 protocol@10 {
666 reg = <0x10>;
667 };
668
669 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200670 reg = <0x14>;
671 #clock-cells = <1>;
672 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200673
Etienne Carriere09665cb2022-02-21 09:22:39 +0100674 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200675 reg = <0x16>;
676 #reset-cells = <1>;
677 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100678
679 protocol@17 {
680 reg = <0x17>;
681
682 regulators {
683 #address-cells = <1>;
684 #size-cells = <0>;
685
Etienne Carriere09665cb2022-02-21 09:22:39 +0100686 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100687 reg = <0>;
688 regulator-name = "sandbox-voltd0";
689 regulator-min-microvolt = <1100000>;
690 regulator-max-microvolt = <3300000>;
691 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100692 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100693 reg = <0x1>;
694 regulator-name = "sandbox-voltd1";
695 regulator-min-microvolt = <1800000>;
696 };
697 };
698 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200699 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700700 };
701
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200702 fpga {
703 compatible = "sandbox,fpga";
704 };
705
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100706 pinctrl-gpio {
707 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700708
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100709 gpio_a: base-gpios {
710 compatible = "sandbox,gpio";
711 gpio-controller;
712 #gpio-cells = <1>;
713 gpio-bank-name = "a";
714 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200715 hog_input_active_low {
716 gpio-hog;
717 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200718 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200719 };
720 hog_input_active_high {
721 gpio-hog;
722 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200723 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200724 };
725 hog_output_low {
726 gpio-hog;
727 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200728 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200729 };
730 hog_output_high {
731 gpio-hog;
732 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200733 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200734 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100735 };
736
737 gpio_b: extra-gpios {
738 compatible = "sandbox,gpio";
739 gpio-controller;
740 #gpio-cells = <5>;
741 gpio-bank-name = "b";
742 sandbox,gpio-count = <10>;
743 };
Simon Glass25348a42014-10-13 23:42:11 -0600744
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100745 gpio_c: pinmux-gpios {
746 compatible = "sandbox,gpio";
747 gpio-controller;
748 #gpio-cells = <2>;
749 gpio-bank-name = "c";
750 sandbox,gpio-count = <10>;
751 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100752 };
753
Simon Glass7df766e2014-12-10 08:55:55 -0700754 i2c@0 {
755 #address-cells = <1>;
756 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600757 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700758 compatible = "sandbox,i2c";
759 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200760 pinctrl-names = "default";
761 pinctrl-0 = <&pinmux_i2c0_pins>;
762
Simon Glass7df766e2014-12-10 08:55:55 -0700763 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400764 #address-cells = <1>;
765 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700766 reg = <0x2c>;
767 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700768 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200769 partitions {
770 compatible = "fixed-partitions";
771 #address-cells = <1>;
772 #size-cells = <1>;
773 bootcount_i2c: bootcount@10 {
774 reg = <10 2>;
775 };
776 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400777
778 eth3_addr: mac-address@24 {
779 reg = <24 6>;
780 };
Simon Glass7df766e2014-12-10 08:55:55 -0700781 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200782
Simon Glass336b2952015-05-22 15:42:17 -0600783 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400784 #address-cells = <1>;
785 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600786 reg = <0x43>;
787 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700788 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400789
790 eth4_addr: mac-address@40 {
791 reg = <0x40 6>;
792 };
Simon Glass336b2952015-05-22 15:42:17 -0600793 };
794
795 rtc_1: rtc@61 {
796 reg = <0x61>;
797 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700798 sandbox,emul = <&emul1>;
799 };
800
801 i2c_emul: emul {
802 reg = <0xff>;
803 compatible = "sandbox,i2c-emul-parent";
804 emul_eeprom: emul-eeprom {
805 compatible = "sandbox,i2c-eeprom";
806 sandbox,filename = "i2c.bin";
807 sandbox,size = <256>;
808 };
809 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700810 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700811 };
812 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700813 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600814 };
815 };
816
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200817 sandbox_pmic: sandbox_pmic {
818 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700819 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200820 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200821
822 mc34708: pmic@41 {
823 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700824 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200825 };
Simon Glass7df766e2014-12-10 08:55:55 -0700826 };
827
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100828 bootcount@0 {
829 compatible = "u-boot,bootcount-rtc";
830 rtc = <&rtc_1>;
831 offset = <0x13>;
832 };
833
Michal Simek4f18f922020-05-28 11:48:55 +0200834 bootcount {
835 compatible = "u-boot,bootcount-i2c-eeprom";
836 i2c-eeprom = <&bootcount_i2c>;
837 };
838
Nandor Han88895812021-06-10 15:40:38 +0300839 bootcount_4@0 {
840 compatible = "u-boot,bootcount-syscon";
841 syscon = <&syscon0>;
842 reg = <0x0 0x04>, <0x0 0x04>;
843 reg-names = "syscon_reg", "offset";
844 };
845
846 bootcount_2@0 {
847 compatible = "u-boot,bootcount-syscon";
848 syscon = <&syscon0>;
849 reg = <0x0 0x04>, <0x0 0x02> ;
850 reg-names = "syscon_reg", "offset";
851 };
852
Marek Szyprowskiad398592021-02-18 11:33:18 +0100853 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100854 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100855 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100856 vdd-supply = <&buck2>;
857 vss-microvolts = <0>;
858 };
859
Mark Kettenis67748ee2021-10-23 16:58:02 +0200860 iommu: iommu@0 {
861 compatible = "sandbox,iommu";
862 #iommu-cells = <0>;
863 };
864
Simon Glass515dcff2020-02-06 09:55:00 -0700865 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700866 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700867 interrupt-controller;
868 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700869 };
870
Simon Glass90b6fef2016-01-18 19:52:26 -0700871 lcd {
872 u-boot,dm-pre-reloc;
873 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200874 pinctrl-names = "default";
875 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700876 xres = <1366>;
877 yres = <768>;
878 };
879
Simon Glassd783eb32015-07-06 12:54:34 -0600880 leds {
881 compatible = "gpio-leds";
882
883 iracibble {
884 gpios = <&gpio_a 1 0>;
885 label = "sandbox:red";
886 };
887
888 martinet {
889 gpios = <&gpio_a 2 0>;
890 label = "sandbox:green";
891 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200892
893 default_on {
894 gpios = <&gpio_a 5 0>;
895 label = "sandbox:default_on";
896 default-state = "on";
897 };
898
899 default_off {
900 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400901 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200902 default-state = "off";
903 };
Simon Glassd783eb32015-07-06 12:54:34 -0600904 };
905
Paul Doelle709f0372022-07-04 09:00:25 +0000906 wdt-gpio-toggle {
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200907 gpios = <&gpio_a 7 0>;
908 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200909 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +0000910 hw_algo = "toggle";
911 always-running;
912 };
913
914 wdt-gpio-level {
915 gpios = <&gpio_a 7 0>;
916 compatible = "linux,wdt-gpio";
917 hw_margin_ms = <100>;
918 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200919 always-running;
920 };
921
Stephen Warren62f2c902016-05-16 17:41:37 -0600922 mbox: mbox {
923 compatible = "sandbox,mbox";
924 #mbox-cells = <1>;
925 };
926
927 mbox-test {
928 compatible = "sandbox,mbox-test";
929 mboxes = <&mbox 100>, <&mbox 1>;
930 mbox-names = "other", "test";
931 };
932
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900933 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200934 #address-cells = <1>;
935 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400936 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200937 cpu1: cpu@1 {
938 device_type = "cpu";
939 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400940 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900941 compatible = "sandbox,cpu_sandbox";
942 u-boot,dm-pre-reloc;
943 };
Mario Sixdea5df72018-08-06 10:23:44 +0200944
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200945 cpu2: cpu@2 {
946 device_type = "cpu";
947 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900948 compatible = "sandbox,cpu_sandbox";
949 u-boot,dm-pre-reloc;
950 };
Mario Sixdea5df72018-08-06 10:23:44 +0200951
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200952 cpu3: cpu@3 {
953 device_type = "cpu";
954 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900955 compatible = "sandbox,cpu_sandbox";
956 u-boot,dm-pre-reloc;
957 };
Mario Sixdea5df72018-08-06 10:23:44 +0200958 };
959
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500960 chipid: chipid {
961 compatible = "sandbox,soc";
962 };
963
Simon Glassc953aaf2018-12-10 10:37:34 -0700964 i2s: i2s {
965 compatible = "sandbox,i2s";
966 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700967 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700968 };
969
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200970 nop-test_0 {
971 compatible = "sandbox,nop_sandbox1";
972 nop-test_1 {
973 compatible = "sandbox,nop_sandbox2";
974 bind = "True";
975 };
976 nop-test_2 {
977 compatible = "sandbox,nop_sandbox2";
978 bind = "False";
979 };
980 };
981
Roger Quadrosb0679a72022-10-20 16:30:46 +0300982 memory-controller {
983 compatible = "sandbox,memory";
984 };
985
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200986 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -0400987 #address-cells = <1>;
988 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200989 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -0400990
991 eth5_addr: mac-address@10 {
992 reg = <0x10 6>;
993 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200994 };
995
Simon Glasse4fef742017-04-23 20:02:07 -0600996 mmc2 {
997 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -0600998 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -0600999 };
1000
Simon Glassb255efc2022-04-24 23:31:24 -06001001 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001002 mmc1 {
1003 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001004 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001005 };
1006
Simon Glassb255efc2022-04-24 23:31:24 -06001007 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301008 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001009 compatible = "sandbox,mmc";
1010 };
1011
Simon Glassf1eba352022-10-20 18:23:20 -06001012 /* This is used for VBE VPL tests */
1013 mmc3 {
1014 status = "disabled";
1015 compatible = "sandbox,mmc";
1016 filename = "image.bin";
1017 non-removable;
1018 };
1019
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001020 /* This is used for bootstd bootmenu tests */
1021 mmc4 {
1022 status = "disabled";
1023 compatible = "sandbox,mmc";
1024 filename = "mmc4.img";
1025 };
1026
Simon Glass53a68b32019-02-16 20:24:50 -07001027 pch {
1028 compatible = "sandbox,pch";
1029 };
1030
Tom Rini4a3ca482020-02-11 12:41:23 -05001031 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001032 compatible = "sandbox,pci";
1033 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001034 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001035 #address-cells = <3>;
1036 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001037 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001038 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001039 iommu-map = <0x0010 &iommu 0 1>;
1040 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001041 pci@0,0 {
1042 compatible = "pci-generic";
1043 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001044 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001045 };
Alex Margineanf1274432019-06-07 11:24:24 +03001046 pci@1,0 {
1047 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001048 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
1049 reg = <0x02000814 0 0 0 0
1050 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001051 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001052 };
Simon Glass937bb472019-12-06 21:41:57 -07001053 p2sb-pci@2,0 {
1054 compatible = "sandbox,p2sb";
1055 reg = <0x02001010 0 0 0 0>;
1056 sandbox,emul = <&p2sb_emul>;
1057
1058 adder {
1059 intel,p2sb-port-id = <3>;
1060 compatible = "sandbox,adder";
1061 };
1062 };
Simon Glass8c501022019-12-06 21:41:54 -07001063 pci@1e,0 {
1064 compatible = "sandbox,pmc";
1065 reg = <0xf000 0 0 0 0>;
1066 sandbox,emul = <&pmc_emul1e>;
1067 acpi-base = <0x400>;
1068 gpe0-dwx-mask = <0xf>;
1069 gpe0-dwx-shift-base = <4>;
1070 gpe0-dw = <6 7 9>;
1071 gpe0-sts = <0x20>;
1072 gpe0-en = <0x30>;
1073 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001074 pci@1f,0 {
1075 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001076 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
1077 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001078 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001079 };
1080 };
1081
Simon Glassb98ba4c2019-09-25 08:56:10 -06001082 pci-emul0 {
1083 compatible = "sandbox,pci-emul-parent";
1084 swap_case_emul0_0: emul0@0,0 {
1085 compatible = "sandbox,swap-case";
1086 };
1087 swap_case_emul0_1: emul0@1,0 {
1088 compatible = "sandbox,swap-case";
1089 use-ea;
1090 };
1091 swap_case_emul0_1f: emul0@1f,0 {
1092 compatible = "sandbox,swap-case";
1093 };
Simon Glass937bb472019-12-06 21:41:57 -07001094 p2sb_emul: emul@2,0 {
1095 compatible = "sandbox,p2sb-emul";
1096 };
Simon Glass8c501022019-12-06 21:41:54 -07001097 pmc_emul1e: emul@1e,0 {
1098 compatible = "sandbox,pmc-emul";
1099 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001100 };
1101
Tom Rini4a3ca482020-02-11 12:41:23 -05001102 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001103 compatible = "sandbox,pci";
1104 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001105 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001106 #address-cells = <3>;
1107 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001108 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001109 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001110 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001111 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001112 0x0c 0x00 0x1234 0x5678
1113 0x10 0x00 0x1234 0x5678>;
1114 pci@10,0 {
1115 reg = <0x8000 0 0 0 0>;
1116 };
Bin Meng408e5902018-08-03 01:14:41 -07001117 };
1118
Tom Rini4a3ca482020-02-11 12:41:23 -05001119 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001120 compatible = "sandbox,pci";
1121 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001122 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001123 #address-cells = <3>;
1124 #size-cells = <2>;
1125 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1126 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1127 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1128 pci@1f,0 {
1129 compatible = "pci-generic";
1130 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001131 sandbox,emul = <&swap_case_emul2_1f>;
1132 };
1133 };
1134
1135 pci-emul2 {
1136 compatible = "sandbox,pci-emul-parent";
1137 swap_case_emul2_1f: emul2@1f,0 {
1138 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001139 };
1140 };
1141
Ramon Friedc64f19b2019-04-27 11:15:23 +03001142 pci_ep: pci_ep {
1143 compatible = "sandbox,pci_ep";
1144 };
1145
Simon Glass9c433fe2017-04-23 20:10:44 -06001146 probing {
1147 compatible = "simple-bus";
1148 test1 {
1149 compatible = "denx,u-boot-probe-test";
1150 };
1151
1152 test2 {
1153 compatible = "denx,u-boot-probe-test";
1154 };
1155
1156 test3 {
1157 compatible = "denx,u-boot-probe-test";
1158 };
1159
1160 test4 {
1161 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001162 first-syscon = <&syscon0>;
1163 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001164 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001165 };
1166 };
1167
Stephen Warren92c67fa2016-07-13 13:45:31 -06001168 pwrdom: power-domain {
1169 compatible = "sandbox,power-domain";
1170 #power-domain-cells = <1>;
1171 };
1172
1173 power-domain-test {
1174 compatible = "sandbox,power-domain-test";
1175 power-domains = <&pwrdom 2>;
1176 };
1177
Simon Glass5620cf82018-10-01 12:22:40 -06001178 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001179 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001180 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001181 pinctrl-names = "default";
1182 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001183 };
1184
1185 pwm2 {
1186 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001187 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001188 };
1189
Simon Glass3d355e62015-07-06 12:54:31 -06001190 ram {
1191 compatible = "sandbox,ram";
1192 };
1193
Simon Glassd860f222015-07-06 12:54:29 -06001194 reset@0 {
1195 compatible = "sandbox,warm-reset";
Michal Suchanek76874302022-10-10 20:29:39 +02001196 u-boot,dm-pre-proper;
Simon Glassd860f222015-07-06 12:54:29 -06001197 };
1198
1199 reset@1 {
1200 compatible = "sandbox,reset";
Michal Suchanek76874302022-10-10 20:29:39 +02001201 u-boot,dm-pre-proper;
Simon Glassd860f222015-07-06 12:54:29 -06001202 };
1203
Stephen Warren6488e642016-06-17 09:43:59 -06001204 resetc: reset-ctl {
1205 compatible = "sandbox,reset-ctl";
1206 #reset-cells = <1>;
1207 };
1208
1209 reset-ctl-test {
1210 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001211 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1212 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001213 };
1214
Sughosh Ganu23e37512019-12-28 23:58:31 +05301215 rng {
1216 compatible = "sandbox,sandbox-rng";
1217 };
1218
Nishanth Menonedf85812015-09-17 15:42:41 -05001219 rproc_1: rproc@1 {
1220 compatible = "sandbox,test-processor";
1221 remoteproc-name = "remoteproc-test-dev1";
1222 };
1223
1224 rproc_2: rproc@2 {
1225 compatible = "sandbox,test-processor";
1226 internal-memory-mapped;
1227 remoteproc-name = "remoteproc-test-dev2";
1228 };
1229
Simon Glass5620cf82018-10-01 12:22:40 -06001230 panel {
1231 compatible = "simple-panel";
1232 backlight = <&backlight 0 100>;
1233 };
1234
Simon Glass509f32e2022-09-21 16:21:47 +02001235 scsi {
1236 compatible = "sandbox,scsi";
1237 sandbox,filepath = "scsi.img";
1238 };
1239
Ramon Fried26ed32e2018-07-02 02:57:59 +03001240 smem@0 {
1241 compatible = "sandbox,smem";
1242 };
1243
Simon Glass76072ac2018-12-10 10:37:36 -07001244 sound {
1245 compatible = "sandbox,sound";
1246 cpu {
1247 sound-dai = <&i2s 0>;
1248 };
1249
1250 codec {
1251 sound-dai = <&audio 0>;
1252 };
1253 };
1254
Simon Glass25348a42014-10-13 23:42:11 -06001255 spi@0 {
1256 #address-cells = <1>;
1257 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001258 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001259 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001260 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001261 pinctrl-names = "default";
1262 pinctrl-0 = <&pinmux_spi0_pins>;
1263
Simon Glass25348a42014-10-13 23:42:11 -06001264 spi.bin@0 {
1265 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001266 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001267 spi-max-frequency = <40000000>;
1268 sandbox,filename = "spi.bin";
1269 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001270 spi.bin@1 {
1271 reg = <1>;
1272 compatible = "spansion,m25p16", "jedec,spi-nor";
1273 spi-max-frequency = <50000000>;
1274 sandbox,filename = "spi.bin";
1275 spi-cpol;
1276 spi-cpha;
1277 };
Simon Glass25348a42014-10-13 23:42:11 -06001278 };
1279
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001280 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001281 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001282 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001283 };
1284
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001285 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001286 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001287 reg = <0x20 5
1288 0x28 6
1289 0x30 7
1290 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001291 };
1292
Patrick Delaunayee010432019-03-07 09:57:13 +01001293 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001294 compatible = "simple-mfd", "syscon";
1295 reg = <0x40 5
1296 0x48 6
1297 0x50 7
1298 0x58 8>;
1299 };
1300
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301301 syscon3: syscon@3 {
1302 compatible = "simple-mfd", "syscon";
1303 reg = <0x000100 0x10>;
1304
1305 muxcontroller0: a-mux-controller {
1306 compatible = "mmio-mux";
1307 #mux-control-cells = <1>;
1308
1309 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1310 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1311 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1312 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1313 u-boot,mux-autoprobe;
1314 };
1315 };
1316
1317 muxcontroller1: emul-mux-controller {
1318 compatible = "mux-emul";
1319 #mux-control-cells = <0>;
1320 u-boot,mux-autoprobe;
1321 idle-state = <0xabcd>;
1322 };
1323
Simon Glass791a17f2020-12-16 21:20:27 -07001324 testfdtm0 {
1325 compatible = "denx,u-boot-fdtm-test";
1326 };
1327
1328 testfdtm1: testfdtm1 {
1329 compatible = "denx,u-boot-fdtm-test";
1330 };
1331
1332 testfdtm2 {
1333 compatible = "denx,u-boot-fdtm-test";
1334 };
1335
Sean Anderson79d3bba2020-09-28 10:52:23 -04001336 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001337 compatible = "sandbox,timer";
1338 clock-frequency = <1000000>;
1339 };
1340
Sean Anderson79d3bba2020-09-28 10:52:23 -04001341 timer@1 {
1342 compatible = "sandbox,timer";
1343 sandbox,timebase-frequency-fallback;
1344 };
1345
Miquel Raynal80938c12018-05-15 11:57:27 +02001346 tpm2 {
1347 compatible = "sandbox,tpm2";
1348 };
1349
Simon Glass5b968632015-05-22 15:42:15 -06001350 uart0: serial {
1351 compatible = "sandbox,serial";
1352 u-boot,dm-pre-reloc;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001353 pinctrl-names = "default";
1354 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001355 };
1356
Simon Glass31680482015-03-25 12:23:05 -06001357 usb_0: usb@0 {
1358 compatible = "sandbox,usb";
1359 status = "disabled";
1360 hub {
1361 compatible = "sandbox,usb-hub";
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1364 flash-stick {
1365 reg = <0>;
1366 compatible = "sandbox,usb-flash";
1367 };
1368 };
1369 };
1370
1371 usb_1: usb@1 {
1372 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001373 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001374 hub {
1375 compatible = "usb-hub";
1376 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001377 #address-cells = <1>;
1378 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001379 hub-emul {
1380 compatible = "sandbox,usb-hub";
1381 #address-cells = <1>;
1382 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001383 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001384 reg = <0>;
1385 compatible = "sandbox,usb-flash";
1386 sandbox,filepath = "testflash.bin";
1387 };
1388
Simon Glass4700fe52015-11-08 23:48:01 -07001389 flash-stick@1 {
1390 reg = <1>;
1391 compatible = "sandbox,usb-flash";
1392 sandbox,filepath = "testflash1.bin";
1393 };
1394
1395 flash-stick@2 {
1396 reg = <2>;
1397 compatible = "sandbox,usb-flash";
1398 sandbox,filepath = "testflash2.bin";
1399 };
1400
Simon Glassc0ccc722015-11-08 23:48:08 -07001401 keyb@3 {
1402 reg = <3>;
1403 compatible = "sandbox,usb-keyb";
1404 };
1405
Simon Glass31680482015-03-25 12:23:05 -06001406 };
Michael Walle7c961322020-06-02 01:47:07 +02001407
1408 usbstor@1 {
1409 reg = <1>;
1410 };
1411 usbstor@3 {
1412 reg = <3>;
1413 };
Simon Glass31680482015-03-25 12:23:05 -06001414 };
1415 };
1416
1417 usb_2: usb@2 {
1418 compatible = "sandbox,usb";
1419 status = "disabled";
1420 };
1421
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001422 spmi: spmi@0 {
1423 compatible = "sandbox,spmi";
1424 #address-cells = <0x1>;
1425 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001426 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001427 pm8916@0 {
1428 compatible = "qcom,spmi-pmic";
1429 reg = <0x0 0x1>;
1430 #address-cells = <0x1>;
1431 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001432 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001433
1434 spmi_gpios: gpios@c000 {
1435 compatible = "qcom,pm8916-gpio";
1436 reg = <0xc000 0x400>;
1437 gpio-controller;
1438 gpio-count = <4>;
1439 #gpio-cells = <2>;
1440 gpio-bank-name="spmi";
1441 };
1442 };
1443 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001444
1445 wdt0: wdt@0 {
1446 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001447 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001448 };
Rob Clarka471b672018-01-10 11:33:30 +01001449
Mario Six95922152018-08-09 14:51:19 +02001450 axi: axi@0 {
1451 compatible = "sandbox,axi";
1452 #address-cells = <0x1>;
1453 #size-cells = <0x1>;
1454 store@0 {
1455 compatible = "sandbox,sandbox_store";
1456 reg = <0x0 0x400>;
1457 };
1458 };
1459
Rob Clarka471b672018-01-10 11:33:30 +01001460 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001461 #address-cells = <1>;
1462 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001463 setting = "sunrise ohoka";
1464 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001465 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001466 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001467 chosen-test {
1468 compatible = "denx,u-boot-fdt-test";
1469 reg = <9 1>;
1470 };
1471 };
Mario Six35616ef2018-03-12 14:53:33 +01001472
1473 translation-test@8000 {
1474 compatible = "simple-bus";
1475 reg = <0x8000 0x4000>;
1476
1477 #address-cells = <0x2>;
1478 #size-cells = <0x1>;
1479
1480 ranges = <0 0x0 0x8000 0x1000
1481 1 0x100 0x9000 0x1000
1482 2 0x200 0xA000 0x1000
1483 3 0x300 0xB000 0x1000
1484 >;
1485
Fabien Dessenne22236e02019-05-31 15:11:30 +02001486 dma-ranges = <0 0x000 0x10000000 0x1000
1487 1 0x100 0x20000000 0x1000
1488 >;
1489
Mario Six35616ef2018-03-12 14:53:33 +01001490 dev@0,0 {
1491 compatible = "denx,u-boot-fdt-dummy";
1492 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojasa3181152018-12-03 19:37:09 +01001493 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001494 };
1495
1496 dev@1,100 {
1497 compatible = "denx,u-boot-fdt-dummy";
1498 reg = <1 0x100 0x1000>;
1499
1500 };
1501
1502 dev@2,200 {
1503 compatible = "denx,u-boot-fdt-dummy";
1504 reg = <2 0x200 0x1000>;
1505 };
1506
1507
1508 noxlatebus@3,300 {
1509 compatible = "simple-bus";
1510 reg = <3 0x300 0x1000>;
1511
1512 #address-cells = <0x1>;
1513 #size-cells = <0x0>;
1514
1515 dev@42 {
1516 compatible = "denx,u-boot-fdt-dummy";
1517 reg = <0x42>;
1518 };
1519 };
1520 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001521
1522 osd {
1523 compatible = "sandbox,sandbox_osd";
1524 };
Tom Rinib93eea72018-09-30 18:16:51 -04001525
Jens Wiklander86afaa62018-09-25 16:40:16 +02001526 sandbox_tee {
1527 compatible = "sandbox,tee";
1528 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001529
1530 sandbox_virtio1 {
1531 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001532 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001533 };
1534
1535 sandbox_virtio2 {
1536 compatible = "sandbox,virtio2";
1537 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001538
Simon Glass8de5a542023-01-17 10:47:51 -07001539 sandbox-virtio-blk {
1540 compatible = "sandbox,virtio1";
1541 virtio-type = <2>; /* block */
1542 };
1543
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001544 sandbox_scmi {
1545 compatible = "sandbox,scmi-devices";
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001546 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001547 resets = <&reset_scmi 3>;
1548 regul0-supply = <&regul0_scmi>;
1549 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001550 };
1551
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001552 pinctrl {
1553 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001554
Sean Anderson3438e3b2020-09-14 11:01:57 -04001555 pinctrl-names = "default", "alternate";
1556 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1557 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001558
Sean Anderson3438e3b2020-09-14 11:01:57 -04001559 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001560 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001561 pins = "P5";
1562 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001563 bias-pull-up;
1564 input-disable;
1565 };
1566 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001567 pins = "P6";
1568 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001569 output-high;
1570 drive-open-drain;
1571 };
1572 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001573 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001574 bias-pull-down;
1575 input-enable;
1576 };
1577 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001578 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001579 bias-disable;
1580 };
1581 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001582
1583 pinctrl_i2c: i2c {
1584 groups {
1585 groups = "I2C_UART";
1586 function = "I2C";
1587 };
1588
1589 pins {
1590 pins = "P0", "P1";
1591 drive-open-drain;
1592 };
1593 };
1594
1595 pinctrl_i2s: i2s {
1596 groups = "SPI_I2S";
1597 function = "I2S";
1598 };
1599
1600 pinctrl_spi: spi {
1601 groups = "SPI_I2S";
1602 function = "SPI";
1603
1604 cs {
1605 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1606 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1607 };
1608 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001609 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001610
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001611 pinctrl-single-no-width {
1612 compatible = "pinctrl-single";
1613 reg = <0x0000 0x238>;
1614 #pinctrl-cells = <1>;
1615 pinctrl-single,function-mask = <0x7f>;
1616 };
1617
1618 pinctrl-single-pins {
1619 compatible = "pinctrl-single";
1620 reg = <0x0000 0x238>;
1621 #pinctrl-cells = <1>;
1622 pinctrl-single,register-width = <32>;
1623 pinctrl-single,function-mask = <0x7f>;
1624
1625 pinmux_pwm_pins: pinmux_pwm_pins {
1626 pinctrl-single,pins = < 0x48 0x06 >;
1627 };
1628
1629 pinmux_spi0_pins: pinmux_spi0_pins {
1630 pinctrl-single,pins = <
1631 0x190 0x0c
1632 0x194 0x0c
1633 0x198 0x23
1634 0x19c 0x0c
1635 >;
1636 };
1637
1638 pinmux_uart0_pins: pinmux_uart0_pins {
1639 pinctrl-single,pins = <
1640 0x70 0x30
1641 0x74 0x00
1642 >;
1643 };
1644 };
1645
1646 pinctrl-single-bits {
1647 compatible = "pinctrl-single";
1648 reg = <0x0000 0x50>;
1649 #pinctrl-cells = <2>;
1650 pinctrl-single,bit-per-mux;
1651 pinctrl-single,register-width = <32>;
1652 pinctrl-single,function-mask = <0xf>;
1653
1654 pinmux_i2c0_pins: pinmux_i2c0_pins {
1655 pinctrl-single,bits = <
1656 0x10 0x00002200 0x0000ff00
1657 >;
1658 };
1659
1660 pinmux_lcd_pins: pinmux_lcd_pins {
1661 pinctrl-single,bits = <
1662 0x40 0x22222200 0xffffff00
1663 0x44 0x22222222 0xffffffff
1664 0x48 0x00000022 0x000000ff
1665 0x48 0x02000000 0x0f000000
1666 0x4c 0x02000022 0x0f0000ff
1667 >;
1668 };
1669 };
1670
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001671 hwspinlock@0 {
1672 compatible = "sandbox,hwspinlock";
1673 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001674
1675 dma: dma {
1676 compatible = "sandbox,dma";
1677 #dma-cells = <1>;
1678
1679 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1680 dma-names = "m2m", "tx0", "rx0";
1681 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001682
Alex Marginean0649be52019-07-12 10:13:53 +03001683 /*
1684 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1685 * end of the test. If parent mdio is removed first, clean-up of the
1686 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1687 * active at the end of the test. That it turn doesn't allow the mdio
1688 * class to be destroyed, triggering an error.
1689 */
1690 mdio-mux-test {
1691 compatible = "sandbox,mdio-mux";
1692 #address-cells = <1>;
1693 #size-cells = <0>;
1694 mdio-parent-bus = <&mdio>;
1695
1696 mdio-ch-test@0 {
1697 reg = <0>;
1698 };
1699 mdio-ch-test@1 {
1700 reg = <1>;
1701 };
1702 };
1703
1704 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001705 compatible = "sandbox,mdio";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +02001706 #address-cells = <1>;
1707 #size-cells = <0>;
1708
1709 ethphy1: ethernet-phy@1 {
1710 reg = <1>;
1711 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001712 };
Sean Andersonb7860542020-06-24 06:41:12 -04001713
1714 pm-bus-test {
1715 compatible = "simple-pm-bus";
1716 clocks = <&clk_sandbox 4>;
1717 power-domains = <&pwrdom 1>;
1718 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001719
1720 resetc2: syscon-reset {
1721 compatible = "syscon-reset";
1722 #reset-cells = <1>;
1723 regmap = <&syscon0>;
1724 offset = <1>;
1725 mask = <0x27FFFFFF>;
1726 assert-high = <0>;
1727 };
1728
1729 syscon-reset-test {
1730 compatible = "sandbox,misc_sandbox";
1731 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1732 reset-names = "valid", "no_mask", "out_of_range";
1733 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301734
Simon Glass458b66a2020-11-05 06:32:05 -07001735 sysinfo {
1736 compatible = "sandbox,sysinfo-sandbox";
1737 };
1738
Sean Anderson1c830672021-04-20 10:50:58 -04001739 sysinfo-gpio {
1740 compatible = "gpio-sysinfo";
1741 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1742 revisions = <19>, <5>;
1743 names = "rev_a", "foo";
1744 };
1745
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301746 some_regmapped-bus {
1747 #address-cells = <0x1>;
1748 #size-cells = <0x1>;
1749
1750 ranges = <0x0 0x0 0x10>;
1751 compatible = "simple-bus";
1752
1753 regmap-test_0 {
1754 reg = <0 0x10>;
1755 compatible = "sandbox,regmap_test";
1756 };
1757 };
Robert Marko9cf87122022-09-06 13:30:35 +02001758
1759 thermal {
1760 compatible = "sandbox,thermal";
1761 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05301762
1763 fwu-mdata {
1764 compatible = "u-boot,fwu-mdata-gpt";
1765 fwu-mdata-store = <&mmc0>;
1766 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001767};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001768
1769#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001770#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06001771
1772#ifdef CONFIG_SANDBOX_VPL
1773#include "sandbox_vpl.dtsi"
1774#endif