blob: 15b2792e619b01c09ffc6aa12a7c89d30a033c97 [file] [log] [blame]
Stefan Roese65da15e2018-09-05 15:12:35 +02001menu "MediaTek MIPS platforms"
developer89f051b2019-04-30 11:13:58 +08002 depends on ARCH_MTMIPS
Stefan Roese65da15e2018-09-05 15:12:35 +02003
Guillaume La Roquea24e1cf2021-09-10 10:21:06 +02004config SYS_VENDOR
5 default "mediatek" if BOARD_MT7628_RFB || BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB
6
Stefan Roese65da15e2018-09-05 15:12:35 +02007config SYS_MALLOC_F_LEN
8 default 0x1000
9
10config SYS_SOC
developer18ec8d62020-11-12 16:35:52 +080011 default "mt7620" if SOC_MT7620
developer2fddd722022-05-20 11:22:21 +080012 default "mt7621" if SOC_MT7621
developer89f051b2019-04-30 11:13:58 +080013 default "mt7628" if SOC_MT7628
Stefan Roese65da15e2018-09-05 15:12:35 +020014
developer26f763e2020-04-21 09:28:26 +020015config SYS_DCACHE_SIZE
16 default 32768
17
18config SYS_DCACHE_LINE_SIZE
19 default 32
20
21config SYS_ICACHE_SIZE
developer2fddd722022-05-20 11:22:21 +080022 default 65536 if SOC_MT7620 || SOC_MT7628
23 default 32768 if SOC_MT7621
developer26f763e2020-04-21 09:28:26 +020024
25config SYS_ICACHE_LINE_SIZE
26 default 32
27
developer2fddd722022-05-20 11:22:21 +080028config SYS_SCACHE_LINE_SIZE
29 default 32 if SOC_MT7621
30
Simon Glass72cc5382022-10-20 18:22:39 -060031config TEXT_BASE
developer2fddd722022-05-20 11:22:21 +080032 default 0x9c000000 if !SPL && !SOC_MT7621
33 default 0x80200000 if SPL || SOC_MT7621
developer19d572e2020-04-21 09:28:47 +020034
35config SPL_TEXT_BASE
developer2fddd722022-05-20 11:22:21 +080036 default 0x9c000000 if !SOC_MT7621
37 default 0x80100000 if SOC_MT7621
38
39config SPL_SIZE_LIMIT
40 default 0x30000 if SOC_MT7621
41
42config TPL_TEXT_BASE
43 default 0xbfc00000 if SOC_MT7621
44
45config TPL_MAX_SIZE
46 default 4096 if SOC_MT7621
developer29b37c52020-04-21 09:28:34 +020047
developer19d572e2020-04-21 09:28:47 +020048config SPL_PAYLOAD
49 default "u-boot-lzma.img" if SPL_LZMA
50
51config BUILD_TARGET
developer2fddd722022-05-20 11:22:21 +080052 default "u-boot-with-spl.bin" if SPL && !SOC_MT7621
53 default "u-boot-lzma.img" if SOC_MT7621
developer18ec8d62020-11-12 16:35:52 +080054 default "u-boot.bin"
developer19d572e2020-04-21 09:28:47 +020055
developer2fddd722022-05-20 11:22:21 +080056config MAX_MEM_SIZE
57 int
58 default 256 if SOC_MT7620 || SOC_MT7628
59 default 512 if SOC_MT7621
60
Stefan Roese65da15e2018-09-05 15:12:35 +020061choice
62 prompt "MediaTek MIPS SoC select"
63
developer18ec8d62020-11-12 16:35:52 +080064config SOC_MT7620
65 bool "MT7620"
Tom Rini3ef67ae2021-08-26 11:47:59 -040066 select SYS_CACHE_SHIFT_5
developer18ec8d62020-11-12 16:35:52 +080067 select SYS_MIPS_CACHE_INIT_RAM_LOAD
68 select PINCTRL_MT7620
69 select MT7620_SERIAL
70 select MISC
71 select SPL_SEPARATE_BSS if SPL
72 select SPL_LOADER_SUPPORT if SPL
73 select SPL_OF_CONTROL if SPL_DM
74 select SPL_OF_PLATDATA if SPL_DM
75 select SPL_DM_SERIAL if SPL_DM
76 help
77 This supports MediaTek MT7620.
78
developer2fddd722022-05-20 11:22:21 +080079config SOC_MT7621
80 bool "MT7621"
81 select MIPS_CM
82 select MIPS_L2_CACHE
83 select SYS_CACHE_SHIFT_5
84 select SYS_MIPS_CACHE_INIT_RAM_LOAD
85 select PINCTRL_MT7621
86 select MTK_SERIAL
87 select REGMAP
88 select SYSCON
89 select BINMAN
90 select SUPPORT_TPL
91 select SPL_LOADER_SUPPORT if SPL
92 select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL
93 help
94 This supports MediaTek MT7621.
95
developer89f051b2019-04-30 11:13:58 +080096config SOC_MT7628
97 bool "MT7628"
Tom Rini3ef67ae2021-08-26 11:47:59 -040098 select SYS_CACHE_SHIFT_5
developer29b37c52020-04-21 09:28:34 +020099 select MIPS_INIT_STACK_IN_SRAM
100 select MIPS_SRAM_INIT
101 select SYS_MIPS_CACHE_INIT_RAM_LOAD
developer591826e2019-09-25 17:45:43 +0800102 select PINCTRL_MT7628
103 select MTK_SERIAL
developer93f74002020-11-12 16:35:28 +0800104 select SYSRESET
developer3b3015f2020-04-21 09:28:30 +0200105 select SYSRESET_RESETCTL
developer19d572e2020-04-21 09:28:47 +0200106 select SPL_SEPARATE_BSS if SPL
107 select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL
108 select SPL_LOADER_SUPPORT if SPL
109 select SPL_OF_CONTROL if SPL_DM
110 select SPL_SIMPLE_BUS if SPL_DM
111 select SPL_DM_SERIAL if SPL_DM
Simon Glassf4d60392021-08-08 12:20:12 -0600112 select SPL_CLK if SPL_DM && SPL_SERIAL
developer19d572e2020-04-21 09:28:47 +0200113 select SPL_SYSRESET if SPL_DM
114 select SPL_OF_LIBFDT if SPL_OF_CONTROL
Stefan Roese65da15e2018-09-05 15:12:35 +0200115 help
developer89f051b2019-04-30 11:13:58 +0800116 This supports MediaTek MT7628/MT7688.
Stefan Roese65da15e2018-09-05 15:12:35 +0200117
118endchoice
119
developer18ec8d62020-11-12 16:35:52 +0800120source "arch/mips/mach-mtmips/mt7620/Kconfig"
developer2fddd722022-05-20 11:22:21 +0800121source "arch/mips/mach-mtmips/mt7621/Kconfig"
developer37e34ba2020-11-12 16:35:23 +0800122source "arch/mips/mach-mtmips/mt7628/Kconfig"
Stefan Roese2052a932018-08-16 15:27:30 +0200123
Stefan Roese65da15e2018-09-05 15:12:35 +0200124endmenu