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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
David Feng3b5458c2013-12-14 11:47:37 +08002/*
3 * Configuration for Versatile Express. Parts were derived from other ARM
4 * configurations.
David Feng3b5458c2013-12-14 11:47:37 +08005 */
6
Peter Hoyes32860372021-11-11 09:26:00 +00007#ifndef __VEXPRESS_AEMV8_H
8#define __VEXPRESS_AEMV8_H
David Feng3b5458c2013-12-14 11:47:37 +08009
Peter Hoyes16fff302021-11-11 09:26:01 +000010#include <linux/stringify.h>
11
David Feng3b5458c2013-12-14 11:47:37 +080012/* Link Definitions */
Peter Hoyes32860372021-11-11 09:26:00 +000013#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
14#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
15#else
Darwin Rambod32d4112014-06-09 11:12:59 -070016/* ATF loads u-boot here for BASE_FVP model */
Darwin Rambod32d4112014-06-09 11:12:59 -070017#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
Darwin Rambod32d4112014-06-09 11:12:59 -070018#endif
David Feng3b5458c2013-12-14 11:47:37 +080019
Ryan Harkin642aa2c2015-10-09 17:18:01 +010020#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
21
David Feng3b5458c2013-12-14 11:47:37 +080022/* CS register bases for the original memory map. */
Peter Hoyes3ca0ea02022-03-04 16:30:18 +000023#ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP
24#define V2M_DRAM_BASE 0x00000000
25#define V2M_PA_BASE 0x80000000
26#else
Andre Przywara87de4b72022-03-04 16:30:16 +000027#define V2M_DRAM_BASE 0x80000000
Peter Hoyes32860372021-11-11 09:26:00 +000028#define V2M_PA_BASE 0x00000000
Peter Hoyes3ca0ea02022-03-04 16:30:18 +000029#endif
Peter Hoyes32860372021-11-11 09:26:00 +000030
31#define V2M_PA_CS0 (V2M_PA_BASE + 0x00000000)
32#define V2M_PA_CS1 (V2M_PA_BASE + 0x14000000)
33#define V2M_PA_CS2 (V2M_PA_BASE + 0x18000000)
34#define V2M_PA_CS3 (V2M_PA_BASE + 0x1c000000)
35#define V2M_PA_CS4 (V2M_PA_BASE + 0x0c000000)
36#define V2M_PA_CS5 (V2M_PA_BASE + 0x10000000)
David Feng3b5458c2013-12-14 11:47:37 +080037
38#define V2M_PERIPH_OFFSET(x) (x << 16)
39#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
40#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
41#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
42
David Feng3b5458c2013-12-14 11:47:37 +080043/* Common peripherals relative to CS7. */
44#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
45#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
46#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
47#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
48
Linus Walleijc5822502015-01-23 14:41:10 +010049#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
50#define V2M_UART0 0x7ff80000
51#define V2M_UART1 0x7ff70000
52#else /* Not Juno */
David Feng3b5458c2013-12-14 11:47:37 +080053#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
54#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
55#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
56#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
Linus Walleijc5822502015-01-23 14:41:10 +010057#endif
David Feng3b5458c2013-12-14 11:47:37 +080058
59#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
60
61#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
62#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
63
64#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
65#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
66
67#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
68
69#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
70
71/* System register offsets. */
72#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
73#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
74#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
75
David Feng3b5458c2013-12-14 11:47:37 +080076/* Generic Interrupt Controller Definitions */
David Feng79bbde02014-03-14 14:26:27 +080077#ifdef CONFIG_GICV3
Peter Hoyes32860372021-11-11 09:26:00 +000078#define GICD_BASE (V2M_PA_BASE + 0x2f000000)
79#define GICR_BASE (V2M_PA_BASE + 0x2f100000)
David Feng79bbde02014-03-14 14:26:27 +080080#else
Darwin Rambod32d4112014-06-09 11:12:59 -070081
Peter Hoyes32860372021-11-11 09:26:00 +000082#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Linus Walleijc5822502015-01-23 14:41:10 +010083#define GICD_BASE (0x2C010000)
84#define GICC_BASE (0x2C02f000)
Peter Hoyes32860372021-11-11 09:26:00 +000085#else
86#define GICD_BASE (V2M_PA_BASE + 0x2f000000)
87#define GICC_BASE (V2M_PA_BASE + 0x2c000000)
David Feng79bbde02014-03-14 14:26:27 +080088#endif
Linus Walleija90caa32015-03-23 11:06:14 +010089#endif /* !CONFIG_GICV3 */
David Feng3b5458c2013-12-14 11:47:37 +080090
Peter Hoyes8194cda2021-11-11 09:26:03 +000091#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && !defined(CONFIG_DM_ETH)
92/* The Vexpress64 BASE_FVP simulator uses SMSC91C111 */
Bhupesh Sharmae997f352014-01-16 09:47:40 -060093#define CONFIG_SMC91111 1
Peter Hoyes32860372021-11-11 09:26:00 +000094#define CONFIG_SMC91111_BASE (V2M_PA_BASE + 0x01A000000)
Linus Walleij48b47552015-02-17 11:35:25 +010095#endif
David Feng3b5458c2013-12-14 11:47:37 +080096
97/* PL011 Serial Configuration */
Linus Walleijc5822502015-01-23 14:41:10 +010098#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Andre Przywarad3457182020-04-27 19:18:00 +010099#define CONFIG_PL011_CLOCK 7372800
Linus Walleijc5822502015-01-23 14:41:10 +0100100#else
David Feng3b5458c2013-12-14 11:47:37 +0800101#define CONFIG_PL011_CLOCK 24000000
Linus Walleijc5822502015-01-23 14:41:10 +0100102#endif
David Feng3b5458c2013-12-14 11:47:37 +0800103
David Feng3b5458c2013-12-14 11:47:37 +0800104/* Physical Memory Map */
Andre Przywara87de4b72022-03-04 16:30:16 +0000105#define PHYS_SDRAM_1 (V2M_DRAM_BASE) /* SDRAM Bank #1 */
Linus Walleij0a38bfe2015-05-11 10:03:57 +0200106/* Top 16MB reserved for secure world use */
107#define DRAM_SEC_SIZE 0x01000000
108#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
109#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
110
Ryan Harkin98d2fff2015-11-18 10:39:07 +0000111#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Ryan Harkin98d2fff2015-11-18 10:39:07 +0000112#define PHYS_SDRAM_2 (0x880000000)
113#define PHYS_SDRAM_2_SIZE 0x180000000
Peter Hoyes32860372021-11-11 09:26:00 +0000114#elif CONFIG_NR_DRAM_BANKS == 2
Diego Sueiro7a02a1b2021-02-15 07:27:57 +0000115#define PHYS_SDRAM_2 (0x880000000)
116#define PHYS_SDRAM_2_SIZE 0x80000000
Ryan Harkin98d2fff2015-11-18 10:39:07 +0000117#endif
118
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000119/* Copy the kernel, initrd and FDT from NOR flash to DRAM memory and boot. */
Andre Przywarabe035312021-07-12 00:25:15 +0100120#define BOOTENV_DEV_AFS(devtypeu, devtypel, instance) \
121 "bootcmd_afs=" \
122 "afs load ${kernel_name} ${kernel_addr_r} ;"\
123 "if test $? -eq 1; then "\
124 " echo Loading ${kernel_alt_name} instead of ${kernel_name}; "\
125 " afs load ${kernel_alt_name} ${kernel_addr_r};"\
126 "fi ; "\
127 "afs load ${fdtfile} ${fdt_addr_r} ;"\
128 "if test $? -eq 1; then "\
129 " echo Loading ${fdt_alt_name} instead of ${fdtfile}; "\
130 " afs load ${fdt_alt_name} ${fdt_addr_r}; "\
131 "fi ; "\
132 "fdt addr ${fdt_addr_r}; fdt resize; " \
133 "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\
134 "then "\
135 " setenv ramdisk_param ${ramdisk_addr_r}; "\
136 "else "\
137 " setenv ramdisk_param -; "\
138 "fi ; " \
139 "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}\0"
140#define BOOTENV_DEV_NAME_AFS(devtypeu, devtypel, instance) "afs "
141
Andre Przywara019753a2022-03-04 16:30:14 +0000142/* Boot by executing a U-Boot script pre-loaded into DRAM. */
143#define BOOTENV_DEV_MEM(devtypeu, devtypel, instance) \
144 "bootcmd_mem= " \
145 "source ${scriptaddr}; " \
146 "if test $? -eq 1; then " \
147 " env import -t ${scriptaddr}; " \
148 " if test -n $uenvcmd; then " \
149 " echo Running uenvcmd ...; " \
150 " run uenvcmd; " \
151 " fi; " \
152 "fi\0"
153#define BOOTENV_DEV_NAME_MEM(devtypeu, devtypel, instance) "mem "
154
155#ifdef CONFIG_CMD_VIRTIO
156#define FUNC_VIRTIO(func) func(VIRTIO, virtio, 0)
157#else
158#define FUNC_VIRTIO(func)
159#endif
160
161/*
162 * Boot by loading an Android image, or kernel, initrd and FDT through
163 * semihosting into DRAM.
164 */
165#define BOOTENV_DEV_SMH(devtypeu, devtypel, instance) \
166 "bootcmd_smh= " \
Sean Anderson3e056ba2022-03-22 16:59:22 -0400167 "if load hostfs - ${boot_addr_r} ${boot_name}; then" \
Andre Przywara019753a2022-03-04 16:30:14 +0000168 " setenv bootargs;" \
169 " abootimg addr ${boot_addr_r};" \
170 " abootimg get dtb --index=0 fdt_addr_r;" \
171 " bootm ${boot_addr_r} ${boot_addr_r} ${fdt_addr_r};" \
172 "else" \
Sean Anderson3e056ba2022-03-22 16:59:22 -0400173 " if load hostfs - ${kernel_addr_r} ${kernel_name}; then" \
Andre Przywara019753a2022-03-04 16:30:14 +0000174 " setenv fdt_high 0xffffffffffffffff;" \
175 " setenv initrd_high 0xffffffffffffffff;" \
Sean Anderson3e056ba2022-03-22 16:59:22 -0400176 " load hostfs - ${fdt_addr_r} ${fdtfile};" \
177 " load hostfs - ${ramdisk_addr_r} ${ramdisk_name};" \
Andre Przywara019753a2022-03-04 16:30:14 +0000178 " fdt addr ${fdt_addr_r};" \
179 " fdt resize;" \
Sean Anderson3e056ba2022-03-22 16:59:22 -0400180 " fdt chosen ${ramdisk_addr_r} ${filesize};" \
Andre Przywara019753a2022-03-04 16:30:14 +0000181 " booti $kernel_addr_r - $fdt_addr_r;" \
182 " fi;" \
183 "fi\0"
184#define BOOTENV_DEV_NAME_SMH(devtypeu, devtypel, instance) "smh "
185
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000186/* Boot sources for distro boot and load addresses, per board */
187
188#ifdef CONFIG_TARGET_VEXPRESS64_JUNO /* Arm Juno board */
189
Andre Przywarabe035312021-07-12 00:25:15 +0100190#define BOOT_TARGET_DEVICES(func) \
191 func(USB, usb, 0) \
192 func(SATA, sata, 0) \
193 func(SATA, sata, 1) \
194 func(PXE, pxe, na) \
195 func(DHCP, dhcp, na) \
196 func(AFS, afs, na)
197
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000198#define VEXPRESS_KERNEL_ADDR 0x80080000
199#define VEXPRESS_PXEFILE_ADDR 0x8fb00000
200#define VEXPRESS_FDT_ADDR 0x8fc00000
201#define VEXPRESS_SCRIPT_ADDR 0x8fd00000
202#define VEXPRESS_RAMDISK_ADDR 0x8fe00000
Linus Walleijc39566a2015-04-05 01:48:32 +0200203
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000204#define EXTRA_ENV_NAMES \
205 "kernel_name=norkern\0" \
206 "kernel_alt_name=Image\0" \
207 "ramdisk_name=ramdisk.img\0" \
208 "fdtfile=board.dtb\0" \
209 "fdt_alt_name=juno\0"
Peter Hoyes16fff302021-11-11 09:26:01 +0000210
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000211#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP /* ARMv8-A base model */
Peter Hoyes16fff302021-11-11 09:26:01 +0000212
Andre Przywara019753a2022-03-04 16:30:14 +0000213#define BOOT_TARGET_DEVICES(func) \
214 func(SMH, smh, na) \
215 func(MEM, mem, na) \
216 FUNC_VIRTIO(func) \
217 func(PXE, pxe, na) \
218 func(DHCP, dhcp, na)
219
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000220#define VEXPRESS_KERNEL_ADDR 0x80080000
221#define VEXPRESS_PXEFILE_ADDR 0x8fa00000
222#define VEXPRESS_SCRIPT_ADDR 0x8fb00000
223#define VEXPRESS_FDT_ADDR 0x8fc00000
224#define VEXPRESS_BOOT_ADDR 0x8fd00000
225#define VEXPRESS_RAMDISK_ADDR 0x8fe00000
226
227#define EXTRA_ENV_NAMES \
228 "kernel_name=Image\0" \
229 "ramdisk_name=ramdisk.img\0" \
230 "fdtfile=devtree.dtb\0" \
231 "boot_name=boot.img\0" \
232 "boot_addr_r=" __stringify(VEXPRESS_BOOT_ADDR) "\0"
233
Peter Hoyes3ca0ea02022-03-04 16:30:18 +0000234#elif CONFIG_TARGET_VEXPRESS64_BASER_FVP /* ARMv8-R base model */
235
236#define BOOT_TARGET_DEVICES(func) \
237 func(MEM, mem, na) \
238 FUNC_VIRTIO(func) \
239 func(PXE, pxe, na) \
240 func(DHCP, dhcp, na)
241
242#define VEXPRESS_KERNEL_ADDR 0x00200000
243#define VEXPRESS_PXEFILE_ADDR 0x0fb00000
244#define VEXPRESS_FDT_ADDR 0x0fc00000
245#define VEXPRESS_SCRIPT_ADDR 0x0fd00000
246#define VEXPRESS_RAMDISK_ADDR 0x0fe00000
247
248#define EXTRA_ENV_NAMES \
249 "kernel_name=Image\0" \
250 "ramdisk_name=ramdisk.img\0" \
251 "fdtfile=board.dtb\0"
Darwin Rambod32d4112014-06-09 11:12:59 -0700252#endif
David Feng3b5458c2013-12-14 11:47:37 +0800253
Andre Przywara019753a2022-03-04 16:30:14 +0000254#include <config_distro_bootcmd.h>
255
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000256/* Default load addresses and names for the different payloads. */
257#define CONFIG_EXTRA_ENV_SETTINGS \
258 "kernel_addr_r=" __stringify(VEXPRESS_KERNEL_ADDR) "\0" \
259 "ramdisk_addr_r=" __stringify(VEXPRESS_RAMDISK_ADDR) "\0" \
260 "pxefile_addr_r=" __stringify(VEXPRESS_PXEFILE_ADDR) "\0" \
261 "fdt_addr_r=" __stringify(VEXPRESS_FDT_ADDR) "\0" \
262 "scriptaddr=" __stringify(VEXPRESS_SCRIPT_ADDR) "\0" \
263 EXTRA_ENV_NAMES \
264 BOOTENV
265
David Feng3b5458c2013-12-14 11:47:37 +0800266/* Monitor Command Prompt */
267#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
David Feng3b5458c2013-12-14 11:47:37 +0800268#define CONFIG_SYS_MAXARGS 64 /* max command args */
269
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000270#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
271#define CONFIG_SYS_FLASH_BASE 0x08000000
272/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
273#define CONFIG_SYS_MAX_FLASH_SECT 259
274/* Store environment at top of flash in the same location as blank.img */
275/* in the Juno firmware. */
Linus Walleij6ba4b6a2015-02-19 17:19:37 +0100276#else
Peter Hoyes32860372021-11-11 09:26:00 +0000277#define CONFIG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000)
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000278/* 256 x 256KiB sectors */
279#define CONFIG_SYS_MAX_FLASH_SECT 256
280/* Store environment at top of flash */
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000281#endif
282
Ryan Harkinb1a4a672015-05-08 18:07:52 +0100283#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
Linus Walleij6ba4b6a2015-02-19 17:19:37 +0100284
Andre Przywarae3e81212020-04-27 19:18:03 +0100285#ifdef CONFIG_USB_EHCI_HCD
286#define CONFIG_USB_OHCI_NEW
287#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
288#endif
289
Linus Walleij6ba4b6a2015-02-19 17:19:37 +0100290#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000291#define FLASH_MAX_SECTOR_SIZE 0x00040000
Linus Walleij6ba4b6a2015-02-19 17:19:37 +0100292
Peter Hoyes32860372021-11-11 09:26:00 +0000293#endif /* __VEXPRESS_AEMV8_H */