blob: 232b22a2faedfb54b525359a520c1eaa33b4aab7 [file] [log] [blame]
Miquel Raynald0935362019-10-03 19:50:03 +02001menuconfig MTD_RAW_NAND
Miquel Raynal8115c452018-08-16 17:30:08 +02002 bool "Raw NAND Device Support"
Alexander Dahl77374532024-03-20 10:02:11 +01003
Miquel Raynald0935362019-10-03 19:50:03 +02004if MTD_RAW_NAND
Miquel Raynal1f1ae152018-08-16 17:30:07 +02005
6config SYS_NAND_SELF_INIT
7 bool
8 help
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
11
Tom Rini98372452021-12-12 22:12:36 -050012config SPL_SYS_NAND_SELF_INIT
13 bool
14 depends on !SPL_NAND_SIMPLE
15 help
16 This option, if enabled, provides more flexible and linux-like
17 NAND initialization process, in SPL.
18
19config TPL_SYS_NAND_SELF_INIT
20 bool
21 depends on TPL_NAND_SUPPORT
22 help
23 This option, if enabled, provides more flexible and linux-like
24 NAND initialization process, in SPL.
25
Tom Rini1a9f23d2022-05-26 14:31:57 -040026config TPL_NAND_INIT
27 bool
28
Roger Quadros685c4282022-12-20 12:22:00 +020029config SPL_NAND_INIT
30 bool
31
Tom Riniac164de2022-10-28 20:27:04 -040032config SYS_MAX_NAND_DEVICE
33 int "Maximum number of NAND devices to support"
34 default 1
35
Stefan Agnerbd186142018-12-06 14:57:09 +010036config SYS_NAND_DRIVER_ECC_LAYOUT
Tom Rinid03e14e2021-12-11 14:55:54 -050037 bool "Omit standard ECC layouts to save space"
Stefan Agnerbd186142018-12-06 14:57:09 +010038 help
Tom Rinid03e14e2021-12-11 14:55:54 -050039 Omit standard ECC layouts to save space. Select this if your driver
Stefan Agnerbd186142018-12-06 14:57:09 +010040 is known to provide its own ECC layout.
41
Stefan Roese23b37f92019-08-22 12:28:04 +020042config SYS_NAND_USE_FLASH_BBT
43 bool "Enable BBT (Bad Block Table) support"
44 help
45 Enable the BBT (Bad Block Table) usage.
46
Tom Rini2b2696a2022-11-12 17:36:48 -050047config SYS_NAND_NO_SUBPAGE_WRITE
48 bool "Disable subpage write support"
49 depends on NAND_ARASAN || NAND_DAVINCI || NAND_KIRKWOOD
50
Balamanikandan Gunasundarfe33c7d2022-10-25 16:21:01 +053051config DM_NAND_ATMEL
Alexander Dahl77374532024-03-20 10:02:11 +010052 bool "Support Atmel NAND controller with DM support"
53 select SYS_NAND_SELF_INIT
54 imply SYS_NAND_USE_FLASH_BBT
55 help
56 Enable this driver for NAND flash platforms using an Atmel NAND
57 controller.
Balamanikandan Gunasundarfe33c7d2022-10-25 16:21:01 +053058
Miquel Raynal1f1ae152018-08-16 17:30:07 +020059config NAND_ATMEL
60 bool "Support Atmel NAND controller"
Tom Rini98372452021-12-12 22:12:36 -050061 select SYS_NAND_SELF_INIT
Miquel Raynal1f1ae152018-08-16 17:30:07 +020062 imply SYS_NAND_USE_FLASH_BBT
63 help
64 Enable this driver for NAND flash platforms using an Atmel NAND
65 controller.
66
Derald D. Woods7830fc52018-12-15 01:36:46 -060067if NAND_ATMEL
68
69config ATMEL_NAND_HWECC
70 bool "Atmel Hardware ECC"
Derald D. Woods7830fc52018-12-15 01:36:46 -060071
72config ATMEL_NAND_HW_PMECC
73 bool "Atmel Programmable Multibit ECC (PMECC)"
74 select ATMEL_NAND_HWECC
Derald D. Woods7830fc52018-12-15 01:36:46 -060075 help
76 The Programmable Multibit ECC (PMECC) controller is a programmable
77 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
78
79config PMECC_CAP
80 int "PMECC Correctable ECC Bits"
81 depends on ATMEL_NAND_HW_PMECC
82 default 2
83 help
84 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
85
86config PMECC_SECTOR_SIZE
87 int "PMECC Sector Size"
88 depends on ATMEL_NAND_HW_PMECC
89 default 512
90 help
91 Sector size, in bytes, can be 512 or 1024.
92
93config SPL_GENERATE_ATMEL_PMECC_HEADER
94 bool "Atmel PMECC Header Generation"
Tom Rini0a83cc22022-06-10 23:03:09 -040095 depends on SPL
Derald D. Woods7830fc52018-12-15 01:36:46 -060096 select ATMEL_NAND_HWECC
97 select ATMEL_NAND_HW_PMECC
Derald D. Woods7830fc52018-12-15 01:36:46 -060098 help
99 Generate Programmable Multibit ECC (PMECC) header for SPL image.
100
Tom Rini70aa87d2022-11-12 17:36:42 -0500101choice
102 prompt "NAND bus width (bits)"
103 default SYS_NAND_DBW_8
104
105config SYS_NAND_DBW_8
106 bool "NAND bus width is 8 bits"
107
108config SYS_NAND_DBW_16
109 bool "NAND bus width is 16 bits"
110
111endchoice
112
Derald D. Woods7830fc52018-12-15 01:36:46 -0600113endif
114
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100115config NAND_BRCMNAND
116 bool "Support Broadcom NAND controller"
Miquel Raynala903be42019-10-03 19:50:04 +0200117 depends on OF_CONTROL && DM && DM_MTD
Tom Rini98372452021-12-12 22:12:36 -0500118 select SYS_NAND_SELF_INIT
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100119 help
120 Enable the driver for NAND flash on platforms using a Broadcom NAND
121 controller.
122
Linus Walleij84998f42024-10-11 16:49:54 +0200123config NAND_BRCMNAND_BCMBCA
124 bool "Support Broadcom NAND controller on BCMBCA platforms"
125 depends on NAND_BRCMNAND && ARCH_BCMBCA
126 help
127 Enable support for broadcom nand driver on BCA (broadband
128 access) platforms such as BCM6846.
129
Álvaro Fernández Rojasd9f9bfc2019-08-28 19:12:15 +0200130config NAND_BRCMNAND_6368
131 bool "Support Broadcom NAND controller on bcm6368"
132 depends on NAND_BRCMNAND && ARCH_BMIPS
133 help
134 Enable support for broadcom nand driver on bcm6368.
135
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100136config NAND_BRCMNAND_6838
Alexander Dahl77374532024-03-20 10:02:11 +0100137 bool "Support Broadcom NAND controller on bcm6838"
138 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
139 help
140 Enable support for broadcom nand driver on bcm6838.
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100141
Linus Walleij2306c332023-03-08 22:42:31 +0100142config NAND_BRCMNAND_IPROC
Alexander Dahl77374532024-03-20 10:02:11 +0100143 bool "Support Broadcom NAND controller on the iproc family"
144 depends on NAND_BRCMNAND
145 help
146 Enable support for broadcom nand driver on the Broadcom
147 iproc family such as Northstar (BCM5301x, BCM4708...)
Linus Walleij2306c332023-03-08 22:42:31 +0100148
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200149config NAND_DAVINCI
150 bool "Support TI Davinci NAND controller"
Tom Rini98372452021-12-12 22:12:36 -0500151 select SYS_NAND_SELF_INIT if TARGET_DA850EVM
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200152 help
153 Enable this driver for NAND flash controllers available in TI Davinci
154 and Keystone2 platforms
155
Tom Rinid1286e12022-11-12 17:36:45 -0500156choice
157 prompt "Type of ECC used on NAND"
158 default SYS_NAND_4BIT_HW_ECC_OOBFIRST
159 depends on NAND_DAVINCI
160
161config SYS_NAND_HW_ECC
162 bool "Use 1-bit HW ECC"
163
Tom Rini7f750f82022-10-28 20:27:11 -0400164config SYS_NAND_4BIT_HW_ECC_OOBFIRST
165 bool "Use 4-bit HW ECC with OOB at the front"
Tom Rinid1286e12022-11-12 17:36:45 -0500166
167config SYS_NAND_SOFT_ECC
168 bool "Use software ECC"
169
170endchoice
Tom Rini7f750f82022-10-28 20:27:11 -0400171
Tom Rini33adefd2022-11-12 17:36:49 -0500172choice
173 prompt "NAND page size"
174 depends on NAND_DAVINCI
175 default SYS_NAND_PAGE_2K
176
177config SYS_NAND_PAGE_2K
178 bool "Page size is 2K"
179
180config SYS_NAND_PAGE_4K
181 bool "Page size is 4K"
182
183endchoice
184
Tom Rinidada0e32021-09-12 20:32:24 -0400185config KEYSTONE_RBL_NAND
186 depends on ARCH_KEYSTONE
187 def_bool y
188
Tom Rinifae1dab2021-09-22 14:50:29 -0400189config SPL_NAND_LOAD
190 def_bool y
191 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
192
Dinesh Maniyam1b8d1062025-02-27 00:18:26 +0800193config NAND_CADENCE
194 bool "Support Cadence NAND controller as a DT device"
195 depends on OF_CONTROL && DM_MTD
196 select SYS_NAND_SELF_INIT
197 imply CMD_NAND
198 help
199 Enable the driver for NAND flash on platforms using a Cadence NAND
200 controller as a DT device.
201
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200202config NAND_DENALI
203 bool
204 select SYS_NAND_SELF_INIT
205 imply CMD_NAND
206
207config NAND_DENALI_DT
208 bool "Support Denali NAND controller as a DT device"
209 select NAND_DENALI
Lokanathan, Raaj791edf72022-12-11 23:37:42 +0800210 select SPL_SYS_NAND_SELF_INIT
Masahiro Yamada8fc53822020-01-30 22:07:59 +0900211 depends on OF_CONTROL && DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200212 help
213 Enable the driver for NAND flash on platforms using a Denali NAND
214 controller as a DT device.
215
Tom Rinia73788c2021-09-22 14:50:37 -0400216config NAND_FSL_ELBC
217 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
Tom Rini98372452021-12-12 22:12:36 -0500218 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
219 select SPL_SYS_NAND_SELF_INIT
220 select SYS_NAND_SELF_INIT
Tom Rinia73788c2021-09-22 14:50:37 -0400221 depends on FSL_ELBC
222 help
223 Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
224
Pali Rohárbb834db2022-04-04 18:17:19 +0200225config NAND_FSL_ELBC_DT
226 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)"
227 depends on NAND_FSL_ELBC
228
Tom Rinia73788c2021-09-22 14:50:37 -0400229config NAND_FSL_IFC
230 bool "Support Freescale Integrated Flash Controller NAND driver"
Tom Rini98372452021-12-12 22:12:36 -0500231 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
Tom Rini1a9f23d2022-05-26 14:31:57 -0400232 select TPL_NAND_INIT if TPL && !TPL_FRAMEWORK
Tom Rini98372452021-12-12 22:12:36 -0500233 select SPL_SYS_NAND_SELF_INIT
234 select SYS_NAND_SELF_INIT
Tom Rini05b419e2021-12-11 14:55:49 -0500235 select FSL_IFC
Tom Rinia73788c2021-09-22 14:50:37 -0400236 help
237 Enable the Freescale Integrated Flash Controller NAND driver.
238
Tom Rinib91baf62022-11-19 18:45:29 -0500239config NAND_KIRKWOOD
240 bool "Support for Kirkwood NAND controller"
241 depends on ARCH_KIRKWOOD
242 default y
243
244config NAND_ECC_BCH
245 bool
246
247config NAND_KMETER1
248 bool "Support KMETER1 NAND controller"
249 depends on VENDOR_KM
250 select NAND_ECC_BCH
251
Tom Rini08204272021-09-22 14:50:28 -0400252config NAND_LPC32XX_MLC
253 bool "Support LPC32XX_MLC controller"
Tom Rini98372452021-12-12 22:12:36 -0500254 select SYS_NAND_SELF_INIT
Tom Rini08204272021-09-22 14:50:28 -0400255 help
256 Enable the LPC32XX MLC NAND controller.
257
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200258config NAND_LPC32XX_SLC
259 bool "Support LPC32XX_SLC controller"
260 help
261 Enable the LPC32XX SLC NAND controller.
262
263config NAND_OMAP_GPMC
264 bool "Support OMAP GPMC NAND controller"
Roger Quadros0bde4972022-10-11 14:50:00 +0300265 depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
Roger Quadros80cf6372022-12-20 12:21:59 +0200266 select SYS_NAND_SELF_INIT if ARCH_K3
Roger Quadros685c4282022-12-20 12:22:00 +0200267 select SPL_NAND_INIT if ARCH_K3
268 select SPL_SYS_NAND_SELF_INIT if ARCH_K3
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200269 help
270 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
271 GPMC controller is used for parallel NAND flash devices, and can
272 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
273 and BCH16 ECC algorithms.
274
Tom Rinif6d26d82021-09-22 14:50:39 -0400275if NAND_OMAP_GPMC
276
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200277config NAND_OMAP_GPMC_PREFETCH
278 bool "Enable GPMC Prefetch"
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200279 default y
280 help
281 On OMAP platforms that use the GPMC controller
282 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
283 uses the prefetch mode to speed up read operations.
284
285config NAND_OMAP_ELM
286 bool "Enable ELM driver for OMAPxx and AMxx platforms."
Tom Rinif6d26d82021-09-22 14:50:39 -0400287 depends on !OMAP34XX
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200288 help
289 ELM controller is used for ECC error detection (not ECC calculation)
290 of BCH4, BCH8 and BCH16 ECC algorithms.
291 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
292 thus such SoC platforms need to depend on software library for ECC error
293 detection. However ECC calculation on such plaforms would still be
294 done by GPMC controller.
295
Tom Rinif6d26d82021-09-22 14:50:39 -0400296choice
297 prompt "ECC scheme"
298 default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
299 help
300 On OMAP platforms, this CONFIG specifies NAND ECC scheme.
301 It can take following values:
302 OMAP_ECC_HAM1_CODE_SW
303 1-bit Hamming code using software lib.
304 (for legacy devices only)
305 OMAP_ECC_HAM1_CODE_HW
306 1-bit Hamming code using GPMC hardware.
307 (for legacy devices only)
308 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
309 4-bit BCH code (unsupported)
310 OMAP_ECC_BCH4_CODE_HW
311 4-bit BCH code (unsupported)
312 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
313 8-bit BCH code with
314 - ecc calculation using GPMC hardware engine,
315 - error detection using software library.
316 - requires CONFIG_BCH to enable software BCH library
317 (For legacy device which do not have ELM h/w engine)
318 OMAP_ECC_BCH8_CODE_HW
319 8-bit BCH code with
320 - ecc calculation using GPMC hardware engine,
321 - error detection using ELM hardware engine.
322 OMAP_ECC_BCH16_CODE_HW
323 16-bit BCH code with
324 - ecc calculation using GPMC hardware engine,
325 - error detection using ELM hardware engine.
326
327 How to select ECC scheme on OMAP and AMxx platforms ?
328 -----------------------------------------------------
329 Though higher ECC schemes have more capability to detect and correct
330 bit-flips, but still selection of ECC scheme is dependent on following
331 - hardware engines present in SoC.
332 Some legacy OMAP SoC do not have ELM h/w engine thus such
333 SoC cannot support BCHx_HW ECC schemes.
334 - size of OOB/Spare region
335 With higher ECC schemes, more OOB/Spare area is required to
336 store ECC. So choice of ECC scheme is limited by NAND oobsize.
337
338 In general following expression can help:
339 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
340 where
341 NAND_OOBSIZE = number of bytes available in
342 OOB/spare area per NAND page.
343 NAND_PAGESIZE = bytes in main-area of NAND page.
344 ECC_BYTES = number of ECC bytes generated to
345 protect 512 bytes of data, which is:
346 3 for HAM1_xx ecc schemes
347 7 for BCH4_xx ecc schemes
348 14 for BCH8_xx ecc schemes
349 26 for BCH16_xx ecc schemes
350
351 example to check for BCH16 on 2K page NAND
352 NAND_PAGESIZE = 2048
353 NAND_OOBSIZE = 64
354 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
355 Thus BCH16 cannot be supported on 2K page NAND.
356
357 However, for 4K pagesize NAND
358 NAND_PAGESIZE = 4096
359 NAND_OOBSIZE = 224
360 ECC_BYTES = 26
361 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
362 Thus BCH16 can be supported on 4K page NAND.
363
364config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
365 bool "1-bit Hamming code using software lib"
366
367config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
368 bool "1-bit Hamming code using GPMC hardware"
369
370config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
371 bool "8-bit BCH code with HW calculation SW error detection"
372
373config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
374 bool "8-bit BCH code with HW calculation and error detection"
375
376config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
377 bool "16-bit BCH code with HW calculation and error detection"
378
379endchoice
380
381config NAND_OMAP_ECCSCHEME
382 int
383 default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
384 default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
385 default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
386 default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
387 default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
388 help
389 This must be kept in sync with the enum in
390 include/linux/mtd/omap_gpmc.h
391
392endif
393
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200394config NAND_VF610_NFC
395 bool "Support for Freescale NFC for VF610"
396 select SYS_NAND_SELF_INIT
Stefan Agnerbd186142018-12-06 14:57:09 +0100397 select SYS_NAND_DRIVER_ECC_LAYOUT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200398 imply CMD_NAND
399 help
400 Enables support for NAND Flash Controller on some Freescale
401 processors like the VF610, MCF54418 or Kinetis K70.
402 The driver supports a maximum 2k page size. The driver
403 currently does not support hardware ECC.
404
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100405if NAND_VF610_NFC
406
407config NAND_VF610_NFC_DT
Alexander Dahl77374532024-03-20 10:02:11 +0100408 bool "Support Vybrid's vf610 NAND controller as a DT device"
409 depends on OF_CONTROL && DM_MTD
410 help
411 Enable the driver for Vybrid's vf610 NAND flash on platforms
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100412 using device tree.
413
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200414choice
415 prompt "Hardware ECC strength"
416 depends on NAND_VF610_NFC
417 default SYS_NAND_VF610_NFC_45_ECC_BYTES
418 help
419 Select the ECC strength used in the hardware BCH ECC block.
420
421config SYS_NAND_VF610_NFC_45_ECC_BYTES
422 bool "24-error correction (45 ECC bytes)"
423
424config SYS_NAND_VF610_NFC_60_ECC_BYTES
425 bool "32-error correction (60 ECC bytes)"
426
427endchoice
428
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100429endif
430
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200431config NAND_PXA3XX
432 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
433 select SYS_NAND_SELF_INIT
Shmuel Hazan759349e2020-10-29 08:52:18 +0200434 select DM_MTD
Shmuel Hazan58983222020-10-29 08:52:20 +0200435 select REGMAP
436 select SYSCON
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200437 imply CMD_NAND
438 help
439 This enables the driver for the NAND flash device found on
440 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
441
Sean Anderson326422b2023-11-04 16:37:52 -0400442config NAND_SANDBOX
443 bool "Support for NAND in sandbox"
444 depends on SANDBOX
445 select SYS_NAND_SELF_INIT
Sean Anderson765dc6a2023-11-04 16:37:53 -0400446 select SPL_SYS_NAND_SELF_INIT
447 select SPL_NAND_INIT
Sean Anderson326422b2023-11-04 16:37:52 -0400448 select SYS_NAND_SOFT_ECC
449 select BCH
450 select NAND_ECC_BCH
451 imply CMD_NAND
452 help
453 Enable a dummy NAND driver for sandbox. It simulates any number of
454 arbitrary NAND chips with a RAM buffer. It will also inject errors to
455 test ECC. At the moment, only 8-bit busses and single-chip devices are
456 supported.
457
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200458config NAND_SUNXI
459 bool "Support for NAND on Allwinner SoCs"
460 default ARCH_SUNXI
461 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
462 select SYS_NAND_SELF_INIT
463 select SYS_NAND_U_BOOT_LOCATIONS
464 select SPL_NAND_SUPPORT
Tom Rini98372452021-12-12 22:12:36 -0500465 select SPL_SYS_NAND_SELF_INIT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200466 imply CMD_NAND
Alexander Dahl77374532024-03-20 10:02:11 +0100467 help
468 Enable support for NAND. This option enables the standard and
469 SPL drivers.
470 The SPL driver only supports reading from the NAND using DMA
471 transfers.
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200472
473if NAND_SUNXI
474
475config NAND_SUNXI_SPL_ECC_STRENGTH
476 int "Allwinner NAND SPL ECC Strength"
477 default 64
478
479config NAND_SUNXI_SPL_ECC_SIZE
480 int "Allwinner NAND SPL ECC Step Size"
481 default 1024
482
483config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
484 int "Allwinner NAND SPL Usable Page Size"
485 default 1024
486
487endif
488
489config NAND_ARASAN
490 bool "Configure Arasan Nand"
491 select SYS_NAND_SELF_INIT
Michal Simekc5587832020-08-19 09:59:52 +0200492 depends on DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200493 imply CMD_NAND
494 help
495 This enables Nand driver support for Arasan nand flash
496 controller. This uses the hardware ECC for read and
497 write operations.
498
Arseniy Krasnov55842b42024-02-11 01:39:27 +0300499config NAND_MESON
500 bool "Meson NAND support"
501 select SYS_NAND_SELF_INIT
502 depends on DM_MTD && ARCH_MESON
503 imply CMD_NAND
504 help
505 This enables Nand driver support for Meson raw NAND flash
506 controller.
507
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200508config NAND_MXC
509 bool "MXC NAND support"
510 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
511 imply CMD_NAND
512 help
513 This enables the NAND driver for the NAND flash controller on the
Haolin Lie8df55b2021-07-18 10:13:39 +0800514 i.MX27 / i.MX31 / i.MX5 processors.
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200515
Tom Rini1ba2a002022-11-12 17:36:50 -0500516config SYS_NAND_SIZE
517 int "Size of NAND in kilobytes"
518 depends on NAND_MXC && SPL_NAND_SUPPORT
519 default 268435456
520
Tom Rini17e67002022-12-02 16:42:37 -0500521config MXC_NAND_HWECC
522 bool "Hardware ECC support in MXC NAND"
523 depends on NAND_MXC
524
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200525config NAND_MXS
526 bool "MXS NAND support"
Peng Fan128abf42020-05-04 22:09:00 +0800527 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
Tom Rini98372452021-12-12 22:12:36 -0500528 select SPL_SYS_NAND_SELF_INIT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200529 select SYS_NAND_SELF_INIT
530 imply CMD_NAND
531 select APBH_DMA
Peng Fan128abf42020-05-04 22:09:00 +0800532 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
533 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200534 help
535 This enables NAND driver for the NAND flash controller on the
536 MXS processors.
537
538if NAND_MXS
539
540config NAND_MXS_DT
541 bool "Support MXS NAND controller as a DT device"
Miquel Raynala903be42019-10-03 19:50:04 +0200542 depends on OF_CONTROL && DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200543 help
544 Enable the driver for MXS NAND flash on platforms using
545 device tree.
546
547config NAND_MXS_USE_MINIMUM_ECC
548 bool "Use minimum ECC strength supported by the controller"
549 default false
550
551endif
552
Zhengxun Li01551712021-09-14 13:43:51 +0800553config NAND_MXIC
554 bool "Macronix raw NAND controller"
555 select SYS_NAND_SELF_INIT
556 help
557 This selects the Macronix raw NAND controller driver.
558
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200559config NAND_ZYNQ
560 bool "Support for Zynq Nand controller"
Tom Rini98372452021-12-12 22:12:36 -0500561 select SPL_SYS_NAND_SELF_INIT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200562 select SYS_NAND_SELF_INIT
Ashok Reddy Somabb8448a2019-12-27 04:47:12 -0700563 select DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200564 imply CMD_NAND
565 help
566 This enables Nand driver support for Nand flash controller
567 found on Zynq SoC.
568
569config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
570 bool "Enable use of 1st stage bootloader timing for NAND"
571 depends on NAND_ZYNQ
572 help
Michal Simek50fa1182023-05-17 09:17:16 +0200573 This flag prevent U-Boot reconfigure NAND flash controller and reuse
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200574 the NAND timing from 1st stage bootloader.
575
Suneel Garapati9de7d2b2020-08-26 14:37:22 +0200576config NAND_OCTEONTX
577 bool "Support for OcteonTX NAND controller"
578 select SYS_NAND_SELF_INIT
579 imply CMD_NAND
580 help
Alexander Dahl77374532024-03-20 10:02:11 +0100581 This enables Nand flash controller hardware found on the OcteonTX
582 processors.
Suneel Garapati9de7d2b2020-08-26 14:37:22 +0200583
584config NAND_OCTEONTX_HW_ECC
585 bool "Support Hardware ECC for OcteonTX NAND controller"
586 depends on NAND_OCTEONTX
587 default y
588 help
Alexander Dahl77374532024-03-20 10:02:11 +0100589 This enables Hardware BCH engine found on the OcteonTX processors to
590 support ECC for NAND flash controller.
Suneel Garapati9de7d2b2020-08-26 14:37:22 +0200591
Christophe Kerelloda141682019-04-05 11:41:50 +0200592config NAND_STM32_FMC2
593 bool "Support for NAND controller on STM32MP SoCs"
594 depends on ARCH_STM32MP
595 select SYS_NAND_SELF_INIT
596 imply CMD_NAND
597 help
598 Enables support for NAND Flash chips on SoCs containing the FMC2
599 NAND controller. This controller is found on STM32MP SoCs.
600 The controller supports a maximum 8k page size and supports
601 a maximum 8-bit correction error per sector of 512 bytes.
602
Kate Liu41ccd2e2020-12-11 13:46:12 -0800603config CORTINA_NAND
604 bool "Support for NAND controller on Cortina-Access SoCs"
605 depends on CORTINA_PLATFORM
606 select SYS_NAND_SELF_INIT
607 select DM_MTD
608 imply CMD_NAND
609 help
610 Enables support for NAND Flash chips on Coartina-Access SoCs platform
611 This controller is found on Presidio/Venus SoCs.
612 The controller supports a maximum 8k page size and supports
613 a maximum 40-bit error correction per sector of 1024 bytes.
614
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800615config ROCKCHIP_NAND
616 bool "Support for NAND controller on Rockchip SoCs"
617 depends on ARCH_ROCKCHIP
618 select SYS_NAND_SELF_INIT
619 select DM_MTD
620 imply CMD_NAND
621 help
622 Enables support for NAND Flash chips on Rockchip SoCs platform.
623 This controller is found on Rockchip SoCs.
624 There are four different versions of NAND FLASH Controllers,
625 including:
626 NFC v600: RK2928, RK3066, RK3188
627 NFC v622: RK3036, RK3128
628 NFC v800: RK3308, RV1108
629 NFC v900: PX30, RK3326
630
Johan Jonker904e0f02023-10-18 16:00:27 +0200631config ROCKCHIP_NAND_SKIP_BBTSCAN
632 bool "Skip the automatic BBT scan with Rockchip NAND controllers"
633 depends on ROCKCHIP_NAND
Johan Jonker904e0f02023-10-18 16:00:27 +0200634 help
635 Skip the automatic BBT scan with the NAND_SKIP_BBTSCAN
636 option when data content is not in MTD format or
637 must remain unchanged.
638
Tom Rini8f37ac42021-12-12 22:12:35 -0500639config TEGRA_NAND
640 bool "Support for NAND controller on Tegra SoCs"
641 depends on ARCH_TEGRA
642 select SYS_NAND_SELF_INIT
643 imply CMD_NAND
644 help
645 Enables support for NAND Flash chips on Tegra SoCs platforms.
646
developer10a61df2022-05-20 11:23:47 +0800647config NAND_MT7621
648 bool "Support for MediaTek MT7621 NAND flash controller"
649 depends on SOC_MT7621
650 select SYS_NAND_SELF_INIT
651 select SPL_SYS_NAND_SELF_INIT
652 imply CMD_NAND
653 help
654 This enables NAND driver for the NAND flash controller on MediaTek
655 MT7621 platform.
656 The controller supports 4~12 bits correction per 512 bytes with a
657 maximum 4KB page size.
658
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200659comment "Generic NAND options"
660
661config SYS_NAND_BLOCK_SIZE
662 hex "NAND chip eraseblock size"
Pali Rohár5c5cf602023-01-10 22:55:21 +0100663 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT || \
664 MVEBU_SPL_BOOT_DEVICE_NAND
developer10a61df2022-05-20 11:23:47 +0800665 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && \
666 !NAND_FSL_IFC && !NAND_MT7621
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200667 help
668 Number of data bytes in one eraseblock for the NAND chip on the
669 board. This is the multiple of NAND_PAGE_SIZE and the number of
670 pages.
671
Tom Rinifdae0072021-09-22 14:50:34 -0400672config SYS_NAND_ONFI_DETECTION
673 bool "Enable detection of ONFI compliant devices during probe"
674 help
675 Enables detection of ONFI compliant devices during probe.
676 And fetching device parameters flashed on device, by parsing
677 ONFI parameter page.
678
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200679config SYS_NAND_PAGE_SIZE
680 hex "NAND chip page size"
Tom Rinifae1dab2021-09-22 14:50:29 -0400681 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
682 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
Pali Rohár5c5cf602023-01-10 22:55:21 +0100683 MVEBU_SPL_BOOT_DEVICE_NAND || \
Sean Anderson765dc6a2023-11-04 16:37:53 -0400684 (NAND_ATMEL && SPL_NAND_SUPPORT) || \
685 SPL_GENERATE_ATMEL_PMECC_HEADER || NAND_SANDBOX
developer10a61df2022-05-20 11:23:47 +0800686 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200687 help
688 Number of data bytes in one page for the NAND chip on the
689 board, not including the OOB area.
690
691config SYS_NAND_OOBSIZE
692 hex "NAND chip OOB size"
Tom Rinifae1dab2021-09-22 14:50:29 -0400693 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
694 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
695 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
Tom Rinid24700f2021-10-30 23:03:56 -0400696 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200697 help
698 Number of bytes in the Out-Of-Band area for the NAND chip on
699 the board.
700
701# Enhance depends when converting drivers to Kconfig which use this config
702# option (mxc_nand, ndfc, omap_gpmc).
703config SYS_NAND_BUSWIDTH_16BIT
704 bool "Use 16-bit NAND interface"
705 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
706 help
707 Indicates that NAND device has 16-bit wide data-bus. In absence of this
708 config, bus-width of NAND device is assumed to be either 8-bit and later
709 determined by reading ONFI params.
710 Above config is useful when NAND device's bus-width information cannot
711 be determined from on-chip ONFI params, like in following scenarios:
712 - SPL boot does not support reading of ONFI parameters. This is done to
713 keep SPL code foot-print small.
714 - In current U-Boot flow using nand_init(), driver initialization
715 happens in board_nand_init() which is called before any device probe
716 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
717 not available while configuring controller. So a static CONFIG_NAND_xx
718 is needed to know the device's bus-width in advance.
719
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200720if SPL
721
Tom Rini8e6d9c72021-09-22 14:50:33 -0400722config SYS_NAND_5_ADDR_CYCLE
723 bool "Wait 5 address cycles during NAND commands"
724 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
725 (SPL_NAND_SUPPORT && NAND_ATMEL)
726 default y
727 help
728 Some controllers require waiting for 5 address cycles when issuing
729 some commands, on NAND chips larger than 128MiB.
730
Tom Rinia2fbd4a2021-09-22 14:50:32 -0400731choice
Tom Rinifdae0072021-09-22 14:50:34 -0400732 prompt "NAND bad block marker/indicator position in the OOB"
Tom Rinia2fbd4a2021-09-22 14:50:32 -0400733 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
734 SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
735 default HAS_NAND_LARGE_BADBLOCK_POS
736 help
737 In the OOB, which position contains the badblock information.
738
739config HAS_NAND_LARGE_BADBLOCK_POS
740 bool "Set the bad block marker/indicator to the 'large' position"
741
742config HAS_NAND_SMALL_BADBLOCK_POS
743 bool "Set the bad block marker/indicator to the 'small' position"
744
745endchoice
746
747config SYS_NAND_BAD_BLOCK_POS
748 int
749 default 0 if HAS_NAND_LARGE_BADBLOCK_POS
750 default 5 if HAS_NAND_SMALL_BADBLOCK_POS
751
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200752config SYS_NAND_U_BOOT_LOCATIONS
Michal Simek50fa1182023-05-17 09:17:16 +0200753 bool "Define U-Boot binaries locations in NAND"
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200754 help
Alexander Dahl77374532024-03-20 10:02:11 +0100755 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
756 This option should not be enabled when compiling U-Boot for boards
757 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
758 file.
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200759
760config SYS_NAND_U_BOOT_OFFS
761 hex "Location in NAND to read U-Boot from"
762 default 0x800000 if NAND_SUNXI
763 depends on SYS_NAND_U_BOOT_LOCATIONS
764 help
Alexander Dahl77374532024-03-20 10:02:11 +0100765 Set the offset from the start of the nand where u-boot should be
766 loaded from.
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200767
768config SYS_NAND_U_BOOT_OFFS_REDUND
769 hex "Location in NAND to read U-Boot from"
770 default SYS_NAND_U_BOOT_OFFS
771 depends on SYS_NAND_U_BOOT_LOCATIONS
772 help
Alexander Dahl77374532024-03-20 10:02:11 +0100773 Set the offset from the start of the nand where the redundant u-boot
774 should be loaded from.
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200775
776config SPL_NAND_AM33XX_BCH
777 bool "Enables SPL-NAND driver which supports ELM based"
Tom Rini0a83cc22022-06-10 23:03:09 -0400778 depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200779 default y
Alexander Dahl77374532024-03-20 10:02:11 +0100780 help
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200781 Hardware ECC correction. This is useful for platforms which have ELM
782 hardware engine and use NAND boot mode.
783 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
784 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
Alexander Dahl77374532024-03-20 10:02:11 +0100785 SPL-NAND driver with software ECC correction support.
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200786
787config SPL_NAND_DENALI
788 bool "Support Denali NAND controller for SPL"
Tom Rini0a83cc22022-06-10 23:03:09 -0400789 depends on SPL_NAND_SUPPORT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200790 help
791 This is a small implementation of the Denali NAND controller
792 for use on SPL.
793
Masahiro Yamada64648cb2020-04-17 16:51:42 +0900794config NAND_DENALI_SPARE_AREA_SKIP_BYTES
795 int "Number of bytes skipped in OOB area"
796 depends on SPL_NAND_DENALI
797 range 0 63
798 help
799 This option specifies the number of bytes to skip from the beginning
800 of OOB area before last ECC sector data starts. This is potentially
801 used to preserve the bad block marker in the OOB area.
802
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200803config SPL_NAND_SIMPLE
804 bool "Use simple SPL NAND driver"
Tom Rini0a83cc22022-06-10 23:03:09 -0400805 depends on !SPL_NAND_AM33XX_BCH && SPL_NAND_SUPPORT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200806 help
807 Support for NAND boot using simple NAND drivers that
808 expose the cmd_ctrl() interface.
Tom Rini4251f7d2022-11-12 17:36:44 -0500809
810config SYS_NAND_HW_ECC_OOBFIRST
811 bool "In SPL, read the OOB first and then the data from NAND"
812 depends on SPL_NAND_SIMPLE
813
Alexander Dahl77374532024-03-20 10:02:11 +0100814endif # if SPL
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200815
Alexander Dahl77374532024-03-20 10:02:11 +0100816endif # if MTD_RAW_NAND