blob: 87ed4a22d644b5ae3a7b9a6c80a86c6d6f559d2e [file] [log] [blame]
Miquel Raynal1f1ae152018-08-16 17:30:07 +02001
Miquel Raynald0935362019-10-03 19:50:03 +02002menuconfig MTD_RAW_NAND
Miquel Raynal8115c452018-08-16 17:30:08 +02003 bool "Raw NAND Device Support"
Miquel Raynald0935362019-10-03 19:50:03 +02004if MTD_RAW_NAND
Miquel Raynal1f1ae152018-08-16 17:30:07 +02005
6config SYS_NAND_SELF_INIT
7 bool
8 help
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
11
Tom Rini98372452021-12-12 22:12:36 -050012config SPL_SYS_NAND_SELF_INIT
13 bool
14 depends on !SPL_NAND_SIMPLE
15 help
16 This option, if enabled, provides more flexible and linux-like
17 NAND initialization process, in SPL.
18
19config TPL_SYS_NAND_SELF_INIT
20 bool
21 depends on TPL_NAND_SUPPORT
22 help
23 This option, if enabled, provides more flexible and linux-like
24 NAND initialization process, in SPL.
25
Tom Rini1a9f23d2022-05-26 14:31:57 -040026config TPL_NAND_INIT
27 bool
28
Tom Riniac164de2022-10-28 20:27:04 -040029config SYS_MAX_NAND_DEVICE
30 int "Maximum number of NAND devices to support"
31 default 1
32
Stefan Agnerbd186142018-12-06 14:57:09 +010033config SYS_NAND_DRIVER_ECC_LAYOUT
Tom Rinid03e14e2021-12-11 14:55:54 -050034 bool "Omit standard ECC layouts to save space"
Stefan Agnerbd186142018-12-06 14:57:09 +010035 help
Tom Rinid03e14e2021-12-11 14:55:54 -050036 Omit standard ECC layouts to save space. Select this if your driver
Stefan Agnerbd186142018-12-06 14:57:09 +010037 is known to provide its own ECC layout.
38
Stefan Roese23b37f92019-08-22 12:28:04 +020039config SYS_NAND_USE_FLASH_BBT
40 bool "Enable BBT (Bad Block Table) support"
41 help
42 Enable the BBT (Bad Block Table) usage.
43
Tom Rini2b2696a2022-11-12 17:36:48 -050044config SYS_NAND_NO_SUBPAGE_WRITE
45 bool "Disable subpage write support"
46 depends on NAND_ARASAN || NAND_DAVINCI || NAND_KIRKWOOD
47
Miquel Raynal1f1ae152018-08-16 17:30:07 +020048config NAND_ATMEL
49 bool "Support Atmel NAND controller"
Tom Rini98372452021-12-12 22:12:36 -050050 select SYS_NAND_SELF_INIT
Miquel Raynal1f1ae152018-08-16 17:30:07 +020051 imply SYS_NAND_USE_FLASH_BBT
52 help
53 Enable this driver for NAND flash platforms using an Atmel NAND
54 controller.
55
Derald D. Woods7830fc52018-12-15 01:36:46 -060056if NAND_ATMEL
57
58config ATMEL_NAND_HWECC
59 bool "Atmel Hardware ECC"
Derald D. Woods7830fc52018-12-15 01:36:46 -060060
61config ATMEL_NAND_HW_PMECC
62 bool "Atmel Programmable Multibit ECC (PMECC)"
63 select ATMEL_NAND_HWECC
Derald D. Woods7830fc52018-12-15 01:36:46 -060064 help
65 The Programmable Multibit ECC (PMECC) controller is a programmable
66 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
67
68config PMECC_CAP
69 int "PMECC Correctable ECC Bits"
70 depends on ATMEL_NAND_HW_PMECC
71 default 2
72 help
73 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
74
75config PMECC_SECTOR_SIZE
76 int "PMECC Sector Size"
77 depends on ATMEL_NAND_HW_PMECC
78 default 512
79 help
80 Sector size, in bytes, can be 512 or 1024.
81
82config SPL_GENERATE_ATMEL_PMECC_HEADER
83 bool "Atmel PMECC Header Generation"
Tom Rini0a83cc22022-06-10 23:03:09 -040084 depends on SPL
Derald D. Woods7830fc52018-12-15 01:36:46 -060085 select ATMEL_NAND_HWECC
86 select ATMEL_NAND_HW_PMECC
Derald D. Woods7830fc52018-12-15 01:36:46 -060087 help
88 Generate Programmable Multibit ECC (PMECC) header for SPL image.
89
Tom Rini70aa87d2022-11-12 17:36:42 -050090choice
91 prompt "NAND bus width (bits)"
92 default SYS_NAND_DBW_8
93
94config SYS_NAND_DBW_8
95 bool "NAND bus width is 8 bits"
96
97config SYS_NAND_DBW_16
98 bool "NAND bus width is 16 bits"
99
100endchoice
101
Derald D. Woods7830fc52018-12-15 01:36:46 -0600102endif
103
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100104config NAND_BRCMNAND
105 bool "Support Broadcom NAND controller"
Miquel Raynala903be42019-10-03 19:50:04 +0200106 depends on OF_CONTROL && DM && DM_MTD
Tom Rini98372452021-12-12 22:12:36 -0500107 select SYS_NAND_SELF_INIT
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100108 help
109 Enable the driver for NAND flash on platforms using a Broadcom NAND
110 controller.
111
Álvaro Fernández Rojasd9f9bfc2019-08-28 19:12:15 +0200112config NAND_BRCMNAND_6368
113 bool "Support Broadcom NAND controller on bcm6368"
114 depends on NAND_BRCMNAND && ARCH_BMIPS
115 help
116 Enable support for broadcom nand driver on bcm6368.
117
Philippe Reynese175c322022-02-11 19:18:36 +0100118config NAND_BRCMNAND_6753
119 bool "Support Broadcom NAND controller on bcm6753"
William Zhang38921822022-08-22 11:49:08 -0700120 depends on NAND_BRCMNAND && BCM6855
Philippe Reynese175c322022-02-11 19:18:36 +0100121 help
122 Enable support for broadcom nand driver on bcm6753.
123
Philippe Reynes74ead742020-01-07 20:14:13 +0100124config NAND_BRCMNAND_68360
125 bool "Support Broadcom NAND controller on bcm68360"
William Zhangdf0b5bb2022-08-22 11:31:43 -0700126 depends on NAND_BRCMNAND && BCM6856
Philippe Reynes74ead742020-01-07 20:14:13 +0100127 help
128 Enable support for broadcom nand driver on bcm68360.
129
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100130config NAND_BRCMNAND_6838
131 bool "Support Broadcom NAND controller on bcm6838"
132 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
133 help
134 Enable support for broadcom nand driver on bcm6838.
135
136config NAND_BRCMNAND_6858
137 bool "Support Broadcom NAND controller on bcm6858"
William Zhang6b45fa62022-08-22 11:39:45 -0700138 depends on NAND_BRCMNAND && BCM6858
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100139 help
140 Enable support for broadcom nand driver on bcm6858.
141
142config NAND_BRCMNAND_63158
143 bool "Support Broadcom NAND controller on bcm63158"
William Zhang35a3ec1b2022-08-22 11:19:46 -0700144 depends on NAND_BRCMNAND && BCM63158
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100145 help
146 Enable support for broadcom nand driver on bcm63158.
147
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200148config NAND_DAVINCI
149 bool "Support TI Davinci NAND controller"
Tom Rini98372452021-12-12 22:12:36 -0500150 select SYS_NAND_SELF_INIT if TARGET_DA850EVM
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200151 help
152 Enable this driver for NAND flash controllers available in TI Davinci
153 and Keystone2 platforms
154
Tom Rinid1286e12022-11-12 17:36:45 -0500155choice
156 prompt "Type of ECC used on NAND"
157 default SYS_NAND_4BIT_HW_ECC_OOBFIRST
158 depends on NAND_DAVINCI
159
160config SYS_NAND_HW_ECC
161 bool "Use 1-bit HW ECC"
162
Tom Rini7f750f82022-10-28 20:27:11 -0400163config SYS_NAND_4BIT_HW_ECC_OOBFIRST
164 bool "Use 4-bit HW ECC with OOB at the front"
Tom Rinid1286e12022-11-12 17:36:45 -0500165
166config SYS_NAND_SOFT_ECC
167 bool "Use software ECC"
168
169endchoice
Tom Rini7f750f82022-10-28 20:27:11 -0400170
Tom Rini33adefd2022-11-12 17:36:49 -0500171choice
172 prompt "NAND page size"
173 depends on NAND_DAVINCI
174 default SYS_NAND_PAGE_2K
175
176config SYS_NAND_PAGE_2K
177 bool "Page size is 2K"
178
179config SYS_NAND_PAGE_4K
180 bool "Page size is 4K"
181
182endchoice
183
Tom Rinidada0e32021-09-12 20:32:24 -0400184config KEYSTONE_RBL_NAND
185 depends on ARCH_KEYSTONE
186 def_bool y
187
Tom Rinifae1dab2021-09-22 14:50:29 -0400188config SPL_NAND_LOAD
189 def_bool y
190 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
191
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200192config NAND_DENALI
193 bool
194 select SYS_NAND_SELF_INIT
195 imply CMD_NAND
196
197config NAND_DENALI_DT
198 bool "Support Denali NAND controller as a DT device"
199 select NAND_DENALI
Lokanathan, Raaj791edf72022-12-11 23:37:42 +0800200 select SPL_SYS_NAND_SELF_INIT
Masahiro Yamada8fc53822020-01-30 22:07:59 +0900201 depends on OF_CONTROL && DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200202 help
203 Enable the driver for NAND flash on platforms using a Denali NAND
204 controller as a DT device.
205
Tom Rinia73788c2021-09-22 14:50:37 -0400206config NAND_FSL_ELBC
207 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
Tom Rini98372452021-12-12 22:12:36 -0500208 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
209 select SPL_SYS_NAND_SELF_INIT
210 select SYS_NAND_SELF_INIT
Tom Rinia73788c2021-09-22 14:50:37 -0400211 depends on FSL_ELBC
212 help
213 Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
214
Pali Rohárbb834db2022-04-04 18:17:19 +0200215config NAND_FSL_ELBC_DT
216 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)"
217 depends on NAND_FSL_ELBC
218
Tom Rinia73788c2021-09-22 14:50:37 -0400219config NAND_FSL_IFC
220 bool "Support Freescale Integrated Flash Controller NAND driver"
Tom Rini98372452021-12-12 22:12:36 -0500221 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
Tom Rini1a9f23d2022-05-26 14:31:57 -0400222 select TPL_NAND_INIT if TPL && !TPL_FRAMEWORK
Tom Rini98372452021-12-12 22:12:36 -0500223 select SPL_SYS_NAND_SELF_INIT
224 select SYS_NAND_SELF_INIT
Tom Rini05b419e2021-12-11 14:55:49 -0500225 select FSL_IFC
Tom Rinia73788c2021-09-22 14:50:37 -0400226 help
227 Enable the Freescale Integrated Flash Controller NAND driver.
228
Tom Rinib91baf62022-11-19 18:45:29 -0500229config NAND_KIRKWOOD
230 bool "Support for Kirkwood NAND controller"
231 depends on ARCH_KIRKWOOD
232 default y
233
234config NAND_ECC_BCH
235 bool
236
237config NAND_KMETER1
238 bool "Support KMETER1 NAND controller"
239 depends on VENDOR_KM
240 select NAND_ECC_BCH
241
Tom Rini08204272021-09-22 14:50:28 -0400242config NAND_LPC32XX_MLC
243 bool "Support LPC32XX_MLC controller"
Tom Rini98372452021-12-12 22:12:36 -0500244 select SYS_NAND_SELF_INIT
Tom Rini08204272021-09-22 14:50:28 -0400245 help
246 Enable the LPC32XX MLC NAND controller.
247
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200248config NAND_LPC32XX_SLC
249 bool "Support LPC32XX_SLC controller"
250 help
251 Enable the LPC32XX SLC NAND controller.
252
253config NAND_OMAP_GPMC
254 bool "Support OMAP GPMC NAND controller"
Roger Quadros0bde4972022-10-11 14:50:00 +0300255 depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3
Roger Quadros80cf6372022-12-20 12:21:59 +0200256 select SYS_NAND_SELF_INIT if ARCH_K3
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200257 help
258 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
259 GPMC controller is used for parallel NAND flash devices, and can
260 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
261 and BCH16 ECC algorithms.
262
Tom Rinif6d26d82021-09-22 14:50:39 -0400263if NAND_OMAP_GPMC
264
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200265config NAND_OMAP_GPMC_PREFETCH
266 bool "Enable GPMC Prefetch"
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200267 default y
268 help
269 On OMAP platforms that use the GPMC controller
270 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
271 uses the prefetch mode to speed up read operations.
272
273config NAND_OMAP_ELM
274 bool "Enable ELM driver for OMAPxx and AMxx platforms."
Tom Rinif6d26d82021-09-22 14:50:39 -0400275 depends on !OMAP34XX
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200276 help
277 ELM controller is used for ECC error detection (not ECC calculation)
278 of BCH4, BCH8 and BCH16 ECC algorithms.
279 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
280 thus such SoC platforms need to depend on software library for ECC error
281 detection. However ECC calculation on such plaforms would still be
282 done by GPMC controller.
283
Tom Rinif6d26d82021-09-22 14:50:39 -0400284choice
285 prompt "ECC scheme"
286 default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
287 help
288 On OMAP platforms, this CONFIG specifies NAND ECC scheme.
289 It can take following values:
290 OMAP_ECC_HAM1_CODE_SW
291 1-bit Hamming code using software lib.
292 (for legacy devices only)
293 OMAP_ECC_HAM1_CODE_HW
294 1-bit Hamming code using GPMC hardware.
295 (for legacy devices only)
296 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
297 4-bit BCH code (unsupported)
298 OMAP_ECC_BCH4_CODE_HW
299 4-bit BCH code (unsupported)
300 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
301 8-bit BCH code with
302 - ecc calculation using GPMC hardware engine,
303 - error detection using software library.
304 - requires CONFIG_BCH to enable software BCH library
305 (For legacy device which do not have ELM h/w engine)
306 OMAP_ECC_BCH8_CODE_HW
307 8-bit BCH code with
308 - ecc calculation using GPMC hardware engine,
309 - error detection using ELM hardware engine.
310 OMAP_ECC_BCH16_CODE_HW
311 16-bit BCH code with
312 - ecc calculation using GPMC hardware engine,
313 - error detection using ELM hardware engine.
314
315 How to select ECC scheme on OMAP and AMxx platforms ?
316 -----------------------------------------------------
317 Though higher ECC schemes have more capability to detect and correct
318 bit-flips, but still selection of ECC scheme is dependent on following
319 - hardware engines present in SoC.
320 Some legacy OMAP SoC do not have ELM h/w engine thus such
321 SoC cannot support BCHx_HW ECC schemes.
322 - size of OOB/Spare region
323 With higher ECC schemes, more OOB/Spare area is required to
324 store ECC. So choice of ECC scheme is limited by NAND oobsize.
325
326 In general following expression can help:
327 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
328 where
329 NAND_OOBSIZE = number of bytes available in
330 OOB/spare area per NAND page.
331 NAND_PAGESIZE = bytes in main-area of NAND page.
332 ECC_BYTES = number of ECC bytes generated to
333 protect 512 bytes of data, which is:
334 3 for HAM1_xx ecc schemes
335 7 for BCH4_xx ecc schemes
336 14 for BCH8_xx ecc schemes
337 26 for BCH16_xx ecc schemes
338
339 example to check for BCH16 on 2K page NAND
340 NAND_PAGESIZE = 2048
341 NAND_OOBSIZE = 64
342 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
343 Thus BCH16 cannot be supported on 2K page NAND.
344
345 However, for 4K pagesize NAND
346 NAND_PAGESIZE = 4096
347 NAND_OOBSIZE = 224
348 ECC_BYTES = 26
349 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
350 Thus BCH16 can be supported on 4K page NAND.
351
352config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
353 bool "1-bit Hamming code using software lib"
354
355config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
356 bool "1-bit Hamming code using GPMC hardware"
357
358config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
359 bool "8-bit BCH code with HW calculation SW error detection"
360
361config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
362 bool "8-bit BCH code with HW calculation and error detection"
363
364config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
365 bool "16-bit BCH code with HW calculation and error detection"
366
367endchoice
368
369config NAND_OMAP_ECCSCHEME
370 int
371 default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
372 default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
373 default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
374 default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
375 default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
376 help
377 This must be kept in sync with the enum in
378 include/linux/mtd/omap_gpmc.h
379
380endif
381
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200382config NAND_VF610_NFC
383 bool "Support for Freescale NFC for VF610"
384 select SYS_NAND_SELF_INIT
Stefan Agnerbd186142018-12-06 14:57:09 +0100385 select SYS_NAND_DRIVER_ECC_LAYOUT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200386 imply CMD_NAND
387 help
388 Enables support for NAND Flash Controller on some Freescale
389 processors like the VF610, MCF54418 or Kinetis K70.
390 The driver supports a maximum 2k page size. The driver
391 currently does not support hardware ECC.
392
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100393if NAND_VF610_NFC
394
395config NAND_VF610_NFC_DT
396 bool "Support Vybrid's vf610 NAND controller as a DT device"
Miquel Raynala903be42019-10-03 19:50:04 +0200397 depends on OF_CONTROL && DM_MTD
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100398 help
399 Enable the driver for Vybrid's vf610 NAND flash on platforms
400 using device tree.
401
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200402choice
403 prompt "Hardware ECC strength"
404 depends on NAND_VF610_NFC
405 default SYS_NAND_VF610_NFC_45_ECC_BYTES
406 help
407 Select the ECC strength used in the hardware BCH ECC block.
408
409config SYS_NAND_VF610_NFC_45_ECC_BYTES
410 bool "24-error correction (45 ECC bytes)"
411
412config SYS_NAND_VF610_NFC_60_ECC_BYTES
413 bool "32-error correction (60 ECC bytes)"
414
415endchoice
416
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100417endif
418
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200419config NAND_PXA3XX
420 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
421 select SYS_NAND_SELF_INIT
Shmuel Hazan759349e2020-10-29 08:52:18 +0200422 select DM_MTD
Shmuel Hazan58983222020-10-29 08:52:20 +0200423 select REGMAP
424 select SYSCON
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200425 imply CMD_NAND
426 help
427 This enables the driver for the NAND flash device found on
428 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
429
430config NAND_SUNXI
431 bool "Support for NAND on Allwinner SoCs"
432 default ARCH_SUNXI
433 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
434 select SYS_NAND_SELF_INIT
435 select SYS_NAND_U_BOOT_LOCATIONS
436 select SPL_NAND_SUPPORT
Tom Rini98372452021-12-12 22:12:36 -0500437 select SPL_SYS_NAND_SELF_INIT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200438 imply CMD_NAND
439 ---help---
440 Enable support for NAND. This option enables the standard and
441 SPL drivers.
442 The SPL driver only supports reading from the NAND using DMA
443 transfers.
444
445if NAND_SUNXI
446
447config NAND_SUNXI_SPL_ECC_STRENGTH
448 int "Allwinner NAND SPL ECC Strength"
449 default 64
450
451config NAND_SUNXI_SPL_ECC_SIZE
452 int "Allwinner NAND SPL ECC Step Size"
453 default 1024
454
455config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
456 int "Allwinner NAND SPL Usable Page Size"
457 default 1024
458
459endif
460
461config NAND_ARASAN
462 bool "Configure Arasan Nand"
463 select SYS_NAND_SELF_INIT
Michal Simekc5587832020-08-19 09:59:52 +0200464 depends on DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200465 imply CMD_NAND
466 help
467 This enables Nand driver support for Arasan nand flash
468 controller. This uses the hardware ECC for read and
469 write operations.
470
471config NAND_MXC
472 bool "MXC NAND support"
473 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
474 imply CMD_NAND
475 help
476 This enables the NAND driver for the NAND flash controller on the
Haolin Lie8df55b2021-07-18 10:13:39 +0800477 i.MX27 / i.MX31 / i.MX5 processors.
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200478
Tom Rini1ba2a002022-11-12 17:36:50 -0500479config SYS_NAND_SIZE
480 int "Size of NAND in kilobytes"
481 depends on NAND_MXC && SPL_NAND_SUPPORT
482 default 268435456
483
Tom Rini17e67002022-12-02 16:42:37 -0500484config MXC_NAND_HWECC
485 bool "Hardware ECC support in MXC NAND"
486 depends on NAND_MXC
487
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200488config NAND_MXS
489 bool "MXS NAND support"
Peng Fan128abf42020-05-04 22:09:00 +0800490 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
Tom Rini98372452021-12-12 22:12:36 -0500491 select SPL_SYS_NAND_SELF_INIT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200492 select SYS_NAND_SELF_INIT
493 imply CMD_NAND
494 select APBH_DMA
Peng Fan128abf42020-05-04 22:09:00 +0800495 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
496 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200497 help
498 This enables NAND driver for the NAND flash controller on the
499 MXS processors.
500
501if NAND_MXS
502
503config NAND_MXS_DT
504 bool "Support MXS NAND controller as a DT device"
Miquel Raynala903be42019-10-03 19:50:04 +0200505 depends on OF_CONTROL && DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200506 help
507 Enable the driver for MXS NAND flash on platforms using
508 device tree.
509
510config NAND_MXS_USE_MINIMUM_ECC
511 bool "Use minimum ECC strength supported by the controller"
512 default false
513
514endif
515
Zhengxun Li01551712021-09-14 13:43:51 +0800516config NAND_MXIC
517 bool "Macronix raw NAND controller"
518 select SYS_NAND_SELF_INIT
519 help
520 This selects the Macronix raw NAND controller driver.
521
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200522config NAND_ZYNQ
523 bool "Support for Zynq Nand controller"
Tom Rini98372452021-12-12 22:12:36 -0500524 select SPL_SYS_NAND_SELF_INIT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200525 select SYS_NAND_SELF_INIT
Ashok Reddy Somabb8448a2019-12-27 04:47:12 -0700526 select DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200527 imply CMD_NAND
528 help
529 This enables Nand driver support for Nand flash controller
530 found on Zynq SoC.
531
532config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
533 bool "Enable use of 1st stage bootloader timing for NAND"
534 depends on NAND_ZYNQ
535 help
536 This flag prevent U-boot reconfigure NAND flash controller and reuse
537 the NAND timing from 1st stage bootloader.
538
Suneel Garapati9de7d2b2020-08-26 14:37:22 +0200539config NAND_OCTEONTX
540 bool "Support for OcteonTX NAND controller"
541 select SYS_NAND_SELF_INIT
542 imply CMD_NAND
543 help
544 This enables Nand flash controller hardware found on the OcteonTX
545 processors.
546
547config NAND_OCTEONTX_HW_ECC
548 bool "Support Hardware ECC for OcteonTX NAND controller"
549 depends on NAND_OCTEONTX
550 default y
551 help
552 This enables Hardware BCH engine found on the OcteonTX processors to
553 support ECC for NAND flash controller.
554
Christophe Kerelloda141682019-04-05 11:41:50 +0200555config NAND_STM32_FMC2
556 bool "Support for NAND controller on STM32MP SoCs"
557 depends on ARCH_STM32MP
558 select SYS_NAND_SELF_INIT
559 imply CMD_NAND
560 help
561 Enables support for NAND Flash chips on SoCs containing the FMC2
562 NAND controller. This controller is found on STM32MP SoCs.
563 The controller supports a maximum 8k page size and supports
564 a maximum 8-bit correction error per sector of 512 bytes.
565
Kate Liu41ccd2e2020-12-11 13:46:12 -0800566config CORTINA_NAND
567 bool "Support for NAND controller on Cortina-Access SoCs"
568 depends on CORTINA_PLATFORM
569 select SYS_NAND_SELF_INIT
570 select DM_MTD
571 imply CMD_NAND
572 help
573 Enables support for NAND Flash chips on Coartina-Access SoCs platform
574 This controller is found on Presidio/Venus SoCs.
575 The controller supports a maximum 8k page size and supports
576 a maximum 40-bit error correction per sector of 1024 bytes.
577
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800578config ROCKCHIP_NAND
579 bool "Support for NAND controller on Rockchip SoCs"
580 depends on ARCH_ROCKCHIP
581 select SYS_NAND_SELF_INIT
582 select DM_MTD
583 imply CMD_NAND
584 help
585 Enables support for NAND Flash chips on Rockchip SoCs platform.
586 This controller is found on Rockchip SoCs.
587 There are four different versions of NAND FLASH Controllers,
588 including:
589 NFC v600: RK2928, RK3066, RK3188
590 NFC v622: RK3036, RK3128
591 NFC v800: RK3308, RV1108
592 NFC v900: PX30, RK3326
593
Tom Rini8f37ac42021-12-12 22:12:35 -0500594config TEGRA_NAND
595 bool "Support for NAND controller on Tegra SoCs"
596 depends on ARCH_TEGRA
597 select SYS_NAND_SELF_INIT
598 imply CMD_NAND
599 help
600 Enables support for NAND Flash chips on Tegra SoCs platforms.
601
developer10a61df2022-05-20 11:23:47 +0800602config NAND_MT7621
603 bool "Support for MediaTek MT7621 NAND flash controller"
604 depends on SOC_MT7621
605 select SYS_NAND_SELF_INIT
606 select SPL_SYS_NAND_SELF_INIT
607 imply CMD_NAND
608 help
609 This enables NAND driver for the NAND flash controller on MediaTek
610 MT7621 platform.
611 The controller supports 4~12 bits correction per 512 bytes with a
612 maximum 4KB page size.
613
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200614comment "Generic NAND options"
615
616config SYS_NAND_BLOCK_SIZE
617 hex "NAND chip eraseblock size"
Tom Rinifae1dab2021-09-22 14:50:29 -0400618 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
developer10a61df2022-05-20 11:23:47 +0800619 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && \
620 !NAND_FSL_IFC && !NAND_MT7621
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200621 help
622 Number of data bytes in one eraseblock for the NAND chip on the
623 board. This is the multiple of NAND_PAGE_SIZE and the number of
624 pages.
625
Tom Rinifdae0072021-09-22 14:50:34 -0400626config SYS_NAND_ONFI_DETECTION
627 bool "Enable detection of ONFI compliant devices during probe"
628 help
629 Enables detection of ONFI compliant devices during probe.
630 And fetching device parameters flashed on device, by parsing
631 ONFI parameter page.
632
Tom Rini2510a812021-09-22 14:50:30 -0400633config SYS_NAND_PAGE_COUNT
634 hex "NAND chip page count"
635 depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
636 SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
637 help
638 Number of pages in the NAND chip.
639
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200640config SYS_NAND_PAGE_SIZE
641 hex "NAND chip page size"
Tom Rinifae1dab2021-09-22 14:50:29 -0400642 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
643 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
644 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
developer10a61df2022-05-20 11:23:47 +0800645 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200646 help
647 Number of data bytes in one page for the NAND chip on the
648 board, not including the OOB area.
649
650config SYS_NAND_OOBSIZE
651 hex "NAND chip OOB size"
Tom Rinifae1dab2021-09-22 14:50:29 -0400652 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
653 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
654 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
Tom Rinid24700f2021-10-30 23:03:56 -0400655 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200656 help
657 Number of bytes in the Out-Of-Band area for the NAND chip on
658 the board.
659
660# Enhance depends when converting drivers to Kconfig which use this config
661# option (mxc_nand, ndfc, omap_gpmc).
662config SYS_NAND_BUSWIDTH_16BIT
663 bool "Use 16-bit NAND interface"
664 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
665 help
666 Indicates that NAND device has 16-bit wide data-bus. In absence of this
667 config, bus-width of NAND device is assumed to be either 8-bit and later
668 determined by reading ONFI params.
669 Above config is useful when NAND device's bus-width information cannot
670 be determined from on-chip ONFI params, like in following scenarios:
671 - SPL boot does not support reading of ONFI parameters. This is done to
672 keep SPL code foot-print small.
673 - In current U-Boot flow using nand_init(), driver initialization
674 happens in board_nand_init() which is called before any device probe
675 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
676 not available while configuring controller. So a static CONFIG_NAND_xx
677 is needed to know the device's bus-width in advance.
678
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200679if SPL
680
Tom Rini8e6d9c72021-09-22 14:50:33 -0400681config SYS_NAND_5_ADDR_CYCLE
682 bool "Wait 5 address cycles during NAND commands"
683 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
684 (SPL_NAND_SUPPORT && NAND_ATMEL)
685 default y
686 help
687 Some controllers require waiting for 5 address cycles when issuing
688 some commands, on NAND chips larger than 128MiB.
689
Tom Rinia2fbd4a2021-09-22 14:50:32 -0400690choice
Tom Rinifdae0072021-09-22 14:50:34 -0400691 prompt "NAND bad block marker/indicator position in the OOB"
Tom Rinia2fbd4a2021-09-22 14:50:32 -0400692 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
693 SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
694 default HAS_NAND_LARGE_BADBLOCK_POS
695 help
696 In the OOB, which position contains the badblock information.
697
698config HAS_NAND_LARGE_BADBLOCK_POS
699 bool "Set the bad block marker/indicator to the 'large' position"
700
701config HAS_NAND_SMALL_BADBLOCK_POS
702 bool "Set the bad block marker/indicator to the 'small' position"
703
704endchoice
705
706config SYS_NAND_BAD_BLOCK_POS
707 int
708 default 0 if HAS_NAND_LARGE_BADBLOCK_POS
709 default 5 if HAS_NAND_SMALL_BADBLOCK_POS
710
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200711config SYS_NAND_U_BOOT_LOCATIONS
712 bool "Define U-boot binaries locations in NAND"
713 help
714 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
715 This option should not be enabled when compiling U-boot for boards
716 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
717 file.
718
719config SYS_NAND_U_BOOT_OFFS
720 hex "Location in NAND to read U-Boot from"
721 default 0x800000 if NAND_SUNXI
722 depends on SYS_NAND_U_BOOT_LOCATIONS
723 help
724 Set the offset from the start of the nand where u-boot should be
725 loaded from.
726
727config SYS_NAND_U_BOOT_OFFS_REDUND
728 hex "Location in NAND to read U-Boot from"
729 default SYS_NAND_U_BOOT_OFFS
730 depends on SYS_NAND_U_BOOT_LOCATIONS
731 help
732 Set the offset from the start of the nand where the redundant u-boot
733 should be loaded from.
734
735config SPL_NAND_AM33XX_BCH
736 bool "Enables SPL-NAND driver which supports ELM based"
Tom Rini0a83cc22022-06-10 23:03:09 -0400737 depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200738 default y
739 help
740 Hardware ECC correction. This is useful for platforms which have ELM
741 hardware engine and use NAND boot mode.
742 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
743 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
744 SPL-NAND driver with software ECC correction support.
745
746config SPL_NAND_DENALI
747 bool "Support Denali NAND controller for SPL"
Tom Rini0a83cc22022-06-10 23:03:09 -0400748 depends on SPL_NAND_SUPPORT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200749 help
750 This is a small implementation of the Denali NAND controller
751 for use on SPL.
752
Masahiro Yamada64648cb2020-04-17 16:51:42 +0900753config NAND_DENALI_SPARE_AREA_SKIP_BYTES
754 int "Number of bytes skipped in OOB area"
755 depends on SPL_NAND_DENALI
756 range 0 63
757 help
758 This option specifies the number of bytes to skip from the beginning
759 of OOB area before last ECC sector data starts. This is potentially
760 used to preserve the bad block marker in the OOB area.
761
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200762config SPL_NAND_SIMPLE
763 bool "Use simple SPL NAND driver"
Tom Rini0a83cc22022-06-10 23:03:09 -0400764 depends on !SPL_NAND_AM33XX_BCH && SPL_NAND_SUPPORT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200765 help
766 Support for NAND boot using simple NAND drivers that
767 expose the cmd_ctrl() interface.
Tom Rini4251f7d2022-11-12 17:36:44 -0500768
769config SYS_NAND_HW_ECC_OOBFIRST
770 bool "In SPL, read the OOB first and then the data from NAND"
771 depends on SPL_NAND_SIMPLE
772
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200773endif
774
775endif # if NAND