blob: 0e428418b25d880e44640978775df6be5fe84c03 [file] [log] [blame]
Miquel Raynal1f1ae152018-08-16 17:30:07 +02001
Miquel Raynald0935362019-10-03 19:50:03 +02002menuconfig MTD_RAW_NAND
Miquel Raynal8115c452018-08-16 17:30:08 +02003 bool "Raw NAND Device Support"
Miquel Raynald0935362019-10-03 19:50:03 +02004if MTD_RAW_NAND
Miquel Raynal1f1ae152018-08-16 17:30:07 +02005
6config SYS_NAND_SELF_INIT
7 bool
8 help
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
11
Tom Rini98372452021-12-12 22:12:36 -050012config SPL_SYS_NAND_SELF_INIT
13 bool
14 depends on !SPL_NAND_SIMPLE
15 help
16 This option, if enabled, provides more flexible and linux-like
17 NAND initialization process, in SPL.
18
19config TPL_SYS_NAND_SELF_INIT
20 bool
21 depends on TPL_NAND_SUPPORT
22 help
23 This option, if enabled, provides more flexible and linux-like
24 NAND initialization process, in SPL.
25
Tom Rini1a9f23d2022-05-26 14:31:57 -040026config TPL_NAND_INIT
27 bool
28
Tom Riniac164de2022-10-28 20:27:04 -040029config SYS_MAX_NAND_DEVICE
30 int "Maximum number of NAND devices to support"
31 default 1
32
Stefan Agnerbd186142018-12-06 14:57:09 +010033config SYS_NAND_DRIVER_ECC_LAYOUT
Tom Rinid03e14e2021-12-11 14:55:54 -050034 bool "Omit standard ECC layouts to save space"
Stefan Agnerbd186142018-12-06 14:57:09 +010035 help
Tom Rinid03e14e2021-12-11 14:55:54 -050036 Omit standard ECC layouts to save space. Select this if your driver
Stefan Agnerbd186142018-12-06 14:57:09 +010037 is known to provide its own ECC layout.
38
Stefan Roese23b37f92019-08-22 12:28:04 +020039config SYS_NAND_USE_FLASH_BBT
40 bool "Enable BBT (Bad Block Table) support"
41 help
42 Enable the BBT (Bad Block Table) usage.
43
Miquel Raynal1f1ae152018-08-16 17:30:07 +020044config NAND_ATMEL
45 bool "Support Atmel NAND controller"
Tom Rini98372452021-12-12 22:12:36 -050046 select SYS_NAND_SELF_INIT
Miquel Raynal1f1ae152018-08-16 17:30:07 +020047 imply SYS_NAND_USE_FLASH_BBT
48 help
49 Enable this driver for NAND flash platforms using an Atmel NAND
50 controller.
51
Derald D. Woods7830fc52018-12-15 01:36:46 -060052if NAND_ATMEL
53
54config ATMEL_NAND_HWECC
55 bool "Atmel Hardware ECC"
Derald D. Woods7830fc52018-12-15 01:36:46 -060056
57config ATMEL_NAND_HW_PMECC
58 bool "Atmel Programmable Multibit ECC (PMECC)"
59 select ATMEL_NAND_HWECC
Derald D. Woods7830fc52018-12-15 01:36:46 -060060 help
61 The Programmable Multibit ECC (PMECC) controller is a programmable
62 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
63
64config PMECC_CAP
65 int "PMECC Correctable ECC Bits"
66 depends on ATMEL_NAND_HW_PMECC
67 default 2
68 help
69 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
70
71config PMECC_SECTOR_SIZE
72 int "PMECC Sector Size"
73 depends on ATMEL_NAND_HW_PMECC
74 default 512
75 help
76 Sector size, in bytes, can be 512 or 1024.
77
78config SPL_GENERATE_ATMEL_PMECC_HEADER
79 bool "Atmel PMECC Header Generation"
Tom Rini0a83cc22022-06-10 23:03:09 -040080 depends on SPL
Derald D. Woods7830fc52018-12-15 01:36:46 -060081 select ATMEL_NAND_HWECC
82 select ATMEL_NAND_HW_PMECC
Derald D. Woods7830fc52018-12-15 01:36:46 -060083 help
84 Generate Programmable Multibit ECC (PMECC) header for SPL image.
85
Tom Rini70aa87d2022-11-12 17:36:42 -050086choice
87 prompt "NAND bus width (bits)"
88 default SYS_NAND_DBW_8
89
90config SYS_NAND_DBW_8
91 bool "NAND bus width is 8 bits"
92
93config SYS_NAND_DBW_16
94 bool "NAND bus width is 16 bits"
95
96endchoice
97
Derald D. Woods7830fc52018-12-15 01:36:46 -060098endif
99
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100100config NAND_BRCMNAND
101 bool "Support Broadcom NAND controller"
Miquel Raynala903be42019-10-03 19:50:04 +0200102 depends on OF_CONTROL && DM && DM_MTD
Tom Rini98372452021-12-12 22:12:36 -0500103 select SYS_NAND_SELF_INIT
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100104 help
105 Enable the driver for NAND flash on platforms using a Broadcom NAND
106 controller.
107
Álvaro Fernández Rojasd9f9bfc2019-08-28 19:12:15 +0200108config NAND_BRCMNAND_6368
109 bool "Support Broadcom NAND controller on bcm6368"
110 depends on NAND_BRCMNAND && ARCH_BMIPS
111 help
112 Enable support for broadcom nand driver on bcm6368.
113
Philippe Reynese175c322022-02-11 19:18:36 +0100114config NAND_BRCMNAND_6753
115 bool "Support Broadcom NAND controller on bcm6753"
William Zhang38921822022-08-22 11:49:08 -0700116 depends on NAND_BRCMNAND && BCM6855
Philippe Reynese175c322022-02-11 19:18:36 +0100117 help
118 Enable support for broadcom nand driver on bcm6753.
119
Philippe Reynes74ead742020-01-07 20:14:13 +0100120config NAND_BRCMNAND_68360
121 bool "Support Broadcom NAND controller on bcm68360"
William Zhangdf0b5bb2022-08-22 11:31:43 -0700122 depends on NAND_BRCMNAND && BCM6856
Philippe Reynes74ead742020-01-07 20:14:13 +0100123 help
124 Enable support for broadcom nand driver on bcm68360.
125
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100126config NAND_BRCMNAND_6838
127 bool "Support Broadcom NAND controller on bcm6838"
128 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
129 help
130 Enable support for broadcom nand driver on bcm6838.
131
132config NAND_BRCMNAND_6858
133 bool "Support Broadcom NAND controller on bcm6858"
William Zhang6b45fa62022-08-22 11:39:45 -0700134 depends on NAND_BRCMNAND && BCM6858
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100135 help
136 Enable support for broadcom nand driver on bcm6858.
137
138config NAND_BRCMNAND_63158
139 bool "Support Broadcom NAND controller on bcm63158"
William Zhang35a3ec1b2022-08-22 11:19:46 -0700140 depends on NAND_BRCMNAND && BCM63158
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100141 help
142 Enable support for broadcom nand driver on bcm63158.
143
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200144config NAND_DAVINCI
145 bool "Support TI Davinci NAND controller"
Tom Rini98372452021-12-12 22:12:36 -0500146 select SYS_NAND_SELF_INIT if TARGET_DA850EVM
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200147 help
148 Enable this driver for NAND flash controllers available in TI Davinci
149 and Keystone2 platforms
150
Tom Rinid1286e12022-11-12 17:36:45 -0500151choice
152 prompt "Type of ECC used on NAND"
153 default SYS_NAND_4BIT_HW_ECC_OOBFIRST
154 depends on NAND_DAVINCI
155
156config SYS_NAND_HW_ECC
157 bool "Use 1-bit HW ECC"
158
Tom Rini7f750f82022-10-28 20:27:11 -0400159config SYS_NAND_4BIT_HW_ECC_OOBFIRST
160 bool "Use 4-bit HW ECC with OOB at the front"
Tom Rinid1286e12022-11-12 17:36:45 -0500161
162config SYS_NAND_SOFT_ECC
163 bool "Use software ECC"
164
165endchoice
Tom Rini7f750f82022-10-28 20:27:11 -0400166
Tom Rinidada0e32021-09-12 20:32:24 -0400167config KEYSTONE_RBL_NAND
168 depends on ARCH_KEYSTONE
169 def_bool y
170
Tom Rinifae1dab2021-09-22 14:50:29 -0400171config SPL_NAND_LOAD
172 def_bool y
173 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
174
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200175config NAND_DENALI
176 bool
177 select SYS_NAND_SELF_INIT
178 imply CMD_NAND
179
180config NAND_DENALI_DT
181 bool "Support Denali NAND controller as a DT device"
182 select NAND_DENALI
Masahiro Yamada8fc53822020-01-30 22:07:59 +0900183 depends on OF_CONTROL && DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200184 help
185 Enable the driver for NAND flash on platforms using a Denali NAND
186 controller as a DT device.
187
Tom Rinia73788c2021-09-22 14:50:37 -0400188config NAND_FSL_ELBC
189 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
Tom Rini98372452021-12-12 22:12:36 -0500190 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
191 select SPL_SYS_NAND_SELF_INIT
192 select SYS_NAND_SELF_INIT
Tom Rinia73788c2021-09-22 14:50:37 -0400193 depends on FSL_ELBC
194 help
195 Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
196
Pali Rohárbb834db2022-04-04 18:17:19 +0200197config NAND_FSL_ELBC_DT
198 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)"
199 depends on NAND_FSL_ELBC
200
Tom Rinia73788c2021-09-22 14:50:37 -0400201config NAND_FSL_IFC
202 bool "Support Freescale Integrated Flash Controller NAND driver"
Tom Rini98372452021-12-12 22:12:36 -0500203 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
Tom Rini1a9f23d2022-05-26 14:31:57 -0400204 select TPL_NAND_INIT if TPL && !TPL_FRAMEWORK
Tom Rini98372452021-12-12 22:12:36 -0500205 select SPL_SYS_NAND_SELF_INIT
206 select SYS_NAND_SELF_INIT
Tom Rini05b419e2021-12-11 14:55:49 -0500207 select FSL_IFC
Tom Rinia73788c2021-09-22 14:50:37 -0400208 help
209 Enable the Freescale Integrated Flash Controller NAND driver.
210
Tom Rini08204272021-09-22 14:50:28 -0400211config NAND_LPC32XX_MLC
212 bool "Support LPC32XX_MLC controller"
Tom Rini98372452021-12-12 22:12:36 -0500213 select SYS_NAND_SELF_INIT
Tom Rini08204272021-09-22 14:50:28 -0400214 help
215 Enable the LPC32XX MLC NAND controller.
216
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200217config NAND_LPC32XX_SLC
218 bool "Support LPC32XX_SLC controller"
219 help
220 Enable the LPC32XX SLC NAND controller.
221
222config NAND_OMAP_GPMC
223 bool "Support OMAP GPMC NAND controller"
224 depends on ARCH_OMAP2PLUS
225 help
226 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
227 GPMC controller is used for parallel NAND flash devices, and can
228 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
229 and BCH16 ECC algorithms.
230
Tom Rinif6d26d82021-09-22 14:50:39 -0400231if NAND_OMAP_GPMC
232
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200233config NAND_OMAP_GPMC_PREFETCH
234 bool "Enable GPMC Prefetch"
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200235 default y
236 help
237 On OMAP platforms that use the GPMC controller
238 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
239 uses the prefetch mode to speed up read operations.
240
241config NAND_OMAP_ELM
242 bool "Enable ELM driver for OMAPxx and AMxx platforms."
Tom Rinif6d26d82021-09-22 14:50:39 -0400243 depends on !OMAP34XX
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200244 help
245 ELM controller is used for ECC error detection (not ECC calculation)
246 of BCH4, BCH8 and BCH16 ECC algorithms.
247 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
248 thus such SoC platforms need to depend on software library for ECC error
249 detection. However ECC calculation on such plaforms would still be
250 done by GPMC controller.
251
Tom Rinif6d26d82021-09-22 14:50:39 -0400252choice
253 prompt "ECC scheme"
254 default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
255 help
256 On OMAP platforms, this CONFIG specifies NAND ECC scheme.
257 It can take following values:
258 OMAP_ECC_HAM1_CODE_SW
259 1-bit Hamming code using software lib.
260 (for legacy devices only)
261 OMAP_ECC_HAM1_CODE_HW
262 1-bit Hamming code using GPMC hardware.
263 (for legacy devices only)
264 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
265 4-bit BCH code (unsupported)
266 OMAP_ECC_BCH4_CODE_HW
267 4-bit BCH code (unsupported)
268 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
269 8-bit BCH code with
270 - ecc calculation using GPMC hardware engine,
271 - error detection using software library.
272 - requires CONFIG_BCH to enable software BCH library
273 (For legacy device which do not have ELM h/w engine)
274 OMAP_ECC_BCH8_CODE_HW
275 8-bit BCH code with
276 - ecc calculation using GPMC hardware engine,
277 - error detection using ELM hardware engine.
278 OMAP_ECC_BCH16_CODE_HW
279 16-bit BCH code with
280 - ecc calculation using GPMC hardware engine,
281 - error detection using ELM hardware engine.
282
283 How to select ECC scheme on OMAP and AMxx platforms ?
284 -----------------------------------------------------
285 Though higher ECC schemes have more capability to detect and correct
286 bit-flips, but still selection of ECC scheme is dependent on following
287 - hardware engines present in SoC.
288 Some legacy OMAP SoC do not have ELM h/w engine thus such
289 SoC cannot support BCHx_HW ECC schemes.
290 - size of OOB/Spare region
291 With higher ECC schemes, more OOB/Spare area is required to
292 store ECC. So choice of ECC scheme is limited by NAND oobsize.
293
294 In general following expression can help:
295 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
296 where
297 NAND_OOBSIZE = number of bytes available in
298 OOB/spare area per NAND page.
299 NAND_PAGESIZE = bytes in main-area of NAND page.
300 ECC_BYTES = number of ECC bytes generated to
301 protect 512 bytes of data, which is:
302 3 for HAM1_xx ecc schemes
303 7 for BCH4_xx ecc schemes
304 14 for BCH8_xx ecc schemes
305 26 for BCH16_xx ecc schemes
306
307 example to check for BCH16 on 2K page NAND
308 NAND_PAGESIZE = 2048
309 NAND_OOBSIZE = 64
310 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
311 Thus BCH16 cannot be supported on 2K page NAND.
312
313 However, for 4K pagesize NAND
314 NAND_PAGESIZE = 4096
315 NAND_OOBSIZE = 224
316 ECC_BYTES = 26
317 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
318 Thus BCH16 can be supported on 4K page NAND.
319
320config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
321 bool "1-bit Hamming code using software lib"
322
323config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
324 bool "1-bit Hamming code using GPMC hardware"
325
326config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
327 bool "8-bit BCH code with HW calculation SW error detection"
328
329config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
330 bool "8-bit BCH code with HW calculation and error detection"
331
332config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
333 bool "16-bit BCH code with HW calculation and error detection"
334
335endchoice
336
337config NAND_OMAP_ECCSCHEME
338 int
339 default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
340 default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
341 default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
342 default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
343 default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
344 help
345 This must be kept in sync with the enum in
346 include/linux/mtd/omap_gpmc.h
347
348endif
349
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200350config NAND_VF610_NFC
351 bool "Support for Freescale NFC for VF610"
352 select SYS_NAND_SELF_INIT
Stefan Agnerbd186142018-12-06 14:57:09 +0100353 select SYS_NAND_DRIVER_ECC_LAYOUT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200354 imply CMD_NAND
355 help
356 Enables support for NAND Flash Controller on some Freescale
357 processors like the VF610, MCF54418 or Kinetis K70.
358 The driver supports a maximum 2k page size. The driver
359 currently does not support hardware ECC.
360
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100361if NAND_VF610_NFC
362
363config NAND_VF610_NFC_DT
364 bool "Support Vybrid's vf610 NAND controller as a DT device"
Miquel Raynala903be42019-10-03 19:50:04 +0200365 depends on OF_CONTROL && DM_MTD
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100366 help
367 Enable the driver for Vybrid's vf610 NAND flash on platforms
368 using device tree.
369
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200370choice
371 prompt "Hardware ECC strength"
372 depends on NAND_VF610_NFC
373 default SYS_NAND_VF610_NFC_45_ECC_BYTES
374 help
375 Select the ECC strength used in the hardware BCH ECC block.
376
377config SYS_NAND_VF610_NFC_45_ECC_BYTES
378 bool "24-error correction (45 ECC bytes)"
379
380config SYS_NAND_VF610_NFC_60_ECC_BYTES
381 bool "32-error correction (60 ECC bytes)"
382
383endchoice
384
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100385endif
386
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200387config NAND_PXA3XX
388 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
389 select SYS_NAND_SELF_INIT
Shmuel Hazan759349e2020-10-29 08:52:18 +0200390 select DM_MTD
Shmuel Hazan58983222020-10-29 08:52:20 +0200391 select REGMAP
392 select SYSCON
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200393 imply CMD_NAND
394 help
395 This enables the driver for the NAND flash device found on
396 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
397
398config NAND_SUNXI
399 bool "Support for NAND on Allwinner SoCs"
400 default ARCH_SUNXI
401 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
402 select SYS_NAND_SELF_INIT
403 select SYS_NAND_U_BOOT_LOCATIONS
404 select SPL_NAND_SUPPORT
Tom Rini98372452021-12-12 22:12:36 -0500405 select SPL_SYS_NAND_SELF_INIT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200406 imply CMD_NAND
407 ---help---
408 Enable support for NAND. This option enables the standard and
409 SPL drivers.
410 The SPL driver only supports reading from the NAND using DMA
411 transfers.
412
413if NAND_SUNXI
414
415config NAND_SUNXI_SPL_ECC_STRENGTH
416 int "Allwinner NAND SPL ECC Strength"
417 default 64
418
419config NAND_SUNXI_SPL_ECC_SIZE
420 int "Allwinner NAND SPL ECC Step Size"
421 default 1024
422
423config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
424 int "Allwinner NAND SPL Usable Page Size"
425 default 1024
426
427endif
428
429config NAND_ARASAN
430 bool "Configure Arasan Nand"
431 select SYS_NAND_SELF_INIT
Michal Simekc5587832020-08-19 09:59:52 +0200432 depends on DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200433 imply CMD_NAND
434 help
435 This enables Nand driver support for Arasan nand flash
436 controller. This uses the hardware ECC for read and
437 write operations.
438
439config NAND_MXC
440 bool "MXC NAND support"
441 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
442 imply CMD_NAND
443 help
444 This enables the NAND driver for the NAND flash controller on the
Haolin Lie8df55b2021-07-18 10:13:39 +0800445 i.MX27 / i.MX31 / i.MX5 processors.
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200446
447config NAND_MXS
448 bool "MXS NAND support"
Peng Fan128abf42020-05-04 22:09:00 +0800449 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
Tom Rini98372452021-12-12 22:12:36 -0500450 select SPL_SYS_NAND_SELF_INIT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200451 select SYS_NAND_SELF_INIT
452 imply CMD_NAND
453 select APBH_DMA
Peng Fan128abf42020-05-04 22:09:00 +0800454 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
455 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200456 help
457 This enables NAND driver for the NAND flash controller on the
458 MXS processors.
459
460if NAND_MXS
461
462config NAND_MXS_DT
463 bool "Support MXS NAND controller as a DT device"
Miquel Raynala903be42019-10-03 19:50:04 +0200464 depends on OF_CONTROL && DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200465 help
466 Enable the driver for MXS NAND flash on platforms using
467 device tree.
468
469config NAND_MXS_USE_MINIMUM_ECC
470 bool "Use minimum ECC strength supported by the controller"
471 default false
472
473endif
474
Zhengxun Li01551712021-09-14 13:43:51 +0800475config NAND_MXIC
476 bool "Macronix raw NAND controller"
477 select SYS_NAND_SELF_INIT
478 help
479 This selects the Macronix raw NAND controller driver.
480
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200481config NAND_ZYNQ
482 bool "Support for Zynq Nand controller"
Tom Rini98372452021-12-12 22:12:36 -0500483 select SPL_SYS_NAND_SELF_INIT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200484 select SYS_NAND_SELF_INIT
Ashok Reddy Somabb8448a2019-12-27 04:47:12 -0700485 select DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200486 imply CMD_NAND
487 help
488 This enables Nand driver support for Nand flash controller
489 found on Zynq SoC.
490
491config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
492 bool "Enable use of 1st stage bootloader timing for NAND"
493 depends on NAND_ZYNQ
494 help
495 This flag prevent U-boot reconfigure NAND flash controller and reuse
496 the NAND timing from 1st stage bootloader.
497
Suneel Garapati9de7d2b2020-08-26 14:37:22 +0200498config NAND_OCTEONTX
499 bool "Support for OcteonTX NAND controller"
500 select SYS_NAND_SELF_INIT
501 imply CMD_NAND
502 help
503 This enables Nand flash controller hardware found on the OcteonTX
504 processors.
505
506config NAND_OCTEONTX_HW_ECC
507 bool "Support Hardware ECC for OcteonTX NAND controller"
508 depends on NAND_OCTEONTX
509 default y
510 help
511 This enables Hardware BCH engine found on the OcteonTX processors to
512 support ECC for NAND flash controller.
513
Christophe Kerelloda141682019-04-05 11:41:50 +0200514config NAND_STM32_FMC2
515 bool "Support for NAND controller on STM32MP SoCs"
516 depends on ARCH_STM32MP
517 select SYS_NAND_SELF_INIT
518 imply CMD_NAND
519 help
520 Enables support for NAND Flash chips on SoCs containing the FMC2
521 NAND controller. This controller is found on STM32MP SoCs.
522 The controller supports a maximum 8k page size and supports
523 a maximum 8-bit correction error per sector of 512 bytes.
524
Kate Liu41ccd2e2020-12-11 13:46:12 -0800525config CORTINA_NAND
526 bool "Support for NAND controller on Cortina-Access SoCs"
527 depends on CORTINA_PLATFORM
528 select SYS_NAND_SELF_INIT
529 select DM_MTD
530 imply CMD_NAND
531 help
532 Enables support for NAND Flash chips on Coartina-Access SoCs platform
533 This controller is found on Presidio/Venus SoCs.
534 The controller supports a maximum 8k page size and supports
535 a maximum 40-bit error correction per sector of 1024 bytes.
536
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800537config ROCKCHIP_NAND
538 bool "Support for NAND controller on Rockchip SoCs"
539 depends on ARCH_ROCKCHIP
540 select SYS_NAND_SELF_INIT
541 select DM_MTD
542 imply CMD_NAND
543 help
544 Enables support for NAND Flash chips on Rockchip SoCs platform.
545 This controller is found on Rockchip SoCs.
546 There are four different versions of NAND FLASH Controllers,
547 including:
548 NFC v600: RK2928, RK3066, RK3188
549 NFC v622: RK3036, RK3128
550 NFC v800: RK3308, RV1108
551 NFC v900: PX30, RK3326
552
Tom Rini8f37ac42021-12-12 22:12:35 -0500553config TEGRA_NAND
554 bool "Support for NAND controller on Tegra SoCs"
555 depends on ARCH_TEGRA
556 select SYS_NAND_SELF_INIT
557 imply CMD_NAND
558 help
559 Enables support for NAND Flash chips on Tegra SoCs platforms.
560
developer10a61df2022-05-20 11:23:47 +0800561config NAND_MT7621
562 bool "Support for MediaTek MT7621 NAND flash controller"
563 depends on SOC_MT7621
564 select SYS_NAND_SELF_INIT
565 select SPL_SYS_NAND_SELF_INIT
566 imply CMD_NAND
567 help
568 This enables NAND driver for the NAND flash controller on MediaTek
569 MT7621 platform.
570 The controller supports 4~12 bits correction per 512 bytes with a
571 maximum 4KB page size.
572
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200573comment "Generic NAND options"
574
575config SYS_NAND_BLOCK_SIZE
576 hex "NAND chip eraseblock size"
Tom Rinifae1dab2021-09-22 14:50:29 -0400577 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
developer10a61df2022-05-20 11:23:47 +0800578 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && \
579 !NAND_FSL_IFC && !NAND_MT7621
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200580 help
581 Number of data bytes in one eraseblock for the NAND chip on the
582 board. This is the multiple of NAND_PAGE_SIZE and the number of
583 pages.
584
Tom Rinifdae0072021-09-22 14:50:34 -0400585config SYS_NAND_ONFI_DETECTION
586 bool "Enable detection of ONFI compliant devices during probe"
587 help
588 Enables detection of ONFI compliant devices during probe.
589 And fetching device parameters flashed on device, by parsing
590 ONFI parameter page.
591
Tom Rini2510a812021-09-22 14:50:30 -0400592config SYS_NAND_PAGE_COUNT
593 hex "NAND chip page count"
594 depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
595 SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
596 help
597 Number of pages in the NAND chip.
598
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200599config SYS_NAND_PAGE_SIZE
600 hex "NAND chip page size"
Tom Rinifae1dab2021-09-22 14:50:29 -0400601 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
602 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
603 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
developer10a61df2022-05-20 11:23:47 +0800604 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200605 help
606 Number of data bytes in one page for the NAND chip on the
607 board, not including the OOB area.
608
609config SYS_NAND_OOBSIZE
610 hex "NAND chip OOB size"
Tom Rinifae1dab2021-09-22 14:50:29 -0400611 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
612 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
613 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
Tom Rinid24700f2021-10-30 23:03:56 -0400614 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200615 help
616 Number of bytes in the Out-Of-Band area for the NAND chip on
617 the board.
618
619# Enhance depends when converting drivers to Kconfig which use this config
620# option (mxc_nand, ndfc, omap_gpmc).
621config SYS_NAND_BUSWIDTH_16BIT
622 bool "Use 16-bit NAND interface"
623 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
624 help
625 Indicates that NAND device has 16-bit wide data-bus. In absence of this
626 config, bus-width of NAND device is assumed to be either 8-bit and later
627 determined by reading ONFI params.
628 Above config is useful when NAND device's bus-width information cannot
629 be determined from on-chip ONFI params, like in following scenarios:
630 - SPL boot does not support reading of ONFI parameters. This is done to
631 keep SPL code foot-print small.
632 - In current U-Boot flow using nand_init(), driver initialization
633 happens in board_nand_init() which is called before any device probe
634 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
635 not available while configuring controller. So a static CONFIG_NAND_xx
636 is needed to know the device's bus-width in advance.
637
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200638if SPL
639
Tom Rini8e6d9c72021-09-22 14:50:33 -0400640config SYS_NAND_5_ADDR_CYCLE
641 bool "Wait 5 address cycles during NAND commands"
642 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
643 (SPL_NAND_SUPPORT && NAND_ATMEL)
644 default y
645 help
646 Some controllers require waiting for 5 address cycles when issuing
647 some commands, on NAND chips larger than 128MiB.
648
Tom Rinia2fbd4a2021-09-22 14:50:32 -0400649choice
Tom Rinifdae0072021-09-22 14:50:34 -0400650 prompt "NAND bad block marker/indicator position in the OOB"
Tom Rinia2fbd4a2021-09-22 14:50:32 -0400651 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
652 SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
653 default HAS_NAND_LARGE_BADBLOCK_POS
654 help
655 In the OOB, which position contains the badblock information.
656
657config HAS_NAND_LARGE_BADBLOCK_POS
658 bool "Set the bad block marker/indicator to the 'large' position"
659
660config HAS_NAND_SMALL_BADBLOCK_POS
661 bool "Set the bad block marker/indicator to the 'small' position"
662
663endchoice
664
665config SYS_NAND_BAD_BLOCK_POS
666 int
667 default 0 if HAS_NAND_LARGE_BADBLOCK_POS
668 default 5 if HAS_NAND_SMALL_BADBLOCK_POS
669
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200670config SYS_NAND_U_BOOT_LOCATIONS
671 bool "Define U-boot binaries locations in NAND"
672 help
673 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
674 This option should not be enabled when compiling U-boot for boards
675 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
676 file.
677
678config SYS_NAND_U_BOOT_OFFS
679 hex "Location in NAND to read U-Boot from"
680 default 0x800000 if NAND_SUNXI
681 depends on SYS_NAND_U_BOOT_LOCATIONS
682 help
683 Set the offset from the start of the nand where u-boot should be
684 loaded from.
685
686config SYS_NAND_U_BOOT_OFFS_REDUND
687 hex "Location in NAND to read U-Boot from"
688 default SYS_NAND_U_BOOT_OFFS
689 depends on SYS_NAND_U_BOOT_LOCATIONS
690 help
691 Set the offset from the start of the nand where the redundant u-boot
692 should be loaded from.
693
694config SPL_NAND_AM33XX_BCH
695 bool "Enables SPL-NAND driver which supports ELM based"
Tom Rini0a83cc22022-06-10 23:03:09 -0400696 depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200697 default y
698 help
699 Hardware ECC correction. This is useful for platforms which have ELM
700 hardware engine and use NAND boot mode.
701 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
702 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
703 SPL-NAND driver with software ECC correction support.
704
705config SPL_NAND_DENALI
706 bool "Support Denali NAND controller for SPL"
Tom Rini0a83cc22022-06-10 23:03:09 -0400707 depends on SPL_NAND_SUPPORT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200708 help
709 This is a small implementation of the Denali NAND controller
710 for use on SPL.
711
Masahiro Yamada64648cb2020-04-17 16:51:42 +0900712config NAND_DENALI_SPARE_AREA_SKIP_BYTES
713 int "Number of bytes skipped in OOB area"
714 depends on SPL_NAND_DENALI
715 range 0 63
716 help
717 This option specifies the number of bytes to skip from the beginning
718 of OOB area before last ECC sector data starts. This is potentially
719 used to preserve the bad block marker in the OOB area.
720
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200721config SPL_NAND_SIMPLE
722 bool "Use simple SPL NAND driver"
Tom Rini0a83cc22022-06-10 23:03:09 -0400723 depends on !SPL_NAND_AM33XX_BCH && SPL_NAND_SUPPORT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200724 help
725 Support for NAND boot using simple NAND drivers that
726 expose the cmd_ctrl() interface.
Tom Rini4251f7d2022-11-12 17:36:44 -0500727
728config SYS_NAND_HW_ECC_OOBFIRST
729 bool "In SPL, read the OOB first and then the data from NAND"
730 depends on SPL_NAND_SIMPLE
731
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200732endif
733
734endif # if NAND