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Miquel Raynal1f1ae152018-08-16 17:30:07 +02001
Miquel Raynald0935362019-10-03 19:50:03 +02002menuconfig MTD_RAW_NAND
Miquel Raynal8115c452018-08-16 17:30:08 +02003 bool "Raw NAND Device Support"
Miquel Raynald0935362019-10-03 19:50:03 +02004if MTD_RAW_NAND
Miquel Raynal1f1ae152018-08-16 17:30:07 +02005
6config SYS_NAND_SELF_INIT
7 bool
8 help
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
11
Stefan Agnerbd186142018-12-06 14:57:09 +010012config SYS_NAND_DRIVER_ECC_LAYOUT
13 bool
14 help
15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
17
Stefan Roese23b37f92019-08-22 12:28:04 +020018config SYS_NAND_USE_FLASH_BBT
19 bool "Enable BBT (Bad Block Table) support"
20 help
21 Enable the BBT (Bad Block Table) usage.
22
Miquel Raynal1f1ae152018-08-16 17:30:07 +020023config NAND_ATMEL
24 bool "Support Atmel NAND controller"
25 imply SYS_NAND_USE_FLASH_BBT
26 help
27 Enable this driver for NAND flash platforms using an Atmel NAND
28 controller.
29
Derald D. Woods7830fc52018-12-15 01:36:46 -060030if NAND_ATMEL
31
32config ATMEL_NAND_HWECC
33 bool "Atmel Hardware ECC"
Derald D. Woods7830fc52018-12-15 01:36:46 -060034
35config ATMEL_NAND_HW_PMECC
36 bool "Atmel Programmable Multibit ECC (PMECC)"
37 select ATMEL_NAND_HWECC
Derald D. Woods7830fc52018-12-15 01:36:46 -060038 help
39 The Programmable Multibit ECC (PMECC) controller is a programmable
40 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
41
42config PMECC_CAP
43 int "PMECC Correctable ECC Bits"
44 depends on ATMEL_NAND_HW_PMECC
45 default 2
46 help
47 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
48
49config PMECC_SECTOR_SIZE
50 int "PMECC Sector Size"
51 depends on ATMEL_NAND_HW_PMECC
52 default 512
53 help
54 Sector size, in bytes, can be 512 or 1024.
55
56config SPL_GENERATE_ATMEL_PMECC_HEADER
57 bool "Atmel PMECC Header Generation"
58 select ATMEL_NAND_HWECC
59 select ATMEL_NAND_HW_PMECC
Derald D. Woods7830fc52018-12-15 01:36:46 -060060 help
61 Generate Programmable Multibit ECC (PMECC) header for SPL image.
62
63endif
64
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +010065config NAND_BRCMNAND
66 bool "Support Broadcom NAND controller"
Miquel Raynala903be42019-10-03 19:50:04 +020067 depends on OF_CONTROL && DM && DM_MTD
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +010068 help
69 Enable the driver for NAND flash on platforms using a Broadcom NAND
70 controller.
71
Álvaro Fernández Rojasd9f9bfc2019-08-28 19:12:15 +020072config NAND_BRCMNAND_6368
73 bool "Support Broadcom NAND controller on bcm6368"
74 depends on NAND_BRCMNAND && ARCH_BMIPS
75 help
76 Enable support for broadcom nand driver on bcm6368.
77
Philippe Reynes74ead742020-01-07 20:14:13 +010078config NAND_BRCMNAND_68360
79 bool "Support Broadcom NAND controller on bcm68360"
80 depends on NAND_BRCMNAND && ARCH_BCM68360
81 help
82 Enable support for broadcom nand driver on bcm68360.
83
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +010084config NAND_BRCMNAND_6838
85 bool "Support Broadcom NAND controller on bcm6838"
86 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
87 help
88 Enable support for broadcom nand driver on bcm6838.
89
90config NAND_BRCMNAND_6858
91 bool "Support Broadcom NAND controller on bcm6858"
92 depends on NAND_BRCMNAND && ARCH_BCM6858
93 help
94 Enable support for broadcom nand driver on bcm6858.
95
96config NAND_BRCMNAND_63158
97 bool "Support Broadcom NAND controller on bcm63158"
98 depends on NAND_BRCMNAND && ARCH_BCM63158
99 help
100 Enable support for broadcom nand driver on bcm63158.
101
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200102config NAND_DAVINCI
103 bool "Support TI Davinci NAND controller"
104 help
105 Enable this driver for NAND flash controllers available in TI Davinci
106 and Keystone2 platforms
107
Tom Rinidada0e32021-09-12 20:32:24 -0400108config KEYSTONE_RBL_NAND
109 depends on ARCH_KEYSTONE
110 def_bool y
111
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200112config NAND_DENALI
113 bool
114 select SYS_NAND_SELF_INIT
115 imply CMD_NAND
116
117config NAND_DENALI_DT
118 bool "Support Denali NAND controller as a DT device"
119 select NAND_DENALI
Masahiro Yamada8fc53822020-01-30 22:07:59 +0900120 depends on OF_CONTROL && DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200121 help
122 Enable the driver for NAND flash on platforms using a Denali NAND
123 controller as a DT device.
124
Tom Rini08204272021-09-22 14:50:28 -0400125config NAND_LPC32XX_MLC
126 bool "Support LPC32XX_MLC controller"
127 help
128 Enable the LPC32XX MLC NAND controller.
129
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200130config NAND_LPC32XX_SLC
131 bool "Support LPC32XX_SLC controller"
132 help
133 Enable the LPC32XX SLC NAND controller.
134
135config NAND_OMAP_GPMC
136 bool "Support OMAP GPMC NAND controller"
137 depends on ARCH_OMAP2PLUS
138 help
139 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
140 GPMC controller is used for parallel NAND flash devices, and can
141 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
142 and BCH16 ECC algorithms.
143
144config NAND_OMAP_GPMC_PREFETCH
145 bool "Enable GPMC Prefetch"
146 depends on NAND_OMAP_GPMC
147 default y
148 help
149 On OMAP platforms that use the GPMC controller
150 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
151 uses the prefetch mode to speed up read operations.
152
153config NAND_OMAP_ELM
154 bool "Enable ELM driver for OMAPxx and AMxx platforms."
155 depends on NAND_OMAP_GPMC && !OMAP34XX
156 help
157 ELM controller is used for ECC error detection (not ECC calculation)
158 of BCH4, BCH8 and BCH16 ECC algorithms.
159 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
160 thus such SoC platforms need to depend on software library for ECC error
161 detection. However ECC calculation on such plaforms would still be
162 done by GPMC controller.
163
164config NAND_VF610_NFC
165 bool "Support for Freescale NFC for VF610"
166 select SYS_NAND_SELF_INIT
Stefan Agnerbd186142018-12-06 14:57:09 +0100167 select SYS_NAND_DRIVER_ECC_LAYOUT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200168 imply CMD_NAND
169 help
170 Enables support for NAND Flash Controller on some Freescale
171 processors like the VF610, MCF54418 or Kinetis K70.
172 The driver supports a maximum 2k page size. The driver
173 currently does not support hardware ECC.
174
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100175if NAND_VF610_NFC
176
177config NAND_VF610_NFC_DT
178 bool "Support Vybrid's vf610 NAND controller as a DT device"
Miquel Raynala903be42019-10-03 19:50:04 +0200179 depends on OF_CONTROL && DM_MTD
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100180 help
181 Enable the driver for Vybrid's vf610 NAND flash on platforms
182 using device tree.
183
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200184choice
185 prompt "Hardware ECC strength"
186 depends on NAND_VF610_NFC
187 default SYS_NAND_VF610_NFC_45_ECC_BYTES
188 help
189 Select the ECC strength used in the hardware BCH ECC block.
190
191config SYS_NAND_VF610_NFC_45_ECC_BYTES
192 bool "24-error correction (45 ECC bytes)"
193
194config SYS_NAND_VF610_NFC_60_ECC_BYTES
195 bool "32-error correction (60 ECC bytes)"
196
197endchoice
198
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100199endif
200
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200201config NAND_PXA3XX
202 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
203 select SYS_NAND_SELF_INIT
Shmuel Hazan759349e2020-10-29 08:52:18 +0200204 select DM_MTD
Shmuel Hazan58983222020-10-29 08:52:20 +0200205 select REGMAP
206 select SYSCON
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200207 imply CMD_NAND
208 help
209 This enables the driver for the NAND flash device found on
210 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
211
212config NAND_SUNXI
213 bool "Support for NAND on Allwinner SoCs"
214 default ARCH_SUNXI
215 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
216 select SYS_NAND_SELF_INIT
217 select SYS_NAND_U_BOOT_LOCATIONS
218 select SPL_NAND_SUPPORT
219 imply CMD_NAND
220 ---help---
221 Enable support for NAND. This option enables the standard and
222 SPL drivers.
223 The SPL driver only supports reading from the NAND using DMA
224 transfers.
225
226if NAND_SUNXI
227
228config NAND_SUNXI_SPL_ECC_STRENGTH
229 int "Allwinner NAND SPL ECC Strength"
230 default 64
231
232config NAND_SUNXI_SPL_ECC_SIZE
233 int "Allwinner NAND SPL ECC Step Size"
234 default 1024
235
236config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
237 int "Allwinner NAND SPL Usable Page Size"
238 default 1024
239
240endif
241
242config NAND_ARASAN
243 bool "Configure Arasan Nand"
244 select SYS_NAND_SELF_INIT
Michal Simekc5587832020-08-19 09:59:52 +0200245 depends on DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200246 imply CMD_NAND
247 help
248 This enables Nand driver support for Arasan nand flash
249 controller. This uses the hardware ECC for read and
250 write operations.
251
252config NAND_MXC
253 bool "MXC NAND support"
254 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
255 imply CMD_NAND
256 help
257 This enables the NAND driver for the NAND flash controller on the
258 i.MX27 / i.MX31 / i.MX5 rocessors.
259
260config NAND_MXS
261 bool "MXS NAND support"
Peng Fan128abf42020-05-04 22:09:00 +0800262 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200263 select SYS_NAND_SELF_INIT
264 imply CMD_NAND
265 select APBH_DMA
Peng Fan128abf42020-05-04 22:09:00 +0800266 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
267 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200268 help
269 This enables NAND driver for the NAND flash controller on the
270 MXS processors.
271
272if NAND_MXS
273
274config NAND_MXS_DT
275 bool "Support MXS NAND controller as a DT device"
Miquel Raynala903be42019-10-03 19:50:04 +0200276 depends on OF_CONTROL && DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200277 help
278 Enable the driver for MXS NAND flash on platforms using
279 device tree.
280
281config NAND_MXS_USE_MINIMUM_ECC
282 bool "Use minimum ECC strength supported by the controller"
283 default false
284
285endif
286
287config NAND_ZYNQ
288 bool "Support for Zynq Nand controller"
289 select SYS_NAND_SELF_INIT
Ashok Reddy Somabb8448a2019-12-27 04:47:12 -0700290 select DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200291 imply CMD_NAND
292 help
293 This enables Nand driver support for Nand flash controller
294 found on Zynq SoC.
295
296config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
297 bool "Enable use of 1st stage bootloader timing for NAND"
298 depends on NAND_ZYNQ
299 help
300 This flag prevent U-boot reconfigure NAND flash controller and reuse
301 the NAND timing from 1st stage bootloader.
302
Suneel Garapati9de7d2b2020-08-26 14:37:22 +0200303config NAND_OCTEONTX
304 bool "Support for OcteonTX NAND controller"
305 select SYS_NAND_SELF_INIT
306 imply CMD_NAND
307 help
308 This enables Nand flash controller hardware found on the OcteonTX
309 processors.
310
311config NAND_OCTEONTX_HW_ECC
312 bool "Support Hardware ECC for OcteonTX NAND controller"
313 depends on NAND_OCTEONTX
314 default y
315 help
316 This enables Hardware BCH engine found on the OcteonTX processors to
317 support ECC for NAND flash controller.
318
Christophe Kerelloda141682019-04-05 11:41:50 +0200319config NAND_STM32_FMC2
320 bool "Support for NAND controller on STM32MP SoCs"
321 depends on ARCH_STM32MP
322 select SYS_NAND_SELF_INIT
323 imply CMD_NAND
324 help
325 Enables support for NAND Flash chips on SoCs containing the FMC2
326 NAND controller. This controller is found on STM32MP SoCs.
327 The controller supports a maximum 8k page size and supports
328 a maximum 8-bit correction error per sector of 512 bytes.
329
Kate Liu41ccd2e2020-12-11 13:46:12 -0800330config CORTINA_NAND
331 bool "Support for NAND controller on Cortina-Access SoCs"
332 depends on CORTINA_PLATFORM
333 select SYS_NAND_SELF_INIT
334 select DM_MTD
335 imply CMD_NAND
336 help
337 Enables support for NAND Flash chips on Coartina-Access SoCs platform
338 This controller is found on Presidio/Venus SoCs.
339 The controller supports a maximum 8k page size and supports
340 a maximum 40-bit error correction per sector of 1024 bytes.
341
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800342config ROCKCHIP_NAND
343 bool "Support for NAND controller on Rockchip SoCs"
344 depends on ARCH_ROCKCHIP
345 select SYS_NAND_SELF_INIT
346 select DM_MTD
347 imply CMD_NAND
348 help
349 Enables support for NAND Flash chips on Rockchip SoCs platform.
350 This controller is found on Rockchip SoCs.
351 There are four different versions of NAND FLASH Controllers,
352 including:
353 NFC v600: RK2928, RK3066, RK3188
354 NFC v622: RK3036, RK3128
355 NFC v800: RK3308, RV1108
356 NFC v900: PX30, RK3326
357
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200358comment "Generic NAND options"
359
360config SYS_NAND_BLOCK_SIZE
361 hex "NAND chip eraseblock size"
362 depends on ARCH_SUNXI
363 help
364 Number of data bytes in one eraseblock for the NAND chip on the
365 board. This is the multiple of NAND_PAGE_SIZE and the number of
366 pages.
367
368config SYS_NAND_PAGE_SIZE
369 hex "NAND chip page size"
370 depends on ARCH_SUNXI
371 help
372 Number of data bytes in one page for the NAND chip on the
373 board, not including the OOB area.
374
375config SYS_NAND_OOBSIZE
376 hex "NAND chip OOB size"
377 depends on ARCH_SUNXI
378 help
379 Number of bytes in the Out-Of-Band area for the NAND chip on
380 the board.
381
382# Enhance depends when converting drivers to Kconfig which use this config
383# option (mxc_nand, ndfc, omap_gpmc).
384config SYS_NAND_BUSWIDTH_16BIT
385 bool "Use 16-bit NAND interface"
386 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
387 help
388 Indicates that NAND device has 16-bit wide data-bus. In absence of this
389 config, bus-width of NAND device is assumed to be either 8-bit and later
390 determined by reading ONFI params.
391 Above config is useful when NAND device's bus-width information cannot
392 be determined from on-chip ONFI params, like in following scenarios:
393 - SPL boot does not support reading of ONFI parameters. This is done to
394 keep SPL code foot-print small.
395 - In current U-Boot flow using nand_init(), driver initialization
396 happens in board_nand_init() which is called before any device probe
397 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
398 not available while configuring controller. So a static CONFIG_NAND_xx
399 is needed to know the device's bus-width in advance.
400
T Karthik Reddy7cd85222018-12-03 16:11:58 +0530401config SYS_NAND_MAX_CHIPS
402 int "NAND max chips"
403 default 1
404 depends on NAND_ARASAN
405 help
406 The maximum number of NAND chips per device to be supported.
407
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200408if SPL
409
410config SYS_NAND_U_BOOT_LOCATIONS
411 bool "Define U-boot binaries locations in NAND"
412 help
413 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
414 This option should not be enabled when compiling U-boot for boards
415 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
416 file.
417
418config SYS_NAND_U_BOOT_OFFS
419 hex "Location in NAND to read U-Boot from"
420 default 0x800000 if NAND_SUNXI
421 depends on SYS_NAND_U_BOOT_LOCATIONS
422 help
423 Set the offset from the start of the nand where u-boot should be
424 loaded from.
425
426config SYS_NAND_U_BOOT_OFFS_REDUND
427 hex "Location in NAND to read U-Boot from"
428 default SYS_NAND_U_BOOT_OFFS
429 depends on SYS_NAND_U_BOOT_LOCATIONS
430 help
431 Set the offset from the start of the nand where the redundant u-boot
432 should be loaded from.
433
434config SPL_NAND_AM33XX_BCH
435 bool "Enables SPL-NAND driver which supports ELM based"
436 depends on NAND_OMAP_GPMC && !OMAP34XX
437 default y
438 help
439 Hardware ECC correction. This is useful for platforms which have ELM
440 hardware engine and use NAND boot mode.
441 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
442 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
443 SPL-NAND driver with software ECC correction support.
444
445config SPL_NAND_DENALI
446 bool "Support Denali NAND controller for SPL"
447 help
448 This is a small implementation of the Denali NAND controller
449 for use on SPL.
450
Masahiro Yamada64648cb2020-04-17 16:51:42 +0900451config NAND_DENALI_SPARE_AREA_SKIP_BYTES
452 int "Number of bytes skipped in OOB area"
453 depends on SPL_NAND_DENALI
454 range 0 63
455 help
456 This option specifies the number of bytes to skip from the beginning
457 of OOB area before last ECC sector data starts. This is potentially
458 used to preserve the bad block marker in the OOB area.
459
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200460config SPL_NAND_SIMPLE
461 bool "Use simple SPL NAND driver"
462 depends on !SPL_NAND_AM33XX_BCH
463 help
464 Support for NAND boot using simple NAND drivers that
465 expose the cmd_ctrl() interface.
466endif
467
468endif # if NAND