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Miquel Raynal1f1ae152018-08-16 17:30:07 +02001
Miquel Raynald0935362019-10-03 19:50:03 +02002menuconfig MTD_RAW_NAND
Miquel Raynal8115c452018-08-16 17:30:08 +02003 bool "Raw NAND Device Support"
Miquel Raynald0935362019-10-03 19:50:03 +02004if MTD_RAW_NAND
Miquel Raynal1f1ae152018-08-16 17:30:07 +02005
6config SYS_NAND_SELF_INIT
7 bool
8 help
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
11
Stefan Agnerbd186142018-12-06 14:57:09 +010012config SYS_NAND_DRIVER_ECC_LAYOUT
13 bool
14 help
15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
17
Stefan Roese23b37f92019-08-22 12:28:04 +020018config SYS_NAND_USE_FLASH_BBT
19 bool "Enable BBT (Bad Block Table) support"
20 help
21 Enable the BBT (Bad Block Table) usage.
22
Miquel Raynal1f1ae152018-08-16 17:30:07 +020023config NAND_ATMEL
24 bool "Support Atmel NAND controller"
25 imply SYS_NAND_USE_FLASH_BBT
26 help
27 Enable this driver for NAND flash platforms using an Atmel NAND
28 controller.
29
Derald D. Woods7830fc52018-12-15 01:36:46 -060030if NAND_ATMEL
31
32config ATMEL_NAND_HWECC
33 bool "Atmel Hardware ECC"
Derald D. Woods7830fc52018-12-15 01:36:46 -060034
35config ATMEL_NAND_HW_PMECC
36 bool "Atmel Programmable Multibit ECC (PMECC)"
37 select ATMEL_NAND_HWECC
Derald D. Woods7830fc52018-12-15 01:36:46 -060038 help
39 The Programmable Multibit ECC (PMECC) controller is a programmable
40 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
41
42config PMECC_CAP
43 int "PMECC Correctable ECC Bits"
44 depends on ATMEL_NAND_HW_PMECC
45 default 2
46 help
47 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
48
49config PMECC_SECTOR_SIZE
50 int "PMECC Sector Size"
51 depends on ATMEL_NAND_HW_PMECC
52 default 512
53 help
54 Sector size, in bytes, can be 512 or 1024.
55
56config SPL_GENERATE_ATMEL_PMECC_HEADER
57 bool "Atmel PMECC Header Generation"
58 select ATMEL_NAND_HWECC
59 select ATMEL_NAND_HW_PMECC
Derald D. Woods7830fc52018-12-15 01:36:46 -060060 help
61 Generate Programmable Multibit ECC (PMECC) header for SPL image.
62
63endif
64
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +010065config NAND_BRCMNAND
66 bool "Support Broadcom NAND controller"
Miquel Raynala903be42019-10-03 19:50:04 +020067 depends on OF_CONTROL && DM && DM_MTD
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +010068 help
69 Enable the driver for NAND flash on platforms using a Broadcom NAND
70 controller.
71
Álvaro Fernández Rojasd9f9bfc2019-08-28 19:12:15 +020072config NAND_BRCMNAND_6368
73 bool "Support Broadcom NAND controller on bcm6368"
74 depends on NAND_BRCMNAND && ARCH_BMIPS
75 help
76 Enable support for broadcom nand driver on bcm6368.
77
Philippe Reynes74ead742020-01-07 20:14:13 +010078config NAND_BRCMNAND_68360
79 bool "Support Broadcom NAND controller on bcm68360"
80 depends on NAND_BRCMNAND && ARCH_BCM68360
81 help
82 Enable support for broadcom nand driver on bcm68360.
83
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +010084config NAND_BRCMNAND_6838
85 bool "Support Broadcom NAND controller on bcm6838"
86 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
87 help
88 Enable support for broadcom nand driver on bcm6838.
89
90config NAND_BRCMNAND_6858
91 bool "Support Broadcom NAND controller on bcm6858"
92 depends on NAND_BRCMNAND && ARCH_BCM6858
93 help
94 Enable support for broadcom nand driver on bcm6858.
95
96config NAND_BRCMNAND_63158
97 bool "Support Broadcom NAND controller on bcm63158"
98 depends on NAND_BRCMNAND && ARCH_BCM63158
99 help
100 Enable support for broadcom nand driver on bcm63158.
101
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200102config NAND_DAVINCI
103 bool "Support TI Davinci NAND controller"
104 help
105 Enable this driver for NAND flash controllers available in TI Davinci
106 and Keystone2 platforms
107
Tom Rinidada0e32021-09-12 20:32:24 -0400108config KEYSTONE_RBL_NAND
109 depends on ARCH_KEYSTONE
110 def_bool y
111
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200112config NAND_DENALI
113 bool
114 select SYS_NAND_SELF_INIT
115 imply CMD_NAND
116
117config NAND_DENALI_DT
118 bool "Support Denali NAND controller as a DT device"
119 select NAND_DENALI
Masahiro Yamada8fc53822020-01-30 22:07:59 +0900120 depends on OF_CONTROL && DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200121 help
122 Enable the driver for NAND flash on platforms using a Denali NAND
123 controller as a DT device.
124
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200125config NAND_LPC32XX_SLC
126 bool "Support LPC32XX_SLC controller"
127 help
128 Enable the LPC32XX SLC NAND controller.
129
130config NAND_OMAP_GPMC
131 bool "Support OMAP GPMC NAND controller"
132 depends on ARCH_OMAP2PLUS
133 help
134 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
135 GPMC controller is used for parallel NAND flash devices, and can
136 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
137 and BCH16 ECC algorithms.
138
139config NAND_OMAP_GPMC_PREFETCH
140 bool "Enable GPMC Prefetch"
141 depends on NAND_OMAP_GPMC
142 default y
143 help
144 On OMAP platforms that use the GPMC controller
145 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
146 uses the prefetch mode to speed up read operations.
147
148config NAND_OMAP_ELM
149 bool "Enable ELM driver for OMAPxx and AMxx platforms."
150 depends on NAND_OMAP_GPMC && !OMAP34XX
151 help
152 ELM controller is used for ECC error detection (not ECC calculation)
153 of BCH4, BCH8 and BCH16 ECC algorithms.
154 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
155 thus such SoC platforms need to depend on software library for ECC error
156 detection. However ECC calculation on such plaforms would still be
157 done by GPMC controller.
158
159config NAND_VF610_NFC
160 bool "Support for Freescale NFC for VF610"
161 select SYS_NAND_SELF_INIT
Stefan Agnerbd186142018-12-06 14:57:09 +0100162 select SYS_NAND_DRIVER_ECC_LAYOUT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200163 imply CMD_NAND
164 help
165 Enables support for NAND Flash Controller on some Freescale
166 processors like the VF610, MCF54418 or Kinetis K70.
167 The driver supports a maximum 2k page size. The driver
168 currently does not support hardware ECC.
169
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100170if NAND_VF610_NFC
171
172config NAND_VF610_NFC_DT
173 bool "Support Vybrid's vf610 NAND controller as a DT device"
Miquel Raynala903be42019-10-03 19:50:04 +0200174 depends on OF_CONTROL && DM_MTD
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100175 help
176 Enable the driver for Vybrid's vf610 NAND flash on platforms
177 using device tree.
178
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200179choice
180 prompt "Hardware ECC strength"
181 depends on NAND_VF610_NFC
182 default SYS_NAND_VF610_NFC_45_ECC_BYTES
183 help
184 Select the ECC strength used in the hardware BCH ECC block.
185
186config SYS_NAND_VF610_NFC_45_ECC_BYTES
187 bool "24-error correction (45 ECC bytes)"
188
189config SYS_NAND_VF610_NFC_60_ECC_BYTES
190 bool "32-error correction (60 ECC bytes)"
191
192endchoice
193
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100194endif
195
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200196config NAND_PXA3XX
197 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
198 select SYS_NAND_SELF_INIT
Shmuel Hazan759349e2020-10-29 08:52:18 +0200199 select DM_MTD
Shmuel Hazan58983222020-10-29 08:52:20 +0200200 select REGMAP
201 select SYSCON
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200202 imply CMD_NAND
203 help
204 This enables the driver for the NAND flash device found on
205 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
206
207config NAND_SUNXI
208 bool "Support for NAND on Allwinner SoCs"
209 default ARCH_SUNXI
210 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
211 select SYS_NAND_SELF_INIT
212 select SYS_NAND_U_BOOT_LOCATIONS
213 select SPL_NAND_SUPPORT
214 imply CMD_NAND
215 ---help---
216 Enable support for NAND. This option enables the standard and
217 SPL drivers.
218 The SPL driver only supports reading from the NAND using DMA
219 transfers.
220
221if NAND_SUNXI
222
223config NAND_SUNXI_SPL_ECC_STRENGTH
224 int "Allwinner NAND SPL ECC Strength"
225 default 64
226
227config NAND_SUNXI_SPL_ECC_SIZE
228 int "Allwinner NAND SPL ECC Step Size"
229 default 1024
230
231config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
232 int "Allwinner NAND SPL Usable Page Size"
233 default 1024
234
235endif
236
237config NAND_ARASAN
238 bool "Configure Arasan Nand"
239 select SYS_NAND_SELF_INIT
Michal Simekc5587832020-08-19 09:59:52 +0200240 depends on DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200241 imply CMD_NAND
242 help
243 This enables Nand driver support for Arasan nand flash
244 controller. This uses the hardware ECC for read and
245 write operations.
246
247config NAND_MXC
248 bool "MXC NAND support"
249 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
250 imply CMD_NAND
251 help
252 This enables the NAND driver for the NAND flash controller on the
253 i.MX27 / i.MX31 / i.MX5 rocessors.
254
255config NAND_MXS
256 bool "MXS NAND support"
Peng Fan128abf42020-05-04 22:09:00 +0800257 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200258 select SYS_NAND_SELF_INIT
259 imply CMD_NAND
260 select APBH_DMA
Peng Fan128abf42020-05-04 22:09:00 +0800261 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
262 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200263 help
264 This enables NAND driver for the NAND flash controller on the
265 MXS processors.
266
267if NAND_MXS
268
269config NAND_MXS_DT
270 bool "Support MXS NAND controller as a DT device"
Miquel Raynala903be42019-10-03 19:50:04 +0200271 depends on OF_CONTROL && DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200272 help
273 Enable the driver for MXS NAND flash on platforms using
274 device tree.
275
276config NAND_MXS_USE_MINIMUM_ECC
277 bool "Use minimum ECC strength supported by the controller"
278 default false
279
280endif
281
282config NAND_ZYNQ
283 bool "Support for Zynq Nand controller"
284 select SYS_NAND_SELF_INIT
Ashok Reddy Somabb8448a2019-12-27 04:47:12 -0700285 select DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200286 imply CMD_NAND
287 help
288 This enables Nand driver support for Nand flash controller
289 found on Zynq SoC.
290
291config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
292 bool "Enable use of 1st stage bootloader timing for NAND"
293 depends on NAND_ZYNQ
294 help
295 This flag prevent U-boot reconfigure NAND flash controller and reuse
296 the NAND timing from 1st stage bootloader.
297
Suneel Garapati9de7d2b2020-08-26 14:37:22 +0200298config NAND_OCTEONTX
299 bool "Support for OcteonTX NAND controller"
300 select SYS_NAND_SELF_INIT
301 imply CMD_NAND
302 help
303 This enables Nand flash controller hardware found on the OcteonTX
304 processors.
305
306config NAND_OCTEONTX_HW_ECC
307 bool "Support Hardware ECC for OcteonTX NAND controller"
308 depends on NAND_OCTEONTX
309 default y
310 help
311 This enables Hardware BCH engine found on the OcteonTX processors to
312 support ECC for NAND flash controller.
313
Christophe Kerelloda141682019-04-05 11:41:50 +0200314config NAND_STM32_FMC2
315 bool "Support for NAND controller on STM32MP SoCs"
316 depends on ARCH_STM32MP
317 select SYS_NAND_SELF_INIT
318 imply CMD_NAND
319 help
320 Enables support for NAND Flash chips on SoCs containing the FMC2
321 NAND controller. This controller is found on STM32MP SoCs.
322 The controller supports a maximum 8k page size and supports
323 a maximum 8-bit correction error per sector of 512 bytes.
324
Kate Liu41ccd2e2020-12-11 13:46:12 -0800325config CORTINA_NAND
326 bool "Support for NAND controller on Cortina-Access SoCs"
327 depends on CORTINA_PLATFORM
328 select SYS_NAND_SELF_INIT
329 select DM_MTD
330 imply CMD_NAND
331 help
332 Enables support for NAND Flash chips on Coartina-Access SoCs platform
333 This controller is found on Presidio/Venus SoCs.
334 The controller supports a maximum 8k page size and supports
335 a maximum 40-bit error correction per sector of 1024 bytes.
336
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800337config ROCKCHIP_NAND
338 bool "Support for NAND controller on Rockchip SoCs"
339 depends on ARCH_ROCKCHIP
340 select SYS_NAND_SELF_INIT
341 select DM_MTD
342 imply CMD_NAND
343 help
344 Enables support for NAND Flash chips on Rockchip SoCs platform.
345 This controller is found on Rockchip SoCs.
346 There are four different versions of NAND FLASH Controllers,
347 including:
348 NFC v600: RK2928, RK3066, RK3188
349 NFC v622: RK3036, RK3128
350 NFC v800: RK3308, RV1108
351 NFC v900: PX30, RK3326
352
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200353comment "Generic NAND options"
354
355config SYS_NAND_BLOCK_SIZE
356 hex "NAND chip eraseblock size"
357 depends on ARCH_SUNXI
358 help
359 Number of data bytes in one eraseblock for the NAND chip on the
360 board. This is the multiple of NAND_PAGE_SIZE and the number of
361 pages.
362
363config SYS_NAND_PAGE_SIZE
364 hex "NAND chip page size"
365 depends on ARCH_SUNXI
366 help
367 Number of data bytes in one page for the NAND chip on the
368 board, not including the OOB area.
369
370config SYS_NAND_OOBSIZE
371 hex "NAND chip OOB size"
372 depends on ARCH_SUNXI
373 help
374 Number of bytes in the Out-Of-Band area for the NAND chip on
375 the board.
376
377# Enhance depends when converting drivers to Kconfig which use this config
378# option (mxc_nand, ndfc, omap_gpmc).
379config SYS_NAND_BUSWIDTH_16BIT
380 bool "Use 16-bit NAND interface"
381 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
382 help
383 Indicates that NAND device has 16-bit wide data-bus. In absence of this
384 config, bus-width of NAND device is assumed to be either 8-bit and later
385 determined by reading ONFI params.
386 Above config is useful when NAND device's bus-width information cannot
387 be determined from on-chip ONFI params, like in following scenarios:
388 - SPL boot does not support reading of ONFI parameters. This is done to
389 keep SPL code foot-print small.
390 - In current U-Boot flow using nand_init(), driver initialization
391 happens in board_nand_init() which is called before any device probe
392 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
393 not available while configuring controller. So a static CONFIG_NAND_xx
394 is needed to know the device's bus-width in advance.
395
T Karthik Reddy7cd85222018-12-03 16:11:58 +0530396config SYS_NAND_MAX_CHIPS
397 int "NAND max chips"
398 default 1
399 depends on NAND_ARASAN
400 help
401 The maximum number of NAND chips per device to be supported.
402
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200403if SPL
404
405config SYS_NAND_U_BOOT_LOCATIONS
406 bool "Define U-boot binaries locations in NAND"
407 help
408 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
409 This option should not be enabled when compiling U-boot for boards
410 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
411 file.
412
413config SYS_NAND_U_BOOT_OFFS
414 hex "Location in NAND to read U-Boot from"
415 default 0x800000 if NAND_SUNXI
416 depends on SYS_NAND_U_BOOT_LOCATIONS
417 help
418 Set the offset from the start of the nand where u-boot should be
419 loaded from.
420
421config SYS_NAND_U_BOOT_OFFS_REDUND
422 hex "Location in NAND to read U-Boot from"
423 default SYS_NAND_U_BOOT_OFFS
424 depends on SYS_NAND_U_BOOT_LOCATIONS
425 help
426 Set the offset from the start of the nand where the redundant u-boot
427 should be loaded from.
428
429config SPL_NAND_AM33XX_BCH
430 bool "Enables SPL-NAND driver which supports ELM based"
431 depends on NAND_OMAP_GPMC && !OMAP34XX
432 default y
433 help
434 Hardware ECC correction. This is useful for platforms which have ELM
435 hardware engine and use NAND boot mode.
436 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
437 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
438 SPL-NAND driver with software ECC correction support.
439
440config SPL_NAND_DENALI
441 bool "Support Denali NAND controller for SPL"
442 help
443 This is a small implementation of the Denali NAND controller
444 for use on SPL.
445
Masahiro Yamada64648cb2020-04-17 16:51:42 +0900446config NAND_DENALI_SPARE_AREA_SKIP_BYTES
447 int "Number of bytes skipped in OOB area"
448 depends on SPL_NAND_DENALI
449 range 0 63
450 help
451 This option specifies the number of bytes to skip from the beginning
452 of OOB area before last ECC sector data starts. This is potentially
453 used to preserve the bad block marker in the OOB area.
454
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200455config SPL_NAND_SIMPLE
456 bool "Use simple SPL NAND driver"
457 depends on !SPL_NAND_AM33XX_BCH
458 help
459 Support for NAND boot using simple NAND drivers that
460 expose the cmd_ctrl() interface.
461endif
462
463endif # if NAND