blob: 338a3562a4ac9deb4e0c02a39486059fad4aca02 [file] [log] [blame]
Miquel Raynal1f1ae152018-08-16 17:30:07 +02001
Miquel Raynald0935362019-10-03 19:50:03 +02002menuconfig MTD_RAW_NAND
Miquel Raynal8115c452018-08-16 17:30:08 +02003 bool "Raw NAND Device Support"
Miquel Raynald0935362019-10-03 19:50:03 +02004if MTD_RAW_NAND
Miquel Raynal1f1ae152018-08-16 17:30:07 +02005
6config SYS_NAND_SELF_INIT
7 bool
8 help
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
11
Tom Rini98372452021-12-12 22:12:36 -050012config SPL_SYS_NAND_SELF_INIT
13 bool
14 depends on !SPL_NAND_SIMPLE
15 help
16 This option, if enabled, provides more flexible and linux-like
17 NAND initialization process, in SPL.
18
19config TPL_SYS_NAND_SELF_INIT
20 bool
21 depends on TPL_NAND_SUPPORT
22 help
23 This option, if enabled, provides more flexible and linux-like
24 NAND initialization process, in SPL.
25
Tom Rini1a9f23d2022-05-26 14:31:57 -040026config TPL_NAND_INIT
27 bool
28
Tom Riniac164de2022-10-28 20:27:04 -040029config SYS_MAX_NAND_DEVICE
30 int "Maximum number of NAND devices to support"
31 default 1
32
Stefan Agnerbd186142018-12-06 14:57:09 +010033config SYS_NAND_DRIVER_ECC_LAYOUT
Tom Rinid03e14e2021-12-11 14:55:54 -050034 bool "Omit standard ECC layouts to save space"
Stefan Agnerbd186142018-12-06 14:57:09 +010035 help
Tom Rinid03e14e2021-12-11 14:55:54 -050036 Omit standard ECC layouts to save space. Select this if your driver
Stefan Agnerbd186142018-12-06 14:57:09 +010037 is known to provide its own ECC layout.
38
Stefan Roese23b37f92019-08-22 12:28:04 +020039config SYS_NAND_USE_FLASH_BBT
40 bool "Enable BBT (Bad Block Table) support"
41 help
42 Enable the BBT (Bad Block Table) usage.
43
Tom Rini2b2696a2022-11-12 17:36:48 -050044config SYS_NAND_NO_SUBPAGE_WRITE
45 bool "Disable subpage write support"
46 depends on NAND_ARASAN || NAND_DAVINCI || NAND_KIRKWOOD
47
Miquel Raynal1f1ae152018-08-16 17:30:07 +020048config NAND_ATMEL
49 bool "Support Atmel NAND controller"
Tom Rini98372452021-12-12 22:12:36 -050050 select SYS_NAND_SELF_INIT
Miquel Raynal1f1ae152018-08-16 17:30:07 +020051 imply SYS_NAND_USE_FLASH_BBT
52 help
53 Enable this driver for NAND flash platforms using an Atmel NAND
54 controller.
55
Derald D. Woods7830fc52018-12-15 01:36:46 -060056if NAND_ATMEL
57
58config ATMEL_NAND_HWECC
59 bool "Atmel Hardware ECC"
Derald D. Woods7830fc52018-12-15 01:36:46 -060060
61config ATMEL_NAND_HW_PMECC
62 bool "Atmel Programmable Multibit ECC (PMECC)"
63 select ATMEL_NAND_HWECC
Derald D. Woods7830fc52018-12-15 01:36:46 -060064 help
65 The Programmable Multibit ECC (PMECC) controller is a programmable
66 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
67
68config PMECC_CAP
69 int "PMECC Correctable ECC Bits"
70 depends on ATMEL_NAND_HW_PMECC
71 default 2
72 help
73 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
74
75config PMECC_SECTOR_SIZE
76 int "PMECC Sector Size"
77 depends on ATMEL_NAND_HW_PMECC
78 default 512
79 help
80 Sector size, in bytes, can be 512 or 1024.
81
82config SPL_GENERATE_ATMEL_PMECC_HEADER
83 bool "Atmel PMECC Header Generation"
Tom Rini0a83cc22022-06-10 23:03:09 -040084 depends on SPL
Derald D. Woods7830fc52018-12-15 01:36:46 -060085 select ATMEL_NAND_HWECC
86 select ATMEL_NAND_HW_PMECC
Derald D. Woods7830fc52018-12-15 01:36:46 -060087 help
88 Generate Programmable Multibit ECC (PMECC) header for SPL image.
89
Tom Rini70aa87d2022-11-12 17:36:42 -050090choice
91 prompt "NAND bus width (bits)"
92 default SYS_NAND_DBW_8
93
94config SYS_NAND_DBW_8
95 bool "NAND bus width is 8 bits"
96
97config SYS_NAND_DBW_16
98 bool "NAND bus width is 16 bits"
99
100endchoice
101
Derald D. Woods7830fc52018-12-15 01:36:46 -0600102endif
103
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100104config NAND_BRCMNAND
105 bool "Support Broadcom NAND controller"
Miquel Raynala903be42019-10-03 19:50:04 +0200106 depends on OF_CONTROL && DM && DM_MTD
Tom Rini98372452021-12-12 22:12:36 -0500107 select SYS_NAND_SELF_INIT
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100108 help
109 Enable the driver for NAND flash on platforms using a Broadcom NAND
110 controller.
111
Álvaro Fernández Rojasd9f9bfc2019-08-28 19:12:15 +0200112config NAND_BRCMNAND_6368
113 bool "Support Broadcom NAND controller on bcm6368"
114 depends on NAND_BRCMNAND && ARCH_BMIPS
115 help
116 Enable support for broadcom nand driver on bcm6368.
117
Philippe Reynese175c322022-02-11 19:18:36 +0100118config NAND_BRCMNAND_6753
119 bool "Support Broadcom NAND controller on bcm6753"
William Zhang38921822022-08-22 11:49:08 -0700120 depends on NAND_BRCMNAND && BCM6855
Philippe Reynese175c322022-02-11 19:18:36 +0100121 help
122 Enable support for broadcom nand driver on bcm6753.
123
Philippe Reynes74ead742020-01-07 20:14:13 +0100124config NAND_BRCMNAND_68360
125 bool "Support Broadcom NAND controller on bcm68360"
William Zhangdf0b5bb2022-08-22 11:31:43 -0700126 depends on NAND_BRCMNAND && BCM6856
Philippe Reynes74ead742020-01-07 20:14:13 +0100127 help
128 Enable support for broadcom nand driver on bcm68360.
129
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100130config NAND_BRCMNAND_6838
131 bool "Support Broadcom NAND controller on bcm6838"
132 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
133 help
134 Enable support for broadcom nand driver on bcm6838.
135
136config NAND_BRCMNAND_6858
137 bool "Support Broadcom NAND controller on bcm6858"
William Zhang6b45fa62022-08-22 11:39:45 -0700138 depends on NAND_BRCMNAND && BCM6858
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100139 help
140 Enable support for broadcom nand driver on bcm6858.
141
142config NAND_BRCMNAND_63158
143 bool "Support Broadcom NAND controller on bcm63158"
William Zhang35a3ec1b2022-08-22 11:19:46 -0700144 depends on NAND_BRCMNAND && BCM63158
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +0100145 help
146 Enable support for broadcom nand driver on bcm63158.
147
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200148config NAND_DAVINCI
149 bool "Support TI Davinci NAND controller"
Tom Rini98372452021-12-12 22:12:36 -0500150 select SYS_NAND_SELF_INIT if TARGET_DA850EVM
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200151 help
152 Enable this driver for NAND flash controllers available in TI Davinci
153 and Keystone2 platforms
154
Tom Rinid1286e12022-11-12 17:36:45 -0500155choice
156 prompt "Type of ECC used on NAND"
157 default SYS_NAND_4BIT_HW_ECC_OOBFIRST
158 depends on NAND_DAVINCI
159
160config SYS_NAND_HW_ECC
161 bool "Use 1-bit HW ECC"
162
Tom Rini7f750f82022-10-28 20:27:11 -0400163config SYS_NAND_4BIT_HW_ECC_OOBFIRST
164 bool "Use 4-bit HW ECC with OOB at the front"
Tom Rinid1286e12022-11-12 17:36:45 -0500165
166config SYS_NAND_SOFT_ECC
167 bool "Use software ECC"
168
169endchoice
Tom Rini7f750f82022-10-28 20:27:11 -0400170
Tom Rini33adefd2022-11-12 17:36:49 -0500171choice
172 prompt "NAND page size"
173 depends on NAND_DAVINCI
174 default SYS_NAND_PAGE_2K
175
176config SYS_NAND_PAGE_2K
177 bool "Page size is 2K"
178
179config SYS_NAND_PAGE_4K
180 bool "Page size is 4K"
181
182endchoice
183
Tom Rinidada0e32021-09-12 20:32:24 -0400184config KEYSTONE_RBL_NAND
185 depends on ARCH_KEYSTONE
186 def_bool y
187
Tom Rinifae1dab2021-09-22 14:50:29 -0400188config SPL_NAND_LOAD
189 def_bool y
190 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
191
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200192config NAND_DENALI
193 bool
194 select SYS_NAND_SELF_INIT
195 imply CMD_NAND
196
197config NAND_DENALI_DT
198 bool "Support Denali NAND controller as a DT device"
199 select NAND_DENALI
Masahiro Yamada8fc53822020-01-30 22:07:59 +0900200 depends on OF_CONTROL && DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200201 help
202 Enable the driver for NAND flash on platforms using a Denali NAND
203 controller as a DT device.
204
Tom Rinia73788c2021-09-22 14:50:37 -0400205config NAND_FSL_ELBC
206 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
Tom Rini98372452021-12-12 22:12:36 -0500207 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
208 select SPL_SYS_NAND_SELF_INIT
209 select SYS_NAND_SELF_INIT
Tom Rinia73788c2021-09-22 14:50:37 -0400210 depends on FSL_ELBC
211 help
212 Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
213
Pali Rohárbb834db2022-04-04 18:17:19 +0200214config NAND_FSL_ELBC_DT
215 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)"
216 depends on NAND_FSL_ELBC
217
Tom Rinia73788c2021-09-22 14:50:37 -0400218config NAND_FSL_IFC
219 bool "Support Freescale Integrated Flash Controller NAND driver"
Tom Rini98372452021-12-12 22:12:36 -0500220 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
Tom Rini1a9f23d2022-05-26 14:31:57 -0400221 select TPL_NAND_INIT if TPL && !TPL_FRAMEWORK
Tom Rini98372452021-12-12 22:12:36 -0500222 select SPL_SYS_NAND_SELF_INIT
223 select SYS_NAND_SELF_INIT
Tom Rini05b419e2021-12-11 14:55:49 -0500224 select FSL_IFC
Tom Rinia73788c2021-09-22 14:50:37 -0400225 help
226 Enable the Freescale Integrated Flash Controller NAND driver.
227
Tom Rinib91baf62022-11-19 18:45:29 -0500228config NAND_KIRKWOOD
229 bool "Support for Kirkwood NAND controller"
230 depends on ARCH_KIRKWOOD
231 default y
232
233config NAND_ECC_BCH
234 bool
235
236config NAND_KMETER1
237 bool "Support KMETER1 NAND controller"
238 depends on VENDOR_KM
239 select NAND_ECC_BCH
240
Tom Rini08204272021-09-22 14:50:28 -0400241config NAND_LPC32XX_MLC
242 bool "Support LPC32XX_MLC controller"
Tom Rini98372452021-12-12 22:12:36 -0500243 select SYS_NAND_SELF_INIT
Tom Rini08204272021-09-22 14:50:28 -0400244 help
245 Enable the LPC32XX MLC NAND controller.
246
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200247config NAND_LPC32XX_SLC
248 bool "Support LPC32XX_SLC controller"
249 help
250 Enable the LPC32XX SLC NAND controller.
251
252config NAND_OMAP_GPMC
253 bool "Support OMAP GPMC NAND controller"
254 depends on ARCH_OMAP2PLUS
255 help
256 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
257 GPMC controller is used for parallel NAND flash devices, and can
258 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
259 and BCH16 ECC algorithms.
260
Tom Rinif6d26d82021-09-22 14:50:39 -0400261if NAND_OMAP_GPMC
262
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200263config NAND_OMAP_GPMC_PREFETCH
264 bool "Enable GPMC Prefetch"
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200265 default y
266 help
267 On OMAP platforms that use the GPMC controller
268 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
269 uses the prefetch mode to speed up read operations.
270
271config NAND_OMAP_ELM
272 bool "Enable ELM driver for OMAPxx and AMxx platforms."
Tom Rinif6d26d82021-09-22 14:50:39 -0400273 depends on !OMAP34XX
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200274 help
275 ELM controller is used for ECC error detection (not ECC calculation)
276 of BCH4, BCH8 and BCH16 ECC algorithms.
277 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
278 thus such SoC platforms need to depend on software library for ECC error
279 detection. However ECC calculation on such plaforms would still be
280 done by GPMC controller.
281
Tom Rinif6d26d82021-09-22 14:50:39 -0400282choice
283 prompt "ECC scheme"
284 default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
285 help
286 On OMAP platforms, this CONFIG specifies NAND ECC scheme.
287 It can take following values:
288 OMAP_ECC_HAM1_CODE_SW
289 1-bit Hamming code using software lib.
290 (for legacy devices only)
291 OMAP_ECC_HAM1_CODE_HW
292 1-bit Hamming code using GPMC hardware.
293 (for legacy devices only)
294 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
295 4-bit BCH code (unsupported)
296 OMAP_ECC_BCH4_CODE_HW
297 4-bit BCH code (unsupported)
298 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
299 8-bit BCH code with
300 - ecc calculation using GPMC hardware engine,
301 - error detection using software library.
302 - requires CONFIG_BCH to enable software BCH library
303 (For legacy device which do not have ELM h/w engine)
304 OMAP_ECC_BCH8_CODE_HW
305 8-bit BCH code with
306 - ecc calculation using GPMC hardware engine,
307 - error detection using ELM hardware engine.
308 OMAP_ECC_BCH16_CODE_HW
309 16-bit BCH code with
310 - ecc calculation using GPMC hardware engine,
311 - error detection using ELM hardware engine.
312
313 How to select ECC scheme on OMAP and AMxx platforms ?
314 -----------------------------------------------------
315 Though higher ECC schemes have more capability to detect and correct
316 bit-flips, but still selection of ECC scheme is dependent on following
317 - hardware engines present in SoC.
318 Some legacy OMAP SoC do not have ELM h/w engine thus such
319 SoC cannot support BCHx_HW ECC schemes.
320 - size of OOB/Spare region
321 With higher ECC schemes, more OOB/Spare area is required to
322 store ECC. So choice of ECC scheme is limited by NAND oobsize.
323
324 In general following expression can help:
325 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
326 where
327 NAND_OOBSIZE = number of bytes available in
328 OOB/spare area per NAND page.
329 NAND_PAGESIZE = bytes in main-area of NAND page.
330 ECC_BYTES = number of ECC bytes generated to
331 protect 512 bytes of data, which is:
332 3 for HAM1_xx ecc schemes
333 7 for BCH4_xx ecc schemes
334 14 for BCH8_xx ecc schemes
335 26 for BCH16_xx ecc schemes
336
337 example to check for BCH16 on 2K page NAND
338 NAND_PAGESIZE = 2048
339 NAND_OOBSIZE = 64
340 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
341 Thus BCH16 cannot be supported on 2K page NAND.
342
343 However, for 4K pagesize NAND
344 NAND_PAGESIZE = 4096
345 NAND_OOBSIZE = 224
346 ECC_BYTES = 26
347 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
348 Thus BCH16 can be supported on 4K page NAND.
349
350config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
351 bool "1-bit Hamming code using software lib"
352
353config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
354 bool "1-bit Hamming code using GPMC hardware"
355
356config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
357 bool "8-bit BCH code with HW calculation SW error detection"
358
359config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
360 bool "8-bit BCH code with HW calculation and error detection"
361
362config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
363 bool "16-bit BCH code with HW calculation and error detection"
364
365endchoice
366
367config NAND_OMAP_ECCSCHEME
368 int
369 default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
370 default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
371 default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
372 default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
373 default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
374 help
375 This must be kept in sync with the enum in
376 include/linux/mtd/omap_gpmc.h
377
378endif
379
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200380config NAND_VF610_NFC
381 bool "Support for Freescale NFC for VF610"
382 select SYS_NAND_SELF_INIT
Stefan Agnerbd186142018-12-06 14:57:09 +0100383 select SYS_NAND_DRIVER_ECC_LAYOUT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200384 imply CMD_NAND
385 help
386 Enables support for NAND Flash Controller on some Freescale
387 processors like the VF610, MCF54418 or Kinetis K70.
388 The driver supports a maximum 2k page size. The driver
389 currently does not support hardware ECC.
390
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100391if NAND_VF610_NFC
392
393config NAND_VF610_NFC_DT
394 bool "Support Vybrid's vf610 NAND controller as a DT device"
Miquel Raynala903be42019-10-03 19:50:04 +0200395 depends on OF_CONTROL && DM_MTD
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100396 help
397 Enable the driver for Vybrid's vf610 NAND flash on platforms
398 using device tree.
399
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200400choice
401 prompt "Hardware ECC strength"
402 depends on NAND_VF610_NFC
403 default SYS_NAND_VF610_NFC_45_ECC_BYTES
404 help
405 Select the ECC strength used in the hardware BCH ECC block.
406
407config SYS_NAND_VF610_NFC_45_ECC_BYTES
408 bool "24-error correction (45 ECC bytes)"
409
410config SYS_NAND_VF610_NFC_60_ECC_BYTES
411 bool "32-error correction (60 ECC bytes)"
412
413endchoice
414
Lukasz Majewskif006cb32018-12-03 10:24:50 +0100415endif
416
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200417config NAND_PXA3XX
418 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
419 select SYS_NAND_SELF_INIT
Shmuel Hazan759349e2020-10-29 08:52:18 +0200420 select DM_MTD
Shmuel Hazan58983222020-10-29 08:52:20 +0200421 select REGMAP
422 select SYSCON
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200423 imply CMD_NAND
424 help
425 This enables the driver for the NAND flash device found on
426 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
427
428config NAND_SUNXI
429 bool "Support for NAND on Allwinner SoCs"
430 default ARCH_SUNXI
431 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
432 select SYS_NAND_SELF_INIT
433 select SYS_NAND_U_BOOT_LOCATIONS
434 select SPL_NAND_SUPPORT
Tom Rini98372452021-12-12 22:12:36 -0500435 select SPL_SYS_NAND_SELF_INIT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200436 imply CMD_NAND
437 ---help---
438 Enable support for NAND. This option enables the standard and
439 SPL drivers.
440 The SPL driver only supports reading from the NAND using DMA
441 transfers.
442
443if NAND_SUNXI
444
445config NAND_SUNXI_SPL_ECC_STRENGTH
446 int "Allwinner NAND SPL ECC Strength"
447 default 64
448
449config NAND_SUNXI_SPL_ECC_SIZE
450 int "Allwinner NAND SPL ECC Step Size"
451 default 1024
452
453config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
454 int "Allwinner NAND SPL Usable Page Size"
455 default 1024
456
457endif
458
459config NAND_ARASAN
460 bool "Configure Arasan Nand"
461 select SYS_NAND_SELF_INIT
Michal Simekc5587832020-08-19 09:59:52 +0200462 depends on DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200463 imply CMD_NAND
464 help
465 This enables Nand driver support for Arasan nand flash
466 controller. This uses the hardware ECC for read and
467 write operations.
468
469config NAND_MXC
470 bool "MXC NAND support"
471 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
472 imply CMD_NAND
473 help
474 This enables the NAND driver for the NAND flash controller on the
Haolin Lie8df55b2021-07-18 10:13:39 +0800475 i.MX27 / i.MX31 / i.MX5 processors.
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200476
Tom Rini1ba2a002022-11-12 17:36:50 -0500477config SYS_NAND_SIZE
478 int "Size of NAND in kilobytes"
479 depends on NAND_MXC && SPL_NAND_SUPPORT
480 default 268435456
481
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200482config NAND_MXS
483 bool "MXS NAND support"
Peng Fan128abf42020-05-04 22:09:00 +0800484 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
Tom Rini98372452021-12-12 22:12:36 -0500485 select SPL_SYS_NAND_SELF_INIT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200486 select SYS_NAND_SELF_INIT
487 imply CMD_NAND
488 select APBH_DMA
Peng Fan128abf42020-05-04 22:09:00 +0800489 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
490 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200491 help
492 This enables NAND driver for the NAND flash controller on the
493 MXS processors.
494
495if NAND_MXS
496
497config NAND_MXS_DT
498 bool "Support MXS NAND controller as a DT device"
Miquel Raynala903be42019-10-03 19:50:04 +0200499 depends on OF_CONTROL && DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200500 help
501 Enable the driver for MXS NAND flash on platforms using
502 device tree.
503
504config NAND_MXS_USE_MINIMUM_ECC
505 bool "Use minimum ECC strength supported by the controller"
506 default false
507
508endif
509
Zhengxun Li01551712021-09-14 13:43:51 +0800510config NAND_MXIC
511 bool "Macronix raw NAND controller"
512 select SYS_NAND_SELF_INIT
513 help
514 This selects the Macronix raw NAND controller driver.
515
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200516config NAND_ZYNQ
517 bool "Support for Zynq Nand controller"
Tom Rini98372452021-12-12 22:12:36 -0500518 select SPL_SYS_NAND_SELF_INIT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200519 select SYS_NAND_SELF_INIT
Ashok Reddy Somabb8448a2019-12-27 04:47:12 -0700520 select DM_MTD
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200521 imply CMD_NAND
522 help
523 This enables Nand driver support for Nand flash controller
524 found on Zynq SoC.
525
526config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
527 bool "Enable use of 1st stage bootloader timing for NAND"
528 depends on NAND_ZYNQ
529 help
530 This flag prevent U-boot reconfigure NAND flash controller and reuse
531 the NAND timing from 1st stage bootloader.
532
Suneel Garapati9de7d2b2020-08-26 14:37:22 +0200533config NAND_OCTEONTX
534 bool "Support for OcteonTX NAND controller"
535 select SYS_NAND_SELF_INIT
536 imply CMD_NAND
537 help
538 This enables Nand flash controller hardware found on the OcteonTX
539 processors.
540
541config NAND_OCTEONTX_HW_ECC
542 bool "Support Hardware ECC for OcteonTX NAND controller"
543 depends on NAND_OCTEONTX
544 default y
545 help
546 This enables Hardware BCH engine found on the OcteonTX processors to
547 support ECC for NAND flash controller.
548
Christophe Kerelloda141682019-04-05 11:41:50 +0200549config NAND_STM32_FMC2
550 bool "Support for NAND controller on STM32MP SoCs"
551 depends on ARCH_STM32MP
552 select SYS_NAND_SELF_INIT
553 imply CMD_NAND
554 help
555 Enables support for NAND Flash chips on SoCs containing the FMC2
556 NAND controller. This controller is found on STM32MP SoCs.
557 The controller supports a maximum 8k page size and supports
558 a maximum 8-bit correction error per sector of 512 bytes.
559
Kate Liu41ccd2e2020-12-11 13:46:12 -0800560config CORTINA_NAND
561 bool "Support for NAND controller on Cortina-Access SoCs"
562 depends on CORTINA_PLATFORM
563 select SYS_NAND_SELF_INIT
564 select DM_MTD
565 imply CMD_NAND
566 help
567 Enables support for NAND Flash chips on Coartina-Access SoCs platform
568 This controller is found on Presidio/Venus SoCs.
569 The controller supports a maximum 8k page size and supports
570 a maximum 40-bit error correction per sector of 1024 bytes.
571
Yifeng Zhao9e9021e2021-06-07 16:40:29 +0800572config ROCKCHIP_NAND
573 bool "Support for NAND controller on Rockchip SoCs"
574 depends on ARCH_ROCKCHIP
575 select SYS_NAND_SELF_INIT
576 select DM_MTD
577 imply CMD_NAND
578 help
579 Enables support for NAND Flash chips on Rockchip SoCs platform.
580 This controller is found on Rockchip SoCs.
581 There are four different versions of NAND FLASH Controllers,
582 including:
583 NFC v600: RK2928, RK3066, RK3188
584 NFC v622: RK3036, RK3128
585 NFC v800: RK3308, RV1108
586 NFC v900: PX30, RK3326
587
Tom Rini8f37ac42021-12-12 22:12:35 -0500588config TEGRA_NAND
589 bool "Support for NAND controller on Tegra SoCs"
590 depends on ARCH_TEGRA
591 select SYS_NAND_SELF_INIT
592 imply CMD_NAND
593 help
594 Enables support for NAND Flash chips on Tegra SoCs platforms.
595
developer10a61df2022-05-20 11:23:47 +0800596config NAND_MT7621
597 bool "Support for MediaTek MT7621 NAND flash controller"
598 depends on SOC_MT7621
599 select SYS_NAND_SELF_INIT
600 select SPL_SYS_NAND_SELF_INIT
601 imply CMD_NAND
602 help
603 This enables NAND driver for the NAND flash controller on MediaTek
604 MT7621 platform.
605 The controller supports 4~12 bits correction per 512 bytes with a
606 maximum 4KB page size.
607
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200608comment "Generic NAND options"
609
610config SYS_NAND_BLOCK_SIZE
611 hex "NAND chip eraseblock size"
Tom Rinifae1dab2021-09-22 14:50:29 -0400612 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
developer10a61df2022-05-20 11:23:47 +0800613 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && \
614 !NAND_FSL_IFC && !NAND_MT7621
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200615 help
616 Number of data bytes in one eraseblock for the NAND chip on the
617 board. This is the multiple of NAND_PAGE_SIZE and the number of
618 pages.
619
Tom Rinifdae0072021-09-22 14:50:34 -0400620config SYS_NAND_ONFI_DETECTION
621 bool "Enable detection of ONFI compliant devices during probe"
622 help
623 Enables detection of ONFI compliant devices during probe.
624 And fetching device parameters flashed on device, by parsing
625 ONFI parameter page.
626
Tom Rini2510a812021-09-22 14:50:30 -0400627config SYS_NAND_PAGE_COUNT
628 hex "NAND chip page count"
629 depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
630 SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
631 help
632 Number of pages in the NAND chip.
633
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200634config SYS_NAND_PAGE_SIZE
635 hex "NAND chip page size"
Tom Rinifae1dab2021-09-22 14:50:29 -0400636 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
637 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
638 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
developer10a61df2022-05-20 11:23:47 +0800639 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200640 help
641 Number of data bytes in one page for the NAND chip on the
642 board, not including the OOB area.
643
644config SYS_NAND_OOBSIZE
645 hex "NAND chip OOB size"
Tom Rinifae1dab2021-09-22 14:50:29 -0400646 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
647 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
648 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
Tom Rinid24700f2021-10-30 23:03:56 -0400649 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200650 help
651 Number of bytes in the Out-Of-Band area for the NAND chip on
652 the board.
653
654# Enhance depends when converting drivers to Kconfig which use this config
655# option (mxc_nand, ndfc, omap_gpmc).
656config SYS_NAND_BUSWIDTH_16BIT
657 bool "Use 16-bit NAND interface"
658 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
659 help
660 Indicates that NAND device has 16-bit wide data-bus. In absence of this
661 config, bus-width of NAND device is assumed to be either 8-bit and later
662 determined by reading ONFI params.
663 Above config is useful when NAND device's bus-width information cannot
664 be determined from on-chip ONFI params, like in following scenarios:
665 - SPL boot does not support reading of ONFI parameters. This is done to
666 keep SPL code foot-print small.
667 - In current U-Boot flow using nand_init(), driver initialization
668 happens in board_nand_init() which is called before any device probe
669 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
670 not available while configuring controller. So a static CONFIG_NAND_xx
671 is needed to know the device's bus-width in advance.
672
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200673if SPL
674
Tom Rini8e6d9c72021-09-22 14:50:33 -0400675config SYS_NAND_5_ADDR_CYCLE
676 bool "Wait 5 address cycles during NAND commands"
677 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
678 (SPL_NAND_SUPPORT && NAND_ATMEL)
679 default y
680 help
681 Some controllers require waiting for 5 address cycles when issuing
682 some commands, on NAND chips larger than 128MiB.
683
Tom Rinia2fbd4a2021-09-22 14:50:32 -0400684choice
Tom Rinifdae0072021-09-22 14:50:34 -0400685 prompt "NAND bad block marker/indicator position in the OOB"
Tom Rinia2fbd4a2021-09-22 14:50:32 -0400686 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
687 SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
688 default HAS_NAND_LARGE_BADBLOCK_POS
689 help
690 In the OOB, which position contains the badblock information.
691
692config HAS_NAND_LARGE_BADBLOCK_POS
693 bool "Set the bad block marker/indicator to the 'large' position"
694
695config HAS_NAND_SMALL_BADBLOCK_POS
696 bool "Set the bad block marker/indicator to the 'small' position"
697
698endchoice
699
700config SYS_NAND_BAD_BLOCK_POS
701 int
702 default 0 if HAS_NAND_LARGE_BADBLOCK_POS
703 default 5 if HAS_NAND_SMALL_BADBLOCK_POS
704
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200705config SYS_NAND_U_BOOT_LOCATIONS
706 bool "Define U-boot binaries locations in NAND"
707 help
708 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
709 This option should not be enabled when compiling U-boot for boards
710 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
711 file.
712
713config SYS_NAND_U_BOOT_OFFS
714 hex "Location in NAND to read U-Boot from"
715 default 0x800000 if NAND_SUNXI
716 depends on SYS_NAND_U_BOOT_LOCATIONS
717 help
718 Set the offset from the start of the nand where u-boot should be
719 loaded from.
720
721config SYS_NAND_U_BOOT_OFFS_REDUND
722 hex "Location in NAND to read U-Boot from"
723 default SYS_NAND_U_BOOT_OFFS
724 depends on SYS_NAND_U_BOOT_LOCATIONS
725 help
726 Set the offset from the start of the nand where the redundant u-boot
727 should be loaded from.
728
729config SPL_NAND_AM33XX_BCH
730 bool "Enables SPL-NAND driver which supports ELM based"
Tom Rini0a83cc22022-06-10 23:03:09 -0400731 depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200732 default y
733 help
734 Hardware ECC correction. This is useful for platforms which have ELM
735 hardware engine and use NAND boot mode.
736 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
737 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
738 SPL-NAND driver with software ECC correction support.
739
740config SPL_NAND_DENALI
741 bool "Support Denali NAND controller for SPL"
Tom Rini0a83cc22022-06-10 23:03:09 -0400742 depends on SPL_NAND_SUPPORT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200743 help
744 This is a small implementation of the Denali NAND controller
745 for use on SPL.
746
Masahiro Yamada64648cb2020-04-17 16:51:42 +0900747config NAND_DENALI_SPARE_AREA_SKIP_BYTES
748 int "Number of bytes skipped in OOB area"
749 depends on SPL_NAND_DENALI
750 range 0 63
751 help
752 This option specifies the number of bytes to skip from the beginning
753 of OOB area before last ECC sector data starts. This is potentially
754 used to preserve the bad block marker in the OOB area.
755
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200756config SPL_NAND_SIMPLE
757 bool "Use simple SPL NAND driver"
Tom Rini0a83cc22022-06-10 23:03:09 -0400758 depends on !SPL_NAND_AM33XX_BCH && SPL_NAND_SUPPORT
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200759 help
760 Support for NAND boot using simple NAND drivers that
761 expose the cmd_ctrl() interface.
Tom Rini4251f7d2022-11-12 17:36:44 -0500762
763config SYS_NAND_HW_ECC_OOBFIRST
764 bool "In SPL, read the OOB first and then the data from NAND"
765 depends on SPL_NAND_SIMPLE
766
Miquel Raynal1f1ae152018-08-16 17:30:07 +0200767endif
768
769endif # if NAND