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Andy Fleminge52ffb82008-10-30 16:47:16 -05001/*
Jerry Huanged413672011-01-06 23:42:19 -06002 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
Andy Fleminge52ffb82008-10-30 16:47:16 -05003 * Andy Fleming
4 *
5 * Based vaguely on the pxa mmc code:
6 * (C) Copyright 2003
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
8 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Andy Fleminge52ffb82008-10-30 16:47:16 -050010 */
11
12#include <config.h>
13#include <common.h>
14#include <command.h>
Jaehoon Chung7825d202016-07-19 16:33:36 +090015#include <errno.h>
Anton Vorontsovf751a3c2009-06-10 00:25:29 +040016#include <hwconfig.h>
Andy Fleminge52ffb82008-10-30 16:47:16 -050017#include <mmc.h>
18#include <part.h>
Peng Fan5eb8b432017-06-12 17:50:54 +080019#include <power/regulator.h>
Andy Fleminge52ffb82008-10-30 16:47:16 -050020#include <malloc.h>
Andy Fleminge52ffb82008-10-30 16:47:16 -050021#include <fsl_esdhc.h>
Anton Vorontsovf751a3c2009-06-10 00:25:29 +040022#include <fdt_support.h>
Andy Fleminge52ffb82008-10-30 16:47:16 -050023#include <asm/io.h>
Peng Fana4d36f72016-03-25 14:16:56 +080024#include <dm.h>
25#include <asm-generic/gpio.h>
Andy Fleminge52ffb82008-10-30 16:47:16 -050026
Andy Fleminge52ffb82008-10-30 16:47:16 -050027DECLARE_GLOBAL_DATA_PTR;
28
Ye.Li3d46c312014-11-04 15:35:49 +080029#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
30 IRQSTATEN_CINT | \
31 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
32 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
33 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
34 IRQSTATEN_DINT)
35
Andy Fleminge52ffb82008-10-30 16:47:16 -050036struct fsl_esdhc {
Haijun.Zhangd49eb9e2013-10-30 11:37:55 +080037 uint dsaddr; /* SDMA system address register */
38 uint blkattr; /* Block attributes register */
39 uint cmdarg; /* Command argument register */
40 uint xfertyp; /* Transfer type register */
41 uint cmdrsp0; /* Command response 0 register */
42 uint cmdrsp1; /* Command response 1 register */
43 uint cmdrsp2; /* Command response 2 register */
44 uint cmdrsp3; /* Command response 3 register */
45 uint datport; /* Buffer data port register */
46 uint prsstat; /* Present state register */
47 uint proctl; /* Protocol control register */
48 uint sysctl; /* System Control Register */
49 uint irqstat; /* Interrupt status register */
50 uint irqstaten; /* Interrupt status enable register */
51 uint irqsigen; /* Interrupt signal enable register */
52 uint autoc12err; /* Auto CMD error status register */
53 uint hostcapblt; /* Host controller capabilities register */
54 uint wml; /* Watermark level register */
55 uint mixctrl; /* For USDHC */
56 char reserved1[4]; /* reserved */
57 uint fevt; /* Force event register */
58 uint admaes; /* ADMA error status register */
59 uint adsaddr; /* ADMA system address register */
Peng Fana6eadd52016-06-15 10:53:00 +080060 char reserved2[4];
61 uint dllctrl;
62 uint dllstat;
63 uint clktunectrlstatus;
64 char reserved3[84];
65 uint vendorspec;
66 uint mmcboot;
67 uint vendorspec2;
68 char reserved4[48];
Haijun.Zhangd49eb9e2013-10-30 11:37:55 +080069 uint hostver; /* Host controller version register */
Haijun.Zhangd49eb9e2013-10-30 11:37:55 +080070 char reserved5[4]; /* reserved */
Peng Fana6eadd52016-06-15 10:53:00 +080071 uint dmaerraddr; /* DMA error address register */
Otavio Salvadorfad3e062015-02-17 10:42:43 -020072 char reserved6[4]; /* reserved */
Peng Fana6eadd52016-06-15 10:53:00 +080073 uint dmaerrattr; /* DMA error attribute register */
74 char reserved7[4]; /* reserved */
Haijun.Zhangd49eb9e2013-10-30 11:37:55 +080075 uint hostcapblt2; /* Host controller capabilities register 2 */
Peng Fana6eadd52016-06-15 10:53:00 +080076 char reserved8[8]; /* reserved */
Haijun.Zhangd49eb9e2013-10-30 11:37:55 +080077 uint tcr; /* Tuning control register */
Peng Fana6eadd52016-06-15 10:53:00 +080078 char reserved9[28]; /* reserved */
Haijun.Zhangd49eb9e2013-10-30 11:37:55 +080079 uint sddirctl; /* SD direction control register */
Peng Fana6eadd52016-06-15 10:53:00 +080080 char reserved10[712];/* reserved */
Haijun.Zhangd49eb9e2013-10-30 11:37:55 +080081 uint scr; /* eSDHC control register */
Andy Fleminge52ffb82008-10-30 16:47:16 -050082};
83
Simon Glassfa02ca52017-07-29 11:35:21 -060084struct fsl_esdhc_plat {
85 struct mmc_config cfg;
86 struct mmc mmc;
87};
88
Peng Fana4d36f72016-03-25 14:16:56 +080089/**
90 * struct fsl_esdhc_priv
91 *
92 * @esdhc_regs: registers of the sdhc controller
93 * @sdhc_clk: Current clk of the sdhc controller
94 * @bus_width: bus width, 1bit, 4bit or 8bit
95 * @cfg: mmc config
96 * @mmc: mmc
97 * Following is used when Driver Model is enabled for MMC
98 * @dev: pointer for the device
99 * @non_removable: 0: removable; 1: non-removable
Peng Fan01eb1c42016-06-15 10:53:02 +0800100 * @wp_enable: 1: enable checking wp; 0: no check
Peng Fanaee78582017-06-12 17:50:53 +0800101 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
Peng Fana4d36f72016-03-25 14:16:56 +0800102 * @cd_gpio: gpio for card detection
Peng Fan01eb1c42016-06-15 10:53:02 +0800103 * @wp_gpio: gpio for write protection
Peng Fana4d36f72016-03-25 14:16:56 +0800104 */
105struct fsl_esdhc_priv {
106 struct fsl_esdhc *esdhc_regs;
107 unsigned int sdhc_clk;
108 unsigned int bus_width;
Simon Glass407025d2017-07-29 11:35:24 -0600109#if !CONFIG_IS_ENABLED(BLK)
Peng Fana4d36f72016-03-25 14:16:56 +0800110 struct mmc *mmc;
Simon Glass407025d2017-07-29 11:35:24 -0600111#endif
Peng Fana4d36f72016-03-25 14:16:56 +0800112 struct udevice *dev;
113 int non_removable;
Peng Fan01eb1c42016-06-15 10:53:02 +0800114 int wp_enable;
Peng Fanaee78582017-06-12 17:50:53 +0800115 int vs18_enable;
Yangbo Lub99647c2016-12-07 11:54:30 +0800116#ifdef CONFIG_DM_GPIO
Peng Fana4d36f72016-03-25 14:16:56 +0800117 struct gpio_desc cd_gpio;
Peng Fan01eb1c42016-06-15 10:53:02 +0800118 struct gpio_desc wp_gpio;
Yangbo Lub99647c2016-12-07 11:54:30 +0800119#endif
Peng Fana4d36f72016-03-25 14:16:56 +0800120};
121
Andy Fleminge52ffb82008-10-30 16:47:16 -0500122/* Return the XFERTYP flags for a given command and data packet */
Kim Phillipsf9e0b602012-10-29 13:34:44 +0000123static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
Andy Fleminge52ffb82008-10-30 16:47:16 -0500124{
125 uint xfertyp = 0;
126
127 if (data) {
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530128 xfertyp |= XFERTYP_DPSEL;
129#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
130 xfertyp |= XFERTYP_DMAEN;
131#endif
Andy Fleminge52ffb82008-10-30 16:47:16 -0500132 if (data->blocks > 1) {
133 xfertyp |= XFERTYP_MSBSEL;
134 xfertyp |= XFERTYP_BCEN;
Jerry Huanged413672011-01-06 23:42:19 -0600135#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
136 xfertyp |= XFERTYP_AC12EN;
137#endif
Andy Fleminge52ffb82008-10-30 16:47:16 -0500138 }
139
140 if (data->flags & MMC_DATA_READ)
141 xfertyp |= XFERTYP_DTDSEL;
142 }
143
144 if (cmd->resp_type & MMC_RSP_CRC)
145 xfertyp |= XFERTYP_CCCEN;
146 if (cmd->resp_type & MMC_RSP_OPCODE)
147 xfertyp |= XFERTYP_CICEN;
148 if (cmd->resp_type & MMC_RSP_136)
149 xfertyp |= XFERTYP_RSPTYP_136;
150 else if (cmd->resp_type & MMC_RSP_BUSY)
151 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
152 else if (cmd->resp_type & MMC_RSP_PRESENT)
153 xfertyp |= XFERTYP_RSPTYP_48;
154
Jason Liubef0ff02011-03-22 01:32:31 +0000155 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
156 xfertyp |= XFERTYP_CMDTYP_ABORT;
Yangbo Lub73a3d62016-01-21 17:33:19 +0800157
Andy Fleminge52ffb82008-10-30 16:47:16 -0500158 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
159}
160
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530161#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
162/*
163 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
164 */
Simon Glass1d177d42017-07-29 11:35:17 -0600165static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
166 struct mmc_data *data)
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530167{
Peng Fana4d36f72016-03-25 14:16:56 +0800168 struct fsl_esdhc *regs = priv->esdhc_regs;
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530169 uint blocks;
170 char *buffer;
171 uint databuf;
172 uint size;
173 uint irqstat;
174 uint timeout;
175
176 if (data->flags & MMC_DATA_READ) {
177 blocks = data->blocks;
178 buffer = data->dest;
179 while (blocks) {
180 timeout = PIO_TIMEOUT;
181 size = data->blocksize;
182 irqstat = esdhc_read32(&regs->irqstat);
183 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
184 && --timeout);
185 if (timeout <= 0) {
186 printf("\nData Read Failed in PIO Mode.");
Wolfgang Denka40545c2010-05-09 23:52:59 +0200187 return;
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530188 }
189 while (size && (!(irqstat & IRQSTAT_TC))) {
190 udelay(100); /* Wait before last byte transfer complete */
191 irqstat = esdhc_read32(&regs->irqstat);
192 databuf = in_le32(&regs->datport);
193 *((uint *)buffer) = databuf;
194 buffer += 4;
195 size -= 4;
196 }
197 blocks--;
198 }
199 } else {
200 blocks = data->blocks;
Wolfgang Denka40545c2010-05-09 23:52:59 +0200201 buffer = (char *)data->src;
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530202 while (blocks) {
203 timeout = PIO_TIMEOUT;
204 size = data->blocksize;
205 irqstat = esdhc_read32(&regs->irqstat);
206 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
207 && --timeout);
208 if (timeout <= 0) {
209 printf("\nData Write Failed in PIO Mode.");
Wolfgang Denka40545c2010-05-09 23:52:59 +0200210 return;
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530211 }
212 while (size && (!(irqstat & IRQSTAT_TC))) {
213 udelay(100); /* Wait before last byte transfer complete */
214 databuf = *((uint *)buffer);
215 buffer += 4;
216 size -= 4;
217 irqstat = esdhc_read32(&regs->irqstat);
218 out_le32(&regs->datport, databuf);
219 }
220 blocks--;
221 }
222 }
223}
224#endif
225
Simon Glass1d177d42017-07-29 11:35:17 -0600226static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
227 struct mmc_data *data)
Andy Fleminge52ffb82008-10-30 16:47:16 -0500228{
Andy Fleminge52ffb82008-10-30 16:47:16 -0500229 int timeout;
Peng Fana4d36f72016-03-25 14:16:56 +0800230 struct fsl_esdhc *regs = priv->esdhc_regs;
Eddy Petrișor5178dc12016-06-05 03:43:00 +0300231#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
Yangbo Lud0e295d2015-03-20 19:28:31 -0700232 dma_addr_t addr;
233#endif
Wolfgang Denka40545c2010-05-09 23:52:59 +0200234 uint wml_value;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500235
236 wml_value = data->blocksize/4;
237
238 if (data->flags & MMC_DATA_READ) {
Priyanka Jain02449632011-02-09 09:24:10 +0530239 if (wml_value > WML_RD_WML_MAX)
240 wml_value = WML_RD_WML_MAX_VAL;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500241
Roy Zange5853af2010-02-09 18:23:33 +0800242 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
Ye.Li33a56b12014-02-20 18:00:57 +0800243#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
Eddy Petrișor5178dc12016-06-05 03:43:00 +0300244#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
Yangbo Lud0e295d2015-03-20 19:28:31 -0700245 addr = virt_to_phys((void *)(data->dest));
246 if (upper_32_bits(addr))
247 printf("Error found for upper 32 bits\n");
248 else
249 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
250#else
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100251 esdhc_write32(&regs->dsaddr, (u32)data->dest);
Ye.Li33a56b12014-02-20 18:00:57 +0800252#endif
Yangbo Lud0e295d2015-03-20 19:28:31 -0700253#endif
Andy Fleminge52ffb82008-10-30 16:47:16 -0500254 } else {
Ye.Li33a56b12014-02-20 18:00:57 +0800255#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
Eric Nelson30e9cad2012-04-25 14:28:48 +0000256 flush_dcache_range((ulong)data->src,
257 (ulong)data->src+data->blocks
258 *data->blocksize);
Ye.Li33a56b12014-02-20 18:00:57 +0800259#endif
Priyanka Jain02449632011-02-09 09:24:10 +0530260 if (wml_value > WML_WR_WML_MAX)
261 wml_value = WML_WR_WML_MAX_VAL;
Peng Fan01eb1c42016-06-15 10:53:02 +0800262 if (priv->wp_enable) {
263 if ((esdhc_read32(&regs->prsstat) &
264 PRSSTAT_WPSPL) == 0) {
265 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
Jaehoon Chung7825d202016-07-19 16:33:36 +0900266 return -ETIMEDOUT;
Peng Fan01eb1c42016-06-15 10:53:02 +0800267 }
Andy Fleminge52ffb82008-10-30 16:47:16 -0500268 }
Roy Zange5853af2010-02-09 18:23:33 +0800269
270 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
271 wml_value << 16);
Ye.Li33a56b12014-02-20 18:00:57 +0800272#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
Eddy Petrișor5178dc12016-06-05 03:43:00 +0300273#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
Yangbo Lud0e295d2015-03-20 19:28:31 -0700274 addr = virt_to_phys((void *)(data->src));
275 if (upper_32_bits(addr))
276 printf("Error found for upper 32 bits\n");
277 else
278 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
279#else
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100280 esdhc_write32(&regs->dsaddr, (u32)data->src);
Ye.Li33a56b12014-02-20 18:00:57 +0800281#endif
Yangbo Lud0e295d2015-03-20 19:28:31 -0700282#endif
Andy Fleminge52ffb82008-10-30 16:47:16 -0500283 }
284
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100285 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500286
287 /* Calculate the timeout period for data transactions */
Priyanka Jainc51b40d2011-03-03 09:18:56 +0530288 /*
289 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
290 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
291 * So, Number of SD Clock cycles for 0.25sec should be minimum
292 * (SD Clock/sec * 0.25 sec) SD Clock cycles
Andrew Gabbasovd5b48662014-03-24 02:40:41 -0500293 * = (mmc->clock * 1/4) SD Clock cycles
Priyanka Jainc51b40d2011-03-03 09:18:56 +0530294 * As 1) >= 2)
Andrew Gabbasovd5b48662014-03-24 02:40:41 -0500295 * => (2^(timeout+13)) >= mmc->clock * 1/4
Priyanka Jainc51b40d2011-03-03 09:18:56 +0530296 * Taking log2 both the sides
Andrew Gabbasovd5b48662014-03-24 02:40:41 -0500297 * => timeout + 13 >= log2(mmc->clock/4)
Priyanka Jainc51b40d2011-03-03 09:18:56 +0530298 * Rounding up to next power of 2
Andrew Gabbasovd5b48662014-03-24 02:40:41 -0500299 * => timeout + 13 = log2(mmc->clock/4) + 1
300 * => timeout + 13 = fls(mmc->clock/4)
Yangbo Lu9d7f3212015-12-30 14:19:30 +0800301 *
302 * However, the MMC spec "It is strongly recommended for hosts to
303 * implement more than 500ms timeout value even if the card
304 * indicates the 250ms maximum busy length." Even the previous
305 * value of 300ms is known to be insufficient for some cards.
306 * So, we use
307 * => timeout + 13 = fls(mmc->clock/2)
Priyanka Jainc51b40d2011-03-03 09:18:56 +0530308 */
Yangbo Lu9d7f3212015-12-30 14:19:30 +0800309 timeout = fls(mmc->clock/2);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500310 timeout -= 13;
311
312 if (timeout > 14)
313 timeout = 14;
314
315 if (timeout < 0)
316 timeout = 0;
317
Kumar Gala9a878d52011-01-29 15:36:10 -0600318#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
319 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
320 timeout++;
321#endif
322
Haijun.Zhangedeb83a2014-03-18 17:04:23 +0800323#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
324 timeout = 0xE;
325#endif
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100326 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500327
328 return 0;
329}
330
Eric Nelson30e9cad2012-04-25 14:28:48 +0000331static void check_and_invalidate_dcache_range
332 (struct mmc_cmd *cmd,
333 struct mmc_data *data) {
Yangbo Lud0e295d2015-03-20 19:28:31 -0700334 unsigned start = 0;
Yangbo Lue7702c62016-05-12 19:12:58 +0800335 unsigned end = 0;
Eric Nelson30e9cad2012-04-25 14:28:48 +0000336 unsigned size = roundup(ARCH_DMA_MINALIGN,
337 data->blocks*data->blocksize);
Eddy Petrișor5178dc12016-06-05 03:43:00 +0300338#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
Yangbo Lud0e295d2015-03-20 19:28:31 -0700339 dma_addr_t addr;
340
341 addr = virt_to_phys((void *)(data->dest));
342 if (upper_32_bits(addr))
343 printf("Error found for upper 32 bits\n");
344 else
345 start = lower_32_bits(addr);
Yangbo Lue7702c62016-05-12 19:12:58 +0800346#else
347 start = (unsigned)data->dest;
Yangbo Lud0e295d2015-03-20 19:28:31 -0700348#endif
Yangbo Lue7702c62016-05-12 19:12:58 +0800349 end = start + size;
Eric Nelson30e9cad2012-04-25 14:28:48 +0000350 invalidate_dcache_range(start, end);
351}
Tom Rini239dd252014-05-23 09:19:05 -0400352
Andy Fleminge52ffb82008-10-30 16:47:16 -0500353/*
354 * Sends a command out on the bus. Takes the mmc pointer,
355 * a command pointer, and an optional data pointer.
356 */
Simon Glass6aa55dc2017-07-29 11:35:18 -0600357static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
358 struct mmc_cmd *cmd, struct mmc_data *data)
Andy Fleminge52ffb82008-10-30 16:47:16 -0500359{
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500360 int err = 0;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500361 uint xfertyp;
362 uint irqstat;
Peng Fana4d36f72016-03-25 14:16:56 +0800363 struct fsl_esdhc *regs = priv->esdhc_regs;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500364
Jerry Huanged413672011-01-06 23:42:19 -0600365#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
366 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
367 return 0;
368#endif
369
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100370 esdhc_write32(&regs->irqstat, -1);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500371
372 sync();
373
374 /* Wait for the bus to be idle */
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100375 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
376 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
377 ;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500378
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100379 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
380 ;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500381
382 /* Wait at least 8 SD clock cycles before the next command */
383 /*
384 * Note: This is way more than 8 cycles, but 1ms seems to
385 * resolve timing issues with some cards
386 */
387 udelay(1000);
388
389 /* Set up for a data transfer if we have one */
390 if (data) {
Simon Glass1d177d42017-07-29 11:35:17 -0600391 err = esdhc_setup_data(priv, mmc, data);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500392 if(err)
393 return err;
Peng Fan9cb5e992015-06-25 10:32:26 +0800394
395 if (data->flags & MMC_DATA_READ)
396 check_and_invalidate_dcache_range(cmd, data);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500397 }
398
399 /* Figure out the transfer arguments */
400 xfertyp = esdhc_xfertyp(cmd, data);
401
Andrew Gabbasov4816b7a2013-06-11 10:34:22 -0500402 /* Mask all irqs */
403 esdhc_write32(&regs->irqsigen, 0);
404
Andy Fleminge52ffb82008-10-30 16:47:16 -0500405 /* Send the command */
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100406 esdhc_write32(&regs->cmdarg, cmd->cmdarg);
Jason Liu9919d642011-11-25 00:18:04 +0000407#if defined(CONFIG_FSL_USDHC)
408 esdhc_write32(&regs->mixctrl,
Volodymyr Riazantsevd251e112015-01-20 10:16:44 -0500409 (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
410 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
Jason Liu9919d642011-11-25 00:18:04 +0000411 esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
412#else
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100413 esdhc_write32(&regs->xfertyp, xfertyp);
Jason Liu9919d642011-11-25 00:18:04 +0000414#endif
Dirk Behmed8552d62012-03-26 03:13:05 +0000415
Andy Fleminge52ffb82008-10-30 16:47:16 -0500416 /* Wait for the command to complete */
Dirk Behmed8552d62012-03-26 03:13:05 +0000417 while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100418 ;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500419
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100420 irqstat = esdhc_read32(&regs->irqstat);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500421
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500422 if (irqstat & CMD_ERR) {
Jaehoon Chung7825d202016-07-19 16:33:36 +0900423 err = -ECOMM;
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500424 goto out;
Dirk Behmed8552d62012-03-26 03:13:05 +0000425 }
426
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500427 if (irqstat & IRQSTAT_CTOE) {
Jaehoon Chung7825d202016-07-19 16:33:36 +0900428 err = -ETIMEDOUT;
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500429 goto out;
430 }
Andy Fleminge52ffb82008-10-30 16:47:16 -0500431
Otavio Salvadorfad3e062015-02-17 10:42:43 -0200432 /* Switch voltage to 1.8V if CMD11 succeeded */
433 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
434 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
435
436 printf("Run CMD11 1.8V switch\n");
437 /* Sleep for 5 ms - max time for card to switch to 1.8V */
438 udelay(5000);
439 }
440
Dirk Behmed8552d62012-03-26 03:13:05 +0000441 /* Workaround for ESDHC errata ENGcm03648 */
442 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
Yangbo Lu3ffa8512015-04-15 10:13:12 +0800443 int timeout = 6000;
Dirk Behmed8552d62012-03-26 03:13:05 +0000444
Yangbo Lu3ffa8512015-04-15 10:13:12 +0800445 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
Dirk Behmed8552d62012-03-26 03:13:05 +0000446 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
447 PRSSTAT_DAT0)) {
448 udelay(100);
449 timeout--;
450 }
451
452 if (timeout <= 0) {
453 printf("Timeout waiting for DAT0 to go high!\n");
Jaehoon Chung7825d202016-07-19 16:33:36 +0900454 err = -ETIMEDOUT;
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500455 goto out;
Dirk Behmed8552d62012-03-26 03:13:05 +0000456 }
457 }
458
Andy Fleminge52ffb82008-10-30 16:47:16 -0500459 /* Copy the response to the response buffer */
460 if (cmd->resp_type & MMC_RSP_136) {
461 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
462
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100463 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
464 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
465 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
466 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
Rabin Vincentb6eed942009-04-05 13:30:56 +0530467 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
468 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
469 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
470 cmd->response[3] = (cmdrsp0 << 8);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500471 } else
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100472 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500473
474 /* Wait until all of the blocks are transferred */
475 if (data) {
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530476#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
Simon Glass1d177d42017-07-29 11:35:17 -0600477 esdhc_pio_read_write(priv, data);
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530478#else
Andy Fleminge52ffb82008-10-30 16:47:16 -0500479 do {
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100480 irqstat = esdhc_read32(&regs->irqstat);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500481
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500482 if (irqstat & IRQSTAT_DTOE) {
Jaehoon Chung7825d202016-07-19 16:33:36 +0900483 err = -ETIMEDOUT;
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500484 goto out;
485 }
Frans Meulenbroeks010ba982010-07-31 04:45:18 +0000486
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500487 if (irqstat & DATA_ERR) {
Jaehoon Chung7825d202016-07-19 16:33:36 +0900488 err = -ECOMM;
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500489 goto out;
490 }
Andrew Gabbasov4a929622013-04-07 23:06:08 +0000491 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
Ye.Li33a56b12014-02-20 18:00:57 +0800492
Peng Fan9cb5e992015-06-25 10:32:26 +0800493 /*
494 * Need invalidate the dcache here again to avoid any
495 * cache-fill during the DMA operations such as the
496 * speculative pre-fetching etc.
497 */
Eric Nelson70e68692013-04-03 12:31:56 +0000498 if (data->flags & MMC_DATA_READ)
499 check_and_invalidate_dcache_range(cmd, data);
Ye.Li33a56b12014-02-20 18:00:57 +0800500#endif
Andy Fleminge52ffb82008-10-30 16:47:16 -0500501 }
502
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500503out:
504 /* Reset CMD and DATA portions on error */
505 if (err) {
506 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
507 SYSCTL_RSTC);
508 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
509 ;
510
511 if (data) {
512 esdhc_write32(&regs->sysctl,
513 esdhc_read32(&regs->sysctl) |
514 SYSCTL_RSTD);
515 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
516 ;
517 }
Otavio Salvadorfad3e062015-02-17 10:42:43 -0200518
519 /* If this was CMD11, then notify that power cycle is needed */
520 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
521 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500522 }
523
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100524 esdhc_write32(&regs->irqstat, -1);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500525
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500526 return err;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500527}
528
Simon Glass1d177d42017-07-29 11:35:17 -0600529static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
Andy Fleminge52ffb82008-10-30 16:47:16 -0500530{
Benoît Thébaudeaue16e9222017-05-03 11:59:03 +0200531 int div = 1;
532#ifdef ARCH_MXC
533 int pre_div = 1;
534#else
535 int pre_div = 2;
536#endif
537 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
Peng Fana4d36f72016-03-25 14:16:56 +0800538 struct fsl_esdhc *regs = priv->esdhc_regs;
539 int sdhc_clk = priv->sdhc_clk;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500540 uint clk;
541
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200542 if (clock < mmc->cfg->f_min)
543 clock = mmc->cfg->f_min;
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100544
Benoît Thébaudeaue16e9222017-05-03 11:59:03 +0200545 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
546 pre_div *= 2;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500547
Benoît Thébaudeaue16e9222017-05-03 11:59:03 +0200548 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
549 div++;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500550
Benoît Thébaudeaue16e9222017-05-03 11:59:03 +0200551 pre_div >>= 1;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500552 div -= 1;
553
554 clk = (pre_div << 8) | (div << 4);
555
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700556#ifdef CONFIG_FSL_USDHC
Ye Li5a24f292016-06-15 10:53:01 +0800557 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700558#else
Kumar Gala09876a32010-03-18 15:51:05 -0500559 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700560#endif
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100561
562 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500563
564 udelay(10000);
565
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700566#ifdef CONFIG_FSL_USDHC
Ye Li5a24f292016-06-15 10:53:01 +0800567 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700568#else
569 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
570#endif
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100571
Andy Fleminge52ffb82008-10-30 16:47:16 -0500572}
573
Yangbo Lu163beec2015-04-22 13:57:40 +0800574#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
Simon Glass1d177d42017-07-29 11:35:17 -0600575static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
Yangbo Lu163beec2015-04-22 13:57:40 +0800576{
Peng Fana4d36f72016-03-25 14:16:56 +0800577 struct fsl_esdhc *regs = priv->esdhc_regs;
Yangbo Lu163beec2015-04-22 13:57:40 +0800578 u32 value;
579 u32 time_out;
580
581 value = esdhc_read32(&regs->sysctl);
582
583 if (enable)
584 value |= SYSCTL_CKEN;
585 else
586 value &= ~SYSCTL_CKEN;
587
588 esdhc_write32(&regs->sysctl, value);
589
590 time_out = 20;
591 value = PRSSTAT_SDSTB;
592 while (!(esdhc_read32(&regs->prsstat) & value)) {
593 if (time_out == 0) {
594 printf("fsl_esdhc: Internal clock never stabilised.\n");
595 break;
596 }
597 time_out--;
598 mdelay(1);
599 }
600}
601#endif
602
Simon Glass6aa55dc2017-07-29 11:35:18 -0600603static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
Andy Fleminge52ffb82008-10-30 16:47:16 -0500604{
Peng Fana4d36f72016-03-25 14:16:56 +0800605 struct fsl_esdhc *regs = priv->esdhc_regs;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500606
Yangbo Lu163beec2015-04-22 13:57:40 +0800607#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
608 /* Select to use peripheral clock */
Simon Glass1d177d42017-07-29 11:35:17 -0600609 esdhc_clock_control(priv, false);
Yangbo Lu163beec2015-04-22 13:57:40 +0800610 esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);
Simon Glass1d177d42017-07-29 11:35:17 -0600611 esdhc_clock_control(priv, true);
Yangbo Lu163beec2015-04-22 13:57:40 +0800612#endif
Andy Fleminge52ffb82008-10-30 16:47:16 -0500613 /* Set the clock speed */
Simon Glass1d177d42017-07-29 11:35:17 -0600614 set_sysctl(priv, mmc, mmc->clock);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500615
616 /* Set the bus width */
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100617 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500618
619 if (mmc->bus_width == 4)
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100620 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500621 else if (mmc->bus_width == 8)
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100622 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
623
Jaehoon Chungb6cd1d32016-12-30 15:30:16 +0900624 return 0;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500625}
626
Simon Glass6aa55dc2017-07-29 11:35:18 -0600627static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
Andy Fleminge52ffb82008-10-30 16:47:16 -0500628{
Peng Fana4d36f72016-03-25 14:16:56 +0800629 struct fsl_esdhc *regs = priv->esdhc_regs;
Simon Glass0c3ef222017-07-29 11:35:20 -0600630 ulong start;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500631
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100632 /* Reset the entire host controller */
Dirk Behmedbe67252013-07-15 15:44:29 +0200633 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100634
635 /* Wait until the controller is available */
Simon Glass0c3ef222017-07-29 11:35:20 -0600636 start = get_timer(0);
637 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
638 if (get_timer(start) > 1000)
639 return -ETIMEDOUT;
640 }
Andy Fleminge52ffb82008-10-30 16:47:16 -0500641
Peng Fana6eadd52016-06-15 10:53:00 +0800642#if defined(CONFIG_FSL_USDHC)
643 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
644 esdhc_write32(&regs->mmcboot, 0x0);
645 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
646 esdhc_write32(&regs->mixctrl, 0x0);
647 esdhc_write32(&regs->clktunectrlstatus, 0x0);
648
649 /* Put VEND_SPEC to default value */
650 esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
651
652 /* Disable DLL_CTRL delay line */
653 esdhc_write32(&regs->dllctrl, 0x0);
654#endif
655
Benoît Thébaudeauc08d11c2012-08-13 07:28:16 +0000656#ifndef ARCH_MXC
P.V.Suresh7b1868b2010-12-04 10:37:23 +0530657 /* Enable cache snooping */
Benoît Thébaudeauc08d11c2012-08-13 07:28:16 +0000658 esdhc_write32(&regs->scr, 0x00000040);
659#endif
P.V.Suresh7b1868b2010-12-04 10:37:23 +0530660
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700661#ifndef CONFIG_FSL_USDHC
Dirk Behmedbe67252013-07-15 15:44:29 +0200662 esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
Ye Li5a24f292016-06-15 10:53:01 +0800663#else
664 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700665#endif
Andy Fleminge52ffb82008-10-30 16:47:16 -0500666
667 /* Set the initial clock speed */
Jerry Huang0caea1a2010-11-25 17:06:07 +0000668 mmc_set_clock(mmc, 400000);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500669
670 /* Disable the BRR and BWR bits in IRQSTAT */
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100671 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500672
673 /* Put the PROCTL reg back to the default */
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100674 esdhc_write32(&regs->proctl, PROCTL_INIT);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500675
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100676 /* Set timout to the maximum value */
677 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500678
Peng Fanaee78582017-06-12 17:50:53 +0800679 if (priv->vs18_enable)
680 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
681
Thierry Reding8cee4c982012-01-02 01:15:38 +0000682 return 0;
683}
684
Simon Glass6aa55dc2017-07-29 11:35:18 -0600685static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
Thierry Reding8cee4c982012-01-02 01:15:38 +0000686{
Peng Fana4d36f72016-03-25 14:16:56 +0800687 struct fsl_esdhc *regs = priv->esdhc_regs;
Thierry Reding8cee4c982012-01-02 01:15:38 +0000688 int timeout = 1000;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500689
Haijun.Zhang05f58542014-01-10 13:52:17 +0800690#ifdef CONFIG_ESDHC_DETECT_QUIRK
691 if (CONFIG_ESDHC_DETECT_QUIRK)
692 return 1;
693#endif
Peng Fana4d36f72016-03-25 14:16:56 +0800694
Simon Glass407025d2017-07-29 11:35:24 -0600695#if CONFIG_IS_ENABLED(DM_MMC)
Peng Fana4d36f72016-03-25 14:16:56 +0800696 if (priv->non_removable)
697 return 1;
Yangbo Lub99647c2016-12-07 11:54:30 +0800698#ifdef CONFIG_DM_GPIO
Peng Fana4d36f72016-03-25 14:16:56 +0800699 if (dm_gpio_is_valid(&priv->cd_gpio))
700 return dm_gpio_get_value(&priv->cd_gpio);
701#endif
Yangbo Lub99647c2016-12-07 11:54:30 +0800702#endif
Peng Fana4d36f72016-03-25 14:16:56 +0800703
Thierry Reding8cee4c982012-01-02 01:15:38 +0000704 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
705 udelay(1000);
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100706
Thierry Reding8cee4c982012-01-02 01:15:38 +0000707 return timeout > 0;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500708}
709
Simon Glass81357b52017-07-29 11:35:19 -0600710static int esdhc_reset(struct fsl_esdhc *regs)
Jerry Huangb7ef7562010-03-18 15:57:06 -0500711{
Simon Glass81357b52017-07-29 11:35:19 -0600712 ulong start;
Jerry Huangb7ef7562010-03-18 15:57:06 -0500713
714 /* reset the controller */
Dirk Behmedbe67252013-07-15 15:44:29 +0200715 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
Jerry Huangb7ef7562010-03-18 15:57:06 -0500716
717 /* hardware clears the bit when it is done */
Simon Glass81357b52017-07-29 11:35:19 -0600718 start = get_timer(0);
719 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
720 if (get_timer(start) > 100) {
721 printf("MMC/SD: Reset never completed.\n");
722 return -ETIMEDOUT;
723 }
724 }
725
726 return 0;
Jerry Huangb7ef7562010-03-18 15:57:06 -0500727}
728
Simon Glasseba48f92017-07-29 11:35:31 -0600729#if !CONFIG_IS_ENABLED(DM_MMC)
Simon Glass6aa55dc2017-07-29 11:35:18 -0600730static int esdhc_getcd(struct mmc *mmc)
731{
732 struct fsl_esdhc_priv *priv = mmc->priv;
733
734 return esdhc_getcd_common(priv);
735}
736
737static int esdhc_init(struct mmc *mmc)
738{
739 struct fsl_esdhc_priv *priv = mmc->priv;
740
741 return esdhc_init_common(priv, mmc);
742}
743
744static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
745 struct mmc_data *data)
746{
747 struct fsl_esdhc_priv *priv = mmc->priv;
748
749 return esdhc_send_cmd_common(priv, mmc, cmd, data);
750}
751
752static int esdhc_set_ios(struct mmc *mmc)
753{
754 struct fsl_esdhc_priv *priv = mmc->priv;
755
756 return esdhc_set_ios_common(priv, mmc);
757}
758
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200759static const struct mmc_ops esdhc_ops = {
Simon Glass6aa55dc2017-07-29 11:35:18 -0600760 .getcd = esdhc_getcd,
761 .init = esdhc_init,
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200762 .send_cmd = esdhc_send_cmd,
763 .set_ios = esdhc_set_ios,
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200764};
Simon Glass407025d2017-07-29 11:35:24 -0600765#endif
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200766
Simon Glassfa02ca52017-07-29 11:35:21 -0600767static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
768 struct fsl_esdhc_plat *plat)
Andy Fleminge52ffb82008-10-30 16:47:16 -0500769{
Simon Glassfa02ca52017-07-29 11:35:21 -0600770 struct mmc_config *cfg;
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100771 struct fsl_esdhc *regs;
Li Yangd4933f22010-11-25 17:06:09 +0000772 u32 caps, voltage_caps;
Simon Glass81357b52017-07-29 11:35:19 -0600773 int ret;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500774
Peng Fana4d36f72016-03-25 14:16:56 +0800775 if (!priv)
776 return -EINVAL;
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100777
Peng Fana4d36f72016-03-25 14:16:56 +0800778 regs = priv->esdhc_regs;
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100779
Jerry Huangb7ef7562010-03-18 15:57:06 -0500780 /* First reset the eSDHC controller */
Simon Glass81357b52017-07-29 11:35:19 -0600781 ret = esdhc_reset(regs);
782 if (ret)
783 return ret;
Jerry Huangb7ef7562010-03-18 15:57:06 -0500784
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700785#ifndef CONFIG_FSL_USDHC
Jerry Huang4e3bfa02012-05-17 23:57:02 +0000786 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
787 | SYSCTL_IPGEN | SYSCTL_CKEN);
Ye Li5a24f292016-06-15 10:53:01 +0800788#else
789 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
790 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700791#endif
Jerry Huang4e3bfa02012-05-17 23:57:02 +0000792
Peng Fanaee78582017-06-12 17:50:53 +0800793 if (priv->vs18_enable)
794 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
795
Ye.Li3d46c312014-11-04 15:35:49 +0800796 writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
Simon Glassfa02ca52017-07-29 11:35:21 -0600797 cfg = &plat->cfg;
Simon Glass407025d2017-07-29 11:35:24 -0600798#ifndef CONFIG_DM_MMC
Simon Glassfa02ca52017-07-29 11:35:21 -0600799 memset(cfg, '\0', sizeof(*cfg));
Simon Glass407025d2017-07-29 11:35:24 -0600800#endif
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200801
Li Yangd4933f22010-11-25 17:06:09 +0000802 voltage_caps = 0;
Wang Huanc9292132014-09-05 13:52:40 +0800803 caps = esdhc_read32(&regs->hostcapblt);
Roy Zang39356612011-01-07 00:06:47 -0600804
805#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
806 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
807 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
808#endif
Haijun.Zhang8a065e92013-10-31 09:38:19 +0800809
810/* T4240 host controller capabilities register should have VS33 bit */
811#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
812 caps = caps | ESDHC_HOSTCAPBLT_VS33;
813#endif
814
Andy Fleminge52ffb82008-10-30 16:47:16 -0500815 if (caps & ESDHC_HOSTCAPBLT_VS18)
Li Yangd4933f22010-11-25 17:06:09 +0000816 voltage_caps |= MMC_VDD_165_195;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500817 if (caps & ESDHC_HOSTCAPBLT_VS30)
Li Yangd4933f22010-11-25 17:06:09 +0000818 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500819 if (caps & ESDHC_HOSTCAPBLT_VS33)
Li Yangd4933f22010-11-25 17:06:09 +0000820 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
821
Simon Glassfa02ca52017-07-29 11:35:21 -0600822 cfg->name = "FSL_SDHC";
Simon Glasseba48f92017-07-29 11:35:31 -0600823#if !CONFIG_IS_ENABLED(DM_MMC)
Simon Glassfa02ca52017-07-29 11:35:21 -0600824 cfg->ops = &esdhc_ops;
Simon Glass407025d2017-07-29 11:35:24 -0600825#endif
Li Yangd4933f22010-11-25 17:06:09 +0000826#ifdef CONFIG_SYS_SD_VOLTAGE
Simon Glassfa02ca52017-07-29 11:35:21 -0600827 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
Li Yangd4933f22010-11-25 17:06:09 +0000828#else
Simon Glassfa02ca52017-07-29 11:35:21 -0600829 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
Li Yangd4933f22010-11-25 17:06:09 +0000830#endif
Simon Glassfa02ca52017-07-29 11:35:21 -0600831 if ((cfg->voltages & voltage_caps) == 0) {
Li Yangd4933f22010-11-25 17:06:09 +0000832 printf("voltage not supported by controller\n");
833 return -1;
834 }
Andy Fleminge52ffb82008-10-30 16:47:16 -0500835
Peng Fana4d36f72016-03-25 14:16:56 +0800836 if (priv->bus_width == 8)
Simon Glassfa02ca52017-07-29 11:35:21 -0600837 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
Peng Fana4d36f72016-03-25 14:16:56 +0800838 else if (priv->bus_width == 4)
Simon Glassfa02ca52017-07-29 11:35:21 -0600839 cfg->host_caps = MMC_MODE_4BIT;
Peng Fana4d36f72016-03-25 14:16:56 +0800840
Simon Glassfa02ca52017-07-29 11:35:21 -0600841 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
Volodymyr Riazantsevd251e112015-01-20 10:16:44 -0500842#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
Simon Glassfa02ca52017-07-29 11:35:21 -0600843 cfg->host_caps |= MMC_MODE_DDR_52MHz;
Volodymyr Riazantsevd251e112015-01-20 10:16:44 -0500844#endif
Andy Fleminge52ffb82008-10-30 16:47:16 -0500845
Peng Fana4d36f72016-03-25 14:16:56 +0800846 if (priv->bus_width > 0) {
847 if (priv->bus_width < 8)
Simon Glassfa02ca52017-07-29 11:35:21 -0600848 cfg->host_caps &= ~MMC_MODE_8BIT;
Peng Fana4d36f72016-03-25 14:16:56 +0800849 if (priv->bus_width < 4)
Simon Glassfa02ca52017-07-29 11:35:21 -0600850 cfg->host_caps &= ~MMC_MODE_4BIT;
Abbas Razae6bf9772013-03-25 09:13:34 +0000851 }
852
Andy Fleminge52ffb82008-10-30 16:47:16 -0500853 if (caps & ESDHC_HOSTCAPBLT_HSS)
Simon Glassfa02ca52017-07-29 11:35:21 -0600854 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500855
Haijun.Zhangf0fe8ad2014-01-10 13:52:18 +0800856#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
857 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
Simon Glassfa02ca52017-07-29 11:35:21 -0600858 cfg->host_caps &= ~MMC_MODE_8BIT;
Haijun.Zhangf0fe8ad2014-01-10 13:52:18 +0800859#endif
860
Simon Glassfa02ca52017-07-29 11:35:21 -0600861 cfg->f_min = 400000;
862 cfg->f_max = min(priv->sdhc_clk, (u32)52000000);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500863
Simon Glassfa02ca52017-07-29 11:35:21 -0600864 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200865
Peng Fana4d36f72016-03-25 14:16:56 +0800866 return 0;
867}
868
Simon Glassb9876e22017-07-29 11:35:28 -0600869#if !CONFIG_IS_ENABLED(DM_MMC)
Jagan Teki3c2cc6d2017-05-12 17:18:20 +0530870static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
871 struct fsl_esdhc_priv *priv)
872{
873 if (!cfg || !priv)
874 return -EINVAL;
875
876 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
877 priv->bus_width = cfg->max_bus_width;
878 priv->sdhc_clk = cfg->sdhc_clk;
879 priv->wp_enable = cfg->wp_enable;
Peng Fanaee78582017-06-12 17:50:53 +0800880 priv->vs18_enable = cfg->vs18_enable;
Jagan Teki3c2cc6d2017-05-12 17:18:20 +0530881
882 return 0;
883};
884
Peng Fana4d36f72016-03-25 14:16:56 +0800885int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
886{
Simon Glassfa02ca52017-07-29 11:35:21 -0600887 struct fsl_esdhc_plat *plat;
Peng Fana4d36f72016-03-25 14:16:56 +0800888 struct fsl_esdhc_priv *priv;
Simon Glass5ee39802017-07-29 11:35:22 -0600889 struct mmc *mmc;
Peng Fana4d36f72016-03-25 14:16:56 +0800890 int ret;
891
892 if (!cfg)
893 return -EINVAL;
894
895 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
896 if (!priv)
897 return -ENOMEM;
Simon Glassfa02ca52017-07-29 11:35:21 -0600898 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
899 if (!plat) {
900 free(priv);
901 return -ENOMEM;
902 }
Peng Fana4d36f72016-03-25 14:16:56 +0800903
904 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
905 if (ret) {
906 debug("%s xlate failure\n", __func__);
Simon Glassfa02ca52017-07-29 11:35:21 -0600907 free(plat);
Peng Fana4d36f72016-03-25 14:16:56 +0800908 free(priv);
909 return ret;
910 }
911
Simon Glassfa02ca52017-07-29 11:35:21 -0600912 ret = fsl_esdhc_init(priv, plat);
Peng Fana4d36f72016-03-25 14:16:56 +0800913 if (ret) {
914 debug("%s init failure\n", __func__);
Simon Glassfa02ca52017-07-29 11:35:21 -0600915 free(plat);
Peng Fana4d36f72016-03-25 14:16:56 +0800916 free(priv);
917 return ret;
918 }
919
Simon Glass5ee39802017-07-29 11:35:22 -0600920 mmc = mmc_create(&plat->cfg, priv);
921 if (!mmc)
922 return -EIO;
923
924 priv->mmc = mmc;
925
Andy Fleminge52ffb82008-10-30 16:47:16 -0500926 return 0;
927}
928
929int fsl_esdhc_mmc_init(bd_t *bis)
930{
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100931 struct fsl_esdhc_cfg *cfg;
932
Fabio Estevam6592a992012-12-27 08:51:08 +0000933 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100934 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
Simon Glass9e247d12012-12-13 20:49:05 +0000935 cfg->sdhc_clk = gd->arch.sdhc_clk;
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100936 return fsl_esdhc_initialize(bis, cfg);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500937}
Jagan Teki3c2cc6d2017-05-12 17:18:20 +0530938#endif
Anton Vorontsovf751a3c2009-06-10 00:25:29 +0400939
Yangbo Lub124f8a2015-04-22 13:57:00 +0800940#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
941void mmc_adapter_card_type_ident(void)
942{
943 u8 card_id;
944 u8 value;
945
946 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
947 gd->arch.sdhc_adapter = card_id;
948
949 switch (card_id) {
950 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
Yangbo Lu81eacd62015-09-17 10:27:12 +0800951 value = QIXIS_READ(brdcfg[5]);
952 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
953 QIXIS_WRITE(brdcfg[5], value);
Yangbo Lub124f8a2015-04-22 13:57:00 +0800954 break;
955 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
Yangbo Luc6799ce2015-09-17 10:27:48 +0800956 value = QIXIS_READ(pwr_ctl[1]);
957 value |= QIXIS_EVDD_BY_SDHC_VS;
958 QIXIS_WRITE(pwr_ctl[1], value);
Yangbo Lub124f8a2015-04-22 13:57:00 +0800959 break;
960 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
961 value = QIXIS_READ(brdcfg[5]);
962 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
963 QIXIS_WRITE(brdcfg[5], value);
964 break;
965 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
966 break;
967 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
968 break;
969 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
970 break;
971 case QIXIS_ESDHC_NO_ADAPTER:
972 break;
973 default:
974 break;
975 }
976}
977#endif
978
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100979#ifdef CONFIG_OF_LIBFDT
Yangbo Lud84139c2017-01-17 10:43:54 +0800980__weak int esdhc_status_fixup(void *blob, const char *compat)
Anton Vorontsovf751a3c2009-06-10 00:25:29 +0400981{
Chenhui Zhao025eab02011-01-04 17:23:05 +0800982#ifdef CONFIG_FSL_ESDHC_PIN_MUX
Anton Vorontsovf751a3c2009-06-10 00:25:29 +0400983 if (!hwconfig("esdhc")) {
Chenhui Zhao025eab02011-01-04 17:23:05 +0800984 do_fixup_by_compat(blob, compat, "status", "disabled",
Yangbo Lud84139c2017-01-17 10:43:54 +0800985 sizeof("disabled"), 1);
986 return 1;
Anton Vorontsovf751a3c2009-06-10 00:25:29 +0400987 }
Chenhui Zhao025eab02011-01-04 17:23:05 +0800988#endif
Yangbo Lud84139c2017-01-17 10:43:54 +0800989 return 0;
990}
991
992void fdt_fixup_esdhc(void *blob, bd_t *bd)
993{
994 const char *compat = "fsl,esdhc";
995
996 if (esdhc_status_fixup(blob, compat))
997 return;
Anton Vorontsovf751a3c2009-06-10 00:25:29 +0400998
Yangbo Lu163beec2015-04-22 13:57:40 +0800999#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1000 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1001 gd->arch.sdhc_clk, 1);
1002#else
Anton Vorontsovf751a3c2009-06-10 00:25:29 +04001003 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
Simon Glass9e247d12012-12-13 20:49:05 +00001004 gd->arch.sdhc_clk, 1);
Yangbo Lu163beec2015-04-22 13:57:40 +08001005#endif
Yangbo Lub124f8a2015-04-22 13:57:00 +08001006#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1007 do_fixup_by_compat_u32(blob, compat, "adapter-type",
1008 (u32)(gd->arch.sdhc_adapter), 1);
1009#endif
Anton Vorontsovf751a3c2009-06-10 00:25:29 +04001010}
Stefano Babicff7a5ca2010-02-05 15:11:27 +01001011#endif
Peng Fana4d36f72016-03-25 14:16:56 +08001012
Simon Glass407025d2017-07-29 11:35:24 -06001013#if CONFIG_IS_ENABLED(DM_MMC)
Peng Fana4d36f72016-03-25 14:16:56 +08001014#include <asm/arch/clock.h>
Peng Fanaf6dbc02017-02-22 16:21:55 +08001015__weak void init_clk_usdhc(u32 index)
1016{
1017}
1018
Peng Fana4d36f72016-03-25 14:16:56 +08001019static int fsl_esdhc_probe(struct udevice *dev)
1020{
1021 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
Simon Glassfa02ca52017-07-29 11:35:21 -06001022 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
Peng Fana4d36f72016-03-25 14:16:56 +08001023 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
York Sun107a5e42017-08-08 15:45:13 -07001024#ifdef CONFIG_DM_REGULATOR
Peng Fan5eb8b432017-06-12 17:50:54 +08001025 struct udevice *vqmmc_dev;
York Sun107a5e42017-08-08 15:45:13 -07001026#endif
Peng Fana4d36f72016-03-25 14:16:56 +08001027 fdt_addr_t addr;
1028 unsigned int val;
Simon Glass407025d2017-07-29 11:35:24 -06001029 struct mmc *mmc;
Peng Fana4d36f72016-03-25 14:16:56 +08001030 int ret;
1031
Simon Glass80e9df42017-07-29 11:35:23 -06001032 addr = dev_read_addr(dev);
Peng Fana4d36f72016-03-25 14:16:56 +08001033 if (addr == FDT_ADDR_T_NONE)
1034 return -EINVAL;
1035
1036 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1037 priv->dev = dev;
1038
Simon Glass80e9df42017-07-29 11:35:23 -06001039 val = dev_read_u32_default(dev, "bus-width", -1);
Peng Fana4d36f72016-03-25 14:16:56 +08001040 if (val == 8)
1041 priv->bus_width = 8;
1042 else if (val == 4)
1043 priv->bus_width = 4;
1044 else
1045 priv->bus_width = 1;
1046
Simon Glass80e9df42017-07-29 11:35:23 -06001047 if (dev_read_bool(dev, "non-removable")) {
Peng Fana4d36f72016-03-25 14:16:56 +08001048 priv->non_removable = 1;
1049 } else {
1050 priv->non_removable = 0;
Yangbo Lub99647c2016-12-07 11:54:30 +08001051#ifdef CONFIG_DM_GPIO
Simon Glass80e9df42017-07-29 11:35:23 -06001052 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1053 GPIOD_IS_IN);
Yangbo Lub99647c2016-12-07 11:54:30 +08001054#endif
Peng Fana4d36f72016-03-25 14:16:56 +08001055 }
1056
Peng Fan01eb1c42016-06-15 10:53:02 +08001057 priv->wp_enable = 1;
1058
Yangbo Lub99647c2016-12-07 11:54:30 +08001059#ifdef CONFIG_DM_GPIO
Simon Glass80e9df42017-07-29 11:35:23 -06001060 ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1061 GPIOD_IS_IN);
Peng Fan01eb1c42016-06-15 10:53:02 +08001062 if (ret)
1063 priv->wp_enable = 0;
Yangbo Lub99647c2016-12-07 11:54:30 +08001064#endif
Peng Fan5eb8b432017-06-12 17:50:54 +08001065
1066 priv->vs18_enable = 0;
1067
1068#ifdef CONFIG_DM_REGULATOR
1069 /*
1070 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1071 * otherwise, emmc will work abnormally.
1072 */
1073 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1074 if (ret) {
1075 dev_dbg(dev, "no vqmmc-supply\n");
1076 } else {
1077 ret = regulator_set_enable(vqmmc_dev, true);
1078 if (ret) {
1079 dev_err(dev, "fail to enable vqmmc-supply\n");
1080 return ret;
1081 }
1082
1083 if (regulator_get_value(vqmmc_dev) == 1800000)
1084 priv->vs18_enable = 1;
1085 }
1086#endif
1087
Peng Fana4d36f72016-03-25 14:16:56 +08001088 /*
1089 * TODO:
1090 * Because lack of clk driver, if SDHC clk is not enabled,
1091 * need to enable it first before this driver is invoked.
1092 *
1093 * we use MXC_ESDHC_CLK to get clk freq.
1094 * If one would like to make this function work,
1095 * the aliases should be provided in dts as this:
1096 *
1097 * aliases {
1098 * mmc0 = &usdhc1;
1099 * mmc1 = &usdhc2;
1100 * mmc2 = &usdhc3;
1101 * mmc3 = &usdhc4;
1102 * };
1103 * Then if your board only supports mmc2 and mmc3, but we can
1104 * correctly get the seq as 2 and 3, then let mxc_get_clock
1105 * work as expected.
1106 */
Peng Fanaf6dbc02017-02-22 16:21:55 +08001107
1108 init_clk_usdhc(dev->seq);
1109
Peng Fana4d36f72016-03-25 14:16:56 +08001110 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1111 if (priv->sdhc_clk <= 0) {
1112 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1113 return -EINVAL;
1114 }
1115
Simon Glassfa02ca52017-07-29 11:35:21 -06001116 ret = fsl_esdhc_init(priv, plat);
Peng Fana4d36f72016-03-25 14:16:56 +08001117 if (ret) {
1118 dev_err(dev, "fsl_esdhc_init failure\n");
1119 return ret;
1120 }
1121
Simon Glass407025d2017-07-29 11:35:24 -06001122 mmc = &plat->mmc;
1123 mmc->cfg = &plat->cfg;
1124 mmc->dev = dev;
1125 upriv->mmc = mmc;
Peng Fana4d36f72016-03-25 14:16:56 +08001126
Simon Glass407025d2017-07-29 11:35:24 -06001127 return esdhc_init_common(priv, mmc);
Peng Fana4d36f72016-03-25 14:16:56 +08001128}
1129
Simon Glasseba48f92017-07-29 11:35:31 -06001130#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glass407025d2017-07-29 11:35:24 -06001131static int fsl_esdhc_get_cd(struct udevice *dev)
1132{
1133 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1134
1135 return true;
1136 return esdhc_getcd_common(priv);
1137}
1138
1139static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1140 struct mmc_data *data)
1141{
1142 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1143 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1144
1145 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1146}
1147
1148static int fsl_esdhc_set_ios(struct udevice *dev)
1149{
1150 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1151 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1152
1153 return esdhc_set_ios_common(priv, &plat->mmc);
1154}
1155
1156static const struct dm_mmc_ops fsl_esdhc_ops = {
1157 .get_cd = fsl_esdhc_get_cd,
1158 .send_cmd = fsl_esdhc_send_cmd,
1159 .set_ios = fsl_esdhc_set_ios,
1160};
1161#endif
1162
Peng Fana4d36f72016-03-25 14:16:56 +08001163static const struct udevice_id fsl_esdhc_ids[] = {
1164 { .compatible = "fsl,imx6ul-usdhc", },
1165 { .compatible = "fsl,imx6sx-usdhc", },
1166 { .compatible = "fsl,imx6sl-usdhc", },
1167 { .compatible = "fsl,imx6q-usdhc", },
1168 { .compatible = "fsl,imx7d-usdhc", },
Peng Fanaf6dbc02017-02-22 16:21:55 +08001169 { .compatible = "fsl,imx7ulp-usdhc", },
Yangbo Lu2a99b602016-12-07 11:54:31 +08001170 { .compatible = "fsl,esdhc", },
Peng Fana4d36f72016-03-25 14:16:56 +08001171 { /* sentinel */ }
1172};
1173
Simon Glass407025d2017-07-29 11:35:24 -06001174#if CONFIG_IS_ENABLED(BLK)
1175static int fsl_esdhc_bind(struct udevice *dev)
1176{
1177 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1178
1179 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1180}
1181#endif
1182
Peng Fana4d36f72016-03-25 14:16:56 +08001183U_BOOT_DRIVER(fsl_esdhc) = {
1184 .name = "fsl-esdhc-mmc",
1185 .id = UCLASS_MMC,
1186 .of_match = fsl_esdhc_ids,
Simon Glass407025d2017-07-29 11:35:24 -06001187 .ops = &fsl_esdhc_ops,
Simon Glass407025d2017-07-29 11:35:24 -06001188#if CONFIG_IS_ENABLED(BLK)
1189 .bind = fsl_esdhc_bind,
1190#endif
Peng Fana4d36f72016-03-25 14:16:56 +08001191 .probe = fsl_esdhc_probe,
Simon Glassfa02ca52017-07-29 11:35:21 -06001192 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
Peng Fana4d36f72016-03-25 14:16:56 +08001193 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
1194};
1195#endif