| commit | 4a929627dfaa2970630467a7b6b1e8e94a1aadaf | [log] [tgz] |
|---|---|---|
| author | Andrew Gabbasov <andrew_gabbasov@mentor.com> | Sun Apr 07 23:06:08 2013 +0000 |
| committer | Stefano Babic <sbabic@denx.de> | Sun Apr 14 11:22:47 2013 +0200 |
| tree | de12f8c9a57135903b70ae9895fdc8a97397fee7 | |
| parent | 70e68696c7261a71f2f6d5ea6cda9434d7d1d618 [diff] |
fsl_esdhc: Fix DMA transfer completion waiting loop Rework the waiting for transfer completion loop condition to continue waiting until both Transfer Complete and DMA End interrupts occur. Checking of DLA bit in Present State register looks not needed in addition to interrupts status checking, so it can be removed from the condition. Also, DMA Error condition is added to the list of data errors, checked in the loop. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>