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git01.mediatek.com / filogic / uboot / 82a17e6a32be45d053d167286ca4f6e089d36c22 / . / arch / x86 / cpu / i386 / interrupt.c
blob: 47df3172b78f886f952b12b1a59a64a27ebcd541 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]2/*
Graeme Russ45fc1d82011-04-13 19:43:26 +1000[diff] [blame]3 * (C) Copyright 2008-2011
4 * Graeme Russ, <graeme.russ@gmail.com>
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]5 *
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]6 * (C) Copyright 2002
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +0200[diff] [blame]7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]8 *
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]9 * Portions of this file are derived from the Linux kernel source
10 * Copyright (C) 1991, 1992 Linus Torvalds
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]11 */
12
13#include <common.h>
Simon Glass754f55e2016-01-19 21:32:26 -0700[diff] [blame]14#include <dm.h>
Stefan Reinauer2acf8482012-12-02 04:49:50 +0000[diff] [blame]15#include <asm/control_regs.h>
Bin Mengd538c362016-05-22 01:45:33 -0700[diff] [blame]16#include <asm/i8259.h>
Graeme Russ0c8c62e2008-12-07 10:29:01 +1100[diff] [blame]17#include <asm/interrupt.h>
Graeme Russ68699802011-02-12 15:11:28 +1100[diff] [blame]18#include <asm/io.h>
Bin Mengd538c362016-05-22 01:45:33 -0700[diff] [blame]19#include <asm/lapic.h>
Bin Mengd538c362016-05-22 01:45:33 -0700[diff] [blame]20#include <asm/processor-flags.h>
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]21
Simon Glassbb6306c2013-04-17 16:13:33 +0000[diff] [blame]22DECLARE_GLOBAL_DATA_PTR;
23
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]24#define DECLARE_INTERRUPT(x) \
25 ".globl irq_"#x"\n" \
Graeme Russ1aafcc92009-11-24 20:04:19 +1100[diff] [blame]26 ".hidden irq_"#x"\n" \
27 ".type irq_"#x", @function\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]28 "irq_"#x":\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]29 "pushl $"#x"\n" \
J. Tang6c0712a2017-02-09 21:54:13 -0500[diff] [blame]30 "jmp.d32 irq_common_entry\n"
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]31
Bin Mengfdebed82015-07-10 10:51:23 +0800[diff] [blame]32static char *exceptions[] = {
33 "Divide Error",
34 "Debug",
35 "NMI Interrupt",
36 "Breakpoint",
37 "Overflow",
38 "BOUND Range Exceeded",
39 "Invalid Opcode (Undefined Opcode)",
Vagrant Cascadian973c0992019-05-03 14:28:37 -0800[diff] [blame]40 "Device Not Available (No Math Coprocessor)",
Bin Mengfdebed82015-07-10 10:51:23 +0800[diff] [blame]41 "Double Fault",
42 "Coprocessor Segment Overrun",
43 "Invalid TSS",
44 "Segment Not Present",
45 "Stack Segment Fault",
Simon Glassc4b9ef82015-07-31 09:31:32 -0600[diff] [blame]46 "General Protection",
Bin Mengfdebed82015-07-10 10:51:23 +0800[diff] [blame]47 "Page Fault",
48 "Reserved",
49 "x87 FPU Floating-Point Error",
50 "Alignment Check",
51 "Machine Check",
52 "SIMD Floating-Point Exception",
53 "Virtualization Exception",
54 "Reserved",
55 "Reserved",
56 "Reserved",
57 "Reserved",
58 "Reserved",
59 "Reserved",
60 "Reserved",
61 "Reserved",
62 "Reserved",
63 "Reserved",
64 "Reserved"
65};
66
Simon Glass83374332014-11-06 13:20:08 -0700[diff] [blame]67static void dump_regs(struct irq_regs *regs)
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]68{
Bin Meng9ff054b2015-07-10 10:38:32 +0800[diff] [blame]69 unsigned long cs, eip, eflags;
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]70 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
71 unsigned long d0, d1, d2, d3, d6, d7;
Graeme Russ68699802011-02-12 15:11:28 +1100[diff] [blame]72 unsigned long sp;
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]73
Bin Meng9ff054b2015-07-10 10:38:32 +0800[diff] [blame]74 /*
75 * Some exceptions cause an error code to be saved on the current stack
76 * after the EIP value. We should extract CS/EIP/EFLAGS from different
77 * position on the stack based on the exception number.
78 */
79 switch (regs->irq_id) {
80 case EXC_DF:
81 case EXC_TS:
82 case EXC_NP:
83 case EXC_SS:
84 case EXC_GP:
85 case EXC_PF:
86 case EXC_AC:
87 cs = regs->context.ctx2.xcs;
88 eip = regs->context.ctx2.eip;
89 eflags = regs->context.ctx2.eflags;
90 /* We should fix up the ESP due to error code */
91 regs->esp += 4;
92 break;
93 default:
94 cs = regs->context.ctx1.xcs;
95 eip = regs->context.ctx1.eip;
96 eflags = regs->context.ctx1.eflags;
97 break;
98 }
99
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]100 printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
Bin Meng9ff054b2015-07-10 10:38:32 +0800[diff] [blame]101 (u16)cs, eip, eflags);
Simon Glass79dd4342015-08-10 22:02:54 -0600[diff] [blame]102 if (gd->flags & GD_FLG_RELOC)
103 printf("Original EIP :[<%08lx>]\n", eip - gd->reloc_off);
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]104
105 printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
106 regs->eax, regs->ebx, regs->ecx, regs->edx);
107 printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
108 regs->esi, regs->edi, regs->ebp, regs->esp);
109 printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]110 (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
111 (u16)regs->xgs, (u16)regs->xss);
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]112
113 cr0 = read_cr0();
114 cr2 = read_cr2();
115 cr3 = read_cr3();
116 cr4 = read_cr4();
117
118 printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
119 cr0, cr2, cr3, cr4);
120
121 d0 = get_debugreg(0);
122 d1 = get_debugreg(1);
123 d2 = get_debugreg(2);
124 d3 = get_debugreg(3);
125
126 printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
127 d0, d1, d2, d3);
128
129 d6 = get_debugreg(6);
130 d7 = get_debugreg(7);
131 printf("DR6: %08lx DR7: %08lx\n",
132 d6, d7);
Graeme Russ68699802011-02-12 15:11:28 +1100[diff] [blame]133
134 printf("Stack:\n");
135 sp = regs->esp;
136
137 sp += 64;
138
139 while (sp > (regs->esp - 16)) {
140 if (sp == regs->esp)
141 printf("--->");
142 else
143 printf(" ");
144 printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
145 sp -= 4;
146 }
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]147}
148
Bin Mengfdebed82015-07-10 10:51:23 +0800[diff] [blame]149static void do_exception(struct irq_regs *regs)
150{
151 printf("%s\n", exceptions[regs->irq_id]);
152 dump_regs(regs);
153 hang();
154}
155
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]156struct idt_entry {
157 u16 base_low;
158 u16 selector;
159 u8 res;
160 u8 access;
161 u16 base_high;
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]162} __packed;
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]163
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]164struct desc_ptr {
165 unsigned short size;
166 unsigned long address;
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]167} __packed;
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]168
Graeme Russaf3f2c82011-12-19 14:26:18 +1100[diff] [blame]169struct idt_entry idt[256] __aligned(16);
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]170
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]171struct desc_ptr idt_ptr;
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]172
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]173static inline void load_idt(const struct desc_ptr *dtr)
174{
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]175 asm volatile("cs lidt %0" : : "m" (*dtr));
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]176}
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]177
Graeme Russ77290ee2009-02-24 21:13:40 +1100[diff] [blame]178void set_vector(u8 intnum, void *routine)
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]179{
Simon Glassb58770f2016-09-25 21:33:25 -0600[diff] [blame]180 idt[intnum].base_high = (u16)((ulong)(routine) >> 16);
181 idt[intnum].base_low = (u16)((ulong)(routine) & 0xffff);
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]182}
183
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]184/*
185 * Ideally these would be defined static to avoid a checkpatch warning, but
186 * the compiler cannot see them in the inline asm and complains that they
187 * aren't defined
188 */
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]189void irq_0(void);
190void irq_1(void);
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]191
Graeme Russ77290ee2009-02-24 21:13:40 +1100[diff] [blame]192int cpu_init_interrupts(void)
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]193{
194 int i;
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]195
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]196 int irq_entry_size = irq_1 - irq_0;
197 void *irq_entry = (void *)irq_0;
198
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]199 /* Setup the IDT */
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]200 for (i = 0; i < 256; i++) {
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]201 idt[i].access = 0x8e;
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]202 idt[i].res = 0;
Simon Glassc4b9ef82015-07-31 09:31:32 -0600[diff] [blame]203 idt[i].selector = X86_GDT_ENTRY_32BIT_CS * X86_GDT_ENTRY_SIZE;
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]204 set_vector(i, irq_entry);
205 irq_entry += irq_entry_size;
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]206 }
207
Simon Glassc4b9ef82015-07-31 09:31:32 -0600[diff] [blame]208 idt_ptr.size = 256 * 8 - 1;
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]209 idt_ptr.address = (unsigned long) idt;
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]210
211 load_idt(&idt_ptr);
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]212
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]213 return 0;
214}
215
Simon Glass98d7e982015-04-28 20:25:16 -0600[diff] [blame]216void *x86_get_idt(void)
217{
218 return &idt_ptr;
219}
220
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]221void __do_irq(int irq)
222{
223 printf("Unhandled IRQ : %d\n", irq);
224}
225void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
226
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]227void enable_interrupts(void)
228{
229 asm("sti\n");
230}
231
232int disable_interrupts(void)
233{
234 long flags;
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]235
Simon Glass1560a632017-01-16 07:04:00 -0700[diff] [blame]236#if CONFIG_IS_ENABLED(X86_64)
Simon Glass87086d52016-09-25 21:33:23 -0600[diff] [blame]237 asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : );
238#else
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]239 asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
Simon Glass87086d52016-09-25 21:33:23 -0600[diff] [blame]240#endif
Graeme Russfdee8b12011-11-08 02:33:13 +0000[diff] [blame]241 return flags & X86_EFLAGS_IF;
wdenk591dda52002-11-18 00:14:45 +0000[diff] [blame]242}
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]243
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800[diff] [blame]244int interrupt_init(void)
245{
Simon Glass754f55e2016-01-19 21:32:26 -0700[diff] [blame]246 struct udevice *dev;
247 int ret;
248
249 /* Try to set up the interrupt router, but don't require one */
Simon Glassc7298e72016-02-11 13:23:26 -0700[diff] [blame]250 ret = uclass_first_device_err(UCLASS_IRQ, &dev);
Simon Glass754f55e2016-01-19 21:32:26 -0700[diff] [blame]251 if (ret && ret != -ENODEV)
252 return ret;
253
Ben Stoltzab76a472015-08-04 12:33:46 -0600[diff] [blame]254 /*
255 * When running as an EFI application we are not in control of
256 * interrupts and should leave them alone.
257 */
258#ifndef CONFIG_EFI_APP
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800[diff] [blame]259 /* Just in case... */
260 disable_interrupts();
261
Bin Mengb29a08c2015-10-22 19:13:30 -0700[diff] [blame]262#ifdef CONFIG_I8259_PIC
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800[diff] [blame]263 /* Initialize the master/slave i8259 pic */
264 i8259_init();
265#endif
266
Hannes Schmelzerd18df3c2018-11-18 23:19:43 +0100[diff] [blame]267#ifdef CONFIG_APIC
Bin Mengd538c362016-05-22 01:45:33 -0700[diff] [blame]268 lapic_setup();
Hannes Schmelzerd18df3c2018-11-18 23:19:43 +0100[diff] [blame]269#endif
Bin Mengd538c362016-05-22 01:45:33 -0700[diff] [blame]270
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800[diff] [blame]271 /* Initialize core interrupt and exception functionality of CPU */
272 cpu_init_interrupts();
273
Simon Glass2b6d80b2015-08-04 12:34:00 -0600[diff] [blame]274 /*
275 * It is now safe to enable interrupts.
276 *
277 * TODO(sjg@chromium.org): But we don't handle these correctly when
278 * booted from EFI.
279 */
280 if (ll_boot_init())
281 enable_interrupts();
Ben Stoltzab76a472015-08-04 12:33:46 -0600[diff] [blame]282#endif
Bin Mengcb9d9cb2014-11-20 16:11:16 +0800[diff] [blame]283
284 return 0;
285}
286
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]287/* IRQ Low-Level Service Routine */
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]288void irq_llsr(struct irq_regs *regs)
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]289{
290 /*
291 * For detailed description of each exception, refer to:
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +0200[diff] [blame]292 * Intel® 64 and IA-32 Architectures Software Developer's Manual
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]293 * Volume 1: Basic Architecture
294 * Order Number: 253665-029US, November 2008
295 * Table 6-1. Exceptions and Interrupts
296 */
Bin Mengfdebed82015-07-10 10:51:23 +0800[diff] [blame]297 if (regs->irq_id < 32) {
298 /* Architecture defined exception */
299 do_exception(regs);
300 } else {
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]301 /* Hardware or User IRQ */
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]302 do_irq(regs->irq_id);
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]303 }
304}
305
306/*
307 * OK - This looks really horrible, but it serves a purpose - It helps create
308 * fully relocatable code.
309 * - The call to irq_llsr will be a relative jump
310 * - The IRQ entries will be guaranteed to be in order
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]311 * Interrupt entries are now very small (a push and a jump) but they are
312 * now slower (all registers pushed on stack which provides complete
313 * crash dumps in the low level handlers
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]314 *
315 * Interrupt Entry Point:
316 * - Interrupt has caused eflags, CS and EIP to be pushed
317 * - Interrupt Vector Handler has pushed orig_eax
318 * - pt_regs.esp needs to be adjusted by 40 bytes:
319 * 12 bytes pushed by CPU (EFLAGSF, CS, EIP)
320 * 4 bytes pushed by vector handler (irq_id)
321 * 24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
322 * NOTE: Only longs are pushed on/popped off the stack!
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]323 */
324asm(".globl irq_common_entry\n" \
Graeme Russ1aafcc92009-11-24 20:04:19 +1100[diff] [blame]325 ".hidden irq_common_entry\n" \
326 ".type irq_common_entry, @function\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]327 "irq_common_entry:\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]328 "cld\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]329 "pushl %ss\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]330 "pushl %gs\n" \
331 "pushl %fs\n" \
332 "pushl %es\n" \
333 "pushl %ds\n" \
334 "pushl %eax\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]335 "movl %esp, %eax\n" \
336 "addl $40, %eax\n" \
337 "pushl %eax\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]338 "pushl %ebp\n" \
339 "pushl %edi\n" \
340 "pushl %esi\n" \
341 "pushl %edx\n" \
342 "pushl %ecx\n" \
343 "pushl %ebx\n" \
344 "mov %esp, %eax\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]345 "call irq_llsr\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]346 "popl %ebx\n" \
347 "popl %ecx\n" \
348 "popl %edx\n" \
349 "popl %esi\n" \
350 "popl %edi\n" \
351 "popl %ebp\n" \
352 "popl %eax\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]353 "popl %eax\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]354 "popl %ds\n" \
355 "popl %es\n" \
356 "popl %fs\n" \
357 "popl %gs\n" \
Graeme Russ43261532010-10-07 20:03:23 +1100[diff] [blame]358 "popl %ss\n" \
Graeme Russc39acb42010-04-24 00:05:38 +1000[diff] [blame]359 "add $4, %esp\n" \
Graeme Russd11b0852009-11-24 20:04:18 +1100[diff] [blame]360 "iret\n" \
361 DECLARE_INTERRUPT(0) \
362 DECLARE_INTERRUPT(1) \
363 DECLARE_INTERRUPT(2) \
364 DECLARE_INTERRUPT(3) \
365 DECLARE_INTERRUPT(4) \
366 DECLARE_INTERRUPT(5) \
367 DECLARE_INTERRUPT(6) \
368 DECLARE_INTERRUPT(7) \
369 DECLARE_INTERRUPT(8) \
370 DECLARE_INTERRUPT(9) \
371 DECLARE_INTERRUPT(10) \
372 DECLARE_INTERRUPT(11) \
373 DECLARE_INTERRUPT(12) \
374 DECLARE_INTERRUPT(13) \
375 DECLARE_INTERRUPT(14) \
376 DECLARE_INTERRUPT(15) \
377 DECLARE_INTERRUPT(16) \
378 DECLARE_INTERRUPT(17) \
379 DECLARE_INTERRUPT(18) \
380 DECLARE_INTERRUPT(19) \
381 DECLARE_INTERRUPT(20) \
382 DECLARE_INTERRUPT(21) \
383 DECLARE_INTERRUPT(22) \
384 DECLARE_INTERRUPT(23) \
385 DECLARE_INTERRUPT(24) \
386 DECLARE_INTERRUPT(25) \
387 DECLARE_INTERRUPT(26) \
388 DECLARE_INTERRUPT(27) \
389 DECLARE_INTERRUPT(28) \
390 DECLARE_INTERRUPT(29) \
391 DECLARE_INTERRUPT(30) \
392 DECLARE_INTERRUPT(31) \
393 DECLARE_INTERRUPT(32) \
394 DECLARE_INTERRUPT(33) \
395 DECLARE_INTERRUPT(34) \
396 DECLARE_INTERRUPT(35) \
397 DECLARE_INTERRUPT(36) \
398 DECLARE_INTERRUPT(37) \
399 DECLARE_INTERRUPT(38) \
400 DECLARE_INTERRUPT(39) \
401 DECLARE_INTERRUPT(40) \
402 DECLARE_INTERRUPT(41) \
403 DECLARE_INTERRUPT(42) \
404 DECLARE_INTERRUPT(43) \
405 DECLARE_INTERRUPT(44) \
406 DECLARE_INTERRUPT(45) \
407 DECLARE_INTERRUPT(46) \
408 DECLARE_INTERRUPT(47) \
409 DECLARE_INTERRUPT(48) \
410 DECLARE_INTERRUPT(49) \
411 DECLARE_INTERRUPT(50) \
412 DECLARE_INTERRUPT(51) \
413 DECLARE_INTERRUPT(52) \
414 DECLARE_INTERRUPT(53) \
415 DECLARE_INTERRUPT(54) \
416 DECLARE_INTERRUPT(55) \
417 DECLARE_INTERRUPT(56) \
418 DECLARE_INTERRUPT(57) \
419 DECLARE_INTERRUPT(58) \
420 DECLARE_INTERRUPT(59) \
421 DECLARE_INTERRUPT(60) \
422 DECLARE_INTERRUPT(61) \
423 DECLARE_INTERRUPT(62) \
424 DECLARE_INTERRUPT(63) \
425 DECLARE_INTERRUPT(64) \
426 DECLARE_INTERRUPT(65) \
427 DECLARE_INTERRUPT(66) \
428 DECLARE_INTERRUPT(67) \
429 DECLARE_INTERRUPT(68) \
430 DECLARE_INTERRUPT(69) \
431 DECLARE_INTERRUPT(70) \
432 DECLARE_INTERRUPT(71) \
433 DECLARE_INTERRUPT(72) \
434 DECLARE_INTERRUPT(73) \
435 DECLARE_INTERRUPT(74) \
436 DECLARE_INTERRUPT(75) \
437 DECLARE_INTERRUPT(76) \
438 DECLARE_INTERRUPT(77) \
439 DECLARE_INTERRUPT(78) \
440 DECLARE_INTERRUPT(79) \
441 DECLARE_INTERRUPT(80) \
442 DECLARE_INTERRUPT(81) \
443 DECLARE_INTERRUPT(82) \
444 DECLARE_INTERRUPT(83) \
445 DECLARE_INTERRUPT(84) \
446 DECLARE_INTERRUPT(85) \
447 DECLARE_INTERRUPT(86) \
448 DECLARE_INTERRUPT(87) \
449 DECLARE_INTERRUPT(88) \
450 DECLARE_INTERRUPT(89) \
451 DECLARE_INTERRUPT(90) \
452 DECLARE_INTERRUPT(91) \
453 DECLARE_INTERRUPT(92) \
454 DECLARE_INTERRUPT(93) \
455 DECLARE_INTERRUPT(94) \
456 DECLARE_INTERRUPT(95) \
457 DECLARE_INTERRUPT(97) \
458 DECLARE_INTERRUPT(96) \
459 DECLARE_INTERRUPT(98) \
460 DECLARE_INTERRUPT(99) \
461 DECLARE_INTERRUPT(100) \
462 DECLARE_INTERRUPT(101) \
463 DECLARE_INTERRUPT(102) \
464 DECLARE_INTERRUPT(103) \
465 DECLARE_INTERRUPT(104) \
466 DECLARE_INTERRUPT(105) \
467 DECLARE_INTERRUPT(106) \
468 DECLARE_INTERRUPT(107) \
469 DECLARE_INTERRUPT(108) \
470 DECLARE_INTERRUPT(109) \
471 DECLARE_INTERRUPT(110) \
472 DECLARE_INTERRUPT(111) \
473 DECLARE_INTERRUPT(112) \
474 DECLARE_INTERRUPT(113) \
475 DECLARE_INTERRUPT(114) \
476 DECLARE_INTERRUPT(115) \
477 DECLARE_INTERRUPT(116) \
478 DECLARE_INTERRUPT(117) \
479 DECLARE_INTERRUPT(118) \
480 DECLARE_INTERRUPT(119) \
481 DECLARE_INTERRUPT(120) \
482 DECLARE_INTERRUPT(121) \
483 DECLARE_INTERRUPT(122) \
484 DECLARE_INTERRUPT(123) \
485 DECLARE_INTERRUPT(124) \
486 DECLARE_INTERRUPT(125) \
487 DECLARE_INTERRUPT(126) \
488 DECLARE_INTERRUPT(127) \
489 DECLARE_INTERRUPT(128) \
490 DECLARE_INTERRUPT(129) \
491 DECLARE_INTERRUPT(130) \
492 DECLARE_INTERRUPT(131) \
493 DECLARE_INTERRUPT(132) \
494 DECLARE_INTERRUPT(133) \
495 DECLARE_INTERRUPT(134) \
496 DECLARE_INTERRUPT(135) \
497 DECLARE_INTERRUPT(136) \
498 DECLARE_INTERRUPT(137) \
499 DECLARE_INTERRUPT(138) \
500 DECLARE_INTERRUPT(139) \
501 DECLARE_INTERRUPT(140) \
502 DECLARE_INTERRUPT(141) \
503 DECLARE_INTERRUPT(142) \
504 DECLARE_INTERRUPT(143) \
505 DECLARE_INTERRUPT(144) \
506 DECLARE_INTERRUPT(145) \
507 DECLARE_INTERRUPT(146) \
508 DECLARE_INTERRUPT(147) \
509 DECLARE_INTERRUPT(148) \
510 DECLARE_INTERRUPT(149) \
511 DECLARE_INTERRUPT(150) \
512 DECLARE_INTERRUPT(151) \
513 DECLARE_INTERRUPT(152) \
514 DECLARE_INTERRUPT(153) \
515 DECLARE_INTERRUPT(154) \
516 DECLARE_INTERRUPT(155) \
517 DECLARE_INTERRUPT(156) \
518 DECLARE_INTERRUPT(157) \
519 DECLARE_INTERRUPT(158) \
520 DECLARE_INTERRUPT(159) \
521 DECLARE_INTERRUPT(160) \
522 DECLARE_INTERRUPT(161) \
523 DECLARE_INTERRUPT(162) \
524 DECLARE_INTERRUPT(163) \
525 DECLARE_INTERRUPT(164) \
526 DECLARE_INTERRUPT(165) \
527 DECLARE_INTERRUPT(166) \
528 DECLARE_INTERRUPT(167) \
529 DECLARE_INTERRUPT(168) \
530 DECLARE_INTERRUPT(169) \
531 DECLARE_INTERRUPT(170) \
532 DECLARE_INTERRUPT(171) \
533 DECLARE_INTERRUPT(172) \
534 DECLARE_INTERRUPT(173) \
535 DECLARE_INTERRUPT(174) \
536 DECLARE_INTERRUPT(175) \
537 DECLARE_INTERRUPT(176) \
538 DECLARE_INTERRUPT(177) \
539 DECLARE_INTERRUPT(178) \
540 DECLARE_INTERRUPT(179) \
541 DECLARE_INTERRUPT(180) \
542 DECLARE_INTERRUPT(181) \
543 DECLARE_INTERRUPT(182) \
544 DECLARE_INTERRUPT(183) \
545 DECLARE_INTERRUPT(184) \
546 DECLARE_INTERRUPT(185) \
547 DECLARE_INTERRUPT(186) \
548 DECLARE_INTERRUPT(187) \
549 DECLARE_INTERRUPT(188) \
550 DECLARE_INTERRUPT(189) \
551 DECLARE_INTERRUPT(190) \
552 DECLARE_INTERRUPT(191) \
553 DECLARE_INTERRUPT(192) \
554 DECLARE_INTERRUPT(193) \
555 DECLARE_INTERRUPT(194) \
556 DECLARE_INTERRUPT(195) \
557 DECLARE_INTERRUPT(196) \
558 DECLARE_INTERRUPT(197) \
559 DECLARE_INTERRUPT(198) \
560 DECLARE_INTERRUPT(199) \
561 DECLARE_INTERRUPT(200) \
562 DECLARE_INTERRUPT(201) \
563 DECLARE_INTERRUPT(202) \
564 DECLARE_INTERRUPT(203) \
565 DECLARE_INTERRUPT(204) \
566 DECLARE_INTERRUPT(205) \
567 DECLARE_INTERRUPT(206) \
568 DECLARE_INTERRUPT(207) \
569 DECLARE_INTERRUPT(208) \
570 DECLARE_INTERRUPT(209) \
571 DECLARE_INTERRUPT(210) \
572 DECLARE_INTERRUPT(211) \
573 DECLARE_INTERRUPT(212) \
574 DECLARE_INTERRUPT(213) \
575 DECLARE_INTERRUPT(214) \
576 DECLARE_INTERRUPT(215) \
577 DECLARE_INTERRUPT(216) \
578 DECLARE_INTERRUPT(217) \
579 DECLARE_INTERRUPT(218) \
580 DECLARE_INTERRUPT(219) \
581 DECLARE_INTERRUPT(220) \
582 DECLARE_INTERRUPT(221) \
583 DECLARE_INTERRUPT(222) \
584 DECLARE_INTERRUPT(223) \
585 DECLARE_INTERRUPT(224) \
586 DECLARE_INTERRUPT(225) \
587 DECLARE_INTERRUPT(226) \
588 DECLARE_INTERRUPT(227) \
589 DECLARE_INTERRUPT(228) \
590 DECLARE_INTERRUPT(229) \
591 DECLARE_INTERRUPT(230) \
592 DECLARE_INTERRUPT(231) \
593 DECLARE_INTERRUPT(232) \
594 DECLARE_INTERRUPT(233) \
595 DECLARE_INTERRUPT(234) \
596 DECLARE_INTERRUPT(235) \
597 DECLARE_INTERRUPT(236) \
598 DECLARE_INTERRUPT(237) \
599 DECLARE_INTERRUPT(238) \
600 DECLARE_INTERRUPT(239) \
601 DECLARE_INTERRUPT(240) \
602 DECLARE_INTERRUPT(241) \
603 DECLARE_INTERRUPT(242) \
604 DECLARE_INTERRUPT(243) \
605 DECLARE_INTERRUPT(244) \
606 DECLARE_INTERRUPT(245) \
607 DECLARE_INTERRUPT(246) \
608 DECLARE_INTERRUPT(247) \
609 DECLARE_INTERRUPT(248) \
610 DECLARE_INTERRUPT(249) \
611 DECLARE_INTERRUPT(250) \
612 DECLARE_INTERRUPT(251) \
613 DECLARE_INTERRUPT(252) \
614 DECLARE_INTERRUPT(253) \
615 DECLARE_INTERRUPT(254) \
616 DECLARE_INTERRUPT(255));