Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 1 | /* |
ramneek mehresh | 3d33963 | 2012-04-18 19:39:53 +0000 | [diff] [blame] | 2 | * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 3 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * mpc8536ds board configuration file |
| 9 | * |
| 10 | */ |
| 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
Kumar Gala | a1c0a46 | 2010-05-21 04:14:49 -0500 | [diff] [blame] | 14 | #include "../board/freescale/common/ics307_clk.h" |
| 15 | |
Wolfgang Denk | dc25d15 | 2010-10-04 19:58:00 +0200 | [diff] [blame] | 16 | #ifdef CONFIG_SDCARD |
Mingkai Hu | a74e395 | 2009-09-23 15:20:38 +0800 | [diff] [blame] | 17 | #define CONFIG_RAMBOOT_SDCARD 1 |
Haijun.Zhang | bb32793 | 2014-04-10 11:16:30 +0800 | [diff] [blame] | 18 | #define CONFIG_SYS_TEXT_BASE 0xf8f40000 |
Kumar Gala | e727a36 | 2011-01-12 02:48:53 -0600 | [diff] [blame] | 19 | #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc |
Mingkai Hu | a74e395 | 2009-09-23 15:20:38 +0800 | [diff] [blame] | 20 | #endif |
| 21 | |
Wolfgang Denk | dc25d15 | 2010-10-04 19:58:00 +0200 | [diff] [blame] | 22 | #ifdef CONFIG_SPIFLASH |
Mingkai Hu | a74e395 | 2009-09-23 15:20:38 +0800 | [diff] [blame] | 23 | #define CONFIG_RAMBOOT_SPIFLASH 1 |
Haijun.Zhang | bb32793 | 2014-04-10 11:16:30 +0800 | [diff] [blame] | 24 | #define CONFIG_SYS_TEXT_BASE 0xf8f40000 |
Kumar Gala | e727a36 | 2011-01-12 02:48:53 -0600 | [diff] [blame] | 25 | #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 26 | #endif |
| 27 | |
| 28 | #ifndef CONFIG_SYS_TEXT_BASE |
Haijun.Zhang | afdc3f5 | 2014-02-13 09:03:02 +0800 | [diff] [blame] | 29 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
Mingkai Hu | a74e395 | 2009-09-23 15:20:38 +0800 | [diff] [blame] | 30 | #endif |
| 31 | |
Kumar Gala | e727a36 | 2011-01-12 02:48:53 -0600 | [diff] [blame] | 32 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 33 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
| 34 | #endif |
| 35 | |
Haiying Wang | 31b9012 | 2010-11-10 15:37:13 -0500 | [diff] [blame] | 36 | #ifndef CONFIG_SYS_MONITOR_BASE |
| 37 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 38 | #endif |
| 39 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 40 | #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ |
Robert P. J. Day | a809981 | 2016-05-03 19:52:49 -0400 | [diff] [blame] | 41 | #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ |
| 42 | #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ |
| 43 | #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 44 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 45 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 46 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
Kumar Gala | 7738d5c | 2008-10-21 11:33:58 -0500 | [diff] [blame] | 47 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 48 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 49 | |
| 50 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| 51 | #define CONFIG_ENV_OVERWRITE |
| 52 | |
Kumar Gala | a1c0a46 | 2010-05-21 04:14:49 -0500 | [diff] [blame] | 53 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ |
| 54 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 55 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 56 | |
| 57 | /* |
| 58 | * These can be toggled for performance analysis, otherwise use default. |
| 59 | */ |
| 60 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 61 | #define CONFIG_BTB /* toggle branch predition */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 62 | |
| 63 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 64 | |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 65 | #ifdef CONFIG_PHYS_64BIT |
| 66 | #define CONFIG_ADDR_MAP 1 |
| 67 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ |
| 68 | #endif |
| 69 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 70 | #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ |
| 71 | #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 72 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 73 | |
| 74 | /* |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 75 | * Config the L2 Cache as L2 SRAM |
| 76 | */ |
| 77 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| 78 | #ifdef CONFIG_PHYS_64BIT |
| 79 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull |
| 80 | #else |
| 81 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| 82 | #endif |
| 83 | #define CONFIG_SYS_L2_SIZE (512 << 10) |
| 84 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
| 85 | |
Timur Tabi | d8f341c | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 86 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
| 87 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 88 | |
Kumar Gala | 842aa5b | 2011-11-09 09:10:49 -0600 | [diff] [blame] | 89 | #if defined(CONFIG_NAND_SPL) |
Timur Tabi | d8f341c | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 90 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 91 | #endif |
| 92 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 93 | /* DDR Setup */ |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 94 | #define CONFIG_VERY_BIG_RAM |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 95 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 96 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
| 97 | #define CONFIG_DDR_SPD |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 98 | |
Dave Liu | d3ca124 | 2008-10-28 17:53:38 +0800 | [diff] [blame] | 99 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 100 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 101 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 102 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 103 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 104 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 105 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 106 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 |
| 107 | |
| 108 | /* I2C addresses of SPD EEPROMs */ |
| 109 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 110 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 111 | |
| 112 | /* These are used when DDR doesn't use SPD. */ |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 113 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 114 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 115 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 116 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
| 117 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 |
| 118 | #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 |
| 119 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 |
| 120 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 |
| 121 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
| 122 | #define CONFIG_SYS_DDR_INTERVAL 0x06180100 |
| 123 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| 124 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 |
| 125 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 |
| 126 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 127 | #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 128 | #define CONFIG_SYS_DDR_CONTROL2 0x04400010 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 129 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 130 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d |
| 131 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 |
| 132 | #define CONFIG_SYS_DDR_SBE 0x00010000 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 133 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 134 | /* Make sure required options are set */ |
| 135 | #ifndef CONFIG_SPD_EEPROM |
| 136 | #error ("CONFIG_SPD_EEPROM is required") |
| 137 | #endif |
| 138 | |
| 139 | #undef CONFIG_CLOCKS_IN_MHZ |
| 140 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 141 | /* |
| 142 | * Memory map -- xxx -this is wrong, needs updating |
| 143 | * |
| 144 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable |
| 145 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable |
| 146 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable |
| 147 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable |
| 148 | * |
| 149 | * Localbus cacheable (TBD) |
| 150 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable |
| 151 | * |
| 152 | * Localbus non-cacheable |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 153 | * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 154 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 155 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 156 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
| 157 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 |
| 158 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable |
| 159 | */ |
| 160 | |
| 161 | /* |
| 162 | * Local Bus Definitions |
| 163 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 164 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 165 | #ifdef CONFIG_PHYS_64BIT |
| 166 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull |
| 167 | #else |
Kumar Gala | 4be8b57 | 2008-12-02 14:19:34 -0600 | [diff] [blame] | 168 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 169 | #endif |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 170 | |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 171 | #define CONFIG_FLASH_BR_PRELIM \ |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 172 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 173 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 174 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 175 | #define CONFIG_SYS_BR1_PRELIM \ |
| 176 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
| 177 | | BR_PS_16 | BR_V) |
Kumar Gala | 4be8b57 | 2008-12-02 14:19:34 -0600 | [diff] [blame] | 178 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 179 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 180 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ |
| 181 | CONFIG_SYS_FLASH_BASE_PHYS } |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 182 | #define CONFIG_SYS_FLASH_QUIET_TEST |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 183 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 184 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 185 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 186 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 187 | #undef CONFIG_SYS_FLASH_CHECKSUM |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 188 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 189 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 190 | |
Masahiro Yamada | 0c5b8eb | 2014-06-04 10:26:50 +0900 | [diff] [blame] | 191 | #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 192 | #define CONFIG_SYS_RAMBOOT |
Kumar Gala | b1dd51f | 2010-11-29 14:32:11 -0600 | [diff] [blame] | 193 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 194 | #else |
| 195 | #undef CONFIG_SYS_RAMBOOT |
| 196 | #endif |
| 197 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 198 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 199 | #define CONFIG_SYS_FLASH_CFI |
| 200 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 201 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 202 | |
| 203 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ |
| 204 | |
Ramneek Mehresh | a0cce27 | 2011-06-07 10:10:43 +0000 | [diff] [blame] | 205 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 206 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
| 207 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 208 | #ifdef CONFIG_PHYS_64BIT |
| 209 | #define PIXIS_BASE_PHYS 0xfffdf0000ull |
| 210 | #else |
Kumar Gala | 0f492b4 | 2008-12-02 14:19:33 -0600 | [diff] [blame] | 211 | #define PIXIS_BASE_PHYS PIXIS_BASE |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 212 | #endif |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 213 | |
Kumar Gala | 0f492b4 | 2008-12-02 14:19:33 -0600 | [diff] [blame] | 214 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 215 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 216 | |
| 217 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
| 218 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ |
| 219 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ |
| 220 | #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ |
| 221 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ |
| 222 | #define PIXIS_PWR 0x5 /* PIXIS Power status register */ |
| 223 | #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ |
| 224 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ |
| 225 | #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ |
| 226 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ |
| 227 | #define PIXIS_VSTAT 0x11 /* VELA Status Register */ |
| 228 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ |
| 229 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ |
| 230 | #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ |
| 231 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ |
Kumar Gala | e21db03 | 2009-07-14 22:42:01 -0500 | [diff] [blame] | 232 | #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ |
| 233 | #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ |
| 234 | #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ |
| 235 | #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ |
| 236 | #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ |
| 237 | #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ |
| 238 | #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 239 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
| 240 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ |
| 241 | #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ |
| 242 | #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ |
| 243 | #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ |
| 244 | #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ |
| 245 | #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ |
| 246 | #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ |
| 247 | #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ |
| 248 | #define PIXIS_VWATCH 0x24 /* Watchdog Register */ |
| 249 | #define PIXIS_LED 0x25 /* LED Register */ |
| 250 | |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 251 | #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ |
| 252 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 253 | /* old pixis referenced names */ |
| 254 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ |
| 255 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ |
Matthew McClintock | 3cde72b | 2011-02-25 16:20:11 -0600 | [diff] [blame] | 256 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 257 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 258 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 259 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 260 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 261 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 262 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 263 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 264 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 265 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 266 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 267 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 268 | |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 269 | #ifndef CONFIG_NAND_SPL |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 270 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
| 271 | #ifdef CONFIG_PHYS_64BIT |
| 272 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull |
| 273 | #else |
| 274 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 275 | #endif |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 276 | #else |
| 277 | #define CONFIG_SYS_NAND_BASE 0xfff00000 |
| 278 | #ifdef CONFIG_PHYS_64BIT |
| 279 | #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull |
| 280 | #else |
| 281 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 282 | #endif |
| 283 | #endif |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 284 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ |
| 285 | CONFIG_SYS_NAND_BASE + 0x40000, \ |
| 286 | CONFIG_SYS_NAND_BASE + 0x80000, \ |
| 287 | CONFIG_SYS_NAND_BASE + 0xC0000} |
| 288 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 289 | #define CONFIG_CMD_NAND 1 |
| 290 | #define CONFIG_NAND_FSL_ELBC 1 |
| 291 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| 292 | |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 293 | /* NAND boot: 4K NAND loader config */ |
| 294 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 |
Haijun.Zhang | afdc3f5 | 2014-02-13 09:03:02 +0800 | [diff] [blame] | 295 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 296 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) |
| 297 | #define CONFIG_SYS_NAND_U_BOOT_START \ |
| 298 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) |
| 299 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) |
| 300 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) |
| 301 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) |
| 302 | |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 303 | /* NAND flash config */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 304 | #define CONFIG_SYS_NAND_BR_PRELIM \ |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 305 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 306 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 307 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| 308 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 309 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 310 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 311 | | OR_FCM_PGS /* Large Page*/ \ |
| 312 | | OR_FCM_CSCT \ |
| 313 | | OR_FCM_CST \ |
| 314 | | OR_FCM_CHT \ |
| 315 | | OR_FCM_SCY_1 \ |
| 316 | | OR_FCM_TRLX \ |
| 317 | | OR_FCM_EHTR) |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 318 | |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 319 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 320 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 321 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| 322 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 323 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 324 | #define CONFIG_SYS_BR4_PRELIM \ |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 325 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 326 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 327 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| 328 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 329 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 330 | #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 331 | #define CONFIG_SYS_BR5_PRELIM \ |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 332 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 333 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 334 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| 335 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 336 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 337 | #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 338 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 339 | #define CONFIG_SYS_BR6_PRELIM \ |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 340 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 341 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 342 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| 343 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 344 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 345 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Jason Jin | 3a1e04f | 2008-10-31 05:07:04 -0500 | [diff] [blame] | 346 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 347 | /* Serial Port - controlled on board with jumper J8 |
| 348 | * open - index 2 |
| 349 | * shorted - index 1 |
| 350 | */ |
| 351 | #define CONFIG_CONS_INDEX 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 352 | #define CONFIG_SYS_NS16550_SERIAL |
| 353 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 354 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
Kumar Gala | f273623 | 2010-04-07 01:34:11 -0500 | [diff] [blame] | 355 | #ifdef CONFIG_NAND_SPL |
| 356 | #define CONFIG_NS16550_MIN_FUNCTIONS |
| 357 | #endif |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 358 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 359 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 360 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 361 | |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 362 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) |
| 363 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 364 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 365 | /* |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 366 | * I2C |
| 367 | */ |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 368 | #define CONFIG_SYS_I2C |
| 369 | #define CONFIG_SYS_I2C_FSL |
| 370 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 371 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 372 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| 373 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
| 374 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| 375 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 |
| 376 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 377 | |
| 378 | /* |
| 379 | * I2C2 EEPROM |
| 380 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 8349c72 | 2008-08-30 23:54:58 +0200 | [diff] [blame] | 381 | #define CONFIG_ID_EEPROM |
| 382 | #ifdef CONFIG_ID_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 383 | #define CONFIG_SYS_I2C_EEPROM_NXID |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 384 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 385 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 386 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 387 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 388 | |
| 389 | /* |
Xie Xiaobo | 8f3933e | 2011-10-03 12:18:39 -0700 | [diff] [blame] | 390 | * eSPI - Enhanced SPI |
| 391 | */ |
| 392 | #define CONFIG_HARD_SPI |
Xie Xiaobo | 8f3933e | 2011-10-03 12:18:39 -0700 | [diff] [blame] | 393 | |
| 394 | #if defined(CONFIG_SPI_FLASH) |
Xie Xiaobo | 8f3933e | 2011-10-03 12:18:39 -0700 | [diff] [blame] | 395 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
| 396 | #define CONFIG_SF_DEFAULT_MODE 0 |
| 397 | #endif |
| 398 | |
| 399 | /* |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 400 | * General PCI |
| 401 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 402 | */ |
| 403 | |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 404 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 405 | #ifdef CONFIG_PHYS_64BIT |
| 406 | #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 |
| 407 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull |
| 408 | #else |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 409 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
| 410 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 411 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 412 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 413 | #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 |
| 414 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
| 415 | #ifdef CONFIG_PHYS_64BIT |
| 416 | #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull |
| 417 | #else |
| 418 | #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 |
| 419 | #endif |
| 420 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 421 | |
| 422 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ |
Kumar Gala | 06bea37 | 2010-12-17 15:14:54 -0600 | [diff] [blame] | 423 | #define CONFIG_SYS_PCIE1_NAME "Slot 1" |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 424 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 425 | #ifdef CONFIG_PHYS_64BIT |
| 426 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 |
| 427 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull |
| 428 | #else |
Kumar Gala | 3fe8087 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 429 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 430 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 431 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 432 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 433 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 434 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 435 | #ifdef CONFIG_PHYS_64BIT |
| 436 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull |
| 437 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 438 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 439 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 440 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 441 | |
| 442 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ |
Kumar Gala | 06bea37 | 2010-12-17 15:14:54 -0600 | [diff] [blame] | 443 | #define CONFIG_SYS_PCIE2_NAME "Slot 2" |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 444 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 445 | #ifdef CONFIG_PHYS_64BIT |
| 446 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 |
| 447 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull |
| 448 | #else |
Kumar Gala | 3fe8087 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 449 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 450 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 451 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 452 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 453 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 454 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| 455 | #ifdef CONFIG_PHYS_64BIT |
| 456 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull |
| 457 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 458 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 459 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 460 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 461 | |
| 462 | /* controller 3, direct to uli, tgtid 3, Base address 8000 */ |
Kumar Gala | 06bea37 | 2010-12-17 15:14:54 -0600 | [diff] [blame] | 463 | #define CONFIG_SYS_PCIE3_NAME "Slot 3" |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 464 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 465 | #ifdef CONFIG_PHYS_64BIT |
| 466 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
| 467 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull |
| 468 | #else |
Kumar Gala | 3fe8087 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 469 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 470 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 471 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 472 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 473 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 474 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
| 475 | #ifdef CONFIG_PHYS_64BIT |
| 476 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull |
| 477 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 478 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 |
Kumar Gala | ee1ca7e | 2009-07-30 15:54:07 -0500 | [diff] [blame] | 479 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 480 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 481 | |
| 482 | #if defined(CONFIG_PCI) |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 483 | /*PCIE video card used*/ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 484 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 485 | |
| 486 | /*PCI video card used*/ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 487 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 488 | |
| 489 | /* video */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 490 | |
| 491 | #if defined(CONFIG_VIDEO) |
| 492 | #define CONFIG_BIOSEMU |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 493 | #define CONFIG_ATI_RADEON_FB |
| 494 | #define CONFIG_VIDEO_LOGO |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 495 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 496 | #endif |
| 497 | |
| 498 | #undef CONFIG_EEPRO100 |
| 499 | #undef CONFIG_TULIP |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 500 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 501 | #ifndef CONFIG_PCI_PNP |
Kumar Gala | 64bb6d1 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 502 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS |
| 503 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 504 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
| 505 | #endif |
| 506 | |
| 507 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 508 | |
| 509 | #endif /* CONFIG_PCI */ |
| 510 | |
| 511 | /* SATA */ |
| 512 | #define CONFIG_LIBATA |
| 513 | #define CONFIG_FSL_SATA |
| 514 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 515 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 516 | #define CONFIG_SATA1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 517 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
| 518 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 519 | #define CONFIG_SATA2 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 520 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR |
| 521 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 522 | |
| 523 | #ifdef CONFIG_FSL_SATA |
| 524 | #define CONFIG_LBA48 |
| 525 | #define CONFIG_CMD_SATA |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 526 | #endif |
| 527 | |
| 528 | #if defined(CONFIG_TSEC_ENET) |
| 529 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 530 | #define CONFIG_MII 1 /* MII PHY management */ |
| 531 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
| 532 | #define CONFIG_TSEC1 1 |
| 533 | #define CONFIG_TSEC1_NAME "eTSEC1" |
| 534 | #define CONFIG_TSEC3 1 |
| 535 | #define CONFIG_TSEC3_NAME "eTSEC3" |
| 536 | |
Jason Jin | 21181fd | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 537 | #define CONFIG_FSL_SGMII_RISER 1 |
| 538 | #define SGMII_RISER_PHY_OFFSET 0x1c |
| 539 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 540 | #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ |
| 541 | #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ |
| 542 | |
| 543 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 544 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 545 | |
| 546 | #define TSEC1_PHYIDX 0 |
| 547 | #define TSEC3_PHYIDX 0 |
| 548 | |
| 549 | #define CONFIG_ETHPRIME "eTSEC1" |
| 550 | |
| 551 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
| 552 | |
| 553 | #endif /* CONFIG_TSEC_ENET */ |
| 554 | |
| 555 | /* |
| 556 | * Environment |
| 557 | */ |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 558 | |
| 559 | #if defined(CONFIG_SYS_RAMBOOT) |
Masahiro Yamada | 0c5b8eb | 2014-06-04 10:26:50 +0900 | [diff] [blame] | 560 | #if defined(CONFIG_RAMBOOT_SPIFLASH) |
Xie Xiaobo | 93c08de | 2011-10-03 12:54:21 -0700 | [diff] [blame] | 561 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 562 | #define CONFIG_ENV_SPI_BUS 0 |
| 563 | #define CONFIG_ENV_SPI_CS 0 |
| 564 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 |
| 565 | #define CONFIG_ENV_SPI_MODE 0 |
| 566 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
| 567 | #define CONFIG_ENV_OFFSET 0xF0000 |
| 568 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
| 569 | #elif defined(CONFIG_RAMBOOT_SDCARD) |
| 570 | #define CONFIG_ENV_IS_IN_MMC |
Fabio Estevam | ae8c45e | 2012-01-11 09:20:50 +0000 | [diff] [blame] | 571 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
Xie Xiaobo | 93c08de | 2011-10-03 12:54:21 -0700 | [diff] [blame] | 572 | #define CONFIG_ENV_SIZE 0x2000 |
| 573 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 574 | #else |
Mingkai Hu | a74e395 | 2009-09-23 15:20:38 +0800 | [diff] [blame] | 575 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
| 576 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| 577 | #define CONFIG_ENV_SIZE 0x2000 |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 578 | #endif |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 579 | #else |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 580 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 581 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
Mingkai Hu | c2a6dca | 2009-09-23 15:20:37 +0800 | [diff] [blame] | 582 | #define CONFIG_ENV_SIZE 0x2000 |
| 583 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 584 | #endif |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 585 | |
| 586 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 587 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 588 | |
| 589 | /* |
| 590 | * Command line configuration. |
| 591 | */ |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 592 | #define CONFIG_CMD_REGINFO |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 593 | |
| 594 | #if defined(CONFIG_PCI) |
| 595 | #define CONFIG_CMD_PCI |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 596 | #endif |
| 597 | |
| 598 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 599 | |
Andy Fleming | 6843a6e | 2008-10-30 16:51:33 -0500 | [diff] [blame] | 600 | #ifdef CONFIG_MMC |
| 601 | #define CONFIG_FSL_ESDHC |
| 602 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
Fanzc | 6f976fe | 2011-10-03 12:18:42 -0700 | [diff] [blame] | 603 | #endif |
| 604 | |
| 605 | /* |
| 606 | * USB |
| 607 | */ |
ramneek mehresh | 3d33963 | 2012-04-18 19:39:53 +0000 | [diff] [blame] | 608 | #define CONFIG_HAS_FSL_MPH_USB |
| 609 | #ifdef CONFIG_HAS_FSL_MPH_USB |
Tom Rini | ceed5d2 | 2017-05-12 22:33:27 -0400 | [diff] [blame] | 610 | #ifdef CONFIG_USB_EHCI_HCD |
Fanzc | 6f976fe | 2011-10-03 12:18:42 -0700 | [diff] [blame] | 611 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 612 | #define CONFIG_USB_EHCI_FSL |
Fanzc | 6f976fe | 2011-10-03 12:18:42 -0700 | [diff] [blame] | 613 | #endif |
ramneek mehresh | 3d33963 | 2012-04-18 19:39:53 +0000 | [diff] [blame] | 614 | #endif |
Fanzc | 6f976fe | 2011-10-03 12:18:42 -0700 | [diff] [blame] | 615 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 616 | /* |
| 617 | * Miscellaneous configurable options |
| 618 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 619 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 620 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
Kim Phillips | f7758c1 | 2010-07-14 19:47:18 -0500 | [diff] [blame] | 621 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 622 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 623 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 624 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 625 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 626 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 627 | #endif |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 628 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ |
| 629 | + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 630 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 631 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 632 | |
| 633 | /* |
| 634 | * For booting Linux, the board info and command line data |
Kumar Gala | 39ffcc1 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 635 | * have to be in the first 64 MB of memory, since this is |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 636 | * the maximum mapped by the Linux kernel during initialization. |
| 637 | */ |
Kumar Gala | 39ffcc1 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 638 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ |
| 639 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 640 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 641 | #if defined(CONFIG_CMD_KGDB) |
| 642 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 643 | #endif |
| 644 | |
| 645 | /* |
| 646 | * Environment Configuration |
| 647 | */ |
| 648 | |
| 649 | /* The mac addresses for all ethernet interface */ |
| 650 | #if defined(CONFIG_TSEC_ENET) |
| 651 | #define CONFIG_HAS_ETH0 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 652 | #define CONFIG_HAS_ETH1 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 653 | #define CONFIG_HAS_ETH2 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 654 | #define CONFIG_HAS_ETH3 |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 655 | #endif |
| 656 | |
| 657 | #define CONFIG_IPADDR 192.168.1.254 |
| 658 | |
| 659 | #define CONFIG_HOSTNAME unknown |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 660 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 661 | #define CONFIG_BOOTFILE "uImage" |
Mingkai Hu | 9097531 | 2009-09-23 15:19:32 +0800 | [diff] [blame] | 662 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 663 | |
| 664 | #define CONFIG_SERVERIP 192.168.1.1 |
| 665 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 666 | #define CONFIG_NETMASK 255.255.255.0 |
| 667 | |
| 668 | /* default location for tftp and bootm */ |
| 669 | #define CONFIG_LOADADDR 1000000 |
| 670 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 671 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| 672 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 673 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 674 | "netdev=eth0\0" \ |
| 675 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 676 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| 677 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 678 | " +$filesize; " \ |
| 679 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 680 | " +$filesize; " \ |
| 681 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 682 | " $filesize; " \ |
| 683 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 684 | " +$filesize; " \ |
| 685 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 686 | " $filesize\0" \ |
| 687 | "consoledev=ttyS0\0" \ |
| 688 | "ramdiskaddr=2000000\0" \ |
| 689 | "ramdiskfile=8536ds/ramdisk.uboot\0" \ |
Scott Wood | b7f4b85 | 2016-07-19 17:52:06 -0500 | [diff] [blame] | 690 | "fdtaddr=1e00000\0" \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 691 | "fdtfile=8536ds/mpc8536ds.dtb\0" \ |
| 692 | "bdev=sda3\0" \ |
| 693 | "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 694 | |
| 695 | #define CONFIG_HDBOOT \ |
| 696 | "setenv bootargs root=/dev/$bdev rw " \ |
| 697 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 698 | "tftp $loadaddr $bootfile;" \ |
| 699 | "tftp $fdtaddr $fdtfile;" \ |
| 700 | "bootm $loadaddr - $fdtaddr" |
| 701 | |
| 702 | #define CONFIG_NFSBOOTCOMMAND \ |
| 703 | "setenv bootargs root=/dev/nfs rw " \ |
| 704 | "nfsroot=$serverip:$rootpath " \ |
| 705 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 706 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 707 | "tftp $loadaddr $bootfile;" \ |
| 708 | "tftp $fdtaddr $fdtfile;" \ |
| 709 | "bootm $loadaddr - $fdtaddr" |
| 710 | |
| 711 | #define CONFIG_RAMBOOTCOMMAND \ |
| 712 | "setenv bootargs root=/dev/ram rw " \ |
| 713 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 714 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 715 | "tftp $loadaddr $bootfile;" \ |
| 716 | "tftp $fdtaddr $fdtfile;" \ |
| 717 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| 718 | |
| 719 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT |
| 720 | |
| 721 | #endif /* __CONFIG_H */ |