Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> |
| 4 | * |
| 5 | * (C) Copyright 2007-2011 |
| 6 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> |
| 7 | * Tom Cubie <tangliang@allwinnertech.com> |
| 8 | * |
| 9 | * Some init for sunxi platform. |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 10 | */ |
| 11 | |
Simon Glass | 1d91ba7 | 2019-11-14 12:57:37 -0700 | [diff] [blame] | 12 | #include <cpu_func.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 13 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 14 | #include <log.h> |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 15 | #include <mmc.h> |
Hans de Goede | 3352b22 | 2014-06-13 22:55:49 +0200 | [diff] [blame] | 16 | #include <i2c.h> |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 17 | #include <serial.h> |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 18 | #include <spl.h> |
Andre Przywara | f944a61 | 2022-09-06 10:36:38 +0100 | [diff] [blame] | 19 | #include <sunxi_gpio.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 20 | #include <asm/cache.h> |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 21 | #include <asm/gpio.h> |
| 22 | #include <asm/io.h> |
| 23 | #include <asm/arch/clock.h> |
Bernhard Nortmann | ead498a | 2015-09-17 18:52:52 +0200 | [diff] [blame] | 24 | #include <asm/arch/spl.h> |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 25 | #include <asm/arch/sys_proto.h> |
| 26 | #include <asm/arch/timer.h> |
Chen-Yu Tsai | fcc7b70 | 2015-08-25 10:49:19 +0800 | [diff] [blame] | 27 | #include <asm/arch/tzpc.h> |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 28 | #include <asm/arch/mmc.h> |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 29 | |
Ian Campbell | d41e2f67 | 2014-07-06 20:03:20 +0100 | [diff] [blame] | 30 | #include <linux/compiler.h> |
| 31 | |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 32 | struct fel_stash { |
| 33 | uint32_t sp; |
| 34 | uint32_t lr; |
Siarhei Siamashka | 7ef91f0 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 35 | uint32_t cpsr; |
| 36 | uint32_t sctlr; |
| 37 | uint32_t vbar; |
Andre Przywara | 578321c | 2025-02-10 00:25:29 +0000 | [diff] [blame] | 38 | uint32_t sp_irq; |
Andre Przywara | 43aa170 | 2025-01-05 21:51:59 +0000 | [diff] [blame] | 39 | uint32_t icc_pmr; |
| 40 | uint32_t icc_igrpen1; |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 41 | }; |
| 42 | |
Marek Behún | 4bebdd3 | 2021-05-20 13:23:52 +0200 | [diff] [blame] | 43 | struct fel_stash fel_stash __section(".data"); |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 44 | |
Andre Przywara | 3a63c23 | 2017-02-16 01:20:24 +0000 | [diff] [blame] | 45 | #ifdef CONFIG_ARM64 |
Siarhei Siamashka | 26c50fb | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 46 | #include <asm/armv8/mmu.h> |
| 47 | |
| 48 | static struct mm_region sunxi_mem_map[] = { |
| 49 | { |
| 50 | /* SRAM, MMIO regions */ |
York Sun | c7104e5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 51 | .virt = 0x0UL, |
| 52 | .phys = 0x0UL, |
Siarhei Siamashka | 26c50fb | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 53 | .size = 0x40000000UL, |
| 54 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 55 | PTE_BLOCK_NON_SHARE |
| 56 | }, { |
| 57 | /* RAM */ |
York Sun | c7104e5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 58 | .virt = 0x40000000UL, |
| 59 | .phys = 0x40000000UL, |
Andre Przywara | c0387f1 | 2021-04-28 21:29:55 +0100 | [diff] [blame] | 60 | .size = CONFIG_SUNXI_DRAM_MAX_SIZE, |
Siarhei Siamashka | 26c50fb | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 61 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 62 | PTE_BLOCK_INNER_SHARE |
| 63 | }, { |
| 64 | /* List terminator */ |
| 65 | 0, |
| 66 | } |
| 67 | }; |
| 68 | struct mm_region *mem_map = sunxi_mem_map; |
Andre Przywara | c0387f1 | 2021-04-28 21:29:55 +0100 | [diff] [blame] | 69 | |
Heinrich Schuchardt | 51a9aac | 2023-08-12 20:16:58 +0200 | [diff] [blame] | 70 | phys_addr_t board_get_usable_ram_top(phys_size_t total_size) |
Andre Przywara | c0387f1 | 2021-04-28 21:29:55 +0100 | [diff] [blame] | 71 | { |
| 72 | /* Some devices (like the EMAC) have a 32-bit DMA limit. */ |
| 73 | if (gd->ram_top > (1ULL << 32)) |
| 74 | return 1ULL << 32; |
| 75 | |
| 76 | return gd->ram_top; |
| 77 | } |
Andre Przywara | a9aab24 | 2022-11-28 00:02:56 +0000 | [diff] [blame] | 78 | #endif /* CONFIG_ARM64 */ |
Siarhei Siamashka | 26c50fb | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 79 | |
Simon Glass | 85ed77d | 2024-09-29 19:49:46 -0600 | [diff] [blame] | 80 | #ifdef CONFIG_XPL_BUILD |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 81 | static int gpio_init(void) |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 82 | { |
Icenowy Zheng | 112c886 | 2019-04-24 13:44:12 +0800 | [diff] [blame] | 83 | __maybe_unused uint val; |
Chen-Yu Tsai | d4ea92b | 2014-10-22 16:47:42 +0800 | [diff] [blame] | 84 | #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) |
Chen-Yu Tsai | cc2605e | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 85 | #if defined(CONFIG_MACH_SUN4I) || \ |
| 86 | defined(CONFIG_MACH_SUN7I) || \ |
| 87 | defined(CONFIG_MACH_SUN8I_R40) |
Chen-Yu Tsai | d4ea92b | 2014-10-22 16:47:42 +0800 | [diff] [blame] | 88 | /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ |
| 89 | sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); |
| 90 | sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); |
| 91 | #endif |
Andre Przywara | 072e477 | 2022-05-06 00:34:39 +0100 | [diff] [blame] | 92 | #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || \ |
| 93 | defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I_R40) || \ |
| 94 | defined(CONFIG_MACH_SUN9I) |
Chen-Yu Tsai | da2f333 | 2015-06-23 19:57:23 +0800 | [diff] [blame] | 95 | sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); |
| 96 | sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); |
Andre Przywara | 072e477 | 2022-05-06 00:34:39 +0100 | [diff] [blame] | 97 | #else |
| 98 | sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); |
| 99 | sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 100 | #endif |
Andre Przywara | 072e477 | 2022-05-06 00:34:39 +0100 | [diff] [blame] | 101 | sunxi_gpio_set_pull(SUNXI_GPF(4), SUNXI_GPIO_PULL_UP); |
Icenowy Zheng | 8f2d1c0 | 2022-01-29 10:23:07 -0500 | [diff] [blame] | 102 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV) |
| 103 | sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0); |
| 104 | sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0); |
| 105 | sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP); |
Chen-Yu Tsai | cc2605e | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 106 | #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \ |
| 107 | defined(CONFIG_MACH_SUN7I) || \ |
| 108 | defined(CONFIG_MACH_SUN8I_R40)) |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 109 | sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0); |
| 110 | sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0); |
Chen-Yu Tsai | 4e526e2 | 2014-10-03 20:16:21 +0800 | [diff] [blame] | 111 | sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); |
Ian Campbell | 8f32aaa | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 112 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 113 | sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0); |
| 114 | sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0); |
Chen-Yu Tsai | 4e526e2 | 2014-10-03 20:16:21 +0800 | [diff] [blame] | 115 | sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); |
Ian Campbell | 8f32aaa | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 116 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 117 | sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); |
| 118 | sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); |
Maxime Ripard | f139f1e | 2014-10-03 20:16:28 +0800 | [diff] [blame] | 119 | sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); |
Chen-Yu Tsai | 28b7192 | 2015-06-23 19:57:25 +0800 | [diff] [blame] | 120 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) |
| 121 | sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); |
| 122 | sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); |
| 123 | sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); |
Andre Przywara | 5fb9743 | 2017-02-16 01:20:27 +0000 | [diff] [blame] | 124 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5) |
Jens Kuske | f977072 | 2015-11-17 15:12:58 +0100 | [diff] [blame] | 125 | sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); |
| 126 | sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); |
| 127 | sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); |
Siarhei Siamashka | 26c50fb | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 128 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I) |
| 129 | sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0); |
| 130 | sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0); |
| 131 | sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); |
Icenowy Zheng | a78bb07 | 2018-07-21 16:20:28 +0800 | [diff] [blame] | 132 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6) |
| 133 | sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0); |
| 134 | sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0); |
| 135 | sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); |
Jernej Skrabec | 30efb9d | 2021-01-11 21:11:41 +0100 | [diff] [blame] | 136 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616) |
| 137 | sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0); |
| 138 | sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0); |
| 139 | sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); |
vishnupatekar | 133bfbe | 2015-11-29 01:07:20 +0800 | [diff] [blame] | 140 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) |
| 141 | sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); |
| 142 | sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); |
| 143 | sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); |
Icenowy Zheng | 52e6188 | 2017-04-08 15:30:12 +0800 | [diff] [blame] | 144 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S) |
| 145 | sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0); |
| 146 | sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0); |
| 147 | sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); |
Hans de Goede | 7bfe2bb | 2015-01-13 19:25:06 +0100 | [diff] [blame] | 148 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) |
| 149 | sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); |
| 150 | sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); |
| 151 | sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); |
Andre Przywara | 1987b0c | 2022-09-06 15:59:57 +0100 | [diff] [blame] | 152 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_R528) |
| 153 | sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6); |
| 154 | sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6); |
| 155 | sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP); |
Andre Przywara | 72313dc | 2022-10-05 23:19:54 +0100 | [diff] [blame] | 156 | #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV) |
| 157 | sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0); |
| 158 | sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0); |
| 159 | sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP); |
Ian Campbell | 8f32aaa | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 160 | #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 161 | sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); |
| 162 | sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); |
Chen-Yu Tsai | 4e526e2 | 2014-10-03 20:16:21 +0800 | [diff] [blame] | 163 | sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); |
Angelo Dureghello | 47263bd | 2021-10-09 14:18:59 +0200 | [diff] [blame] | 164 | #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3) |
| 165 | sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2); |
| 166 | sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2); |
| 167 | sunxi_gpio_set_pull(SUNXI_GPA(1), SUNXI_GPIO_PULL_UP); |
Laurent Itti | 20dfe00 | 2015-05-05 17:02:00 -0700 | [diff] [blame] | 168 | #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) |
| 169 | sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); |
| 170 | sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); |
| 171 | sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); |
Andre Przywara | 1987b0c | 2022-09-06 15:59:57 +0100 | [diff] [blame] | 172 | #elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_R528) |
| 173 | sunxi_gpio_set_cfgpin(SUNXI_GPB(6), 7); |
| 174 | sunxi_gpio_set_cfgpin(SUNXI_GPB(7), 7); |
| 175 | sunxi_gpio_set_pull(SUNXI_GPB(7), SUNXI_GPIO_PULL_UP); |
Ian Campbell | 8f32aaa | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 176 | #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 177 | sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); |
| 178 | sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); |
Chen-Yu Tsai | 6ee6388 | 2014-10-22 16:47:47 +0800 | [diff] [blame] | 179 | sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); |
Tobias Schramm | 6892a56 | 2021-02-15 00:19:58 +0100 | [diff] [blame] | 180 | #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \ |
| 181 | !defined(CONFIG_MACH_SUN8I_R40) |
| 182 | sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1); |
| 183 | sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1); |
| 184 | sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP); |
Hans de Goede | 8c1c782 | 2014-06-09 11:36:58 +0200 | [diff] [blame] | 185 | #else |
| 186 | #error Unsupported console port number. Please fix pin mux settings in board.c |
| 187 | #endif |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 188 | |
Andre Przywara | 068962b | 2022-10-05 17:54:19 +0100 | [diff] [blame] | 189 | /* |
| 190 | * Update PIO power bias configuration by copying the hardware |
| 191 | * detected value. |
| 192 | */ |
| 193 | if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || |
| 194 | IS_ENABLED(CONFIG_SUN50I_GEN_NCAT2)) { |
| 195 | val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); |
| 196 | writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); |
| 197 | } |
| 198 | if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) { |
| 199 | val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); |
| 200 | writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); |
| 201 | } |
Icenowy Zheng | 112c886 | 2019-04-24 13:44:12 +0800 | [diff] [blame] | 202 | |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 203 | return 0; |
| 204 | } |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 205 | |
Simon Glass | ee30679 | 2016-09-24 18:20:13 -0600 | [diff] [blame] | 206 | static int spl_board_load_image(struct spl_image_info *spl_image, |
| 207 | struct spl_boot_device *bootdev) |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 208 | { |
| 209 | debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr); |
| 210 | return_to_fel(fel_stash.sp, fel_stash.lr); |
Nikita Kiryanov | 33eefe4 | 2015-11-08 17:11:49 +0200 | [diff] [blame] | 211 | |
| 212 | return 0; |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 213 | } |
Simon Glass | 4fc1f25 | 2016-11-30 15:30:50 -0700 | [diff] [blame] | 214 | SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image); |
Simon Glass | 85ed77d | 2024-09-29 19:49:46 -0600 | [diff] [blame] | 215 | #endif /* CONFIG_XPL_BUILD */ |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 216 | |
Andre Przywara | a0a5b21 | 2020-01-10 01:47:31 +0000 | [diff] [blame] | 217 | #define SUNXI_INVALID_BOOT_SOURCE -1 |
| 218 | |
Jesse Taube | fb7bd33 | 2022-02-11 19:32:33 -0500 | [diff] [blame] | 219 | static int suniv_get_boot_source(void) |
| 220 | { |
| 221 | /* Get the last function call from BootROM's stack. */ |
| 222 | u32 brom_call = *(u32 *)(uintptr_t)(fel_stash.sp - 4); |
| 223 | |
| 224 | /* translate SUNIV BootROM stack to standard SUNXI boot sources */ |
| 225 | switch (brom_call) { |
| 226 | case SUNIV_BOOTED_FROM_MMC0: |
| 227 | return SUNXI_BOOTED_FROM_MMC0; |
| 228 | case SUNIV_BOOTED_FROM_SPI: |
| 229 | return SUNXI_BOOTED_FROM_SPI; |
| 230 | case SUNIV_BOOTED_FROM_MMC1: |
| 231 | return SUNXI_BOOTED_FROM_MMC2; |
| 232 | /* SPI NAND is not supported yet. */ |
| 233 | case SUNIV_BOOTED_FROM_NAND: |
| 234 | return SUNXI_INVALID_BOOT_SOURCE; |
| 235 | } |
| 236 | /* If we get here something went wrong try to boot from FEL.*/ |
| 237 | printf("Unknown boot source from BROM: 0x%x\n", brom_call); |
| 238 | return SUNXI_INVALID_BOOT_SOURCE; |
| 239 | } |
| 240 | |
Samuel Holland | 784fcf6 | 2022-03-18 00:00:44 -0500 | [diff] [blame] | 241 | static int sunxi_egon_valid(struct boot_file_head *egon_head) |
| 242 | { |
| 243 | return !memcmp(egon_head->magic, BOOT0_MAGIC, 8); /* eGON.BT0 */ |
| 244 | } |
| 245 | |
| 246 | static int sunxi_toc0_valid(struct toc0_main_info *toc0_info) |
| 247 | { |
| 248 | return !memcmp(toc0_info->name, TOC0_MAIN_INFO_NAME, 8); /* TOC0.GLH */ |
| 249 | } |
| 250 | |
Andre Przywara | a0a5b21 | 2020-01-10 01:47:31 +0000 | [diff] [blame] | 251 | static int sunxi_get_boot_source(void) |
| 252 | { |
Samuel Holland | 784fcf6 | 2022-03-18 00:00:44 -0500 | [diff] [blame] | 253 | struct boot_file_head *egon_head = (void *)SPL_ADDR; |
| 254 | struct toc0_main_info *toc0_info = (void *)SPL_ADDR; |
| 255 | |
Jesse Taube | fb7bd33 | 2022-02-11 19:32:33 -0500 | [diff] [blame] | 256 | /* |
| 257 | * On the ARMv5 SoCs, the SPL header in SRAM is overwritten by the |
| 258 | * exception vectors in U-Boot proper, so we won't find any |
| 259 | * information there. Also the FEL stash is only valid in the SPL, |
| 260 | * so we can't use that either. So if this is called from U-Boot |
| 261 | * proper, just return MMC0 as a placeholder, for now. |
| 262 | */ |
| 263 | if (IS_ENABLED(CONFIG_MACH_SUNIV) && |
Simon Glass | 85ed77d | 2024-09-29 19:49:46 -0600 | [diff] [blame] | 264 | !IS_ENABLED(CONFIG_XPL_BUILD)) |
Jesse Taube | fb7bd33 | 2022-02-11 19:32:33 -0500 | [diff] [blame] | 265 | return SUNXI_BOOTED_FROM_MMC0; |
| 266 | |
Jesse Taube | fb7bd33 | 2022-02-11 19:32:33 -0500 | [diff] [blame] | 267 | if (IS_ENABLED(CONFIG_MACH_SUNIV)) |
| 268 | return suniv_get_boot_source(); |
Samuel Holland | 784fcf6 | 2022-03-18 00:00:44 -0500 | [diff] [blame] | 269 | if (sunxi_egon_valid(egon_head)) |
| 270 | return readb(&egon_head->boot_media); |
| 271 | if (sunxi_toc0_valid(toc0_info)) |
| 272 | return readb(&toc0_info->platform[0]); |
| 273 | |
| 274 | /* Not a valid image, so we must have been booted via FEL. */ |
| 275 | return SUNXI_INVALID_BOOT_SOURCE; |
Andre Przywara | a0a5b21 | 2020-01-10 01:47:31 +0000 | [diff] [blame] | 276 | } |
| 277 | |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 278 | /* The sunxi internal brom will try to loader external bootloader |
| 279 | * from mmc0, nand flash, mmc2. |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 280 | */ |
Maxime Ripard | 1941be8 | 2017-08-23 10:06:30 +0200 | [diff] [blame] | 281 | uint32_t sunxi_get_boot_device(void) |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 282 | { |
Andre Przywara | a0a5b21 | 2020-01-10 01:47:31 +0000 | [diff] [blame] | 283 | int boot_source = sunxi_get_boot_source(); |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 284 | |
Siarhei Siamashka | 7ef91f0 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 285 | /* |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 286 | * When booting from the SD card or NAND memory, the "eGON.BT0" |
| 287 | * signature is expected to be found in memory at the address 0x0004 |
| 288 | * (see the "mksunxiboot" tool, which generates this header). |
Siarhei Siamashka | 7ef91f0 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 289 | * |
| 290 | * When booting in the FEL mode over USB, this signature is patched in |
| 291 | * memory and replaced with something else by the 'fel' tool. This other |
| 292 | * signature is selected in such a way, that it can't be present in a |
| 293 | * valid bootable SD card image (because the BROM would refuse to |
| 294 | * execute the SPL in this case). |
| 295 | * |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 296 | * This checks for the signature and if it is not found returns to |
| 297 | * the FEL code in the BROM to wait and receive the main u-boot |
| 298 | * binary over USB. If it is found, it determines where SPL was |
| 299 | * read from. |
Siarhei Siamashka | 7ef91f0 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 300 | */ |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 301 | switch (boot_source) { |
Andre Przywara | a0a5b21 | 2020-01-10 01:47:31 +0000 | [diff] [blame] | 302 | case SUNXI_INVALID_BOOT_SOURCE: |
| 303 | return BOOT_DEVICE_BOARD; |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 304 | case SUNXI_BOOTED_FROM_MMC0: |
Andre Przywara | 946e9db | 2018-12-16 02:04:58 +0000 | [diff] [blame] | 305 | case SUNXI_BOOTED_FROM_MMC0_HIGH: |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 306 | return BOOT_DEVICE_MMC1; |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 307 | case SUNXI_BOOTED_FROM_NAND: |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 308 | return BOOT_DEVICE_NAND; |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 309 | case SUNXI_BOOTED_FROM_MMC2: |
Andre Przywara | 946e9db | 2018-12-16 02:04:58 +0000 | [diff] [blame] | 310 | case SUNXI_BOOTED_FROM_MMC2_HIGH: |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 311 | return BOOT_DEVICE_MMC2; |
| 312 | case SUNXI_BOOTED_FROM_SPI: |
| 313 | return BOOT_DEVICE_SPI; |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 314 | } |
| 315 | |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 316 | panic("Unknown boot source %d\n", boot_source); |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 317 | return -1; /* Never reached */ |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 318 | } |
| 319 | |
Simon Glass | 85ed77d | 2024-09-29 19:49:46 -0600 | [diff] [blame] | 320 | #ifdef CONFIG_XPL_BUILD |
Samuel Holland | 784fcf6 | 2022-03-18 00:00:44 -0500 | [diff] [blame] | 321 | uint32_t sunxi_get_spl_size(void) |
Andre Przywara | d42cbee | 2021-01-11 21:11:39 +0100 | [diff] [blame] | 322 | { |
Samuel Holland | 784fcf6 | 2022-03-18 00:00:44 -0500 | [diff] [blame] | 323 | struct boot_file_head *egon_head = (void *)SPL_ADDR; |
| 324 | struct toc0_main_info *toc0_info = (void *)SPL_ADDR; |
| 325 | |
| 326 | if (sunxi_egon_valid(egon_head)) |
| 327 | return readl(&egon_head->length); |
| 328 | if (sunxi_toc0_valid(toc0_info)) |
| 329 | return readl(&toc0_info->length); |
Andre Przywara | d42cbee | 2021-01-11 21:11:39 +0100 | [diff] [blame] | 330 | |
Samuel Holland | 784fcf6 | 2022-03-18 00:00:44 -0500 | [diff] [blame] | 331 | /* Not a valid image, so use the default U-Boot offset. */ |
| 332 | return 0; |
Andre Przywara | d42cbee | 2021-01-11 21:11:39 +0100 | [diff] [blame] | 333 | } |
| 334 | |
Andre Przywara | 9ba18e8 | 2020-01-10 01:47:32 +0000 | [diff] [blame] | 335 | /* |
| 336 | * The eGON SPL image can be located at 8KB or at 128KB into an SD card or |
| 337 | * an eMMC device. The boot source has bit 4 set in the latter case. |
| 338 | * By adding 120KB to the normal offset when booting from a "high" location |
Andre Przywara | f25cec9 | 2024-05-10 00:13:16 +0100 | [diff] [blame] | 339 | * we can support both cases. The H616 has the alternative location |
| 340 | * moved up to 256 KB instead of 128KB, so cater for that, too. |
Andre Przywara | d42cbee | 2021-01-11 21:11:39 +0100 | [diff] [blame] | 341 | * Also U-Boot proper is located at least 32KB after the SPL, but will |
| 342 | * immediately follow the SPL if that is bigger than that. |
Andre Przywara | 9ba18e8 | 2020-01-10 01:47:32 +0000 | [diff] [blame] | 343 | */ |
Marek Vasut | f9a921e | 2023-10-16 18:16:12 +0200 | [diff] [blame] | 344 | unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, |
| 345 | unsigned long raw_sect) |
Andre Przywara | 9ba18e8 | 2020-01-10 01:47:32 +0000 | [diff] [blame] | 346 | { |
Andre Przywara | d42cbee | 2021-01-11 21:11:39 +0100 | [diff] [blame] | 347 | unsigned long spl_size = sunxi_get_spl_size(); |
| 348 | unsigned long sector; |
| 349 | |
| 350 | sector = max(raw_sect, spl_size / 512); |
Andre Przywara | 9ba18e8 | 2020-01-10 01:47:32 +0000 | [diff] [blame] | 351 | |
| 352 | switch (sunxi_get_boot_source()) { |
| 353 | case SUNXI_BOOTED_FROM_MMC0_HIGH: |
| 354 | case SUNXI_BOOTED_FROM_MMC2_HIGH: |
| 355 | sector += (128 - 8) * 2; |
Andre Przywara | f25cec9 | 2024-05-10 00:13:16 +0100 | [diff] [blame] | 356 | if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) |
| 357 | sector += 128 * 2; |
Andre Przywara | 9ba18e8 | 2020-01-10 01:47:32 +0000 | [diff] [blame] | 358 | break; |
| 359 | } |
| 360 | |
| 361 | return sector; |
| 362 | } |
| 363 | |
Maxime Ripard | 1941be8 | 2017-08-23 10:06:30 +0200 | [diff] [blame] | 364 | u32 spl_boot_device(void) |
| 365 | { |
| 366 | return sunxi_get_boot_device(); |
| 367 | } |
| 368 | |
Andre Przywara | b277429 | 2022-01-23 00:28:43 +0000 | [diff] [blame] | 369 | __weak void sunxi_sram_init(void) |
| 370 | { |
| 371 | } |
| 372 | |
Andre Przywara | c7175be | 2021-07-12 11:06:50 +0100 | [diff] [blame] | 373 | /* |
| 374 | * When booting from an eMMC boot partition, the SPL puts the same boot |
| 375 | * source code into SRAM A1 as when loading the SPL from the normal |
| 376 | * eMMC user data partition: 0x2. So to know where we have been loaded |
| 377 | * from, we repeat the BROM algorithm here: checking for a valid eGON boot |
| 378 | * image at offset 0 of a (potentially) selected boot partition. |
| 379 | * If any of the conditions is not met, it must have been the eMMC user |
| 380 | * data partition. |
| 381 | */ |
| 382 | static bool sunxi_valid_emmc_boot(struct mmc *mmc) |
| 383 | { |
| 384 | struct blk_desc *bd = mmc_get_blk_desc(mmc); |
Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 385 | u32 *buffer = (void *)(uintptr_t)CONFIG_TEXT_BASE; |
Andre Przywara | c7175be | 2021-07-12 11:06:50 +0100 | [diff] [blame] | 386 | struct boot_file_head *egon_head = (void *)buffer; |
Andre Przywara | 98d724e | 2022-11-25 01:38:06 +0000 | [diff] [blame] | 387 | struct toc0_main_info *toc0_info = (void *)buffer; |
Andre Przywara | c7175be | 2021-07-12 11:06:50 +0100 | [diff] [blame] | 388 | int bootpart = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); |
| 389 | uint32_t spl_size, emmc_checksum, chksum = 0; |
| 390 | ulong count; |
| 391 | |
| 392 | /* The BROM requires BOOT_ACK to be enabled. */ |
| 393 | if (!EXT_CSD_EXTRACT_BOOT_ACK(mmc->part_config)) |
| 394 | return false; |
| 395 | |
| 396 | /* |
| 397 | * The BOOT_BUS_CONDITION register must be 4-bit SDR, with (0x09) |
| 398 | * or without (0x01) high speed timings. |
| 399 | */ |
| 400 | if ((mmc->ext_csd[EXT_CSD_BOOT_BUS_WIDTH] & 0x1b) != 0x01 && |
| 401 | (mmc->ext_csd[EXT_CSD_BOOT_BUS_WIDTH] & 0x1b) != 0x09) |
| 402 | return false; |
| 403 | |
| 404 | /* Partition 0 is the user data partition, bootpart must be 1 or 2. */ |
Tim Harvey | a4e7839 | 2024-05-31 08:36:33 -0700 | [diff] [blame] | 405 | if (bootpart != EMMC_BOOT_PART_BOOT1 && bootpart != EMMC_BOOT_PART_BOOT2) |
Andre Przywara | c7175be | 2021-07-12 11:06:50 +0100 | [diff] [blame] | 406 | return false; |
| 407 | |
| 408 | /* Failure to switch to the boot partition is fatal. */ |
| 409 | if (mmc_switch_part(mmc, bootpart)) |
| 410 | return false; |
| 411 | |
| 412 | /* Read the first block to do some sanity checks on the eGON header. */ |
| 413 | count = blk_dread(bd, 0, 1, buffer); |
Andre Przywara | 98d724e | 2022-11-25 01:38:06 +0000 | [diff] [blame] | 414 | if (count != 1) |
Andre Przywara | c7175be | 2021-07-12 11:06:50 +0100 | [diff] [blame] | 415 | return false; |
| 416 | |
Andre Przywara | 98d724e | 2022-11-25 01:38:06 +0000 | [diff] [blame] | 417 | if (sunxi_egon_valid(egon_head)) |
| 418 | spl_size = egon_head->length; |
| 419 | else if (sunxi_toc0_valid(toc0_info)) |
| 420 | spl_size = toc0_info->length; |
| 421 | else |
| 422 | return false; |
| 423 | |
Andre Przywara | c7175be | 2021-07-12 11:06:50 +0100 | [diff] [blame] | 424 | /* Read the rest of the SPL now we know it's halfway sane. */ |
Andre Przywara | c7175be | 2021-07-12 11:06:50 +0100 | [diff] [blame] | 425 | count = blk_dread(bd, 1, DIV_ROUND_UP(spl_size, bd->blksz) - 1, |
| 426 | buffer + bd->blksz / 4); |
| 427 | |
| 428 | /* Save the checksum and replace it with the "stamp value". */ |
| 429 | emmc_checksum = buffer[3]; |
| 430 | buffer[3] = 0x5f0a6c39; |
| 431 | |
| 432 | /* The checksum is a simple ignore-carry addition of all words. */ |
| 433 | for (count = 0; count < spl_size / 4; count++) |
| 434 | chksum += buffer[count]; |
| 435 | |
| 436 | debug("eMMC boot part SPL checksum: stored: 0x%08x, computed: 0x%08x\n", |
| 437 | emmc_checksum, chksum); |
| 438 | |
| 439 | return emmc_checksum == chksum; |
| 440 | } |
| 441 | |
| 442 | u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) |
| 443 | { |
| 444 | static u32 result = ~0; |
| 445 | |
| 446 | if (result != ~0) |
| 447 | return result; |
| 448 | |
| 449 | result = MMCSD_MODE_RAW; |
| 450 | if (!IS_SD(mmc) && IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) { |
| 451 | if (sunxi_valid_emmc_boot(mmc)) |
| 452 | result = MMCSD_MODE_EMMCBOOT; |
| 453 | else |
| 454 | mmc_switch_part(mmc, 0); |
| 455 | } |
| 456 | |
| 457 | debug("%s(): %s part\n", __func__, |
| 458 | result == MMCSD_MODE_RAW ? "user" : "boot"); |
| 459 | |
| 460 | return result; |
| 461 | } |
| 462 | |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 463 | void board_init_f(ulong dummy) |
| 464 | { |
Andre Przywara | b277429 | 2022-01-23 00:28:43 +0000 | [diff] [blame] | 465 | sunxi_sram_init(); |
| 466 | |
Andre Przywara | e2c133d | 2022-01-22 10:05:12 +0000 | [diff] [blame] | 467 | /* Enable non-secure access to some peripherals */ |
| 468 | tzpc_init(); |
Andre Przywara | e2c133d | 2022-01-22 10:05:12 +0000 | [diff] [blame] | 469 | |
| 470 | clock_init(); |
| 471 | timer_init(); |
| 472 | gpio_init(); |
Andre Przywara | e2c133d | 2022-01-22 10:05:12 +0000 | [diff] [blame] | 473 | |
Hans de Goede | 76fa0b2 | 2015-09-13 12:31:24 +0200 | [diff] [blame] | 474 | spl_init(); |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 475 | preloader_console_init(); |
| 476 | |
Samuel Holland | 35e9f63 | 2021-10-08 00:17:17 -0500 | [diff] [blame] | 477 | #if CONFIG_IS_ENABLED(I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY) |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 478 | /* Needed early by sunxi_board_init if PMU is enabled */ |
Andre Przywara | e2c133d | 2022-01-22 10:05:12 +0000 | [diff] [blame] | 479 | i2c_init_board(); |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 480 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
| 481 | #endif |
| 482 | sunxi_board_init(); |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 483 | } |
Simon Glass | 85ed77d | 2024-09-29 19:49:46 -0600 | [diff] [blame] | 484 | #endif /* CONFIG_XPL_BUILD */ |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 485 | |
Samuel Holland | 01477b3 | 2021-11-03 22:55:15 -0500 | [diff] [blame] | 486 | #if !CONFIG_IS_ENABLED(SYSRESET) |
Harald Seiler | 6f14d5f | 2020-12-15 16:47:52 +0100 | [diff] [blame] | 487 | void reset_cpu(void) |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 488 | { |
Chen-Yu Tsai | 84f3bb4 | 2016-11-30 16:27:14 +0800 | [diff] [blame] | 489 | #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40) |
Hans de Goede | 1374e89 | 2014-06-09 11:36:56 +0200 | [diff] [blame] | 490 | static const struct sunxi_wdog *wdog = |
| 491 | &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; |
| 492 | |
| 493 | /* Set the watchdog for its shortest interval (.5s) and wait */ |
| 494 | writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); |
| 495 | writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); |
Hans de Goede | fa43a6e | 2014-06-13 22:55:52 +0200 | [diff] [blame] | 496 | |
| 497 | while (1) { |
| 498 | /* sun5i sometimes gets stuck without this */ |
| 499 | writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); |
| 500 | } |
Andre Przywara | 068962b | 2022-10-05 17:54:19 +0100 | [diff] [blame] | 501 | #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) |
Clément Péron | 3344544 | 2019-04-17 19:41:05 +0200 | [diff] [blame] | 502 | #if defined(CONFIG_MACH_SUN50I_H6) |
| 503 | /* WDOG is broken for some H6 rev. use the R_WDOG instead */ |
| 504 | static const struct sunxi_wdog *wdog = |
| 505 | (struct sunxi_wdog *)SUNXI_R_WDOG_BASE; |
| 506 | #else |
Chen-Yu Tsai | 1275c48 | 2014-10-04 20:37:28 +0800 | [diff] [blame] | 507 | static const struct sunxi_wdog *wdog = |
Clément Péron | 3344544 | 2019-04-17 19:41:05 +0200 | [diff] [blame] | 508 | ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; |
| 509 | #endif |
Chen-Yu Tsai | 1275c48 | 2014-10-04 20:37:28 +0800 | [diff] [blame] | 510 | /* Set the watchdog for its shortest interval (.5s) and wait */ |
| 511 | writel(WDT_CFG_RESET, &wdog->cfg); |
| 512 | writel(WDT_MODE_EN, &wdog->mode); |
| 513 | writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); |
Hans de Goede | b25d3c9 | 2015-06-14 16:53:15 +0200 | [diff] [blame] | 514 | while (1) { } |
Chen-Yu Tsai | 1275c48 | 2014-10-04 20:37:28 +0800 | [diff] [blame] | 515 | #endif |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 516 | } |
Andre Przywara | a9aab24 | 2022-11-28 00:02:56 +0000 | [diff] [blame] | 517 | #endif /* CONFIG_SYSRESET */ |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 518 | |
Icenowy Zheng | 96b82b6 | 2022-10-13 21:26:44 +0800 | [diff] [blame] | 519 | #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && defined(CONFIG_CPU_V7A) |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 520 | void enable_caches(void) |
| 521 | { |
| 522 | /* Enable D-cache. I-cache is already enabled in start.S */ |
| 523 | dcache_enable(); |
| 524 | } |
| 525 | #endif |