blob: 2bcc2e84a74e09f2fbe08048a81eca657fde0a16 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070040 pci0 = &pci0;
41 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070042 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020043 remoteproc0 = &rproc_1;
44 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060045 rtc0 = &rtc_0;
46 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060047 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020048 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070049 testbus3 = "/some-bus";
50 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070051 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070052 testfdt3 = "/b-test";
53 testfdt5 = "/some-bus/c-test@5";
54 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070055 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020056 fdt-dummy0 = "/translation-test@8000/dev@0,0";
57 fdt-dummy1 = "/translation-test@8000/dev@1,100";
58 fdt-dummy2 = "/translation-test@8000/dev@2,200";
59 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060060 usb0 = &usb_0;
61 usb1 = &usb_1;
62 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020063 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020064 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060065 };
66
Philippe Reynes462d1632022-03-28 22:56:53 +020067 binman {
68 };
69
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020070 config {
Simon Glass0034d962021-08-07 07:24:01 -060071 testing-bool;
72 testing-int = <123>;
73 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020074 environment {
75 from_fdt = "yes";
76 fdt_env_path = "";
77 };
78 };
79
Simon Glassb255efc2022-04-24 23:31:24 -060080 bootstd {
Simon Glassa9289612022-10-20 18:23:14 -060081 u-boot,dm-vpl;
Simon Glassb255efc2022-04-24 23:31:24 -060082 compatible = "u-boot,boot-std";
83
84 filename-prefixes = "/", "/boot/";
85 bootdev-order = "mmc2", "mmc1";
86
87 syslinux {
88 compatible = "u-boot,distro-syslinux";
89 };
90
91 efi {
92 compatible = "u-boot,distro-efi";
93 };
Simon Glassa9289612022-10-20 18:23:14 -060094
95 firmware0 {
96 u-boot,dm-vpl;
97 compatible = "fwupd,vbe-simple";
98 storage = "mmc1";
99 skip-offset = <0x200>;
100 area-start = <0x400>;
101 area-size = <0x1000>;
102 state-offset = <0x400>;
103 state-size = <0x40>;
104 version-offset = <0x800>;
105 version-size = <0x100>;
106 };
Simon Glassb255efc2022-04-24 23:31:24 -0600107 };
108
Andrew Scull451b8b12022-05-30 10:00:12 +0000109 fuzzing-engine {
110 compatible = "sandbox,fuzzing-engine";
111 };
112
Nandor Han6521e5d2021-06-10 16:56:44 +0300113 reboot-mode0 {
114 compatible = "reboot-mode-gpio";
115 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
116 u-boot,env-variable = "bootstatus";
117 mode-test = <0x01>;
118 mode-download = <0x03>;
119 };
120
Nandor Han7e4067a2021-06-10 16:56:45 +0300121 reboot_mode1: reboot-mode@14 {
122 compatible = "reboot-mode-rtc";
123 rtc = <&rtc_0>;
124 reg = <0x30 4>;
125 u-boot,env-variable = "bootstatus";
126 big-endian;
127 mode-test = <0x21969147>;
128 mode-download = <0x51939147>;
129 };
130
Simon Glassed96cde2018-12-10 10:37:33 -0700131 audio: audio-codec {
132 compatible = "sandbox,audio-codec";
133 #sound-dai-cells = <1>;
134 };
135
Philippe Reynes1ee26482020-07-24 18:19:51 +0200136 buttons {
137 compatible = "gpio-keys";
138
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200139 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200140 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200141 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200142 };
143
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200144 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200145 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200146 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200147 };
148 };
149
Marek Szyprowskiad398592021-02-18 11:33:18 +0100150 buttons2 {
151 compatible = "adc-keys";
152 io-channels = <&adc 3>;
153 keyup-threshold-microvolt = <3000000>;
154
155 button-up {
156 label = "button3";
157 linux,code = <KEY_F3>;
158 press-threshold-microvolt = <1500000>;
159 };
160
161 button-down {
162 label = "button4";
163 linux,code = <KEY_F4>;
164 press-threshold-microvolt = <1000000>;
165 };
166
167 button-enter {
168 label = "button5";
169 linux,code = <KEY_F5>;
170 press-threshold-microvolt = <500000>;
171 };
172 };
173
Simon Glassc953aaf2018-12-10 10:37:34 -0700174 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600175 reg = <0 0>;
176 compatible = "google,cros-ec-sandbox";
177
178 /*
179 * This describes the flash memory within the EC. Note
180 * that the STM32L flash erases to 0, not 0xff.
181 */
182 flash {
183 image-pos = <0x08000000>;
184 size = <0x20000>;
185 erase-value = <0>;
186
187 /* Information for sandbox */
188 ro {
189 image-pos = <0>;
190 size = <0xf000>;
191 };
192 wp-ro {
193 image-pos = <0xf000>;
194 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700195 used = <0x884>;
196 compress = "lz4";
197 uncomp-size = <0xcf8>;
198 hash {
199 algo = "sha256";
200 value = [00 01 02 03 04 05 06 07
201 08 09 0a 0b 0c 0d 0e 0f
202 10 11 12 13 14 15 16 17
203 18 19 1a 1b 1c 1d 1e 1f];
204 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600205 };
206 rw {
207 image-pos = <0x10000>;
208 size = <0x10000>;
209 };
210 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300211
212 cros_ec_pwm: cros-ec-pwm {
213 compatible = "google,cros-ec-pwm";
214 #pwm-cells = <1>;
215 };
216
Simon Glass699c9ca2018-10-01 12:22:08 -0600217 };
218
Yannick Fertré9712c822019-10-07 15:29:05 +0200219 dsi_host: dsi_host {
220 compatible = "sandbox,dsi-host";
221 };
222
Simon Glassb2c1cac2014-02-26 15:59:21 -0700223 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600224 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700225 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600226 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700227 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600228 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100229 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
230 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700231 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100232 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
233 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
234 <&gpio_b 7 GPIO_IN 3 2 1>,
235 <&gpio_b 8 GPIO_OUT 3 2 1>,
236 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100237 test3-gpios =
238 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
239 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
240 <&gpio_c 2 GPIO_OUT>,
241 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
242 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200243 <&gpio_c 5 GPIO_IN>,
244 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
245 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530246 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
247 test5-gpios = <&gpio_a 19>;
248
Simon Glass73025392021-10-23 17:26:04 -0600249 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200250 int8-value = /bits/ 8 <0x12>;
251 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700252 int-value = <1234>;
253 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200254 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200255 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600256 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700257 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600258 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200259 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530260
261 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
262 <&muxcontroller0 2>, <&muxcontroller0 3>,
263 <&muxcontroller1>;
264 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
265 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100266 display-timings {
267 timing0: 240x320 {
268 clock-frequency = <6500000>;
269 hactive = <240>;
270 vactive = <320>;
271 hfront-porch = <6>;
272 hback-porch = <7>;
273 hsync-len = <1>;
274 vback-porch = <5>;
275 vfront-porch = <8>;
276 vsync-len = <2>;
277 hsync-active = <1>;
278 vsync-active = <0>;
279 de-active = <1>;
280 pixelclk-active = <1>;
281 interlaced;
282 doublescan;
283 doubleclk;
284 };
285 timing1: 480x800 {
286 clock-frequency = <9000000>;
287 hactive = <480>;
288 vactive = <800>;
289 hfront-porch = <10>;
290 hback-porch = <59>;
291 hsync-len = <12>;
292 vback-porch = <15>;
293 vfront-porch = <17>;
294 vsync-len = <16>;
295 hsync-active = <0>;
296 vsync-active = <1>;
297 de-active = <0>;
298 pixelclk-active = <0>;
299 };
300 timing2: 800x480 {
301 clock-frequency = <33500000>;
302 hactive = <800>;
303 vactive = <480>;
304 hback-porch = <89>;
305 hfront-porch = <164>;
306 vback-porch = <23>;
307 vfront-porch = <10>;
308 hsync-len = <11>;
309 vsync-len = <13>;
310 };
311 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700312 };
313
314 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600315 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700316 compatible = "not,compatible";
317 };
318
319 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600320 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700321 };
322
Simon Glass5620cf82018-10-01 12:22:40 -0600323 backlight: backlight {
324 compatible = "pwm-backlight";
325 enable-gpios = <&gpio_a 1>;
326 power-supply = <&ldo_1>;
327 pwms = <&pwm 0 1000>;
328 default-brightness-level = <5>;
329 brightness-levels = <0 16 32 64 128 170 202 234 255>;
330 };
331
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200332 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200333 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200334 bind-test-child1 {
335 compatible = "sandbox,phy";
336 #phy-cells = <1>;
337 };
338
339 bind-test-child2 {
340 compatible = "simple-bus";
341 };
342 };
343
Simon Glassb2c1cac2014-02-26 15:59:21 -0700344 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600345 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700346 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600347 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700348 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530349
350 mux-controls = <&muxcontroller0 0>;
351 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700352 };
353
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200354 phy_provider0: gen_phy@0 {
355 compatible = "sandbox,phy";
356 #phy-cells = <1>;
357 };
358
359 phy_provider1: gen_phy@1 {
360 compatible = "sandbox,phy";
361 #phy-cells = <0>;
362 broken;
363 };
364
developer71092972020-05-02 11:35:12 +0200365 phy_provider2: gen_phy@2 {
366 compatible = "sandbox,phy";
367 #phy-cells = <0>;
368 };
369
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200370 gen_phy_user: gen_phy_user {
371 compatible = "simple-bus";
372 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
373 phy-names = "phy1", "phy2", "phy3";
374 };
375
developer71092972020-05-02 11:35:12 +0200376 gen_phy_user1: gen_phy_user1 {
377 compatible = "simple-bus";
378 phys = <&phy_provider0 0>, <&phy_provider2>;
379 phy-names = "phy1", "phy2";
380 };
381
Simon Glassb2c1cac2014-02-26 15:59:21 -0700382 some-bus {
383 #address-cells = <1>;
384 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600385 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600386 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600387 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700388 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600389 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700390 compatible = "denx,u-boot-fdt-test";
391 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600392 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700393 ping-add = <5>;
394 };
Simon Glass40717422014-07-23 06:55:18 -0600395 c-test@0 {
396 compatible = "denx,u-boot-fdt-test";
397 reg = <0>;
398 ping-expect = <6>;
399 ping-add = <6>;
400 };
401 c-test@1 {
402 compatible = "denx,u-boot-fdt-test";
403 reg = <1>;
404 ping-expect = <7>;
405 ping-add = <7>;
406 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700407 };
408
409 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600410 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600411 ping-expect = <6>;
412 ping-add = <6>;
413 compatible = "google,another-fdt-test";
414 };
415
416 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600417 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600418 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700419 ping-add = <6>;
420 compatible = "google,another-fdt-test";
421 };
422
Simon Glass0ccb0972015-01-25 08:27:05 -0700423 f-test {
424 compatible = "denx,u-boot-fdt-test";
425 };
426
427 g-test {
428 compatible = "denx,u-boot-fdt-test";
429 };
430
Bin Mengd9d24782018-10-10 22:07:01 -0700431 h-test {
432 compatible = "denx,u-boot-fdt-test1";
433 };
434
developercf8bc132020-05-02 11:35:10 +0200435 i-test {
436 compatible = "mediatek,u-boot-fdt-test";
437 #address-cells = <1>;
438 #size-cells = <0>;
439
440 subnode@0 {
441 reg = <0>;
442 };
443
444 subnode@1 {
445 reg = <1>;
446 };
447
448 subnode@2 {
449 reg = <2>;
450 };
451 };
452
Simon Glass204675c2019-12-29 21:19:25 -0700453 devres-test {
454 compatible = "denx,u-boot-devres-test";
455 };
456
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530457 another-test {
458 reg = <0 2>;
459 compatible = "denx,u-boot-fdt-test";
460 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
461 test5-gpios = <&gpio_a 19>;
462 };
463
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100464 mmio-bus@0 {
465 #address-cells = <1>;
466 #size-cells = <1>;
467 compatible = "denx,u-boot-test-bus";
468 dma-ranges = <0x10000000 0x00000000 0x00040000>;
469
470 subnode@0 {
471 compatible = "denx,u-boot-fdt-test";
472 };
473 };
474
475 mmio-bus@1 {
476 #address-cells = <1>;
477 #size-cells = <1>;
478 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100479
480 subnode@0 {
481 compatible = "denx,u-boot-fdt-test";
482 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100483 };
484
Simon Glass3c601b12020-07-07 13:12:06 -0600485 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600486 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600487 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600488 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600489 child {
490 compatible = "denx,u-boot-acpi-test";
491 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600492 };
493
Simon Glass3c601b12020-07-07 13:12:06 -0600494 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600495 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600496 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600497 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600498 };
499
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200500 clocks {
501 clk_fixed: clk-fixed {
502 compatible = "fixed-clock";
503 #clock-cells = <0>;
504 clock-frequency = <1234>;
505 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000506
507 clk_fixed_factor: clk-fixed-factor {
508 compatible = "fixed-factor-clock";
509 #clock-cells = <0>;
510 clock-div = <3>;
511 clock-mult = <2>;
512 clocks = <&clk_fixed>;
513 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200514
515 osc {
516 compatible = "fixed-clock";
517 #clock-cells = <0>;
518 clock-frequency = <20000000>;
519 };
Stephen Warrena9622432016-06-17 09:44:00 -0600520 };
521
522 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600523 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600524 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200525 assigned-clocks = <&clk_sandbox 3>;
526 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600527 };
528
529 clk-test {
530 compatible = "sandbox,clk-test";
531 clocks = <&clk_fixed>,
532 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200533 <&clk_sandbox 0>,
534 <&clk_sandbox 3>,
535 <&clk_sandbox 2>;
536 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600537 };
538
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200539 ccf: clk-ccf {
540 compatible = "sandbox,clk-ccf";
541 };
542
Simon Glass507ab962021-12-04 08:56:31 -0700543 efi-media {
544 compatible = "sandbox,efi-media";
545 };
546
Simon Glass5b968632015-05-22 15:42:15 -0600547 eth@10002000 {
548 compatible = "sandbox,eth";
549 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600550 };
551
552 eth_5: eth@10003000 {
553 compatible = "sandbox,eth";
554 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400555 nvmem-cells = <&eth5_addr>;
556 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600557 };
558
Bin Meng04a11cb2015-08-27 22:25:53 -0700559 eth_3: sbe5 {
560 compatible = "sandbox,eth";
561 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400562 nvmem-cells = <&eth3_addr>;
563 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700564 };
565
Simon Glass5b968632015-05-22 15:42:15 -0600566 eth@10004000 {
567 compatible = "sandbox,eth";
568 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600569 };
570
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200571 phy_eth0: phy-test-eth {
572 compatible = "sandbox,eth";
573 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400574 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200575 phy-handle = <&ethphy1>;
Marek BehĂșnbc194772022-04-07 00:33:01 +0200576 phy-mode = "2500base-x";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200577 };
578
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800579 dsa_eth0: dsa-test-eth {
580 compatible = "sandbox,eth";
581 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400582 nvmem-cells = <&eth4_addr>;
583 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800584 };
585
586 dsa-test {
587 compatible = "sandbox,dsa";
588
589 ports {
590 #address-cells = <1>;
591 #size-cells = <0>;
592 swp_0: port@0 {
593 reg = <0>;
594 label = "lan0";
595 phy-mode = "rgmii-rxid";
596
597 fixed-link {
598 speed = <100>;
599 full-duplex;
600 };
601 };
602
603 swp_1: port@1 {
604 reg = <1>;
605 label = "lan1";
606 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800607 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800608 };
609
610 port@2 {
611 reg = <2>;
612 ethernet = <&dsa_eth0>;
613
614 fixed-link {
615 speed = <1000>;
616 full-duplex;
617 };
618 };
619 };
620 };
621
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700622 firmware {
623 sandbox_firmware: sandbox-firmware {
624 compatible = "sandbox,firmware";
625 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200626
Etienne Carriere09665cb2022-02-21 09:22:39 +0100627 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200628 compatible = "sandbox,scmi-agent";
629 #address-cells = <1>;
630 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200631
Etienne Carriere09665cb2022-02-21 09:22:39 +0100632 protocol@10 {
633 reg = <0x10>;
634 };
635
636 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200637 reg = <0x14>;
638 #clock-cells = <1>;
639 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200640
Etienne Carriere09665cb2022-02-21 09:22:39 +0100641 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200642 reg = <0x16>;
643 #reset-cells = <1>;
644 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100645
646 protocol@17 {
647 reg = <0x17>;
648
649 regulators {
650 #address-cells = <1>;
651 #size-cells = <0>;
652
Etienne Carriere09665cb2022-02-21 09:22:39 +0100653 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100654 reg = <0>;
655 regulator-name = "sandbox-voltd0";
656 regulator-min-microvolt = <1100000>;
657 regulator-max-microvolt = <3300000>;
658 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100659 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100660 reg = <0x1>;
661 regulator-name = "sandbox-voltd1";
662 regulator-min-microvolt = <1800000>;
663 };
664 };
665 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200666 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700667 };
668
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200669 fpga {
670 compatible = "sandbox,fpga";
671 };
672
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100673 pinctrl-gpio {
674 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700675
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100676 gpio_a: base-gpios {
677 compatible = "sandbox,gpio";
678 gpio-controller;
679 #gpio-cells = <1>;
680 gpio-bank-name = "a";
681 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200682 hog_input_active_low {
683 gpio-hog;
684 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200685 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200686 };
687 hog_input_active_high {
688 gpio-hog;
689 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200690 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200691 };
692 hog_output_low {
693 gpio-hog;
694 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200695 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200696 };
697 hog_output_high {
698 gpio-hog;
699 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200700 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200701 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100702 };
703
704 gpio_b: extra-gpios {
705 compatible = "sandbox,gpio";
706 gpio-controller;
707 #gpio-cells = <5>;
708 gpio-bank-name = "b";
709 sandbox,gpio-count = <10>;
710 };
Simon Glass25348a42014-10-13 23:42:11 -0600711
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100712 gpio_c: pinmux-gpios {
713 compatible = "sandbox,gpio";
714 gpio-controller;
715 #gpio-cells = <2>;
716 gpio-bank-name = "c";
717 sandbox,gpio-count = <10>;
718 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100719 };
720
Simon Glass7df766e2014-12-10 08:55:55 -0700721 i2c@0 {
722 #address-cells = <1>;
723 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600724 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700725 compatible = "sandbox,i2c";
726 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200727 pinctrl-names = "default";
728 pinctrl-0 = <&pinmux_i2c0_pins>;
729
Simon Glass7df766e2014-12-10 08:55:55 -0700730 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400731 #address-cells = <1>;
732 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700733 reg = <0x2c>;
734 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700735 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200736 partitions {
737 compatible = "fixed-partitions";
738 #address-cells = <1>;
739 #size-cells = <1>;
740 bootcount_i2c: bootcount@10 {
741 reg = <10 2>;
742 };
743 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400744
745 eth3_addr: mac-address@24 {
746 reg = <24 6>;
747 };
Simon Glass7df766e2014-12-10 08:55:55 -0700748 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200749
Simon Glass336b2952015-05-22 15:42:17 -0600750 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400751 #address-cells = <1>;
752 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600753 reg = <0x43>;
754 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700755 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400756
757 eth4_addr: mac-address@40 {
758 reg = <0x40 6>;
759 };
Simon Glass336b2952015-05-22 15:42:17 -0600760 };
761
762 rtc_1: rtc@61 {
763 reg = <0x61>;
764 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700765 sandbox,emul = <&emul1>;
766 };
767
768 i2c_emul: emul {
769 reg = <0xff>;
770 compatible = "sandbox,i2c-emul-parent";
771 emul_eeprom: emul-eeprom {
772 compatible = "sandbox,i2c-eeprom";
773 sandbox,filename = "i2c.bin";
774 sandbox,size = <256>;
775 };
776 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700777 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700778 };
779 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700780 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600781 };
782 };
783
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200784 sandbox_pmic: sandbox_pmic {
785 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700786 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200787 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200788
789 mc34708: pmic@41 {
790 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700791 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200792 };
Simon Glass7df766e2014-12-10 08:55:55 -0700793 };
794
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100795 bootcount@0 {
796 compatible = "u-boot,bootcount-rtc";
797 rtc = <&rtc_1>;
798 offset = <0x13>;
799 };
800
Michal Simek4f18f922020-05-28 11:48:55 +0200801 bootcount {
802 compatible = "u-boot,bootcount-i2c-eeprom";
803 i2c-eeprom = <&bootcount_i2c>;
804 };
805
Nandor Han88895812021-06-10 15:40:38 +0300806 bootcount_4@0 {
807 compatible = "u-boot,bootcount-syscon";
808 syscon = <&syscon0>;
809 reg = <0x0 0x04>, <0x0 0x04>;
810 reg-names = "syscon_reg", "offset";
811 };
812
813 bootcount_2@0 {
814 compatible = "u-boot,bootcount-syscon";
815 syscon = <&syscon0>;
816 reg = <0x0 0x04>, <0x0 0x02> ;
817 reg-names = "syscon_reg", "offset";
818 };
819
Marek Szyprowskiad398592021-02-18 11:33:18 +0100820 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100821 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100822 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100823 vdd-supply = <&buck2>;
824 vss-microvolts = <0>;
825 };
826
Mark Kettenis67748ee2021-10-23 16:58:02 +0200827 iommu: iommu@0 {
828 compatible = "sandbox,iommu";
829 #iommu-cells = <0>;
830 };
831
Simon Glass515dcff2020-02-06 09:55:00 -0700832 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700833 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700834 interrupt-controller;
835 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700836 };
837
Simon Glass90b6fef2016-01-18 19:52:26 -0700838 lcd {
839 u-boot,dm-pre-reloc;
840 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200841 pinctrl-names = "default";
842 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700843 xres = <1366>;
844 yres = <768>;
845 };
846
Simon Glassd783eb32015-07-06 12:54:34 -0600847 leds {
848 compatible = "gpio-leds";
849
850 iracibble {
851 gpios = <&gpio_a 1 0>;
852 label = "sandbox:red";
853 };
854
855 martinet {
856 gpios = <&gpio_a 2 0>;
857 label = "sandbox:green";
858 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200859
860 default_on {
861 gpios = <&gpio_a 5 0>;
862 label = "sandbox:default_on";
863 default-state = "on";
864 };
865
866 default_off {
867 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400868 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200869 default-state = "off";
870 };
Simon Glassd783eb32015-07-06 12:54:34 -0600871 };
872
Paul Doelle709f0372022-07-04 09:00:25 +0000873 wdt-gpio-toggle {
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200874 gpios = <&gpio_a 7 0>;
875 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200876 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +0000877 hw_algo = "toggle";
878 always-running;
879 };
880
881 wdt-gpio-level {
882 gpios = <&gpio_a 7 0>;
883 compatible = "linux,wdt-gpio";
884 hw_margin_ms = <100>;
885 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200886 always-running;
887 };
888
Stephen Warren62f2c902016-05-16 17:41:37 -0600889 mbox: mbox {
890 compatible = "sandbox,mbox";
891 #mbox-cells = <1>;
892 };
893
894 mbox-test {
895 compatible = "sandbox,mbox-test";
896 mboxes = <&mbox 100>, <&mbox 1>;
897 mbox-names = "other", "test";
898 };
899
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900900 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200901 #address-cells = <1>;
902 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400903 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200904 cpu1: cpu@1 {
905 device_type = "cpu";
906 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400907 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900908 compatible = "sandbox,cpu_sandbox";
909 u-boot,dm-pre-reloc;
910 };
Mario Sixdea5df72018-08-06 10:23:44 +0200911
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200912 cpu2: cpu@2 {
913 device_type = "cpu";
914 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900915 compatible = "sandbox,cpu_sandbox";
916 u-boot,dm-pre-reloc;
917 };
Mario Sixdea5df72018-08-06 10:23:44 +0200918
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200919 cpu3: cpu@3 {
920 device_type = "cpu";
921 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900922 compatible = "sandbox,cpu_sandbox";
923 u-boot,dm-pre-reloc;
924 };
Mario Sixdea5df72018-08-06 10:23:44 +0200925 };
926
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500927 chipid: chipid {
928 compatible = "sandbox,soc";
929 };
930
Simon Glassc953aaf2018-12-10 10:37:34 -0700931 i2s: i2s {
932 compatible = "sandbox,i2s";
933 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700934 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700935 };
936
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200937 nop-test_0 {
938 compatible = "sandbox,nop_sandbox1";
939 nop-test_1 {
940 compatible = "sandbox,nop_sandbox2";
941 bind = "True";
942 };
943 nop-test_2 {
944 compatible = "sandbox,nop_sandbox2";
945 bind = "False";
946 };
947 };
948
Roger Quadrosb0679a72022-10-20 16:30:46 +0300949 memory-controller {
950 compatible = "sandbox,memory";
951 };
952
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200953 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -0400954 #address-cells = <1>;
955 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200956 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -0400957
958 eth5_addr: mac-address@10 {
959 reg = <0x10 6>;
960 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200961 };
962
Simon Glasse4fef742017-04-23 20:02:07 -0600963 mmc2 {
964 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -0600965 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -0600966 };
967
Simon Glassb255efc2022-04-24 23:31:24 -0600968 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -0600969 mmc1 {
970 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -0600971 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -0600972 };
973
Simon Glassb255efc2022-04-24 23:31:24 -0600974 /* This is used for the fastboot tests */
Simon Glasse4fef742017-04-23 20:02:07 -0600975 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600976 compatible = "sandbox,mmc";
977 };
978
Simon Glass53a68b32019-02-16 20:24:50 -0700979 pch {
980 compatible = "sandbox,pch";
981 };
982
Tom Rini4a3ca482020-02-11 12:41:23 -0500983 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700984 compatible = "sandbox,pci";
985 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500986 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700987 #address-cells = <3>;
988 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600989 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700990 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700991 pci@0,0 {
992 compatible = "pci-generic";
993 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600994 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700995 };
Alex Margineanf1274432019-06-07 11:24:24 +0300996 pci@1,0 {
997 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600998 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
999 reg = <0x02000814 0 0 0 0
1000 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001001 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001002 };
Simon Glass937bb472019-12-06 21:41:57 -07001003 p2sb-pci@2,0 {
1004 compatible = "sandbox,p2sb";
1005 reg = <0x02001010 0 0 0 0>;
1006 sandbox,emul = <&p2sb_emul>;
1007
1008 adder {
1009 intel,p2sb-port-id = <3>;
1010 compatible = "sandbox,adder";
1011 };
1012 };
Simon Glass8c501022019-12-06 21:41:54 -07001013 pci@1e,0 {
1014 compatible = "sandbox,pmc";
1015 reg = <0xf000 0 0 0 0>;
1016 sandbox,emul = <&pmc_emul1e>;
1017 acpi-base = <0x400>;
1018 gpe0-dwx-mask = <0xf>;
1019 gpe0-dwx-shift-base = <4>;
1020 gpe0-dw = <6 7 9>;
1021 gpe0-sts = <0x20>;
1022 gpe0-en = <0x30>;
1023 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001024 pci@1f,0 {
1025 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001026 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
1027 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001028 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001029 };
1030 };
1031
Simon Glassb98ba4c2019-09-25 08:56:10 -06001032 pci-emul0 {
1033 compatible = "sandbox,pci-emul-parent";
1034 swap_case_emul0_0: emul0@0,0 {
1035 compatible = "sandbox,swap-case";
1036 };
1037 swap_case_emul0_1: emul0@1,0 {
1038 compatible = "sandbox,swap-case";
1039 use-ea;
1040 };
1041 swap_case_emul0_1f: emul0@1f,0 {
1042 compatible = "sandbox,swap-case";
1043 };
Simon Glass937bb472019-12-06 21:41:57 -07001044 p2sb_emul: emul@2,0 {
1045 compatible = "sandbox,p2sb-emul";
1046 };
Simon Glass8c501022019-12-06 21:41:54 -07001047 pmc_emul1e: emul@1e,0 {
1048 compatible = "sandbox,pmc-emul";
1049 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001050 };
1051
Tom Rini4a3ca482020-02-11 12:41:23 -05001052 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001053 compatible = "sandbox,pci";
1054 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001055 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001056 #address-cells = <3>;
1057 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001058 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001059 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001060 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001061 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001062 0x0c 0x00 0x1234 0x5678
1063 0x10 0x00 0x1234 0x5678>;
1064 pci@10,0 {
1065 reg = <0x8000 0 0 0 0>;
1066 };
Bin Meng408e5902018-08-03 01:14:41 -07001067 };
1068
Tom Rini4a3ca482020-02-11 12:41:23 -05001069 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001070 compatible = "sandbox,pci";
1071 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001072 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001073 #address-cells = <3>;
1074 #size-cells = <2>;
1075 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1076 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1077 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1078 pci@1f,0 {
1079 compatible = "pci-generic";
1080 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001081 sandbox,emul = <&swap_case_emul2_1f>;
1082 };
1083 };
1084
1085 pci-emul2 {
1086 compatible = "sandbox,pci-emul-parent";
1087 swap_case_emul2_1f: emul2@1f,0 {
1088 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001089 };
1090 };
1091
Ramon Friedc64f19b2019-04-27 11:15:23 +03001092 pci_ep: pci_ep {
1093 compatible = "sandbox,pci_ep";
1094 };
1095
Simon Glass9c433fe2017-04-23 20:10:44 -06001096 probing {
1097 compatible = "simple-bus";
1098 test1 {
1099 compatible = "denx,u-boot-probe-test";
1100 };
1101
1102 test2 {
1103 compatible = "denx,u-boot-probe-test";
1104 };
1105
1106 test3 {
1107 compatible = "denx,u-boot-probe-test";
1108 };
1109
1110 test4 {
1111 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001112 first-syscon = <&syscon0>;
1113 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001114 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001115 };
1116 };
1117
Stephen Warren92c67fa2016-07-13 13:45:31 -06001118 pwrdom: power-domain {
1119 compatible = "sandbox,power-domain";
1120 #power-domain-cells = <1>;
1121 };
1122
1123 power-domain-test {
1124 compatible = "sandbox,power-domain-test";
1125 power-domains = <&pwrdom 2>;
1126 };
1127
Simon Glass5620cf82018-10-01 12:22:40 -06001128 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001129 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001130 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001131 pinctrl-names = "default";
1132 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001133 };
1134
1135 pwm2 {
1136 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001137 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001138 };
1139
Simon Glass3d355e62015-07-06 12:54:31 -06001140 ram {
1141 compatible = "sandbox,ram";
1142 };
1143
Simon Glassd860f222015-07-06 12:54:29 -06001144 reset@0 {
1145 compatible = "sandbox,warm-reset";
Michal Suchanek76874302022-10-10 20:29:39 +02001146 u-boot,dm-pre-proper;
Simon Glassd860f222015-07-06 12:54:29 -06001147 };
1148
1149 reset@1 {
1150 compatible = "sandbox,reset";
Michal Suchanek76874302022-10-10 20:29:39 +02001151 u-boot,dm-pre-proper;
Simon Glassd860f222015-07-06 12:54:29 -06001152 };
1153
Stephen Warren6488e642016-06-17 09:43:59 -06001154 resetc: reset-ctl {
1155 compatible = "sandbox,reset-ctl";
1156 #reset-cells = <1>;
1157 };
1158
1159 reset-ctl-test {
1160 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001161 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1162 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001163 };
1164
Sughosh Ganu23e37512019-12-28 23:58:31 +05301165 rng {
1166 compatible = "sandbox,sandbox-rng";
1167 };
1168
Nishanth Menonedf85812015-09-17 15:42:41 -05001169 rproc_1: rproc@1 {
1170 compatible = "sandbox,test-processor";
1171 remoteproc-name = "remoteproc-test-dev1";
1172 };
1173
1174 rproc_2: rproc@2 {
1175 compatible = "sandbox,test-processor";
1176 internal-memory-mapped;
1177 remoteproc-name = "remoteproc-test-dev2";
1178 };
1179
Simon Glass5620cf82018-10-01 12:22:40 -06001180 panel {
1181 compatible = "simple-panel";
1182 backlight = <&backlight 0 100>;
1183 };
1184
Simon Glass509f32e2022-09-21 16:21:47 +02001185 scsi {
1186 compatible = "sandbox,scsi";
1187 sandbox,filepath = "scsi.img";
1188 };
1189
Ramon Fried26ed32e2018-07-02 02:57:59 +03001190 smem@0 {
1191 compatible = "sandbox,smem";
1192 };
1193
Simon Glass76072ac2018-12-10 10:37:36 -07001194 sound {
1195 compatible = "sandbox,sound";
1196 cpu {
1197 sound-dai = <&i2s 0>;
1198 };
1199
1200 codec {
1201 sound-dai = <&audio 0>;
1202 };
1203 };
1204
Simon Glass25348a42014-10-13 23:42:11 -06001205 spi@0 {
1206 #address-cells = <1>;
1207 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001208 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001209 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001210 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001211 pinctrl-names = "default";
1212 pinctrl-0 = <&pinmux_spi0_pins>;
1213
Simon Glass25348a42014-10-13 23:42:11 -06001214 spi.bin@0 {
1215 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001216 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001217 spi-max-frequency = <40000000>;
1218 sandbox,filename = "spi.bin";
1219 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001220 spi.bin@1 {
1221 reg = <1>;
1222 compatible = "spansion,m25p16", "jedec,spi-nor";
1223 spi-max-frequency = <50000000>;
1224 sandbox,filename = "spi.bin";
1225 spi-cpol;
1226 spi-cpha;
1227 };
Simon Glass25348a42014-10-13 23:42:11 -06001228 };
1229
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001230 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001231 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001232 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001233 };
1234
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001235 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001236 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001237 reg = <0x20 5
1238 0x28 6
1239 0x30 7
1240 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001241 };
1242
Patrick Delaunayee010432019-03-07 09:57:13 +01001243 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001244 compatible = "simple-mfd", "syscon";
1245 reg = <0x40 5
1246 0x48 6
1247 0x50 7
1248 0x58 8>;
1249 };
1250
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301251 syscon3: syscon@3 {
1252 compatible = "simple-mfd", "syscon";
1253 reg = <0x000100 0x10>;
1254
1255 muxcontroller0: a-mux-controller {
1256 compatible = "mmio-mux";
1257 #mux-control-cells = <1>;
1258
1259 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1260 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1261 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1262 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1263 u-boot,mux-autoprobe;
1264 };
1265 };
1266
1267 muxcontroller1: emul-mux-controller {
1268 compatible = "mux-emul";
1269 #mux-control-cells = <0>;
1270 u-boot,mux-autoprobe;
1271 idle-state = <0xabcd>;
1272 };
1273
Simon Glass791a17f2020-12-16 21:20:27 -07001274 testfdtm0 {
1275 compatible = "denx,u-boot-fdtm-test";
1276 };
1277
1278 testfdtm1: testfdtm1 {
1279 compatible = "denx,u-boot-fdtm-test";
1280 };
1281
1282 testfdtm2 {
1283 compatible = "denx,u-boot-fdtm-test";
1284 };
1285
Sean Anderson79d3bba2020-09-28 10:52:23 -04001286 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001287 compatible = "sandbox,timer";
1288 clock-frequency = <1000000>;
1289 };
1290
Sean Anderson79d3bba2020-09-28 10:52:23 -04001291 timer@1 {
1292 compatible = "sandbox,timer";
1293 sandbox,timebase-frequency-fallback;
1294 };
1295
Miquel Raynal80938c12018-05-15 11:57:27 +02001296 tpm2 {
1297 compatible = "sandbox,tpm2";
1298 };
1299
Simon Glass5b968632015-05-22 15:42:15 -06001300 uart0: serial {
1301 compatible = "sandbox,serial";
1302 u-boot,dm-pre-reloc;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001303 pinctrl-names = "default";
1304 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001305 };
1306
Simon Glass31680482015-03-25 12:23:05 -06001307 usb_0: usb@0 {
1308 compatible = "sandbox,usb";
1309 status = "disabled";
1310 hub {
1311 compatible = "sandbox,usb-hub";
1312 #address-cells = <1>;
1313 #size-cells = <0>;
1314 flash-stick {
1315 reg = <0>;
1316 compatible = "sandbox,usb-flash";
1317 };
1318 };
1319 };
1320
1321 usb_1: usb@1 {
1322 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001323 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001324 hub {
1325 compatible = "usb-hub";
1326 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001327 #address-cells = <1>;
1328 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001329 hub-emul {
1330 compatible = "sandbox,usb-hub";
1331 #address-cells = <1>;
1332 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001333 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001334 reg = <0>;
1335 compatible = "sandbox,usb-flash";
1336 sandbox,filepath = "testflash.bin";
1337 };
1338
Simon Glass4700fe52015-11-08 23:48:01 -07001339 flash-stick@1 {
1340 reg = <1>;
1341 compatible = "sandbox,usb-flash";
1342 sandbox,filepath = "testflash1.bin";
1343 };
1344
1345 flash-stick@2 {
1346 reg = <2>;
1347 compatible = "sandbox,usb-flash";
1348 sandbox,filepath = "testflash2.bin";
1349 };
1350
Simon Glassc0ccc722015-11-08 23:48:08 -07001351 keyb@3 {
1352 reg = <3>;
1353 compatible = "sandbox,usb-keyb";
1354 };
1355
Simon Glass31680482015-03-25 12:23:05 -06001356 };
Michael Walle7c961322020-06-02 01:47:07 +02001357
1358 usbstor@1 {
1359 reg = <1>;
1360 };
1361 usbstor@3 {
1362 reg = <3>;
1363 };
Simon Glass31680482015-03-25 12:23:05 -06001364 };
1365 };
1366
1367 usb_2: usb@2 {
1368 compatible = "sandbox,usb";
1369 status = "disabled";
1370 };
1371
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001372 spmi: spmi@0 {
1373 compatible = "sandbox,spmi";
1374 #address-cells = <0x1>;
1375 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001376 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001377 pm8916@0 {
1378 compatible = "qcom,spmi-pmic";
1379 reg = <0x0 0x1>;
1380 #address-cells = <0x1>;
1381 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001382 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001383
1384 spmi_gpios: gpios@c000 {
1385 compatible = "qcom,pm8916-gpio";
1386 reg = <0xc000 0x400>;
1387 gpio-controller;
1388 gpio-count = <4>;
1389 #gpio-cells = <2>;
1390 gpio-bank-name="spmi";
1391 };
1392 };
1393 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001394
1395 wdt0: wdt@0 {
1396 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001397 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001398 };
Rob Clarka471b672018-01-10 11:33:30 +01001399
Mario Six95922152018-08-09 14:51:19 +02001400 axi: axi@0 {
1401 compatible = "sandbox,axi";
1402 #address-cells = <0x1>;
1403 #size-cells = <0x1>;
1404 store@0 {
1405 compatible = "sandbox,sandbox_store";
1406 reg = <0x0 0x400>;
1407 };
1408 };
1409
Rob Clarka471b672018-01-10 11:33:30 +01001410 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001411 #address-cells = <1>;
1412 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001413 setting = "sunrise ohoka";
1414 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001415 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001416 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001417 chosen-test {
1418 compatible = "denx,u-boot-fdt-test";
1419 reg = <9 1>;
1420 };
1421 };
Mario Six35616ef2018-03-12 14:53:33 +01001422
1423 translation-test@8000 {
1424 compatible = "simple-bus";
1425 reg = <0x8000 0x4000>;
1426
1427 #address-cells = <0x2>;
1428 #size-cells = <0x1>;
1429
1430 ranges = <0 0x0 0x8000 0x1000
1431 1 0x100 0x9000 0x1000
1432 2 0x200 0xA000 0x1000
1433 3 0x300 0xB000 0x1000
1434 >;
1435
Fabien Dessenne22236e02019-05-31 15:11:30 +02001436 dma-ranges = <0 0x000 0x10000000 0x1000
1437 1 0x100 0x20000000 0x1000
1438 >;
1439
Mario Six35616ef2018-03-12 14:53:33 +01001440 dev@0,0 {
1441 compatible = "denx,u-boot-fdt-dummy";
1442 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojasa3181152018-12-03 19:37:09 +01001443 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001444 };
1445
1446 dev@1,100 {
1447 compatible = "denx,u-boot-fdt-dummy";
1448 reg = <1 0x100 0x1000>;
1449
1450 };
1451
1452 dev@2,200 {
1453 compatible = "denx,u-boot-fdt-dummy";
1454 reg = <2 0x200 0x1000>;
1455 };
1456
1457
1458 noxlatebus@3,300 {
1459 compatible = "simple-bus";
1460 reg = <3 0x300 0x1000>;
1461
1462 #address-cells = <0x1>;
1463 #size-cells = <0x0>;
1464
1465 dev@42 {
1466 compatible = "denx,u-boot-fdt-dummy";
1467 reg = <0x42>;
1468 };
1469 };
1470 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001471
1472 osd {
1473 compatible = "sandbox,sandbox_osd";
1474 };
Tom Rinib93eea72018-09-30 18:16:51 -04001475
Jens Wiklander86afaa62018-09-25 16:40:16 +02001476 sandbox_tee {
1477 compatible = "sandbox,tee";
1478 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001479
1480 sandbox_virtio1 {
1481 compatible = "sandbox,virtio1";
1482 };
1483
1484 sandbox_virtio2 {
1485 compatible = "sandbox,virtio2";
1486 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001487
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001488 sandbox_scmi {
1489 compatible = "sandbox,scmi-devices";
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001490 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001491 resets = <&reset_scmi 3>;
1492 regul0-supply = <&regul0_scmi>;
1493 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001494 };
1495
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001496 pinctrl {
1497 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001498
Sean Anderson3438e3b2020-09-14 11:01:57 -04001499 pinctrl-names = "default", "alternate";
1500 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1501 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001502
Sean Anderson3438e3b2020-09-14 11:01:57 -04001503 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001504 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001505 pins = "P5";
1506 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001507 bias-pull-up;
1508 input-disable;
1509 };
1510 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001511 pins = "P6";
1512 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001513 output-high;
1514 drive-open-drain;
1515 };
1516 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001517 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001518 bias-pull-down;
1519 input-enable;
1520 };
1521 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001522 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001523 bias-disable;
1524 };
1525 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001526
1527 pinctrl_i2c: i2c {
1528 groups {
1529 groups = "I2C_UART";
1530 function = "I2C";
1531 };
1532
1533 pins {
1534 pins = "P0", "P1";
1535 drive-open-drain;
1536 };
1537 };
1538
1539 pinctrl_i2s: i2s {
1540 groups = "SPI_I2S";
1541 function = "I2S";
1542 };
1543
1544 pinctrl_spi: spi {
1545 groups = "SPI_I2S";
1546 function = "SPI";
1547
1548 cs {
1549 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1550 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1551 };
1552 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001553 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001554
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001555 pinctrl-single-no-width {
1556 compatible = "pinctrl-single";
1557 reg = <0x0000 0x238>;
1558 #pinctrl-cells = <1>;
1559 pinctrl-single,function-mask = <0x7f>;
1560 };
1561
1562 pinctrl-single-pins {
1563 compatible = "pinctrl-single";
1564 reg = <0x0000 0x238>;
1565 #pinctrl-cells = <1>;
1566 pinctrl-single,register-width = <32>;
1567 pinctrl-single,function-mask = <0x7f>;
1568
1569 pinmux_pwm_pins: pinmux_pwm_pins {
1570 pinctrl-single,pins = < 0x48 0x06 >;
1571 };
1572
1573 pinmux_spi0_pins: pinmux_spi0_pins {
1574 pinctrl-single,pins = <
1575 0x190 0x0c
1576 0x194 0x0c
1577 0x198 0x23
1578 0x19c 0x0c
1579 >;
1580 };
1581
1582 pinmux_uart0_pins: pinmux_uart0_pins {
1583 pinctrl-single,pins = <
1584 0x70 0x30
1585 0x74 0x00
1586 >;
1587 };
1588 };
1589
1590 pinctrl-single-bits {
1591 compatible = "pinctrl-single";
1592 reg = <0x0000 0x50>;
1593 #pinctrl-cells = <2>;
1594 pinctrl-single,bit-per-mux;
1595 pinctrl-single,register-width = <32>;
1596 pinctrl-single,function-mask = <0xf>;
1597
1598 pinmux_i2c0_pins: pinmux_i2c0_pins {
1599 pinctrl-single,bits = <
1600 0x10 0x00002200 0x0000ff00
1601 >;
1602 };
1603
1604 pinmux_lcd_pins: pinmux_lcd_pins {
1605 pinctrl-single,bits = <
1606 0x40 0x22222200 0xffffff00
1607 0x44 0x22222222 0xffffffff
1608 0x48 0x00000022 0x000000ff
1609 0x48 0x02000000 0x0f000000
1610 0x4c 0x02000022 0x0f0000ff
1611 >;
1612 };
1613 };
1614
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001615 hwspinlock@0 {
1616 compatible = "sandbox,hwspinlock";
1617 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001618
1619 dma: dma {
1620 compatible = "sandbox,dma";
1621 #dma-cells = <1>;
1622
1623 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1624 dma-names = "m2m", "tx0", "rx0";
1625 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001626
Alex Marginean0649be52019-07-12 10:13:53 +03001627 /*
1628 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1629 * end of the test. If parent mdio is removed first, clean-up of the
1630 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1631 * active at the end of the test. That it turn doesn't allow the mdio
1632 * class to be destroyed, triggering an error.
1633 */
1634 mdio-mux-test {
1635 compatible = "sandbox,mdio-mux";
1636 #address-cells = <1>;
1637 #size-cells = <0>;
1638 mdio-parent-bus = <&mdio>;
1639
1640 mdio-ch-test@0 {
1641 reg = <0>;
1642 };
1643 mdio-ch-test@1 {
1644 reg = <1>;
1645 };
1646 };
1647
1648 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001649 compatible = "sandbox,mdio";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +02001650 #address-cells = <1>;
1651 #size-cells = <0>;
1652
1653 ethphy1: ethernet-phy@1 {
1654 reg = <1>;
1655 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001656 };
Sean Andersonb7860542020-06-24 06:41:12 -04001657
1658 pm-bus-test {
1659 compatible = "simple-pm-bus";
1660 clocks = <&clk_sandbox 4>;
1661 power-domains = <&pwrdom 1>;
1662 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001663
1664 resetc2: syscon-reset {
1665 compatible = "syscon-reset";
1666 #reset-cells = <1>;
1667 regmap = <&syscon0>;
1668 offset = <1>;
1669 mask = <0x27FFFFFF>;
1670 assert-high = <0>;
1671 };
1672
1673 syscon-reset-test {
1674 compatible = "sandbox,misc_sandbox";
1675 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1676 reset-names = "valid", "no_mask", "out_of_range";
1677 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301678
Simon Glass458b66a2020-11-05 06:32:05 -07001679 sysinfo {
1680 compatible = "sandbox,sysinfo-sandbox";
1681 };
1682
Sean Anderson1c830672021-04-20 10:50:58 -04001683 sysinfo-gpio {
1684 compatible = "gpio-sysinfo";
1685 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1686 revisions = <19>, <5>;
1687 names = "rev_a", "foo";
1688 };
1689
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301690 some_regmapped-bus {
1691 #address-cells = <0x1>;
1692 #size-cells = <0x1>;
1693
1694 ranges = <0x0 0x0 0x10>;
1695 compatible = "simple-bus";
1696
1697 regmap-test_0 {
1698 reg = <0 0x10>;
1699 compatible = "sandbox,regmap_test";
1700 };
1701 };
Robert Marko9cf87122022-09-06 13:30:35 +02001702
1703 thermal {
1704 compatible = "sandbox,thermal";
1705 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001706};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001707
1708#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001709#include "cros-ec-keyboard.dtsi"