Kever Yang | 6fc9ebf | 2018-12-20 11:33:42 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2016-2017 Rockchip Inc. |
| 4 | * |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 5 | * Adapted from coreboot. |
| 6 | */ |
Philipp Tomsich | c69b309 | 2017-05-31 18:16:34 +0200 | [diff] [blame] | 7 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 8 | #include <common.h> |
| 9 | #include <clk.h> |
| 10 | #include <dm.h> |
| 11 | #include <dt-structs.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 12 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 13 | #include <log.h> |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 14 | #include <ram.h> |
| 15 | #include <regmap.h> |
| 16 | #include <syscon.h> |
| 17 | #include <asm/io.h> |
Kever Yang | 9fbe17c | 2019-03-28 11:01:23 +0800 | [diff] [blame] | 18 | #include <asm/arch-rockchip/clock.h> |
Jagan Teki | 783acfd | 2020-01-09 14:22:17 +0530 | [diff] [blame] | 19 | #include <asm/arch-rockchip/cru.h> |
Kever Yang | 9fbe17c | 2019-03-28 11:01:23 +0800 | [diff] [blame] | 20 | #include <asm/arch-rockchip/grf_rk3399.h> |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 21 | #include <asm/arch-rockchip/pmu_rk3399.h> |
Kever Yang | 9fbe17c | 2019-03-28 11:01:23 +0800 | [diff] [blame] | 22 | #include <asm/arch-rockchip/hardware.h> |
Kever Yang | e47db83 | 2019-11-15 11:04:33 +0800 | [diff] [blame] | 23 | #include <asm/arch-rockchip/sdram.h> |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 24 | #include <asm/arch-rockchip/sdram_rk3399.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 25 | #include <linux/delay.h> |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 26 | #include <linux/err.h> |
Philipp Tomsich | c69b309 | 2017-05-31 18:16:34 +0200 | [diff] [blame] | 27 | #include <time.h> |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 28 | |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 29 | #define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6)) |
| 30 | #define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7)) |
| 31 | #define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8)) |
| 32 | |
| 33 | #define PHY_DRV_ODT_HI_Z 0x0 |
| 34 | #define PHY_DRV_ODT_240 0x1 |
| 35 | #define PHY_DRV_ODT_120 0x8 |
| 36 | #define PHY_DRV_ODT_80 0x9 |
| 37 | #define PHY_DRV_ODT_60 0xc |
| 38 | #define PHY_DRV_ODT_48 0xd |
| 39 | #define PHY_DRV_ODT_40 0xe |
| 40 | #define PHY_DRV_ODT_34_3 0xf |
| 41 | |
Jagan Teki | 5d15217 | 2019-07-16 17:27:15 +0530 | [diff] [blame] | 42 | #define PHY_BOOSTP_EN 0x1 |
| 43 | #define PHY_BOOSTN_EN 0x1 |
Jagan Teki | d868184 | 2019-07-16 17:27:16 +0530 | [diff] [blame] | 44 | #define PHY_SLEWP_EN 0x1 |
| 45 | #define PHY_SLEWN_EN 0x1 |
Jagan Teki | 65535a2 | 2019-07-16 17:27:17 +0530 | [diff] [blame] | 46 | #define PHY_RX_CM_INPUT 0x1 |
Jagan Teki | 0cb3112 | 2019-07-16 17:27:24 +0530 | [diff] [blame] | 47 | #define CS0_MR22_VAL 0 |
| 48 | #define CS1_MR22_VAL 3 |
Jagan Teki | 5d15217 | 2019-07-16 17:27:15 +0530 | [diff] [blame] | 49 | |
YouMin Chen | 79f4d91 | 2019-11-15 11:04:53 +0800 | [diff] [blame] | 50 | /* LPDDR3 DRAM DS */ |
| 51 | #define LPDDR3_DS_34 0x1 |
| 52 | #define LPDDR3_DS_40 0x2 |
| 53 | #define LPDDR3_DS_48 0x3 |
| 54 | |
Jagan Teki | ce75cfb | 2019-07-15 23:58:43 +0530 | [diff] [blame] | 55 | #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ |
| 56 | ((n) << (8 + (ch) * 4))) |
| 57 | #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ |
| 58 | ((n) << (9 + (ch) * 4))) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 59 | struct chan_info { |
| 60 | struct rk3399_ddr_pctl_regs *pctl; |
| 61 | struct rk3399_ddr_pi_regs *pi; |
| 62 | struct rk3399_ddr_publ_regs *publ; |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 63 | struct msch_regs *msch; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 64 | }; |
| 65 | |
| 66 | struct dram_info { |
Kever Yang | 7f34784 | 2019-04-01 17:20:53 +0800 | [diff] [blame] | 67 | #if defined(CONFIG_TPL_BUILD) || \ |
| 68 | (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 69 | u32 pwrup_srefresh_exit[2]; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 70 | struct chan_info chan[2]; |
| 71 | struct clk ddr_clk; |
Jagan Teki | 783acfd | 2020-01-09 14:22:17 +0530 | [diff] [blame] | 72 | struct rockchip_cru *cru; |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 73 | struct rk3399_grf_regs *grf; |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 74 | struct rk3399_pmu_regs *pmu; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 75 | struct rk3399_pmucru *pmucru; |
| 76 | struct rk3399_pmusgrf_regs *pmusgrf; |
| 77 | struct rk3399_ddr_cic_regs *cic; |
Jagan Teki | 9eb935a | 2019-07-16 17:27:30 +0530 | [diff] [blame] | 78 | const struct sdram_rk3399_ops *ops; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 79 | #endif |
| 80 | struct ram_info info; |
| 81 | struct rk3399_pmugrf_regs *pmugrf; |
| 82 | }; |
| 83 | |
Jagan Teki | 9eb935a | 2019-07-16 17:27:30 +0530 | [diff] [blame] | 84 | struct sdram_rk3399_ops { |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 85 | int (*data_training_first)(struct dram_info *dram, u32 channel, u8 rank, |
| 86 | struct rk3399_sdram_params *sdram); |
| 87 | int (*set_rate_index)(struct dram_info *dram, |
| 88 | struct rk3399_sdram_params *params); |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 89 | void (*modify_param)(const struct chan_info *chan, |
| 90 | struct rk3399_sdram_params *params); |
| 91 | struct rk3399_sdram_params * |
| 92 | (*get_phy_index_params)(u32 phy_fn, |
| 93 | struct rk3399_sdram_params *params); |
Jagan Teki | 9eb935a | 2019-07-16 17:27:30 +0530 | [diff] [blame] | 94 | }; |
| 95 | |
Kever Yang | 7f34784 | 2019-04-01 17:20:53 +0800 | [diff] [blame] | 96 | #if defined(CONFIG_TPL_BUILD) || \ |
| 97 | (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 98 | |
| 99 | struct rockchip_dmc_plat { |
| 100 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 101 | struct dtd_rockchip_rk3399_dmc dtplat; |
| 102 | #else |
| 103 | struct rk3399_sdram_params sdram_params; |
| 104 | #endif |
| 105 | struct regmap *map; |
| 106 | }; |
| 107 | |
Jagan Teki | e3619d1 | 2019-07-16 17:27:21 +0530 | [diff] [blame] | 108 | struct io_setting { |
| 109 | u32 mhz; |
| 110 | u32 mr5; |
| 111 | /* dram side */ |
| 112 | u32 dq_odt; |
| 113 | u32 ca_odt; |
| 114 | u32 pdds; |
| 115 | u32 dq_vref; |
| 116 | u32 ca_vref; |
| 117 | /* phy side */ |
| 118 | u32 rd_odt; |
| 119 | u32 wr_dq_drv; |
| 120 | u32 wr_ca_drv; |
| 121 | u32 wr_ckcs_drv; |
| 122 | u32 rd_odt_en; |
| 123 | u32 rd_vref; |
| 124 | } lpddr4_io_setting[] = { |
| 125 | { |
| 126 | 50 * MHz, |
| 127 | 0, |
| 128 | /* dram side */ |
| 129 | 0, /* dq_odt; */ |
| 130 | 0, /* ca_odt; */ |
| 131 | 6, /* pdds; */ |
| 132 | 0x72, /* dq_vref; */ |
| 133 | 0x72, /* ca_vref; */ |
| 134 | /* phy side */ |
| 135 | PHY_DRV_ODT_HI_Z, /* rd_odt; */ |
| 136 | PHY_DRV_ODT_40, /* wr_dq_drv; */ |
| 137 | PHY_DRV_ODT_40, /* wr_ca_drv; */ |
| 138 | PHY_DRV_ODT_40, /* wr_ckcs_drv; */ |
| 139 | 0, /* rd_odt_en;*/ |
| 140 | 41, /* rd_vref; (unit %, range 3.3% - 48.7%) */ |
| 141 | }, |
| 142 | { |
| 143 | 600 * MHz, |
| 144 | 0, |
| 145 | /* dram side */ |
| 146 | 1, /* dq_odt; */ |
| 147 | 0, /* ca_odt; */ |
| 148 | 6, /* pdds; */ |
| 149 | 0x72, /* dq_vref; */ |
| 150 | 0x72, /* ca_vref; */ |
| 151 | /* phy side */ |
| 152 | PHY_DRV_ODT_HI_Z, /* rd_odt; */ |
| 153 | PHY_DRV_ODT_48, /* wr_dq_drv; */ |
| 154 | PHY_DRV_ODT_40, /* wr_ca_drv; */ |
| 155 | PHY_DRV_ODT_40, /* wr_ckcs_drv; */ |
| 156 | 0, /* rd_odt_en; */ |
| 157 | 32, /* rd_vref; (unit %, range 3.3% - 48.7%) */ |
| 158 | }, |
| 159 | { |
Kever Yang | bc9b156 | 2019-11-15 11:04:51 +0800 | [diff] [blame] | 160 | 933 * MHz, |
Jagan Teki | e3619d1 | 2019-07-16 17:27:21 +0530 | [diff] [blame] | 161 | 0, |
| 162 | /* dram side */ |
| 163 | 1, /* dq_odt; */ |
| 164 | 0, /* ca_odt; */ |
Kever Yang | bc9b156 | 2019-11-15 11:04:51 +0800 | [diff] [blame] | 165 | 3, /* pdds; */ |
Jagan Teki | e3619d1 | 2019-07-16 17:27:21 +0530 | [diff] [blame] | 166 | 0x72, /* dq_vref; */ |
| 167 | 0x72, /* ca_vref; */ |
| 168 | /* phy side */ |
Kever Yang | bc9b156 | 2019-11-15 11:04:51 +0800 | [diff] [blame] | 169 | PHY_DRV_ODT_80, /* rd_odt; */ |
| 170 | PHY_DRV_ODT_40, /* wr_dq_drv; */ |
Jagan Teki | e3619d1 | 2019-07-16 17:27:21 +0530 | [diff] [blame] | 171 | PHY_DRV_ODT_40, /* wr_ca_drv; */ |
| 172 | PHY_DRV_ODT_40, /* wr_ckcs_drv; */ |
| 173 | 1, /* rd_odt_en; */ |
Kever Yang | bc9b156 | 2019-11-15 11:04:51 +0800 | [diff] [blame] | 174 | 20, /* rd_vref; (unit %, range 3.3% - 48.7%) */ |
Jagan Teki | e3619d1 | 2019-07-16 17:27:21 +0530 | [diff] [blame] | 175 | }, |
| 176 | { |
| 177 | 1066 * MHz, |
| 178 | 0, |
| 179 | /* dram side */ |
| 180 | 6, /* dq_odt; */ |
| 181 | 0, /* ca_odt; */ |
Kever Yang | bc9b156 | 2019-11-15 11:04:51 +0800 | [diff] [blame] | 182 | 3, /* pdds; */ |
Jagan Teki | e3619d1 | 2019-07-16 17:27:21 +0530 | [diff] [blame] | 183 | 0x10, /* dq_vref; */ |
| 184 | 0x72, /* ca_vref; */ |
| 185 | /* phy side */ |
Kever Yang | bc9b156 | 2019-11-15 11:04:51 +0800 | [diff] [blame] | 186 | PHY_DRV_ODT_80, /* rd_odt; */ |
Jagan Teki | e3619d1 | 2019-07-16 17:27:21 +0530 | [diff] [blame] | 187 | PHY_DRV_ODT_60, /* wr_dq_drv; */ |
| 188 | PHY_DRV_ODT_40, /* wr_ca_drv; */ |
| 189 | PHY_DRV_ODT_40, /* wr_ckcs_drv; */ |
| 190 | 1, /* rd_odt_en; */ |
Kever Yang | bc9b156 | 2019-11-15 11:04:51 +0800 | [diff] [blame] | 191 | 20, /* rd_vref; (unit %, range 3.3% - 48.7%) */ |
Jagan Teki | e3619d1 | 2019-07-16 17:27:21 +0530 | [diff] [blame] | 192 | }, |
| 193 | }; |
| 194 | |
Jagan Teki | d33056b | 2019-07-16 17:27:22 +0530 | [diff] [blame] | 195 | static struct io_setting * |
| 196 | lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5) |
| 197 | { |
| 198 | struct io_setting *io = NULL; |
| 199 | u32 n; |
| 200 | |
| 201 | for (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) { |
| 202 | io = &lpddr4_io_setting[n]; |
| 203 | |
| 204 | if (io->mr5 != 0) { |
| 205 | if (io->mhz >= params->base.ddr_freq && |
| 206 | io->mr5 == mr5) |
| 207 | break; |
| 208 | } else { |
| 209 | if (io->mhz >= params->base.ddr_freq) |
| 210 | break; |
| 211 | } |
| 212 | } |
| 213 | |
| 214 | return io; |
| 215 | } |
| 216 | |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 217 | static void *get_denali_ctl(const struct chan_info *chan, |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 218 | struct rk3399_sdram_params *params, bool reg) |
| 219 | { |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 220 | return reg ? &chan->pctl->denali_ctl : ¶ms->pctl_regs.denali_ctl; |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 221 | } |
| 222 | |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 223 | static void *get_denali_phy(const struct chan_info *chan, |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 224 | struct rk3399_sdram_params *params, bool reg) |
| 225 | { |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 226 | return reg ? &chan->publ->denali_phy : ¶ms->phy_regs.denali_phy; |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 227 | } |
| 228 | |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 229 | static void *get_ddrc0_con(struct dram_info *dram, u8 channel) |
| 230 | { |
YouMin Chen | cafbf9f | 2019-11-15 11:04:47 +0800 | [diff] [blame] | 231 | return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc1_con0; |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 232 | } |
| 233 | |
Jagan Teki | 783acfd | 2020-01-09 14:22:17 +0530 | [diff] [blame] | 234 | static void rkclk_ddr_reset(struct rockchip_cru *cru, u32 channel, u32 ctl, |
Jagan Teki | ce75cfb | 2019-07-15 23:58:43 +0530 | [diff] [blame] | 235 | u32 phy) |
| 236 | { |
| 237 | channel &= 0x1; |
| 238 | ctl &= 0x1; |
| 239 | phy &= 0x1; |
| 240 | writel(CRU_SFTRST_DDR_CTRL(channel, ctl) | |
| 241 | CRU_SFTRST_DDR_PHY(channel, phy), |
| 242 | &cru->softrst_con[4]); |
| 243 | } |
| 244 | |
Jagan Teki | 783acfd | 2020-01-09 14:22:17 +0530 | [diff] [blame] | 245 | static void phy_pctrl_reset(struct rockchip_cru *cru, u32 channel) |
Jagan Teki | ce75cfb | 2019-07-15 23:58:43 +0530 | [diff] [blame] | 246 | { |
| 247 | rkclk_ddr_reset(cru, channel, 1, 1); |
| 248 | udelay(10); |
| 249 | |
| 250 | rkclk_ddr_reset(cru, channel, 1, 0); |
| 251 | udelay(10); |
| 252 | |
| 253 | rkclk_ddr_reset(cru, channel, 0, 0); |
| 254 | udelay(10); |
| 255 | } |
| 256 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 257 | static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs, |
| 258 | u32 freq) |
| 259 | { |
| 260 | u32 *denali_phy = ddr_publ_regs->denali_phy; |
| 261 | |
| 262 | /* From IP spec, only freq small than 125 can enter dll bypass mode */ |
| 263 | if (freq <= 125) { |
| 264 | /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ |
| 265 | setbits_le32(&denali_phy[86], (0x3 << 2) << 8); |
| 266 | setbits_le32(&denali_phy[214], (0x3 << 2) << 8); |
| 267 | setbits_le32(&denali_phy[342], (0x3 << 2) << 8); |
| 268 | setbits_le32(&denali_phy[470], (0x3 << 2) << 8); |
| 269 | |
| 270 | /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ |
| 271 | setbits_le32(&denali_phy[547], (0x3 << 2) << 16); |
| 272 | setbits_le32(&denali_phy[675], (0x3 << 2) << 16); |
| 273 | setbits_le32(&denali_phy[803], (0x3 << 2) << 16); |
| 274 | } else { |
| 275 | /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ |
| 276 | clrbits_le32(&denali_phy[86], (0x3 << 2) << 8); |
| 277 | clrbits_le32(&denali_phy[214], (0x3 << 2) << 8); |
| 278 | clrbits_le32(&denali_phy[342], (0x3 << 2) << 8); |
| 279 | clrbits_le32(&denali_phy[470], (0x3 << 2) << 8); |
| 280 | |
| 281 | /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ |
| 282 | clrbits_le32(&denali_phy[547], (0x3 << 2) << 16); |
| 283 | clrbits_le32(&denali_phy[675], (0x3 << 2) << 16); |
| 284 | clrbits_le32(&denali_phy[803], (0x3 << 2) << 16); |
| 285 | } |
| 286 | } |
| 287 | |
| 288 | static void set_memory_map(const struct chan_info *chan, u32 channel, |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 289 | const struct rk3399_sdram_params *params) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 290 | { |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 291 | const struct rk3399_sdram_channel *sdram_ch = ¶ms->ch[channel]; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 292 | u32 *denali_ctl = chan->pctl->denali_ctl; |
| 293 | u32 *denali_pi = chan->pi->denali_pi; |
| 294 | u32 cs_map; |
| 295 | u32 reduc; |
| 296 | u32 row; |
| 297 | |
| 298 | /* Get row number from ddrconfig setting */ |
Jagan Teki | 97867c8 | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 299 | if (sdram_ch->cap_info.ddrconfig < 2 || |
| 300 | sdram_ch->cap_info.ddrconfig == 4) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 301 | row = 16; |
YouMin Chen | 79f4d91 | 2019-11-15 11:04:53 +0800 | [diff] [blame] | 302 | else if (sdram_ch->cap_info.ddrconfig == 3 || |
| 303 | sdram_ch->cap_info.ddrconfig == 5) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 304 | row = 14; |
| 305 | else |
| 306 | row = 15; |
| 307 | |
Jagan Teki | 97867c8 | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 308 | cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1; |
| 309 | reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 310 | |
| 311 | /* Set the dram configuration to ctrl */ |
Jagan Teki | 97867c8 | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 312 | clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col)); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 313 | clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), |
Jagan Teki | 97867c8 | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 314 | ((3 - sdram_ch->cap_info.bk) << 16) | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 315 | ((16 - row) << 24)); |
| 316 | |
| 317 | clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), |
| 318 | cs_map | (reduc << 16)); |
| 319 | |
| 320 | /* PI_199 PI_COL_DIFF:RW:0:4 */ |
Jagan Teki | 97867c8 | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 321 | clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col)); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 322 | |
| 323 | /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ |
| 324 | clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), |
Jagan Teki | 97867c8 | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 325 | ((3 - sdram_ch->cap_info.bk) << 16) | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 326 | ((16 - row) << 24)); |
Jagan Teki | 9337cb3 | 2019-07-16 17:27:18 +0530 | [diff] [blame] | 327 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 328 | if (params->base.dramtype == LPDDR4) { |
Jagan Teki | 9337cb3 | 2019-07-16 17:27:18 +0530 | [diff] [blame] | 329 | if (cs_map == 1) |
| 330 | cs_map = 0x5; |
| 331 | else if (cs_map == 2) |
| 332 | cs_map = 0xa; |
| 333 | else |
| 334 | cs_map = 0xF; |
| 335 | } |
| 336 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 337 | /* PI_41 PI_CS_MAP:RW:24:4 */ |
| 338 | clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); |
Jagan Teki | 97867c8 | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 339 | if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 340 | writel(0x2EC7FFFF, &denali_pi[34]); |
| 341 | } |
| 342 | |
Thomas Hebb | d8105ab | 2019-12-20 12:28:15 -0800 | [diff] [blame] | 343 | static int phy_io_config(u32 *denali_phy, u32 *denali_ctl, |
Jagan Teki | 2dd3efc | 2019-07-16 17:27:26 +0530 | [diff] [blame] | 344 | const struct rk3399_sdram_params *params, u32 mr5) |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 345 | { |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 346 | u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac; |
| 347 | u32 mode_sel; |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 348 | u32 speed; |
YouMin Chen | 79f4d91 | 2019-11-15 11:04:53 +0800 | [diff] [blame] | 349 | u32 reg_value; |
| 350 | u32 ds_value, odt_value; |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 351 | |
Jagan Teki | 59a9a57 | 2019-07-16 17:27:27 +0530 | [diff] [blame] | 352 | /* vref setting & mode setting */ |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 353 | if (params->base.dramtype == LPDDR4) { |
Jagan Teki | 2dd3efc | 2019-07-16 17:27:26 +0530 | [diff] [blame] | 354 | struct io_setting *io = lpddr4_get_io_settings(params, mr5); |
| 355 | u32 rd_vref = io->rd_vref * 1000; |
| 356 | |
| 357 | if (rd_vref < 36700) { |
| 358 | /* MODE_LV[2:0] = LPDDR4 (Range 2)*/ |
| 359 | vref_mode_dq = 0x7; |
Jagan Teki | 59a9a57 | 2019-07-16 17:27:27 +0530 | [diff] [blame] | 360 | /* MODE[2:0]= LPDDR4 Range 2(0.4*VDDQ) */ |
| 361 | mode_sel = 0x5; |
Jagan Teki | 2dd3efc | 2019-07-16 17:27:26 +0530 | [diff] [blame] | 362 | vref_value_dq = (rd_vref - 3300) / 521; |
| 363 | } else { |
| 364 | /* MODE_LV[2:0] = LPDDR4 (Range 1)*/ |
| 365 | vref_mode_dq = 0x6; |
Jagan Teki | 59a9a57 | 2019-07-16 17:27:27 +0530 | [diff] [blame] | 366 | /* MODE[2:0]= LPDDR4 Range 1(0.33*VDDQ) */ |
| 367 | mode_sel = 0x4; |
Jagan Teki | 2dd3efc | 2019-07-16 17:27:26 +0530 | [diff] [blame] | 368 | vref_value_dq = (rd_vref - 15300) / 521; |
| 369 | } |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 370 | vref_mode_ac = 0x6; |
Jagan Teki | a5b0719 | 2019-07-16 17:27:28 +0530 | [diff] [blame] | 371 | /* VDDQ/3/2=16.8% */ |
| 372 | vref_value_ac = 0x3; |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 373 | } else if (params->base.dramtype == LPDDR3) { |
| 374 | if (params->base.odt == 1) { |
| 375 | vref_mode_dq = 0x5; /* LPDDR3 ODT */ |
YouMin Chen | 79f4d91 | 2019-11-15 11:04:53 +0800 | [diff] [blame] | 376 | ds_value = readl(&denali_ctl[138]) & 0xf; |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 377 | odt_value = (readl(&denali_phy[6]) >> 4) & 0xf; |
YouMin Chen | 79f4d91 | 2019-11-15 11:04:53 +0800 | [diff] [blame] | 378 | if (ds_value == LPDDR3_DS_48) { |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 379 | switch (odt_value) { |
| 380 | case PHY_DRV_ODT_240: |
YouMin Chen | 79f4d91 | 2019-11-15 11:04:53 +0800 | [diff] [blame] | 381 | vref_value_dq = 0x1B; |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 382 | break; |
| 383 | case PHY_DRV_ODT_120: |
| 384 | vref_value_dq = 0x26; |
| 385 | break; |
| 386 | case PHY_DRV_ODT_60: |
| 387 | vref_value_dq = 0x36; |
| 388 | break; |
| 389 | default: |
| 390 | debug("Invalid ODT value.\n"); |
| 391 | return -EINVAL; |
| 392 | } |
YouMin Chen | 79f4d91 | 2019-11-15 11:04:53 +0800 | [diff] [blame] | 393 | } else if (ds_value == LPDDR3_DS_40) { |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 394 | switch (odt_value) { |
| 395 | case PHY_DRV_ODT_240: |
| 396 | vref_value_dq = 0x19; |
| 397 | break; |
| 398 | case PHY_DRV_ODT_120: |
| 399 | vref_value_dq = 0x23; |
| 400 | break; |
| 401 | case PHY_DRV_ODT_60: |
| 402 | vref_value_dq = 0x31; |
| 403 | break; |
| 404 | default: |
| 405 | debug("Invalid ODT value.\n"); |
| 406 | return -EINVAL; |
| 407 | } |
YouMin Chen | 79f4d91 | 2019-11-15 11:04:53 +0800 | [diff] [blame] | 408 | } else if (ds_value == LPDDR3_DS_34) { |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 409 | switch (odt_value) { |
| 410 | case PHY_DRV_ODT_240: |
| 411 | vref_value_dq = 0x17; |
| 412 | break; |
| 413 | case PHY_DRV_ODT_120: |
| 414 | vref_value_dq = 0x20; |
| 415 | break; |
| 416 | case PHY_DRV_ODT_60: |
| 417 | vref_value_dq = 0x2e; |
| 418 | break; |
| 419 | default: |
| 420 | debug("Invalid ODT value.\n"); |
| 421 | return -EINVAL; |
| 422 | } |
| 423 | } else { |
| 424 | debug("Invalid DRV value.\n"); |
| 425 | return -EINVAL; |
| 426 | } |
| 427 | } else { |
| 428 | vref_mode_dq = 0x2; /* LPDDR3 */ |
| 429 | vref_value_dq = 0x1f; |
| 430 | } |
| 431 | vref_mode_ac = 0x2; |
| 432 | vref_value_ac = 0x1f; |
Jagan Teki | 213b9ba | 2019-07-16 17:27:11 +0530 | [diff] [blame] | 433 | mode_sel = 0x0; |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 434 | } else if (params->base.dramtype == DDR3) { |
| 435 | /* DDR3L */ |
| 436 | vref_mode_dq = 0x1; |
| 437 | vref_value_dq = 0x1f; |
| 438 | vref_mode_ac = 0x1; |
| 439 | vref_value_ac = 0x1f; |
Jagan Teki | 213b9ba | 2019-07-16 17:27:11 +0530 | [diff] [blame] | 440 | mode_sel = 0x1; |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 441 | } else { |
| 442 | debug("Unknown DRAM type.\n"); |
| 443 | return -EINVAL; |
| 444 | } |
| 445 | |
| 446 | reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq; |
| 447 | |
| 448 | /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */ |
| 449 | clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8); |
| 450 | /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */ |
| 451 | clrsetbits_le32(&denali_phy[914], 0xfff, reg_value); |
| 452 | /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */ |
| 453 | clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16); |
| 454 | /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */ |
| 455 | clrsetbits_le32(&denali_phy[915], 0xfff, reg_value); |
| 456 | |
| 457 | reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac; |
| 458 | |
| 459 | /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ |
| 460 | clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); |
| 461 | |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 462 | /* PHY_924 PHY_PAD_FDBK_DRIVE */ |
| 463 | clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15); |
| 464 | /* PHY_926 PHY_PAD_DATA_DRIVE */ |
| 465 | clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6); |
| 466 | /* PHY_927 PHY_PAD_DQS_DRIVE */ |
| 467 | clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6); |
| 468 | /* PHY_928 PHY_PAD_ADDR_DRIVE */ |
| 469 | clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14); |
| 470 | /* PHY_929 PHY_PAD_CLK_DRIVE */ |
| 471 | clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14); |
| 472 | /* PHY_935 PHY_PAD_CKE_DRIVE */ |
| 473 | clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14); |
| 474 | /* PHY_937 PHY_PAD_RST_DRIVE */ |
| 475 | clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14); |
| 476 | /* PHY_939 PHY_PAD_CS_DRIVE */ |
| 477 | clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); |
| 478 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 479 | if (params->base.dramtype == LPDDR4) { |
Jagan Teki | 5d15217 | 2019-07-16 17:27:15 +0530 | [diff] [blame] | 480 | /* BOOSTP_EN & BOOSTN_EN */ |
| 481 | reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN); |
| 482 | /* PHY_925 PHY_PAD_FDBK_DRIVE2 */ |
| 483 | clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8); |
| 484 | /* PHY_926 PHY_PAD_DATA_DRIVE */ |
| 485 | clrsetbits_le32(&denali_phy[926], 0xff << 12, reg_value << 12); |
| 486 | /* PHY_927 PHY_PAD_DQS_DRIVE */ |
| 487 | clrsetbits_le32(&denali_phy[927], 0xff << 14, reg_value << 14); |
| 488 | /* PHY_928 PHY_PAD_ADDR_DRIVE */ |
| 489 | clrsetbits_le32(&denali_phy[928], 0xff << 20, reg_value << 20); |
| 490 | /* PHY_929 PHY_PAD_CLK_DRIVE */ |
| 491 | clrsetbits_le32(&denali_phy[929], 0xff << 22, reg_value << 22); |
| 492 | /* PHY_935 PHY_PAD_CKE_DRIVE */ |
| 493 | clrsetbits_le32(&denali_phy[935], 0xff << 20, reg_value << 20); |
| 494 | /* PHY_937 PHY_PAD_RST_DRIVE */ |
| 495 | clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20); |
| 496 | /* PHY_939 PHY_PAD_CS_DRIVE */ |
| 497 | clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20); |
Jagan Teki | d868184 | 2019-07-16 17:27:16 +0530 | [diff] [blame] | 498 | |
| 499 | /* SLEWP_EN & SLEWN_EN */ |
| 500 | reg_value = ((PHY_SLEWP_EN << 3) | PHY_SLEWN_EN); |
| 501 | /* PHY_924 PHY_PAD_FDBK_DRIVE */ |
| 502 | clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8); |
| 503 | /* PHY_926 PHY_PAD_DATA_DRIVE */ |
| 504 | clrsetbits_le32(&denali_phy[926], 0x3f, reg_value); |
| 505 | /* PHY_927 PHY_PAD_DQS_DRIVE */ |
| 506 | clrsetbits_le32(&denali_phy[927], 0x3f, reg_value); |
| 507 | /* PHY_928 PHY_PAD_ADDR_DRIVE */ |
| 508 | clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8); |
| 509 | /* PHY_929 PHY_PAD_CLK_DRIVE */ |
| 510 | clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8); |
| 511 | /* PHY_935 PHY_PAD_CKE_DRIVE */ |
| 512 | clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8); |
| 513 | /* PHY_937 PHY_PAD_RST_DRIVE */ |
| 514 | clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8); |
| 515 | /* PHY_939 PHY_PAD_CS_DRIVE */ |
| 516 | clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8); |
Jagan Teki | 5d15217 | 2019-07-16 17:27:15 +0530 | [diff] [blame] | 517 | } |
| 518 | |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 519 | /* speed setting */ |
YouMin Chen | 79f4d91 | 2019-11-15 11:04:53 +0800 | [diff] [blame] | 520 | speed = 0x2; |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 521 | |
| 522 | /* PHY_924 PHY_PAD_FDBK_DRIVE */ |
| 523 | clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); |
| 524 | /* PHY_926 PHY_PAD_DATA_DRIVE */ |
| 525 | clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); |
| 526 | /* PHY_927 PHY_PAD_DQS_DRIVE */ |
| 527 | clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); |
| 528 | /* PHY_928 PHY_PAD_ADDR_DRIVE */ |
| 529 | clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); |
| 530 | /* PHY_929 PHY_PAD_CLK_DRIVE */ |
| 531 | clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); |
| 532 | /* PHY_935 PHY_PAD_CKE_DRIVE */ |
| 533 | clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); |
| 534 | /* PHY_937 PHY_PAD_RST_DRIVE */ |
| 535 | clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); |
| 536 | /* PHY_939 PHY_PAD_CS_DRIVE */ |
| 537 | clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); |
| 538 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 539 | if (params->base.dramtype == LPDDR4) { |
Jagan Teki | 65535a2 | 2019-07-16 17:27:17 +0530 | [diff] [blame] | 540 | /* RX_CM_INPUT */ |
| 541 | reg_value = PHY_RX_CM_INPUT; |
| 542 | /* PHY_924 PHY_PAD_FDBK_DRIVE */ |
| 543 | clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14); |
| 544 | /* PHY_926 PHY_PAD_DATA_DRIVE */ |
| 545 | clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11); |
| 546 | /* PHY_927 PHY_PAD_DQS_DRIVE */ |
| 547 | clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13); |
| 548 | /* PHY_928 PHY_PAD_ADDR_DRIVE */ |
| 549 | clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19); |
| 550 | /* PHY_929 PHY_PAD_CLK_DRIVE */ |
| 551 | clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21); |
| 552 | /* PHY_935 PHY_PAD_CKE_DRIVE */ |
| 553 | clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19); |
| 554 | /* PHY_937 PHY_PAD_RST_DRIVE */ |
| 555 | clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19); |
| 556 | /* PHY_939 PHY_PAD_CS_DRIVE */ |
| 557 | clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19); |
| 558 | } |
| 559 | |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 560 | return 0; |
| 561 | } |
| 562 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 563 | static void set_ds_odt(const struct chan_info *chan, |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 564 | struct rk3399_sdram_params *params, |
| 565 | bool ctl_phy_reg, u32 mr5) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 566 | { |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 567 | u32 *denali_phy = get_denali_phy(chan, params, ctl_phy_reg); |
| 568 | u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 569 | u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; |
Jagan Teki | 5c3251f | 2019-07-15 23:51:04 +0530 | [diff] [blame] | 570 | u32 tsel_idle_select_p, tsel_rd_select_p; |
| 571 | u32 tsel_idle_select_n, tsel_rd_select_n; |
| 572 | u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p; |
| 573 | u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n; |
Jagan Teki | c7ffdb7 | 2019-07-16 17:27:23 +0530 | [diff] [blame] | 574 | u32 tsel_ckcs_select_p, tsel_ckcs_select_n; |
Jagan Teki | d33056b | 2019-07-16 17:27:22 +0530 | [diff] [blame] | 575 | struct io_setting *io = NULL; |
Jagan Teki | 0cb3112 | 2019-07-16 17:27:24 +0530 | [diff] [blame] | 576 | u32 soc_odt = 0; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 577 | u32 reg_value; |
| 578 | |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 579 | if (params->base.dramtype == LPDDR4) { |
Jagan Teki | d33056b | 2019-07-16 17:27:22 +0530 | [diff] [blame] | 580 | io = lpddr4_get_io_settings(params, mr5); |
| 581 | |
Jagan Teki | f676c7c | 2019-07-15 23:50:56 +0530 | [diff] [blame] | 582 | tsel_rd_select_p = PHY_DRV_ODT_HI_Z; |
Jagan Teki | d33056b | 2019-07-16 17:27:22 +0530 | [diff] [blame] | 583 | tsel_rd_select_n = io->rd_odt; |
Jagan Teki | 5c3251f | 2019-07-15 23:51:04 +0530 | [diff] [blame] | 584 | |
Jagan Teki | f676c7c | 2019-07-15 23:50:56 +0530 | [diff] [blame] | 585 | tsel_idle_select_p = PHY_DRV_ODT_HI_Z; |
Kever Yang | bc9b156 | 2019-11-15 11:04:51 +0800 | [diff] [blame] | 586 | tsel_idle_select_n = PHY_DRV_ODT_HI_Z; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 587 | |
Jagan Teki | d33056b | 2019-07-16 17:27:22 +0530 | [diff] [blame] | 588 | tsel_wr_select_dq_p = io->wr_dq_drv; |
Kever Yang | bc9b156 | 2019-11-15 11:04:51 +0800 | [diff] [blame] | 589 | tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; |
Jagan Teki | 5c3251f | 2019-07-15 23:51:04 +0530 | [diff] [blame] | 590 | |
Jagan Teki | d33056b | 2019-07-16 17:27:22 +0530 | [diff] [blame] | 591 | tsel_wr_select_ca_p = io->wr_ca_drv; |
Kever Yang | bc9b156 | 2019-11-15 11:04:51 +0800 | [diff] [blame] | 592 | tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; |
Jagan Teki | c7ffdb7 | 2019-07-16 17:27:23 +0530 | [diff] [blame] | 593 | |
| 594 | tsel_ckcs_select_p = io->wr_ckcs_drv; |
| 595 | tsel_ckcs_select_n = PHY_DRV_ODT_34_3; |
Kever Yang | bc9b156 | 2019-11-15 11:04:51 +0800 | [diff] [blame] | 596 | |
Jagan Teki | 0cb3112 | 2019-07-16 17:27:24 +0530 | [diff] [blame] | 597 | switch (tsel_rd_select_n) { |
| 598 | case PHY_DRV_ODT_240: |
| 599 | soc_odt = 1; |
| 600 | break; |
| 601 | case PHY_DRV_ODT_120: |
| 602 | soc_odt = 2; |
| 603 | break; |
| 604 | case PHY_DRV_ODT_80: |
| 605 | soc_odt = 3; |
| 606 | break; |
| 607 | case PHY_DRV_ODT_60: |
| 608 | soc_odt = 4; |
| 609 | break; |
| 610 | case PHY_DRV_ODT_48: |
| 611 | soc_odt = 5; |
| 612 | break; |
| 613 | case PHY_DRV_ODT_40: |
| 614 | soc_odt = 6; |
| 615 | break; |
| 616 | case PHY_DRV_ODT_34_3: |
| 617 | soc_odt = 6; |
| 618 | printf("%s: Unable to support LPDDR4 MR22 Soc ODT\n", |
| 619 | __func__); |
| 620 | break; |
| 621 | case PHY_DRV_ODT_HI_Z: |
| 622 | default: |
| 623 | soc_odt = 0; |
| 624 | break; |
| 625 | } |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 626 | } else if (params->base.dramtype == LPDDR3) { |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 627 | tsel_rd_select_p = PHY_DRV_ODT_240; |
Jagan Teki | 5c3251f | 2019-07-15 23:51:04 +0530 | [diff] [blame] | 628 | tsel_rd_select_n = PHY_DRV_ODT_HI_Z; |
| 629 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 630 | tsel_idle_select_p = PHY_DRV_ODT_240; |
Jagan Teki | 5c3251f | 2019-07-15 23:51:04 +0530 | [diff] [blame] | 631 | tsel_idle_select_n = PHY_DRV_ODT_HI_Z; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 632 | |
Jagan Teki | 5c3251f | 2019-07-15 23:51:04 +0530 | [diff] [blame] | 633 | tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; |
Jagan Teki | 3666714 | 2019-07-15 23:51:00 +0530 | [diff] [blame] | 634 | tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; |
Jagan Teki | 5c3251f | 2019-07-15 23:51:04 +0530 | [diff] [blame] | 635 | |
Kever Yang | bc9b156 | 2019-11-15 11:04:51 +0800 | [diff] [blame] | 636 | tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; |
| 637 | tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; |
Jagan Teki | c7ffdb7 | 2019-07-16 17:27:23 +0530 | [diff] [blame] | 638 | |
| 639 | tsel_ckcs_select_p = PHY_DRV_ODT_34_3; |
| 640 | tsel_ckcs_select_n = PHY_DRV_ODT_34_3; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 641 | } else { |
| 642 | tsel_rd_select_p = PHY_DRV_ODT_240; |
Jagan Teki | 5c3251f | 2019-07-15 23:51:04 +0530 | [diff] [blame] | 643 | tsel_rd_select_n = PHY_DRV_ODT_240; |
| 644 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 645 | tsel_idle_select_p = PHY_DRV_ODT_240; |
Jagan Teki | 5c3251f | 2019-07-15 23:51:04 +0530 | [diff] [blame] | 646 | tsel_idle_select_n = PHY_DRV_ODT_240; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 647 | |
Jagan Teki | 5c3251f | 2019-07-15 23:51:04 +0530 | [diff] [blame] | 648 | tsel_wr_select_dq_p = PHY_DRV_ODT_34_3; |
Jagan Teki | 3666714 | 2019-07-15 23:51:00 +0530 | [diff] [blame] | 649 | tsel_wr_select_dq_n = PHY_DRV_ODT_34_3; |
Jagan Teki | 5c3251f | 2019-07-15 23:51:04 +0530 | [diff] [blame] | 650 | |
| 651 | tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; |
Jagan Teki | 0fd5efb | 2019-07-15 23:51:02 +0530 | [diff] [blame] | 652 | tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; |
Jagan Teki | c7ffdb7 | 2019-07-16 17:27:23 +0530 | [diff] [blame] | 653 | |
| 654 | tsel_ckcs_select_p = PHY_DRV_ODT_34_3; |
| 655 | tsel_ckcs_select_n = PHY_DRV_ODT_34_3; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 656 | } |
| 657 | |
Jagan Teki | b958417 | 2019-07-16 17:27:25 +0530 | [diff] [blame] | 658 | if (params->base.odt == 1) { |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 659 | tsel_rd_en = 1; |
Jagan Teki | b958417 | 2019-07-16 17:27:25 +0530 | [diff] [blame] | 660 | |
| 661 | if (params->base.dramtype == LPDDR4) |
| 662 | tsel_rd_en = io->rd_odt_en; |
| 663 | } else { |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 664 | tsel_rd_en = 0; |
Jagan Teki | b958417 | 2019-07-16 17:27:25 +0530 | [diff] [blame] | 665 | } |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 666 | |
| 667 | tsel_wr_en = 0; |
| 668 | tsel_idle_en = 0; |
| 669 | |
Jagan Teki | 0cb3112 | 2019-07-16 17:27:24 +0530 | [diff] [blame] | 670 | /* F0_0 */ |
| 671 | clrsetbits_le32(&denali_ctl[145], 0xFF << 16, |
| 672 | (soc_odt | (CS0_MR22_VAL << 3)) << 16); |
| 673 | /* F2_0, F1_0 */ |
| 674 | clrsetbits_le32(&denali_ctl[146], 0xFF00FF, |
| 675 | ((soc_odt | (CS0_MR22_VAL << 3)) << 16) | |
| 676 | (soc_odt | (CS0_MR22_VAL << 3))); |
| 677 | /* F0_1 */ |
| 678 | clrsetbits_le32(&denali_ctl[159], 0xFF << 16, |
| 679 | (soc_odt | (CS1_MR22_VAL << 3)) << 16); |
| 680 | /* F2_1, F1_1 */ |
| 681 | clrsetbits_le32(&denali_ctl[160], 0xFF00FF, |
| 682 | ((soc_odt | (CS1_MR22_VAL << 3)) << 16) | |
| 683 | (soc_odt | (CS1_MR22_VAL << 3))); |
| 684 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 685 | /* |
| 686 | * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0 |
| 687 | * sets termination values for read/idle cycles and drive strength |
| 688 | * for write cycles for DQ/DM |
| 689 | */ |
| 690 | reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | |
Jagan Teki | b3b3439 | 2019-07-15 23:51:01 +0530 | [diff] [blame] | 691 | (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 692 | (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); |
| 693 | clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); |
| 694 | clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); |
| 695 | clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value); |
| 696 | clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value); |
| 697 | |
| 698 | /* |
| 699 | * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0 |
| 700 | * sets termination values for read/idle cycles and drive strength |
| 701 | * for write cycles for DQS |
| 702 | */ |
| 703 | clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value); |
| 704 | clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value); |
| 705 | clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value); |
| 706 | clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); |
| 707 | |
| 708 | /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ |
Jagan Teki | 7caa3e9 | 2019-07-15 23:51:03 +0530 | [diff] [blame] | 709 | reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4); |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 710 | if (params->base.dramtype == LPDDR4) { |
Jagan Teki | 539ffed | 2019-07-16 17:27:19 +0530 | [diff] [blame] | 711 | /* LPDDR4 these register read always return 0, so |
| 712 | * can not use clrsetbits_le32(), need to write32 |
| 713 | */ |
| 714 | writel((0x300 << 8) | reg_value, &denali_phy[544]); |
| 715 | writel((0x300 << 8) | reg_value, &denali_phy[672]); |
| 716 | writel((0x300 << 8) | reg_value, &denali_phy[800]); |
| 717 | } else { |
| 718 | clrsetbits_le32(&denali_phy[544], 0xff, reg_value); |
| 719 | clrsetbits_le32(&denali_phy[672], 0xff, reg_value); |
| 720 | clrsetbits_le32(&denali_phy[800], 0xff, reg_value); |
| 721 | } |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 722 | |
| 723 | /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ |
| 724 | clrsetbits_le32(&denali_phy[928], 0xff, reg_value); |
| 725 | |
| 726 | /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 727 | if (!ctl_phy_reg) |
| 728 | clrsetbits_le32(&denali_phy[937], 0xff, reg_value); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 729 | |
| 730 | /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */ |
| 731 | clrsetbits_le32(&denali_phy[935], 0xff, reg_value); |
| 732 | |
| 733 | /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ |
Jagan Teki | c7ffdb7 | 2019-07-16 17:27:23 +0530 | [diff] [blame] | 734 | clrsetbits_le32(&denali_phy[939], 0xff, |
| 735 | tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4)); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 736 | |
| 737 | /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ |
Jagan Teki | c7ffdb7 | 2019-07-16 17:27:23 +0530 | [diff] [blame] | 738 | clrsetbits_le32(&denali_phy[929], 0xff, |
| 739 | tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4)); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 740 | |
| 741 | /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ |
| 742 | clrsetbits_le32(&denali_phy[924], 0xff, |
YouMin Chen | 79f4d91 | 2019-11-15 11:04:53 +0800 | [diff] [blame] | 743 | tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 4)); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 744 | clrsetbits_le32(&denali_phy[925], 0xff, |
YouMin Chen | 79f4d91 | 2019-11-15 11:04:53 +0800 | [diff] [blame] | 745 | tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4)); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 746 | |
| 747 | /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */ |
| 748 | reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) |
| 749 | << 16; |
| 750 | clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value); |
| 751 | clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value); |
| 752 | clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value); |
| 753 | clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value); |
| 754 | |
| 755 | /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */ |
| 756 | reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) |
| 757 | << 24; |
| 758 | clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value); |
| 759 | clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value); |
| 760 | clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value); |
| 761 | clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value); |
| 762 | |
| 763 | /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */ |
| 764 | reg_value = tsel_wr_en << 8; |
| 765 | clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value); |
| 766 | clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value); |
| 767 | clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value); |
| 768 | |
| 769 | /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */ |
| 770 | reg_value = tsel_wr_en << 17; |
| 771 | clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value); |
| 772 | /* |
| 773 | * pad_rst/cke/cs/clk_term tsel 1bits |
| 774 | * DENALI_PHY_938/936/940/934 offset_17 |
| 775 | */ |
| 776 | clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value); |
| 777 | clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value); |
| 778 | clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value); |
| 779 | clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value); |
| 780 | |
| 781 | /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ |
| 782 | clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value); |
Jagan Teki | b5d4663 | 2019-07-16 17:27:07 +0530 | [diff] [blame] | 783 | |
Thomas Hebb | d8105ab | 2019-12-20 12:28:15 -0800 | [diff] [blame] | 784 | phy_io_config(denali_phy, denali_ctl, params, mr5); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 785 | } |
| 786 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 787 | static void pctl_start(struct dram_info *dram, |
| 788 | struct rk3399_sdram_params *params, |
| 789 | u32 channel_mask) |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 790 | { |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 791 | const struct chan_info *chan_0 = &dram->chan[0]; |
| 792 | const struct chan_info *chan_1 = &dram->chan[1]; |
| 793 | |
| 794 | u32 *denali_ctl_0 = chan_0->pctl->denali_ctl; |
| 795 | u32 *denali_phy_0 = chan_0->publ->denali_phy; |
| 796 | u32 *ddrc0_con_0 = get_ddrc0_con(dram, 0); |
| 797 | u32 *denali_ctl_1 = chan_1->pctl->denali_ctl; |
| 798 | u32 *denali_phy_1 = chan_1->publ->denali_phy; |
| 799 | u32 *ddrc1_con_0 = get_ddrc0_con(dram, 1); |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 800 | u32 count = 0; |
| 801 | u32 byte, tmp; |
| 802 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 803 | /* PHY_DLL_RST_EN */ |
| 804 | if (channel_mask & 1) { |
| 805 | writel(0x01000000, &ddrc0_con_0); |
| 806 | clrsetbits_le32(&denali_phy_0[957], 0x3 << 24, 0x2 << 24); |
| 807 | } |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 808 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 809 | if (channel_mask & 1) { |
| 810 | count = 0; |
| 811 | while (!(readl(&denali_ctl_0[203]) & (1 << 3))) { |
| 812 | if (count > 1000) { |
| 813 | printf("%s: Failed to init pctl channel 0\n", |
| 814 | __func__); |
| 815 | while (1) |
| 816 | ; |
| 817 | } |
| 818 | udelay(1); |
| 819 | count++; |
| 820 | } |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 821 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 822 | writel(0x01000100, &ddrc0_con_0); |
| 823 | for (byte = 0; byte < 4; byte++) { |
| 824 | tmp = 0x820; |
| 825 | writel((tmp << 16) | tmp, |
| 826 | &denali_phy_0[53 + (128 * byte)]); |
| 827 | writel((tmp << 16) | tmp, |
| 828 | &denali_phy_0[54 + (128 * byte)]); |
| 829 | writel((tmp << 16) | tmp, |
| 830 | &denali_phy_0[55 + (128 * byte)]); |
| 831 | writel((tmp << 16) | tmp, |
| 832 | &denali_phy_0[56 + (128 * byte)]); |
| 833 | writel((tmp << 16) | tmp, |
| 834 | &denali_phy_0[57 + (128 * byte)]); |
| 835 | clrsetbits_le32(&denali_phy_0[58 + (128 * byte)], |
| 836 | 0xffff, tmp); |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 837 | } |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 838 | clrsetbits_le32(&denali_ctl_0[68], PWRUP_SREFRESH_EXIT, |
| 839 | dram->pwrup_srefresh_exit[0]); |
| 840 | } |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 841 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 842 | if (channel_mask & 2) { |
| 843 | writel(0x01000000, &ddrc1_con_0); |
| 844 | clrsetbits_le32(&denali_phy_1[957], 0x3 << 24, 0x2 << 24); |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 845 | } |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 846 | if (channel_mask & 2) { |
| 847 | count = 0; |
| 848 | while (!(readl(&denali_ctl_1[203]) & (1 << 3))) { |
| 849 | if (count > 1000) { |
| 850 | printf("%s: Failed to init pctl channel 1\n", |
| 851 | __func__); |
| 852 | while (1) |
| 853 | ; |
| 854 | } |
| 855 | udelay(1); |
| 856 | count++; |
| 857 | } |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 858 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 859 | writel(0x01000100, &ddrc1_con_0); |
| 860 | for (byte = 0; byte < 4; byte++) { |
| 861 | tmp = 0x820; |
| 862 | writel((tmp << 16) | tmp, |
| 863 | &denali_phy_1[53 + (128 * byte)]); |
| 864 | writel((tmp << 16) | tmp, |
| 865 | &denali_phy_1[54 + (128 * byte)]); |
| 866 | writel((tmp << 16) | tmp, |
| 867 | &denali_phy_1[55 + (128 * byte)]); |
| 868 | writel((tmp << 16) | tmp, |
| 869 | &denali_phy_1[56 + (128 * byte)]); |
| 870 | writel((tmp << 16) | tmp, |
| 871 | &denali_phy_1[57 + (128 * byte)]); |
| 872 | clrsetbits_le32(&denali_phy_1[58 + (128 * byte)], |
| 873 | 0xffff, tmp); |
| 874 | } |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 875 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 876 | clrsetbits_le32(&denali_ctl_1[68], PWRUP_SREFRESH_EXIT, |
| 877 | dram->pwrup_srefresh_exit[1]); |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 878 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 879 | /* |
| 880 | * restore channel 1 RESET original setting |
| 881 | * to avoid 240ohm too weak to prevent ESD test |
| 882 | */ |
| 883 | if (params->base.dramtype == LPDDR4) |
| 884 | clrsetbits_le32(&denali_phy_1[937], 0xff, |
| 885 | params->phy_regs.denali_phy[937] & |
| 886 | 0xFF); |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 887 | } |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 888 | } |
| 889 | |
Jagan Teki | 4ef5c01 | 2019-07-15 23:58:44 +0530 | [diff] [blame] | 890 | static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, |
Jagan Teki | d33056b | 2019-07-16 17:27:22 +0530 | [diff] [blame] | 891 | u32 channel, struct rk3399_sdram_params *params) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 892 | { |
| 893 | u32 *denali_ctl = chan->pctl->denali_ctl; |
| 894 | u32 *denali_pi = chan->pi->denali_pi; |
| 895 | u32 *denali_phy = chan->publ->denali_phy; |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 896 | const u32 *params_ctl = params->pctl_regs.denali_ctl; |
| 897 | const u32 *params_phy = params->phy_regs.denali_phy; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 898 | u32 tmp, tmp1, tmp2; |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 899 | struct rk3399_sdram_params *params_cfg; |
| 900 | u32 byte; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 901 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 902 | dram->ops->modify_param(chan, params); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 903 | /* |
| 904 | * work around controller bug: |
| 905 | * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed |
| 906 | */ |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 907 | sdram_copy_to_reg(&denali_ctl[1], ¶ms_ctl[1], |
| 908 | sizeof(struct rk3399_ddr_pctl_regs) - 4); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 909 | writel(params_ctl[0], &denali_ctl[0]); |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 910 | |
Jagan Teki | cc9da9a | 2019-07-16 17:27:13 +0530 | [diff] [blame] | 911 | /* |
| 912 | * two channel init at the same time, then ZQ Cal Start |
| 913 | * at the same time, it will use the same RZQ, but cannot |
| 914 | * start at the same time. |
| 915 | * |
| 916 | * So, increase tINIT3 for channel 1, will avoid two |
| 917 | * channel ZQ Cal Start at the same time |
| 918 | */ |
| 919 | if (params->base.dramtype == LPDDR4 && channel == 1) { |
| 920 | tmp = ((params->base.ddr_freq * MHz + 999) / 1000); |
| 921 | tmp1 = readl(&denali_ctl[14]); |
| 922 | writel(tmp + tmp1, &denali_ctl[14]); |
| 923 | } |
| 924 | |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 925 | sdram_copy_to_reg(denali_pi, ¶ms->pi_regs.denali_pi[0], |
| 926 | sizeof(struct rk3399_ddr_pi_regs)); |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 927 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 928 | /* rank count need to set for init */ |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 929 | set_memory_map(chan, channel, params); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 930 | |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 931 | writel(params->phy_regs.denali_phy[910], &denali_phy[910]); |
| 932 | writel(params->phy_regs.denali_phy[911], &denali_phy[911]); |
| 933 | writel(params->phy_regs.denali_phy[912], &denali_phy[912]); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 934 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 935 | if (params->base.dramtype == LPDDR4) { |
Jagan Teki | b49b5dc | 2019-07-16 17:27:14 +0530 | [diff] [blame] | 936 | writel(params->phy_regs.denali_phy[898], &denali_phy[898]); |
| 937 | writel(params->phy_regs.denali_phy[919], &denali_phy[919]); |
| 938 | } |
| 939 | |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 940 | dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) & |
| 941 | PWRUP_SREFRESH_EXIT; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 942 | clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); |
| 943 | |
| 944 | /* PHY_DLL_RST_EN */ |
| 945 | clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24); |
| 946 | |
| 947 | setbits_le32(&denali_pi[0], START); |
| 948 | setbits_le32(&denali_ctl[0], START); |
| 949 | |
Jagan Teki | 5e92718 | 2019-07-16 17:27:12 +0530 | [diff] [blame] | 950 | /** |
| 951 | * LPDDR4 use PLL bypass mode for init |
| 952 | * not need to wait for the PLL to lock |
| 953 | */ |
| 954 | if (params->base.dramtype != LPDDR4) { |
| 955 | /* Waiting for phy DLL lock */ |
| 956 | while (1) { |
| 957 | tmp = readl(&denali_phy[920]); |
| 958 | tmp1 = readl(&denali_phy[921]); |
| 959 | tmp2 = readl(&denali_phy[922]); |
| 960 | if ((((tmp >> 16) & 0x1) == 0x1) && |
| 961 | (((tmp1 >> 16) & 0x1) == 0x1) && |
| 962 | (((tmp1 >> 0) & 0x1) == 0x1) && |
| 963 | (((tmp2 >> 0) & 0x1) == 0x1)) |
| 964 | break; |
| 965 | } |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 966 | } |
| 967 | |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 968 | sdram_copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4); |
| 969 | sdram_copy_to_reg(&denali_phy[0], ¶ms_phy[0], (90 - 0 + 1) * 4); |
| 970 | sdram_copy_to_reg(&denali_phy[128], ¶ms_phy[128], |
| 971 | (218 - 128 + 1) * 4); |
| 972 | sdram_copy_to_reg(&denali_phy[256], ¶ms_phy[256], |
| 973 | (346 - 256 + 1) * 4); |
| 974 | sdram_copy_to_reg(&denali_phy[384], ¶ms_phy[384], |
| 975 | (474 - 384 + 1) * 4); |
| 976 | sdram_copy_to_reg(&denali_phy[512], ¶ms_phy[512], |
| 977 | (549 - 512 + 1) * 4); |
| 978 | sdram_copy_to_reg(&denali_phy[640], ¶ms_phy[640], |
| 979 | (677 - 640 + 1) * 4); |
| 980 | sdram_copy_to_reg(&denali_phy[768], ¶ms_phy[768], |
| 981 | (805 - 768 + 1) * 4); |
| 982 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 983 | if (params->base.dramtype == LPDDR4) |
| 984 | params_cfg = dram->ops->get_phy_index_params(1, params); |
| 985 | else |
| 986 | params_cfg = dram->ops->get_phy_index_params(0, params); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 987 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 988 | clrsetbits_le32(¶ms_cfg->phy_regs.denali_phy[896], 0x3 << 8, |
| 989 | 0 << 8); |
| 990 | writel(params_cfg->phy_regs.denali_phy[896], &denali_phy[896]); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 991 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 992 | writel(params->phy_regs.denali_phy[83] + (0x10 << 16), |
| 993 | &denali_phy[83]); |
| 994 | writel(params->phy_regs.denali_phy[84] + (0x10 << 8), |
| 995 | &denali_phy[84]); |
| 996 | writel(params->phy_regs.denali_phy[211] + (0x10 << 16), |
| 997 | &denali_phy[211]); |
| 998 | writel(params->phy_regs.denali_phy[212] + (0x10 << 8), |
| 999 | &denali_phy[212]); |
| 1000 | writel(params->phy_regs.denali_phy[339] + (0x10 << 16), |
| 1001 | &denali_phy[339]); |
| 1002 | writel(params->phy_regs.denali_phy[340] + (0x10 << 8), |
| 1003 | &denali_phy[340]); |
| 1004 | writel(params->phy_regs.denali_phy[467] + (0x10 << 16), |
| 1005 | &denali_phy[467]); |
| 1006 | writel(params->phy_regs.denali_phy[468] + (0x10 << 8), |
| 1007 | &denali_phy[468]); |
| 1008 | |
| 1009 | if (params->base.dramtype == LPDDR4) { |
| 1010 | /* |
| 1011 | * to improve write dqs and dq phase from 1.5ns to 3.5ns |
| 1012 | * at 50MHz. this's the measure result from oscilloscope |
| 1013 | * of dqs and dq write signal. |
| 1014 | */ |
| 1015 | for (byte = 0; byte < 4; byte++) { |
| 1016 | tmp = 0x680; |
| 1017 | clrsetbits_le32(&denali_phy[1 + (128 * byte)], |
| 1018 | 0xfff << 8, tmp << 8); |
| 1019 | } |
| 1020 | /* |
| 1021 | * to workaround 366ball two channel's RESET connect to |
| 1022 | * one RESET signal of die |
| 1023 | */ |
| 1024 | if (channel == 1) |
| 1025 | clrsetbits_le32(&denali_phy[937], 0xff, |
| 1026 | PHY_DRV_ODT_240 | |
| 1027 | (PHY_DRV_ODT_240 << 0x4)); |
| 1028 | } |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1029 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1030 | return 0; |
| 1031 | } |
| 1032 | |
| 1033 | static void select_per_cs_training_index(const struct chan_info *chan, |
| 1034 | u32 rank) |
| 1035 | { |
| 1036 | u32 *denali_phy = chan->publ->denali_phy; |
| 1037 | |
| 1038 | /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */ |
Jagan Teki | f676c7c | 2019-07-15 23:50:56 +0530 | [diff] [blame] | 1039 | if ((readl(&denali_phy[84]) >> 16) & 1) { |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1040 | /* |
| 1041 | * PHY_8/136/264/392 |
| 1042 | * phy_per_cs_training_index_X 1bit offset_24 |
| 1043 | */ |
| 1044 | clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24); |
| 1045 | clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24); |
| 1046 | clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24); |
| 1047 | clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24); |
| 1048 | } |
| 1049 | } |
| 1050 | |
| 1051 | static void override_write_leveling_value(const struct chan_info *chan) |
| 1052 | { |
| 1053 | u32 *denali_ctl = chan->pctl->denali_ctl; |
| 1054 | u32 *denali_phy = chan->publ->denali_phy; |
| 1055 | u32 byte; |
| 1056 | |
| 1057 | /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ |
| 1058 | setbits_le32(&denali_phy[896], 1); |
| 1059 | |
| 1060 | /* |
| 1061 | * PHY_8/136/264/392 |
| 1062 | * phy_per_cs_training_multicast_en_X 1bit offset_16 |
| 1063 | */ |
| 1064 | clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16); |
| 1065 | clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16); |
| 1066 | clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16); |
| 1067 | clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16); |
| 1068 | |
| 1069 | for (byte = 0; byte < 4; byte++) |
| 1070 | clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16, |
| 1071 | 0x200 << 16); |
| 1072 | |
| 1073 | /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ |
| 1074 | clrbits_le32(&denali_phy[896], 1); |
| 1075 | |
| 1076 | /* CTL_200 ctrlupd_req 1bit offset_8 */ |
| 1077 | clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); |
| 1078 | } |
| 1079 | |
| 1080 | static int data_training_ca(const struct chan_info *chan, u32 channel, |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1081 | const struct rk3399_sdram_params *params) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1082 | { |
| 1083 | u32 *denali_pi = chan->pi->denali_pi; |
| 1084 | u32 *denali_phy = chan->publ->denali_phy; |
| 1085 | u32 i, tmp; |
| 1086 | u32 obs_0, obs_1, obs_2, obs_err = 0; |
Jagan Teki | 97867c8 | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 1087 | u32 rank = params->ch[channel].cap_info.rank; |
Jagan Teki | bafcc14 | 2019-07-15 23:58:41 +0530 | [diff] [blame] | 1088 | u32 rank_mask; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1089 | |
Jagan Teki | a607961 | 2019-07-15 23:58:40 +0530 | [diff] [blame] | 1090 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 1091 | writel(0x00003f7c, (&denali_pi[175])); |
| 1092 | |
Jagan Teki | f05675e | 2019-07-16 17:27:09 +0530 | [diff] [blame] | 1093 | if (params->base.dramtype == LPDDR4) |
| 1094 | rank_mask = (rank == 1) ? 0x5 : 0xf; |
| 1095 | else |
| 1096 | rank_mask = (rank == 1) ? 0x1 : 0x3; |
Jagan Teki | bafcc14 | 2019-07-15 23:58:41 +0530 | [diff] [blame] | 1097 | |
| 1098 | for (i = 0; i < 4; i++) { |
| 1099 | if (!(rank_mask & (1 << i))) |
| 1100 | continue; |
| 1101 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1102 | select_per_cs_training_index(chan, i); |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1103 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1104 | /* PI_100 PI_CALVL_EN:RW:8:2 */ |
| 1105 | clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8); |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1106 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1107 | /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ |
| 1108 | clrsetbits_le32(&denali_pi[92], |
| 1109 | (0x1 << 16) | (0x3 << 24), |
| 1110 | (0x1 << 16) | (i << 24)); |
| 1111 | |
| 1112 | /* Waiting for training complete */ |
| 1113 | while (1) { |
| 1114 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
| 1115 | tmp = readl(&denali_pi[174]) >> 8; |
| 1116 | /* |
| 1117 | * check status obs |
| 1118 | * PHY_532/660/789 phy_adr_calvl_obs1_:0:32 |
| 1119 | */ |
| 1120 | obs_0 = readl(&denali_phy[532]); |
| 1121 | obs_1 = readl(&denali_phy[660]); |
| 1122 | obs_2 = readl(&denali_phy[788]); |
| 1123 | if (((obs_0 >> 30) & 0x3) || |
| 1124 | ((obs_1 >> 30) & 0x3) || |
| 1125 | ((obs_2 >> 30) & 0x3)) |
| 1126 | obs_err = 1; |
| 1127 | if ((((tmp >> 11) & 0x1) == 0x1) && |
| 1128 | (((tmp >> 13) & 0x1) == 0x1) && |
| 1129 | (((tmp >> 5) & 0x1) == 0x0) && |
Jagan Teki | f676c7c | 2019-07-15 23:50:56 +0530 | [diff] [blame] | 1130 | obs_err == 0) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1131 | break; |
| 1132 | else if ((((tmp >> 5) & 0x1) == 0x1) || |
| 1133 | (obs_err == 1)) |
| 1134 | return -EIO; |
| 1135 | } |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1136 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1137 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 1138 | writel(0x00003f7c, (&denali_pi[175])); |
| 1139 | } |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1140 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1141 | clrbits_le32(&denali_pi[100], 0x3 << 8); |
| 1142 | |
| 1143 | return 0; |
| 1144 | } |
| 1145 | |
| 1146 | static int data_training_wl(const struct chan_info *chan, u32 channel, |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1147 | const struct rk3399_sdram_params *params) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1148 | { |
| 1149 | u32 *denali_pi = chan->pi->denali_pi; |
| 1150 | u32 *denali_phy = chan->publ->denali_phy; |
| 1151 | u32 i, tmp; |
| 1152 | u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; |
Jagan Teki | 97867c8 | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 1153 | u32 rank = params->ch[channel].cap_info.rank; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1154 | |
Jagan Teki | a607961 | 2019-07-15 23:58:40 +0530 | [diff] [blame] | 1155 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 1156 | writel(0x00003f7c, (&denali_pi[175])); |
| 1157 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1158 | for (i = 0; i < rank; i++) { |
| 1159 | select_per_cs_training_index(chan, i); |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1160 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1161 | /* PI_60 PI_WRLVL_EN:RW:8:2 */ |
| 1162 | clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1163 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1164 | /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ |
| 1165 | clrsetbits_le32(&denali_pi[59], |
| 1166 | (0x1 << 8) | (0x3 << 16), |
| 1167 | (0x1 << 8) | (i << 16)); |
| 1168 | |
| 1169 | /* Waiting for training complete */ |
| 1170 | while (1) { |
| 1171 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
| 1172 | tmp = readl(&denali_pi[174]) >> 8; |
| 1173 | |
| 1174 | /* |
| 1175 | * check status obs, if error maybe can not |
| 1176 | * get leveling done PHY_40/168/296/424 |
| 1177 | * phy_wrlvl_status_obs_X:0:13 |
| 1178 | */ |
| 1179 | obs_0 = readl(&denali_phy[40]); |
| 1180 | obs_1 = readl(&denali_phy[168]); |
| 1181 | obs_2 = readl(&denali_phy[296]); |
| 1182 | obs_3 = readl(&denali_phy[424]); |
| 1183 | if (((obs_0 >> 12) & 0x1) || |
| 1184 | ((obs_1 >> 12) & 0x1) || |
| 1185 | ((obs_2 >> 12) & 0x1) || |
| 1186 | ((obs_3 >> 12) & 0x1)) |
| 1187 | obs_err = 1; |
| 1188 | if ((((tmp >> 10) & 0x1) == 0x1) && |
| 1189 | (((tmp >> 13) & 0x1) == 0x1) && |
| 1190 | (((tmp >> 4) & 0x1) == 0x0) && |
Jagan Teki | f676c7c | 2019-07-15 23:50:56 +0530 | [diff] [blame] | 1191 | obs_err == 0) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1192 | break; |
| 1193 | else if ((((tmp >> 4) & 0x1) == 0x1) || |
| 1194 | (obs_err == 1)) |
| 1195 | return -EIO; |
| 1196 | } |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1197 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1198 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 1199 | writel(0x00003f7c, (&denali_pi[175])); |
| 1200 | } |
| 1201 | |
| 1202 | override_write_leveling_value(chan); |
| 1203 | clrbits_le32(&denali_pi[60], 0x3 << 8); |
| 1204 | |
| 1205 | return 0; |
| 1206 | } |
| 1207 | |
| 1208 | static int data_training_rg(const struct chan_info *chan, u32 channel, |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1209 | const struct rk3399_sdram_params *params) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1210 | { |
| 1211 | u32 *denali_pi = chan->pi->denali_pi; |
| 1212 | u32 *denali_phy = chan->publ->denali_phy; |
| 1213 | u32 i, tmp; |
| 1214 | u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; |
Jagan Teki | 97867c8 | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 1215 | u32 rank = params->ch[channel].cap_info.rank; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1216 | |
Jagan Teki | a607961 | 2019-07-15 23:58:40 +0530 | [diff] [blame] | 1217 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 1218 | writel(0x00003f7c, (&denali_pi[175])); |
| 1219 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1220 | for (i = 0; i < rank; i++) { |
| 1221 | select_per_cs_training_index(chan, i); |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1222 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1223 | /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ |
| 1224 | clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24); |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1225 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1226 | /* |
| 1227 | * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 |
| 1228 | * PI_RDLVL_CS:RW:24:2 |
| 1229 | */ |
| 1230 | clrsetbits_le32(&denali_pi[74], |
| 1231 | (0x1 << 16) | (0x3 << 24), |
| 1232 | (0x1 << 16) | (i << 24)); |
| 1233 | |
| 1234 | /* Waiting for training complete */ |
| 1235 | while (1) { |
| 1236 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
| 1237 | tmp = readl(&denali_pi[174]) >> 8; |
| 1238 | |
| 1239 | /* |
| 1240 | * check status obs |
| 1241 | * PHY_43/171/299/427 |
| 1242 | * PHY_GTLVL_STATUS_OBS_x:16:8 |
| 1243 | */ |
| 1244 | obs_0 = readl(&denali_phy[43]); |
| 1245 | obs_1 = readl(&denali_phy[171]); |
| 1246 | obs_2 = readl(&denali_phy[299]); |
| 1247 | obs_3 = readl(&denali_phy[427]); |
| 1248 | if (((obs_0 >> (16 + 6)) & 0x3) || |
| 1249 | ((obs_1 >> (16 + 6)) & 0x3) || |
| 1250 | ((obs_2 >> (16 + 6)) & 0x3) || |
| 1251 | ((obs_3 >> (16 + 6)) & 0x3)) |
| 1252 | obs_err = 1; |
| 1253 | if ((((tmp >> 9) & 0x1) == 0x1) && |
| 1254 | (((tmp >> 13) & 0x1) == 0x1) && |
| 1255 | (((tmp >> 3) & 0x1) == 0x0) && |
Jagan Teki | f676c7c | 2019-07-15 23:50:56 +0530 | [diff] [blame] | 1256 | obs_err == 0) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1257 | break; |
| 1258 | else if ((((tmp >> 3) & 0x1) == 0x1) || |
| 1259 | (obs_err == 1)) |
| 1260 | return -EIO; |
| 1261 | } |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1262 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1263 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 1264 | writel(0x00003f7c, (&denali_pi[175])); |
| 1265 | } |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1266 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1267 | clrbits_le32(&denali_pi[80], 0x3 << 24); |
| 1268 | |
| 1269 | return 0; |
| 1270 | } |
| 1271 | |
| 1272 | static int data_training_rl(const struct chan_info *chan, u32 channel, |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1273 | const struct rk3399_sdram_params *params) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1274 | { |
| 1275 | u32 *denali_pi = chan->pi->denali_pi; |
| 1276 | u32 i, tmp; |
Jagan Teki | 97867c8 | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 1277 | u32 rank = params->ch[channel].cap_info.rank; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1278 | |
Jagan Teki | a607961 | 2019-07-15 23:58:40 +0530 | [diff] [blame] | 1279 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 1280 | writel(0x00003f7c, (&denali_pi[175])); |
| 1281 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1282 | for (i = 0; i < rank; i++) { |
| 1283 | select_per_cs_training_index(chan, i); |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1284 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1285 | /* PI_80 PI_RDLVL_EN:RW:16:2 */ |
| 1286 | clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16); |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1287 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1288 | /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ |
| 1289 | clrsetbits_le32(&denali_pi[74], |
| 1290 | (0x1 << 8) | (0x3 << 24), |
| 1291 | (0x1 << 8) | (i << 24)); |
| 1292 | |
| 1293 | /* Waiting for training complete */ |
| 1294 | while (1) { |
| 1295 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
| 1296 | tmp = readl(&denali_pi[174]) >> 8; |
| 1297 | |
| 1298 | /* |
| 1299 | * make sure status obs not report error bit |
| 1300 | * PHY_46/174/302/430 |
| 1301 | * phy_rdlvl_status_obs_X:16:8 |
| 1302 | */ |
| 1303 | if ((((tmp >> 8) & 0x1) == 0x1) && |
| 1304 | (((tmp >> 13) & 0x1) == 0x1) && |
| 1305 | (((tmp >> 2) & 0x1) == 0x0)) |
| 1306 | break; |
| 1307 | else if (((tmp >> 2) & 0x1) == 0x1) |
| 1308 | return -EIO; |
| 1309 | } |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1310 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1311 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 1312 | writel(0x00003f7c, (&denali_pi[175])); |
| 1313 | } |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1314 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1315 | clrbits_le32(&denali_pi[80], 0x3 << 16); |
| 1316 | |
| 1317 | return 0; |
| 1318 | } |
| 1319 | |
| 1320 | static int data_training_wdql(const struct chan_info *chan, u32 channel, |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1321 | const struct rk3399_sdram_params *params) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1322 | { |
| 1323 | u32 *denali_pi = chan->pi->denali_pi; |
| 1324 | u32 i, tmp; |
Jagan Teki | 97867c8 | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 1325 | u32 rank = params->ch[channel].cap_info.rank; |
Jagan Teki | 8772359 | 2019-07-15 23:58:42 +0530 | [diff] [blame] | 1326 | u32 rank_mask; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1327 | |
Jagan Teki | a607961 | 2019-07-15 23:58:40 +0530 | [diff] [blame] | 1328 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 1329 | writel(0x00003f7c, (&denali_pi[175])); |
| 1330 | |
Jagan Teki | d7504c0 | 2019-07-16 17:27:10 +0530 | [diff] [blame] | 1331 | if (params->base.dramtype == LPDDR4) |
| 1332 | rank_mask = (rank == 1) ? 0x5 : 0xf; |
| 1333 | else |
| 1334 | rank_mask = (rank == 1) ? 0x1 : 0x3; |
Jagan Teki | 8772359 | 2019-07-15 23:58:42 +0530 | [diff] [blame] | 1335 | |
| 1336 | for (i = 0; i < 4; i++) { |
| 1337 | if (!(rank_mask & (1 << i))) |
| 1338 | continue; |
| 1339 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1340 | select_per_cs_training_index(chan, i); |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1341 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1342 | /* |
| 1343 | * disable PI_WDQLVL_VREF_EN before wdq leveling? |
YouMin Chen | 79f4d91 | 2019-11-15 11:04:53 +0800 | [diff] [blame] | 1344 | * PI_117 PI_WDQLVL_VREF_EN:RW:8:1 |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1345 | */ |
YouMin Chen | 79f4d91 | 2019-11-15 11:04:53 +0800 | [diff] [blame] | 1346 | clrbits_le32(&denali_pi[117], 0x1 << 8); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1347 | /* PI_124 PI_WDQLVL_EN:RW:16:2 */ |
| 1348 | clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16); |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1349 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1350 | /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ |
| 1351 | clrsetbits_le32(&denali_pi[121], |
| 1352 | (0x1 << 8) | (0x3 << 16), |
| 1353 | (0x1 << 8) | (i << 16)); |
| 1354 | |
| 1355 | /* Waiting for training complete */ |
| 1356 | while (1) { |
| 1357 | /* PI_174 PI_INT_STATUS:RD:8:18 */ |
| 1358 | tmp = readl(&denali_pi[174]) >> 8; |
| 1359 | if ((((tmp >> 12) & 0x1) == 0x1) && |
| 1360 | (((tmp >> 13) & 0x1) == 0x1) && |
| 1361 | (((tmp >> 6) & 0x1) == 0x0)) |
| 1362 | break; |
| 1363 | else if (((tmp >> 6) & 0x1) == 0x1) |
| 1364 | return -EIO; |
| 1365 | } |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1366 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1367 | /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ |
| 1368 | writel(0x00003f7c, (&denali_pi[175])); |
| 1369 | } |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 1370 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1371 | clrbits_le32(&denali_pi[124], 0x3 << 16); |
| 1372 | |
| 1373 | return 0; |
| 1374 | } |
| 1375 | |
Jagan Teki | 5ff7abe | 2019-07-16 17:27:29 +0530 | [diff] [blame] | 1376 | static int data_training(struct dram_info *dram, u32 channel, |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1377 | const struct rk3399_sdram_params *params, |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1378 | u32 training_flag) |
| 1379 | { |
Jagan Teki | 5ff7abe | 2019-07-16 17:27:29 +0530 | [diff] [blame] | 1380 | struct chan_info *chan = &dram->chan[channel]; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1381 | u32 *denali_phy = chan->publ->denali_phy; |
Jagan Teki | 6214ff2 | 2019-07-15 23:58:39 +0530 | [diff] [blame] | 1382 | int ret; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1383 | |
| 1384 | /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ |
| 1385 | setbits_le32(&denali_phy[927], (1 << 22)); |
| 1386 | |
| 1387 | if (training_flag == PI_FULL_TRAINING) { |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1388 | if (params->base.dramtype == LPDDR4) { |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1389 | training_flag = PI_WRITE_LEVELING | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1390 | PI_READ_GATE_TRAINING | |
| 1391 | PI_READ_LEVELING | PI_WDQ_LEVELING; |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1392 | } else if (params->base.dramtype == LPDDR3) { |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1393 | training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | |
| 1394 | PI_READ_GATE_TRAINING; |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1395 | } else if (params->base.dramtype == DDR3) { |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1396 | training_flag = PI_WRITE_LEVELING | |
| 1397 | PI_READ_GATE_TRAINING | |
| 1398 | PI_READ_LEVELING; |
| 1399 | } |
| 1400 | } |
| 1401 | |
| 1402 | /* ca training(LPDDR4,LPDDR3 support) */ |
Jagan Teki | 6214ff2 | 2019-07-15 23:58:39 +0530 | [diff] [blame] | 1403 | if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) { |
| 1404 | ret = data_training_ca(chan, channel, params); |
| 1405 | if (ret < 0) { |
| 1406 | debug("%s: data training ca failed\n", __func__); |
| 1407 | return ret; |
| 1408 | } |
| 1409 | } |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1410 | |
| 1411 | /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ |
Jagan Teki | 6214ff2 | 2019-07-15 23:58:39 +0530 | [diff] [blame] | 1412 | if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) { |
| 1413 | ret = data_training_wl(chan, channel, params); |
| 1414 | if (ret < 0) { |
| 1415 | debug("%s: data training wl failed\n", __func__); |
| 1416 | return ret; |
| 1417 | } |
| 1418 | } |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1419 | |
| 1420 | /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ |
Jagan Teki | 6214ff2 | 2019-07-15 23:58:39 +0530 | [diff] [blame] | 1421 | if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) { |
| 1422 | ret = data_training_rg(chan, channel, params); |
| 1423 | if (ret < 0) { |
| 1424 | debug("%s: data training rg failed\n", __func__); |
| 1425 | return ret; |
| 1426 | } |
| 1427 | } |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1428 | |
| 1429 | /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ |
Jagan Teki | 6214ff2 | 2019-07-15 23:58:39 +0530 | [diff] [blame] | 1430 | if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) { |
| 1431 | ret = data_training_rl(chan, channel, params); |
| 1432 | if (ret < 0) { |
| 1433 | debug("%s: data training rl failed\n", __func__); |
| 1434 | return ret; |
| 1435 | } |
| 1436 | } |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1437 | |
| 1438 | /* wdq leveling(LPDDR4 support) */ |
Jagan Teki | 6214ff2 | 2019-07-15 23:58:39 +0530 | [diff] [blame] | 1439 | if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) { |
| 1440 | ret = data_training_wdql(chan, channel, params); |
| 1441 | if (ret < 0) { |
| 1442 | debug("%s: data training wdql failed\n", __func__); |
| 1443 | return ret; |
| 1444 | } |
| 1445 | } |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1446 | |
| 1447 | /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ |
| 1448 | clrbits_le32(&denali_phy[927], (1 << 22)); |
| 1449 | |
| 1450 | return 0; |
| 1451 | } |
| 1452 | |
| 1453 | static void set_ddrconfig(const struct chan_info *chan, |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1454 | const struct rk3399_sdram_params *params, |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1455 | unsigned char channel, u32 ddrconfig) |
| 1456 | { |
| 1457 | /* only need to set ddrconfig */ |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 1458 | struct msch_regs *ddr_msch_regs = chan->msch; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1459 | unsigned int cs0_cap = 0; |
| 1460 | unsigned int cs1_cap = 0; |
| 1461 | |
Jagan Teki | 97867c8 | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 1462 | cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row |
| 1463 | + params->ch[channel].cap_info.col |
| 1464 | + params->ch[channel].cap_info.bk |
| 1465 | + params->ch[channel].cap_info.bw - 20)); |
| 1466 | if (params->ch[channel].cap_info.rank > 1) |
| 1467 | cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row |
| 1468 | - params->ch[channel].cap_info.cs1_row); |
| 1469 | if (params->ch[channel].cap_info.row_3_4) { |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1470 | cs0_cap = cs0_cap * 3 / 4; |
| 1471 | cs1_cap = cs1_cap * 3 / 4; |
| 1472 | } |
| 1473 | |
| 1474 | writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf); |
| 1475 | writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8), |
| 1476 | &ddr_msch_regs->ddrsize); |
| 1477 | } |
| 1478 | |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 1479 | static void sdram_msch_config(struct msch_regs *msch, |
| 1480 | struct sdram_msch_timings *noc_timings) |
| 1481 | { |
| 1482 | writel(noc_timings->ddrtiminga0.d32, |
| 1483 | &msch->ddrtiminga0.d32); |
| 1484 | writel(noc_timings->ddrtimingb0.d32, |
| 1485 | &msch->ddrtimingb0.d32); |
| 1486 | writel(noc_timings->ddrtimingc0.d32, |
| 1487 | &msch->ddrtimingc0.d32); |
| 1488 | writel(noc_timings->devtodev0.d32, |
| 1489 | &msch->devtodev0.d32); |
| 1490 | writel(noc_timings->ddrmode.d32, |
| 1491 | &msch->ddrmode.d32); |
| 1492 | } |
| 1493 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1494 | static void dram_all_config(struct dram_info *dram, |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 1495 | struct rk3399_sdram_params *params) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1496 | { |
Jagan Teki | 2d33712 | 2019-07-16 17:27:00 +0530 | [diff] [blame] | 1497 | u32 sys_reg2 = 0; |
Jagan Teki | 9d8769c | 2019-07-16 17:27:01 +0530 | [diff] [blame] | 1498 | u32 sys_reg3 = 0; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1499 | unsigned int channel, idx; |
| 1500 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1501 | for (channel = 0, idx = 0; |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1502 | (idx < params->base.num_channels) && (channel < 2); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1503 | channel++) { |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 1504 | struct msch_regs *ddr_msch_regs; |
| 1505 | struct sdram_msch_timings *noc_timing; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1506 | |
Jagan Teki | 97867c8 | 2019-07-15 23:51:05 +0530 | [diff] [blame] | 1507 | if (params->ch[channel].cap_info.col == 0) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1508 | continue; |
| 1509 | idx++; |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 1510 | sdram_org_config(¶ms->ch[channel].cap_info, |
| 1511 | ¶ms->base, &sys_reg2, |
| 1512 | &sys_reg3, channel); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1513 | ddr_msch_regs = dram->chan[channel].msch; |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1514 | noc_timing = ¶ms->ch[channel].noc_timings; |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 1515 | sdram_msch_config(ddr_msch_regs, noc_timing); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1516 | |
Jagan Teki | b02c548 | 2019-07-16 17:27:20 +0530 | [diff] [blame] | 1517 | /** |
| 1518 | * rank 1 memory clock disable (dfi_dram_clk_disable = 1) |
| 1519 | * |
| 1520 | * The hardware for LPDDR4 with |
| 1521 | * - CLK0P/N connect to lower 16-bits |
| 1522 | * - CLK1P/N connect to higher 16-bits |
| 1523 | * |
| 1524 | * dfi dram clk is configured via CLK1P/N, so disabling |
| 1525 | * dfi dram clk will disable the CLK1P/N as well for lpddr4. |
| 1526 | */ |
| 1527 | if (params->ch[channel].cap_info.rank == 1 && |
| 1528 | params->base.dramtype != LPDDR4) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1529 | setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], |
| 1530 | 1 << 17); |
| 1531 | } |
| 1532 | |
Jagan Teki | 2d33712 | 2019-07-16 17:27:00 +0530 | [diff] [blame] | 1533 | writel(sys_reg2, &dram->pmugrf->os_reg2); |
Jagan Teki | 9d8769c | 2019-07-16 17:27:01 +0530 | [diff] [blame] | 1534 | writel(sys_reg3, &dram->pmugrf->os_reg3); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1535 | rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1536 | params->base.stride << 10); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1537 | |
| 1538 | /* reboot hold register set */ |
| 1539 | writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) | |
| 1540 | PRESET_GPIO1_HOLD(1), |
| 1541 | &dram->pmucru->pmucru_rstnhold_con[1]); |
| 1542 | clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3); |
| 1543 | } |
| 1544 | |
Kever Yang | e723a55 | 2019-08-12 20:02:29 +0800 | [diff] [blame] | 1545 | static void set_cap_relate_config(const struct chan_info *chan, |
| 1546 | struct rk3399_sdram_params *params, |
| 1547 | unsigned int channel) |
| 1548 | { |
| 1549 | u32 *denali_ctl = chan->pctl->denali_ctl; |
| 1550 | u32 tmp; |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 1551 | struct sdram_msch_timings *noc_timing; |
Kever Yang | e723a55 | 2019-08-12 20:02:29 +0800 | [diff] [blame] | 1552 | |
| 1553 | if (params->base.dramtype == LPDDR3) { |
| 1554 | tmp = (8 << params->ch[channel].cap_info.bw) / |
| 1555 | (8 << params->ch[channel].cap_info.dbw); |
| 1556 | |
| 1557 | /** |
| 1558 | * memdata_ratio |
| 1559 | * 1 -> 0, 2 -> 1, 4 -> 2 |
| 1560 | */ |
| 1561 | clrsetbits_le32(&denali_ctl[197], 0x7, |
| 1562 | (tmp >> 1)); |
| 1563 | clrsetbits_le32(&denali_ctl[198], 0x7 << 8, |
| 1564 | (tmp >> 1) << 8); |
| 1565 | } |
| 1566 | |
| 1567 | noc_timing = ¶ms->ch[channel].noc_timings; |
| 1568 | |
| 1569 | /* |
| 1570 | * noc timing bw relate timing is 32 bit, and real bw is 16bit |
| 1571 | * actually noc reg is setting at function dram_all_config |
| 1572 | */ |
| 1573 | if (params->ch[channel].cap_info.bw == 16 && |
| 1574 | noc_timing->ddrmode.b.mwrsize == 2) { |
| 1575 | if (noc_timing->ddrmode.b.burstsize) |
| 1576 | noc_timing->ddrmode.b.burstsize -= 1; |
| 1577 | noc_timing->ddrmode.b.mwrsize -= 1; |
| 1578 | noc_timing->ddrtimingc0.b.burstpenalty *= 2; |
| 1579 | noc_timing->ddrtimingc0.b.wrtomwr *= 2; |
| 1580 | } |
| 1581 | } |
| 1582 | |
| 1583 | static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel) |
| 1584 | { |
| 1585 | unsigned int cs0_row = params->ch[channel].cap_info.cs0_row; |
| 1586 | unsigned int col = params->ch[channel].cap_info.col; |
| 1587 | unsigned int bw = params->ch[channel].cap_info.bw; |
| 1588 | u16 ddr_cfg_2_rbc[] = { |
| 1589 | /* |
| 1590 | * [6] highest bit col |
| 1591 | * [5:3] max row(14+n) |
| 1592 | * [2] insertion row |
| 1593 | * [1:0] col(9+n),col, data bus 32bit |
| 1594 | * |
| 1595 | * highbitcol, max_row, insertion_row, col |
| 1596 | */ |
| 1597 | ((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */ |
| 1598 | ((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */ |
| 1599 | ((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */ |
| 1600 | ((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */ |
| 1601 | ((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */ |
| 1602 | ((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */ |
| 1603 | ((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */ |
| 1604 | ((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */ |
| 1605 | }; |
| 1606 | u32 i; |
| 1607 | |
| 1608 | col -= (bw == 2) ? 0 : 1; |
| 1609 | col -= 9; |
| 1610 | |
| 1611 | for (i = 0; i < 4; i++) { |
| 1612 | if ((col == (ddr_cfg_2_rbc[i] & 0x3)) && |
| 1613 | (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14))) |
| 1614 | break; |
| 1615 | } |
| 1616 | |
| 1617 | if (i >= 4) |
| 1618 | i = -EINVAL; |
| 1619 | |
| 1620 | return i; |
| 1621 | } |
| 1622 | |
YouMin Chen | 6ba388f | 2019-11-15 11:04:49 +0800 | [diff] [blame] | 1623 | static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride) |
| 1624 | { |
| 1625 | rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10); |
| 1626 | } |
| 1627 | |
Jagan Teki | cc117bb | 2019-07-16 17:27:31 +0530 | [diff] [blame] | 1628 | #if !defined(CONFIG_RAM_RK3399_LPDDR4) |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 1629 | static int data_training_first(struct dram_info *dram, u32 channel, u8 rank, |
| 1630 | struct rk3399_sdram_params *params) |
Jagan Teki | 9eb935a | 2019-07-16 17:27:30 +0530 | [diff] [blame] | 1631 | { |
| 1632 | u8 training_flag = PI_READ_GATE_TRAINING; |
| 1633 | |
| 1634 | /* |
| 1635 | * LPDDR3 CA training msut be trigger before |
| 1636 | * other training. |
| 1637 | * DDR3 is not have CA training. |
| 1638 | */ |
| 1639 | |
| 1640 | if (params->base.dramtype == LPDDR3) |
| 1641 | training_flag |= PI_CA_TRAINING; |
| 1642 | |
| 1643 | return data_training(dram, channel, params, training_flag); |
| 1644 | } |
| 1645 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1646 | static int switch_to_phy_index1(struct dram_info *dram, |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1647 | struct rk3399_sdram_params *params) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1648 | { |
| 1649 | u32 channel; |
| 1650 | u32 *denali_phy; |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 1651 | u32 ch_count = params->base.num_channels; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1652 | int ret; |
| 1653 | int i = 0; |
| 1654 | |
| 1655 | writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1, |
| 1656 | 1 << 4 | 1 << 2 | 1), |
| 1657 | &dram->cic->cic_ctrl0); |
| 1658 | while (!(readl(&dram->cic->cic_status0) & (1 << 2))) { |
| 1659 | mdelay(10); |
| 1660 | i++; |
| 1661 | if (i > 10) { |
| 1662 | debug("index1 frequency change overtime\n"); |
| 1663 | return -ETIME; |
| 1664 | } |
| 1665 | } |
| 1666 | |
| 1667 | i = 0; |
| 1668 | writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0); |
| 1669 | while (!(readl(&dram->cic->cic_status0) & (1 << 0))) { |
| 1670 | mdelay(10); |
Heinrich Schuchardt | 8051659 | 2018-03-18 12:10:55 +0100 | [diff] [blame] | 1671 | i++; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1672 | if (i > 10) { |
| 1673 | debug("index1 frequency done overtime\n"); |
| 1674 | return -ETIME; |
| 1675 | } |
| 1676 | } |
| 1677 | |
| 1678 | for (channel = 0; channel < ch_count; channel++) { |
| 1679 | denali_phy = dram->chan[channel].publ->denali_phy; |
| 1680 | clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); |
Jagan Teki | 5ff7abe | 2019-07-16 17:27:29 +0530 | [diff] [blame] | 1681 | ret = data_training(dram, channel, params, PI_FULL_TRAINING); |
Jagan Teki | 6214ff2 | 2019-07-15 23:58:39 +0530 | [diff] [blame] | 1682 | if (ret < 0) { |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 1683 | debug("index1 training failed\n"); |
| 1684 | return ret; |
| 1685 | } |
| 1686 | } |
| 1687 | |
| 1688 | return 0; |
| 1689 | } |
| 1690 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 1691 | struct rk3399_sdram_params |
| 1692 | *get_phy_index_params(u32 phy_fn, |
| 1693 | struct rk3399_sdram_params *params) |
| 1694 | { |
| 1695 | if (phy_fn == 0) |
| 1696 | return params; |
| 1697 | else |
| 1698 | return NULL; |
| 1699 | } |
| 1700 | |
| 1701 | void modify_param(const struct chan_info *chan, |
| 1702 | struct rk3399_sdram_params *params) |
| 1703 | { |
| 1704 | struct rk3399_sdram_params *params_cfg; |
| 1705 | u32 *denali_pi_params; |
| 1706 | |
| 1707 | denali_pi_params = params->pi_regs.denali_pi; |
| 1708 | |
| 1709 | /* modify PHY F0/F1/F2 params */ |
| 1710 | params_cfg = get_phy_index_params(0, params); |
| 1711 | set_ds_odt(chan, params_cfg, false, 0); |
| 1712 | |
| 1713 | clrsetbits_le32(&denali_pi_params[45], 0x1 << 24, 0x1 << 24); |
| 1714 | clrsetbits_le32(&denali_pi_params[61], 0x1 << 24, 0x1 << 24); |
| 1715 | clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24); |
| 1716 | clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1); |
| 1717 | } |
Jagan Teki | 940d125 | 2019-07-16 17:27:39 +0530 | [diff] [blame] | 1718 | #else |
| 1719 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 1720 | struct rk3399_sdram_params dfs_cfgs_lpddr4[] = { |
| 1721 | #include "sdram-rk3399-lpddr4-400.inc" |
| 1722 | #include "sdram-rk3399-lpddr4-800.inc" |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1723 | }; |
| 1724 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 1725 | static struct rk3399_sdram_params |
| 1726 | *lpddr4_get_phy_index_params(u32 phy_fn, |
| 1727 | struct rk3399_sdram_params *params) |
| 1728 | { |
| 1729 | if (phy_fn == 0) |
| 1730 | return params; |
| 1731 | else if (phy_fn == 1) |
| 1732 | return &dfs_cfgs_lpddr4[1]; |
| 1733 | else if (phy_fn == 2) |
| 1734 | return &dfs_cfgs_lpddr4[0]; |
| 1735 | else |
| 1736 | return NULL; |
| 1737 | } |
| 1738 | |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1739 | static void *get_denali_pi(const struct chan_info *chan, |
| 1740 | struct rk3399_sdram_params *params, bool reg) |
| 1741 | { |
| 1742 | return reg ? &chan->pi->denali_pi : ¶ms->pi_regs.denali_pi; |
| 1743 | } |
| 1744 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 1745 | static u32 lpddr4_get_phy_fn(struct rk3399_sdram_params *params, u32 ctl_fn) |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1746 | { |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 1747 | u32 lpddr4_phy_fn[] = {1, 0, 0xb}; |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1748 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 1749 | return lpddr4_phy_fn[ctl_fn]; |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1750 | } |
| 1751 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 1752 | static u32 lpddr4_get_ctl_fn(struct rk3399_sdram_params *params, u32 phy_fn) |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1753 | { |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 1754 | u32 lpddr4_ctl_fn[] = {1, 0, 2}; |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1755 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 1756 | return lpddr4_ctl_fn[phy_fn]; |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1757 | } |
| 1758 | |
Jagan Teki | cc117bb | 2019-07-16 17:27:31 +0530 | [diff] [blame] | 1759 | static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf) |
| 1760 | { |
| 1761 | return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F); |
| 1762 | } |
| 1763 | |
YouMin Chen | 6ba388f | 2019-11-15 11:04:49 +0800 | [diff] [blame] | 1764 | /* |
Jagan Teki | cc117bb | 2019-07-16 17:27:31 +0530 | [diff] [blame] | 1765 | * read mr_num mode register |
| 1766 | * rank = 1: cs0 |
| 1767 | * rank = 2: cs1 |
| 1768 | */ |
| 1769 | static int read_mr(struct rk3399_ddr_pctl_regs *ddr_pctl_regs, u32 rank, |
| 1770 | u32 mr_num, u32 *buf) |
| 1771 | { |
| 1772 | s32 timeout = 100; |
| 1773 | |
| 1774 | writel(((1 << 16) | (((rank == 2) ? 1 : 0) << 8) | mr_num) << 8, |
| 1775 | &ddr_pctl_regs->denali_ctl[118]); |
| 1776 | |
| 1777 | while (0 == (readl(&ddr_pctl_regs->denali_ctl[203]) & |
| 1778 | ((1 << 21) | (1 << 12)))) { |
| 1779 | udelay(1); |
| 1780 | |
| 1781 | if (timeout <= 0) { |
| 1782 | printf("%s: pctl timeout!\n", __func__); |
| 1783 | return -ETIMEDOUT; |
| 1784 | } |
| 1785 | |
| 1786 | timeout--; |
| 1787 | } |
| 1788 | |
| 1789 | if (!(readl(&ddr_pctl_regs->denali_ctl[203]) & (1 << 12))) { |
| 1790 | *buf = readl(&ddr_pctl_regs->denali_ctl[119]) & 0xFF; |
| 1791 | } else { |
| 1792 | printf("%s: read mr failed with 0x%x status\n", __func__, |
| 1793 | readl(&ddr_pctl_regs->denali_ctl[17]) & 0x3); |
| 1794 | *buf = 0; |
| 1795 | } |
| 1796 | |
| 1797 | setbits_le32(&ddr_pctl_regs->denali_ctl[205], (1 << 21) | (1 << 12)); |
| 1798 | |
| 1799 | return 0; |
| 1800 | } |
| 1801 | |
| 1802 | static int lpddr4_mr_detect(struct dram_info *dram, u32 channel, u8 rank, |
| 1803 | struct rk3399_sdram_params *params) |
| 1804 | { |
| 1805 | u64 cs0_cap; |
| 1806 | u32 stride; |
| 1807 | u32 cs = 0, col = 0, bk = 0, bw = 0, row_3_4 = 0; |
| 1808 | u32 cs0_row = 0, cs1_row = 0, ddrconfig = 0; |
| 1809 | u32 mr5, mr12, mr14; |
| 1810 | struct chan_info *chan = &dram->chan[channel]; |
| 1811 | struct rk3399_ddr_pctl_regs *ddr_pctl_regs = chan->pctl; |
| 1812 | void __iomem *addr = NULL; |
| 1813 | int ret = 0; |
| 1814 | u32 val; |
| 1815 | |
| 1816 | stride = get_ddr_stride(dram->pmusgrf); |
| 1817 | |
| 1818 | if (params->ch[channel].cap_info.col == 0) { |
| 1819 | ret = -EPERM; |
| 1820 | goto end; |
| 1821 | } |
| 1822 | |
| 1823 | cs = params->ch[channel].cap_info.rank; |
| 1824 | col = params->ch[channel].cap_info.col; |
| 1825 | bk = params->ch[channel].cap_info.bk; |
| 1826 | bw = params->ch[channel].cap_info.bw; |
| 1827 | row_3_4 = params->ch[channel].cap_info.row_3_4; |
| 1828 | cs0_row = params->ch[channel].cap_info.cs0_row; |
| 1829 | cs1_row = params->ch[channel].cap_info.cs1_row; |
| 1830 | ddrconfig = params->ch[channel].cap_info.ddrconfig; |
| 1831 | |
| 1832 | /* 2GB */ |
| 1833 | params->ch[channel].cap_info.rank = 2; |
| 1834 | params->ch[channel].cap_info.col = 10; |
| 1835 | params->ch[channel].cap_info.bk = 3; |
| 1836 | params->ch[channel].cap_info.bw = 2; |
| 1837 | params->ch[channel].cap_info.row_3_4 = 0; |
| 1838 | params->ch[channel].cap_info.cs0_row = 15; |
| 1839 | params->ch[channel].cap_info.cs1_row = 15; |
| 1840 | params->ch[channel].cap_info.ddrconfig = 1; |
| 1841 | |
| 1842 | set_memory_map(chan, channel, params); |
| 1843 | params->ch[channel].cap_info.ddrconfig = |
| 1844 | calculate_ddrconfig(params, channel); |
| 1845 | set_ddrconfig(chan, params, channel, |
| 1846 | params->ch[channel].cap_info.ddrconfig); |
| 1847 | set_cap_relate_config(chan, params, channel); |
| 1848 | |
| 1849 | cs0_cap = (1 << (params->ch[channel].cap_info.bw |
| 1850 | + params->ch[channel].cap_info.col |
| 1851 | + params->ch[channel].cap_info.bk |
| 1852 | + params->ch[channel].cap_info.cs0_row)); |
| 1853 | |
| 1854 | if (params->ch[channel].cap_info.row_3_4) |
| 1855 | cs0_cap = cs0_cap * 3 / 4; |
| 1856 | |
| 1857 | if (channel == 0) |
| 1858 | set_ddr_stride(dram->pmusgrf, 0x17); |
| 1859 | else |
| 1860 | set_ddr_stride(dram->pmusgrf, 0x18); |
| 1861 | |
| 1862 | /* read and write data to DRAM, avoid be optimized by compiler. */ |
| 1863 | if (rank == 1) |
| 1864 | addr = (void __iomem *)0x100; |
| 1865 | else if (rank == 2) |
| 1866 | addr = (void __iomem *)(cs0_cap + 0x100); |
| 1867 | |
| 1868 | val = readl(addr); |
| 1869 | writel(val + 1, addr); |
| 1870 | |
| 1871 | read_mr(ddr_pctl_regs, rank, 5, &mr5); |
| 1872 | read_mr(ddr_pctl_regs, rank, 12, &mr12); |
| 1873 | read_mr(ddr_pctl_regs, rank, 14, &mr14); |
| 1874 | |
| 1875 | if (mr5 == 0 || mr12 != 0x4d || mr14 != 0x4d) { |
| 1876 | ret = -EINVAL; |
| 1877 | goto end; |
| 1878 | } |
| 1879 | end: |
| 1880 | params->ch[channel].cap_info.rank = cs; |
| 1881 | params->ch[channel].cap_info.col = col; |
| 1882 | params->ch[channel].cap_info.bk = bk; |
| 1883 | params->ch[channel].cap_info.bw = bw; |
| 1884 | params->ch[channel].cap_info.row_3_4 = row_3_4; |
| 1885 | params->ch[channel].cap_info.cs0_row = cs0_row; |
| 1886 | params->ch[channel].cap_info.cs1_row = cs1_row; |
| 1887 | params->ch[channel].cap_info.ddrconfig = ddrconfig; |
| 1888 | |
| 1889 | set_ddr_stride(dram->pmusgrf, stride); |
| 1890 | |
| 1891 | return ret; |
| 1892 | } |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1893 | |
| 1894 | static void set_lpddr4_dq_odt(const struct chan_info *chan, |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 1895 | struct rk3399_sdram_params *params, u32 ctl_fn, |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1896 | bool en, bool ctl_phy_reg, u32 mr5) |
| 1897 | { |
| 1898 | u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); |
| 1899 | u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg); |
| 1900 | struct io_setting *io; |
| 1901 | u32 reg_value; |
| 1902 | |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1903 | io = lpddr4_get_io_settings(params, mr5); |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 1904 | if (en) |
| 1905 | reg_value = io->dq_odt; |
| 1906 | else |
| 1907 | reg_value = 0; |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1908 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 1909 | switch (ctl_fn) { |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1910 | case 0: |
| 1911 | clrsetbits_le32(&denali_ctl[139], 0x7 << 24, reg_value << 24); |
| 1912 | clrsetbits_le32(&denali_ctl[153], 0x7 << 24, reg_value << 24); |
| 1913 | |
| 1914 | clrsetbits_le32(&denali_pi[132], 0x7 << 0, (reg_value << 0)); |
| 1915 | clrsetbits_le32(&denali_pi[139], 0x7 << 16, (reg_value << 16)); |
| 1916 | clrsetbits_le32(&denali_pi[147], 0x7 << 0, (reg_value << 0)); |
| 1917 | clrsetbits_le32(&denali_pi[154], 0x7 << 16, (reg_value << 16)); |
| 1918 | break; |
| 1919 | case 1: |
| 1920 | clrsetbits_le32(&denali_ctl[140], 0x7 << 0, reg_value << 0); |
| 1921 | clrsetbits_le32(&denali_ctl[154], 0x7 << 0, reg_value << 0); |
| 1922 | |
| 1923 | clrsetbits_le32(&denali_pi[129], 0x7 << 16, (reg_value << 16)); |
| 1924 | clrsetbits_le32(&denali_pi[137], 0x7 << 0, (reg_value << 0)); |
| 1925 | clrsetbits_le32(&denali_pi[144], 0x7 << 16, (reg_value << 16)); |
| 1926 | clrsetbits_le32(&denali_pi[152], 0x7 << 0, (reg_value << 0)); |
| 1927 | break; |
| 1928 | case 2: |
| 1929 | default: |
| 1930 | clrsetbits_le32(&denali_ctl[140], 0x7 << 8, (reg_value << 8)); |
| 1931 | clrsetbits_le32(&denali_ctl[154], 0x7 << 8, (reg_value << 8)); |
| 1932 | |
| 1933 | clrsetbits_le32(&denali_pi[127], 0x7 << 0, (reg_value << 0)); |
| 1934 | clrsetbits_le32(&denali_pi[134], 0x7 << 16, (reg_value << 16)); |
| 1935 | clrsetbits_le32(&denali_pi[142], 0x7 << 0, (reg_value << 0)); |
| 1936 | clrsetbits_le32(&denali_pi[149], 0x7 << 16, (reg_value << 16)); |
| 1937 | break; |
| 1938 | } |
| 1939 | } |
| 1940 | |
| 1941 | static void set_lpddr4_ca_odt(const struct chan_info *chan, |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 1942 | struct rk3399_sdram_params *params, u32 ctl_fn, |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1943 | bool en, bool ctl_phy_reg, u32 mr5) |
| 1944 | { |
| 1945 | u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); |
| 1946 | u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg); |
| 1947 | struct io_setting *io; |
| 1948 | u32 reg_value; |
| 1949 | |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1950 | io = lpddr4_get_io_settings(params, mr5); |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 1951 | if (en) |
| 1952 | reg_value = io->ca_odt; |
| 1953 | else |
| 1954 | reg_value = 0; |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1955 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 1956 | switch (ctl_fn) { |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1957 | case 0: |
| 1958 | clrsetbits_le32(&denali_ctl[139], 0x7 << 28, reg_value << 28); |
| 1959 | clrsetbits_le32(&denali_ctl[153], 0x7 << 28, reg_value << 28); |
| 1960 | |
| 1961 | clrsetbits_le32(&denali_pi[132], 0x7 << 4, reg_value << 4); |
| 1962 | clrsetbits_le32(&denali_pi[139], 0x7 << 20, reg_value << 20); |
| 1963 | clrsetbits_le32(&denali_pi[147], 0x7 << 4, reg_value << 4); |
| 1964 | clrsetbits_le32(&denali_pi[154], 0x7 << 20, reg_value << 20); |
| 1965 | break; |
| 1966 | case 1: |
| 1967 | clrsetbits_le32(&denali_ctl[140], 0x7 << 4, reg_value << 4); |
| 1968 | clrsetbits_le32(&denali_ctl[154], 0x7 << 4, reg_value << 4); |
| 1969 | |
| 1970 | clrsetbits_le32(&denali_pi[129], 0x7 << 20, reg_value << 20); |
| 1971 | clrsetbits_le32(&denali_pi[137], 0x7 << 4, reg_value << 4); |
| 1972 | clrsetbits_le32(&denali_pi[144], 0x7 << 20, reg_value << 20); |
| 1973 | clrsetbits_le32(&denali_pi[152], 0x7 << 4, reg_value << 4); |
| 1974 | break; |
| 1975 | case 2: |
| 1976 | default: |
| 1977 | clrsetbits_le32(&denali_ctl[140], 0x7 << 12, (reg_value << 12)); |
| 1978 | clrsetbits_le32(&denali_ctl[154], 0x7 << 12, (reg_value << 12)); |
| 1979 | |
| 1980 | clrsetbits_le32(&denali_pi[127], 0x7 << 4, reg_value << 4); |
| 1981 | clrsetbits_le32(&denali_pi[134], 0x7 << 20, reg_value << 20); |
| 1982 | clrsetbits_le32(&denali_pi[142], 0x7 << 4, reg_value << 4); |
| 1983 | clrsetbits_le32(&denali_pi[149], 0x7 << 20, reg_value << 20); |
| 1984 | break; |
| 1985 | } |
| 1986 | } |
| 1987 | |
| 1988 | static void set_lpddr4_MR3(const struct chan_info *chan, |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 1989 | struct rk3399_sdram_params *params, u32 ctl_fn, |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 1990 | bool ctl_phy_reg, u32 mr5) |
| 1991 | { |
| 1992 | u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); |
| 1993 | u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg); |
| 1994 | struct io_setting *io; |
| 1995 | u32 reg_value; |
| 1996 | |
| 1997 | io = lpddr4_get_io_settings(params, mr5); |
| 1998 | |
| 1999 | reg_value = ((io->pdds << 3) | 1); |
| 2000 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2001 | switch (ctl_fn) { |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2002 | case 0: |
| 2003 | clrsetbits_le32(&denali_ctl[138], 0xFFFF, reg_value); |
| 2004 | clrsetbits_le32(&denali_ctl[152], 0xFFFF, reg_value); |
| 2005 | |
| 2006 | clrsetbits_le32(&denali_pi[131], 0xFFFF << 16, reg_value << 16); |
| 2007 | clrsetbits_le32(&denali_pi[139], 0xFFFF, reg_value); |
| 2008 | clrsetbits_le32(&denali_pi[146], 0xFFFF << 16, reg_value << 16); |
| 2009 | clrsetbits_le32(&denali_pi[154], 0xFFFF, reg_value); |
| 2010 | break; |
| 2011 | case 1: |
| 2012 | clrsetbits_le32(&denali_ctl[138], 0xFFFF << 16, |
| 2013 | reg_value << 16); |
| 2014 | clrsetbits_le32(&denali_ctl[152], 0xFFFF << 16, |
| 2015 | reg_value << 16); |
| 2016 | |
| 2017 | clrsetbits_le32(&denali_pi[129], 0xFFFF, reg_value); |
| 2018 | clrsetbits_le32(&denali_pi[136], 0xFFFF << 16, reg_value << 16); |
| 2019 | clrsetbits_le32(&denali_pi[144], 0xFFFF, reg_value); |
| 2020 | clrsetbits_le32(&denali_pi[151], 0xFFFF << 16, reg_value << 16); |
| 2021 | break; |
| 2022 | case 2: |
| 2023 | default: |
| 2024 | clrsetbits_le32(&denali_ctl[139], 0xFFFF, reg_value); |
| 2025 | clrsetbits_le32(&denali_ctl[153], 0xFFFF, reg_value); |
| 2026 | |
| 2027 | clrsetbits_le32(&denali_pi[126], 0xFFFF << 16, reg_value << 16); |
| 2028 | clrsetbits_le32(&denali_pi[134], 0xFFFF, reg_value); |
| 2029 | clrsetbits_le32(&denali_pi[141], 0xFFFF << 16, reg_value << 16); |
| 2030 | clrsetbits_le32(&denali_pi[149], 0xFFFF, reg_value); |
| 2031 | break; |
| 2032 | } |
| 2033 | } |
| 2034 | |
| 2035 | static void set_lpddr4_MR12(const struct chan_info *chan, |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2036 | struct rk3399_sdram_params *params, u32 ctl_fn, |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2037 | bool ctl_phy_reg, u32 mr5) |
| 2038 | { |
| 2039 | u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); |
| 2040 | u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg); |
| 2041 | struct io_setting *io; |
| 2042 | u32 reg_value; |
| 2043 | |
| 2044 | io = lpddr4_get_io_settings(params, mr5); |
| 2045 | |
| 2046 | reg_value = io->ca_vref; |
| 2047 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2048 | switch (ctl_fn) { |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2049 | case 0: |
| 2050 | clrsetbits_le32(&denali_ctl[140], 0xFFFF << 16, |
| 2051 | reg_value << 16); |
| 2052 | clrsetbits_le32(&denali_ctl[154], 0xFFFF << 16, |
| 2053 | reg_value << 16); |
| 2054 | |
| 2055 | clrsetbits_le32(&denali_pi[132], 0xFF << 8, reg_value << 8); |
| 2056 | clrsetbits_le32(&denali_pi[139], 0xFF << 24, reg_value << 24); |
| 2057 | clrsetbits_le32(&denali_pi[147], 0xFF << 8, reg_value << 8); |
| 2058 | clrsetbits_le32(&denali_pi[154], 0xFF << 24, reg_value << 24); |
| 2059 | break; |
| 2060 | case 1: |
| 2061 | clrsetbits_le32(&denali_ctl[141], 0xFFFF, reg_value); |
| 2062 | clrsetbits_le32(&denali_ctl[155], 0xFFFF, reg_value); |
| 2063 | |
| 2064 | clrsetbits_le32(&denali_pi[129], 0xFF << 24, reg_value << 24); |
| 2065 | clrsetbits_le32(&denali_pi[137], 0xFF << 8, reg_value << 8); |
| 2066 | clrsetbits_le32(&denali_pi[144], 0xFF << 24, reg_value << 24); |
| 2067 | clrsetbits_le32(&denali_pi[152], 0xFF << 8, reg_value << 8); |
| 2068 | break; |
| 2069 | case 2: |
| 2070 | default: |
| 2071 | clrsetbits_le32(&denali_ctl[141], 0xFFFF << 16, |
| 2072 | reg_value << 16); |
| 2073 | clrsetbits_le32(&denali_ctl[155], 0xFFFF << 16, |
| 2074 | reg_value << 16); |
| 2075 | |
| 2076 | clrsetbits_le32(&denali_pi[127], 0xFF << 8, reg_value << 8); |
| 2077 | clrsetbits_le32(&denali_pi[134], 0xFF << 24, reg_value << 24); |
| 2078 | clrsetbits_le32(&denali_pi[142], 0xFF << 8, reg_value << 8); |
| 2079 | clrsetbits_le32(&denali_pi[149], 0xFF << 24, reg_value << 24); |
| 2080 | break; |
| 2081 | } |
| 2082 | } |
| 2083 | |
| 2084 | static void set_lpddr4_MR14(const struct chan_info *chan, |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2085 | struct rk3399_sdram_params *params, u32 ctl_fn, |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2086 | bool ctl_phy_reg, u32 mr5) |
| 2087 | { |
| 2088 | u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg); |
| 2089 | u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg); |
| 2090 | struct io_setting *io; |
| 2091 | u32 reg_value; |
| 2092 | |
| 2093 | io = lpddr4_get_io_settings(params, mr5); |
| 2094 | |
| 2095 | reg_value = io->dq_vref; |
| 2096 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2097 | switch (ctl_fn) { |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2098 | case 0: |
| 2099 | clrsetbits_le32(&denali_ctl[142], 0xFFFF << 16, |
| 2100 | reg_value << 16); |
| 2101 | clrsetbits_le32(&denali_ctl[156], 0xFFFF << 16, |
| 2102 | reg_value << 16); |
| 2103 | |
| 2104 | clrsetbits_le32(&denali_pi[132], 0xFF << 16, reg_value << 16); |
| 2105 | clrsetbits_le32(&denali_pi[140], 0xFF << 0, reg_value << 0); |
| 2106 | clrsetbits_le32(&denali_pi[147], 0xFF << 16, reg_value << 16); |
| 2107 | clrsetbits_le32(&denali_pi[155], 0xFF << 0, reg_value << 0); |
| 2108 | break; |
| 2109 | case 1: |
| 2110 | clrsetbits_le32(&denali_ctl[143], 0xFFFF, reg_value); |
| 2111 | clrsetbits_le32(&denali_ctl[157], 0xFFFF, reg_value); |
| 2112 | |
| 2113 | clrsetbits_le32(&denali_pi[130], 0xFF << 0, reg_value << 0); |
| 2114 | clrsetbits_le32(&denali_pi[137], 0xFF << 16, reg_value << 16); |
| 2115 | clrsetbits_le32(&denali_pi[145], 0xFF << 0, reg_value << 0); |
| 2116 | clrsetbits_le32(&denali_pi[152], 0xFF << 16, reg_value << 16); |
| 2117 | break; |
| 2118 | case 2: |
| 2119 | default: |
| 2120 | clrsetbits_le32(&denali_ctl[143], 0xFFFF << 16, |
| 2121 | reg_value << 16); |
| 2122 | clrsetbits_le32(&denali_ctl[157], 0xFFFF << 16, |
| 2123 | reg_value << 16); |
| 2124 | |
| 2125 | clrsetbits_le32(&denali_pi[127], 0xFF << 16, reg_value << 16); |
| 2126 | clrsetbits_le32(&denali_pi[135], 0xFF << 0, reg_value << 0); |
| 2127 | clrsetbits_le32(&denali_pi[142], 0xFF << 16, reg_value << 16); |
| 2128 | clrsetbits_le32(&denali_pi[150], 0xFF << 0, reg_value << 0); |
| 2129 | break; |
| 2130 | } |
| 2131 | } |
| 2132 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 2133 | void lpddr4_modify_param(const struct chan_info *chan, |
| 2134 | struct rk3399_sdram_params *params) |
| 2135 | { |
| 2136 | struct rk3399_sdram_params *params_cfg; |
| 2137 | u32 *denali_ctl_params; |
| 2138 | u32 *denali_pi_params; |
| 2139 | u32 *denali_phy_params; |
| 2140 | |
| 2141 | denali_ctl_params = params->pctl_regs.denali_ctl; |
| 2142 | denali_pi_params = params->pi_regs.denali_pi; |
| 2143 | denali_phy_params = params->phy_regs.denali_phy; |
| 2144 | |
| 2145 | set_lpddr4_dq_odt(chan, params, 2, true, false, 0); |
| 2146 | set_lpddr4_ca_odt(chan, params, 2, true, false, 0); |
| 2147 | set_lpddr4_MR3(chan, params, 2, false, 0); |
| 2148 | set_lpddr4_MR12(chan, params, 2, false, 0); |
| 2149 | set_lpddr4_MR14(chan, params, 2, false, 0); |
| 2150 | params_cfg = lpddr4_get_phy_index_params(0, params); |
| 2151 | set_ds_odt(chan, params_cfg, false, 0); |
| 2152 | /* read two cycle preamble */ |
| 2153 | clrsetbits_le32(&denali_ctl_params[200], 0x3 << 24, 0x3 << 24); |
| 2154 | clrsetbits_le32(&denali_phy_params[7], 0x3 << 24, 0x3 << 24); |
| 2155 | clrsetbits_le32(&denali_phy_params[135], 0x3 << 24, 0x3 << 24); |
| 2156 | clrsetbits_le32(&denali_phy_params[263], 0x3 << 24, 0x3 << 24); |
| 2157 | clrsetbits_le32(&denali_phy_params[391], 0x3 << 24, 0x3 << 24); |
| 2158 | |
| 2159 | /* boot frequency two cycle preamble */ |
| 2160 | clrsetbits_le32(&denali_phy_params[2], 0x3 << 16, 0x3 << 16); |
| 2161 | clrsetbits_le32(&denali_phy_params[130], 0x3 << 16, 0x3 << 16); |
| 2162 | clrsetbits_le32(&denali_phy_params[258], 0x3 << 16, 0x3 << 16); |
| 2163 | clrsetbits_le32(&denali_phy_params[386], 0x3 << 16, 0x3 << 16); |
| 2164 | |
| 2165 | clrsetbits_le32(&denali_pi_params[45], 0x3 << 8, 0x3 << 8); |
| 2166 | clrsetbits_le32(&denali_pi_params[58], 0x1, 0x1); |
| 2167 | |
| 2168 | /* |
| 2169 | * bypass mode need PHY_SLICE_PWR_RDC_DISABLE_x = 1, |
| 2170 | * boot frequency mode use bypass mode |
| 2171 | */ |
| 2172 | setbits_le32(&denali_phy_params[10], 1 << 16); |
| 2173 | setbits_le32(&denali_phy_params[138], 1 << 16); |
| 2174 | setbits_le32(&denali_phy_params[266], 1 << 16); |
| 2175 | setbits_le32(&denali_phy_params[394], 1 << 16); |
| 2176 | |
| 2177 | clrsetbits_le32(&denali_pi_params[45], 0x1 << 24, 0x1 << 24); |
| 2178 | clrsetbits_le32(&denali_pi_params[61], 0x1 << 24, 0x1 << 24); |
| 2179 | clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24); |
| 2180 | clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1); |
| 2181 | } |
| 2182 | |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2183 | static void lpddr4_copy_phy(struct dram_info *dram, |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2184 | struct rk3399_sdram_params *params, u32 phy_fn, |
| 2185 | struct rk3399_sdram_params *params_cfg, |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2186 | u32 channel) |
| 2187 | { |
| 2188 | u32 *denali_ctl, *denali_phy; |
| 2189 | u32 *denali_phy_params; |
| 2190 | u32 speed = 0; |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2191 | u32 ctl_fn, mr5; |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2192 | |
| 2193 | denali_ctl = dram->chan[channel].pctl->denali_ctl; |
| 2194 | denali_phy = dram->chan[channel].publ->denali_phy; |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2195 | denali_phy_params = params_cfg->phy_regs.denali_phy; |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2196 | |
| 2197 | /* switch index */ |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2198 | clrsetbits_le32(&denali_phy_params[896], 0x3 << 8, |
| 2199 | phy_fn << 8); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2200 | writel(denali_phy_params[896], &denali_phy[896]); |
| 2201 | |
| 2202 | /* phy_pll_ctrl_ca, phy_pll_ctrl */ |
| 2203 | writel(denali_phy_params[911], &denali_phy[911]); |
| 2204 | |
| 2205 | /* phy_low_freq_sel */ |
| 2206 | clrsetbits_le32(&denali_phy[913], 0x1, |
| 2207 | denali_phy_params[913] & 0x1); |
| 2208 | |
| 2209 | /* phy_grp_slave_delay_x, phy_cslvl_dly_step */ |
| 2210 | writel(denali_phy_params[916], &denali_phy[916]); |
| 2211 | writel(denali_phy_params[917], &denali_phy[917]); |
| 2212 | writel(denali_phy_params[918], &denali_phy[918]); |
| 2213 | |
| 2214 | /* phy_adrz_sw_wraddr_shift_x */ |
| 2215 | writel(denali_phy_params[512], &denali_phy[512]); |
| 2216 | clrsetbits_le32(&denali_phy[513], 0xffff, |
| 2217 | denali_phy_params[513] & 0xffff); |
| 2218 | writel(denali_phy_params[640], &denali_phy[640]); |
| 2219 | clrsetbits_le32(&denali_phy[641], 0xffff, |
| 2220 | denali_phy_params[641] & 0xffff); |
| 2221 | writel(denali_phy_params[768], &denali_phy[768]); |
| 2222 | clrsetbits_le32(&denali_phy[769], 0xffff, |
| 2223 | denali_phy_params[769] & 0xffff); |
| 2224 | |
| 2225 | writel(denali_phy_params[544], &denali_phy[544]); |
| 2226 | writel(denali_phy_params[545], &denali_phy[545]); |
| 2227 | writel(denali_phy_params[546], &denali_phy[546]); |
| 2228 | writel(denali_phy_params[547], &denali_phy[547]); |
| 2229 | |
| 2230 | writel(denali_phy_params[672], &denali_phy[672]); |
| 2231 | writel(denali_phy_params[673], &denali_phy[673]); |
| 2232 | writel(denali_phy_params[674], &denali_phy[674]); |
| 2233 | writel(denali_phy_params[675], &denali_phy[675]); |
| 2234 | |
| 2235 | writel(denali_phy_params[800], &denali_phy[800]); |
| 2236 | writel(denali_phy_params[801], &denali_phy[801]); |
| 2237 | writel(denali_phy_params[802], &denali_phy[802]); |
| 2238 | writel(denali_phy_params[803], &denali_phy[803]); |
| 2239 | |
| 2240 | /* |
| 2241 | * phy_adr_master_delay_start_x |
| 2242 | * phy_adr_master_delay_step_x |
| 2243 | * phy_adr_master_delay_wait_x |
| 2244 | */ |
| 2245 | writel(denali_phy_params[548], &denali_phy[548]); |
| 2246 | writel(denali_phy_params[676], &denali_phy[676]); |
| 2247 | writel(denali_phy_params[804], &denali_phy[804]); |
| 2248 | |
| 2249 | /* phy_adr_calvl_dly_step_x */ |
| 2250 | writel(denali_phy_params[549], &denali_phy[549]); |
| 2251 | writel(denali_phy_params[677], &denali_phy[677]); |
| 2252 | writel(denali_phy_params[805], &denali_phy[805]); |
| 2253 | |
| 2254 | /* |
| 2255 | * phy_clk_wrdm_slave_delay_x |
| 2256 | * phy_clk_wrdqz_slave_delay_x |
| 2257 | * phy_clk_wrdqs_slave_delay_x |
| 2258 | */ |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 2259 | sdram_copy_to_reg((u32 *)&denali_phy[59], |
| 2260 | (u32 *)&denali_phy_params[59], (63 - 58) * 4); |
| 2261 | sdram_copy_to_reg((u32 *)&denali_phy[187], |
| 2262 | (u32 *)&denali_phy_params[187], (191 - 186) * 4); |
| 2263 | sdram_copy_to_reg((u32 *)&denali_phy[315], |
| 2264 | (u32 *)&denali_phy_params[315], (319 - 314) * 4); |
| 2265 | sdram_copy_to_reg((u32 *)&denali_phy[443], |
| 2266 | (u32 *)&denali_phy_params[443], (447 - 442) * 4); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2267 | |
| 2268 | /* |
| 2269 | * phy_dqs_tsel_wr_timing_x 8bits denali_phy_84/212/340/468 offset_8 |
| 2270 | * dqs_tsel_wr_end[7:4] add half cycle |
| 2271 | * phy_dq_tsel_wr_timing_x 8bits denali_phy_83/211/339/467 offset_8 |
| 2272 | * dq_tsel_wr_end[7:4] add half cycle |
| 2273 | */ |
| 2274 | writel(denali_phy_params[83] + (0x10 << 16), &denali_phy[83]); |
| 2275 | writel(denali_phy_params[84] + (0x10 << 8), &denali_phy[84]); |
| 2276 | writel(denali_phy_params[85], &denali_phy[85]); |
| 2277 | |
| 2278 | writel(denali_phy_params[211] + (0x10 << 16), &denali_phy[211]); |
| 2279 | writel(denali_phy_params[212] + (0x10 << 8), &denali_phy[212]); |
| 2280 | writel(denali_phy_params[213], &denali_phy[213]); |
| 2281 | |
| 2282 | writel(denali_phy_params[339] + (0x10 << 16), &denali_phy[339]); |
| 2283 | writel(denali_phy_params[340] + (0x10 << 8), &denali_phy[340]); |
| 2284 | writel(denali_phy_params[341], &denali_phy[341]); |
| 2285 | |
| 2286 | writel(denali_phy_params[467] + (0x10 << 16), &denali_phy[467]); |
| 2287 | writel(denali_phy_params[468] + (0x10 << 8), &denali_phy[468]); |
| 2288 | writel(denali_phy_params[469], &denali_phy[469]); |
| 2289 | |
| 2290 | /* |
| 2291 | * phy_gtlvl_resp_wait_cnt_x |
| 2292 | * phy_gtlvl_dly_step_x |
| 2293 | * phy_wrlvl_resp_wait_cnt_x |
| 2294 | * phy_gtlvl_final_step_x |
| 2295 | * phy_gtlvl_back_step_x |
| 2296 | * phy_rdlvl_dly_step_x |
| 2297 | * |
| 2298 | * phy_master_delay_step_x |
| 2299 | * phy_master_delay_wait_x |
| 2300 | * phy_wrlvl_dly_step_x |
| 2301 | * phy_rptr_update_x |
| 2302 | * phy_wdqlvl_dly_step_x |
| 2303 | */ |
| 2304 | writel(denali_phy_params[87], &denali_phy[87]); |
| 2305 | writel(denali_phy_params[88], &denali_phy[88]); |
| 2306 | writel(denali_phy_params[89], &denali_phy[89]); |
| 2307 | writel(denali_phy_params[90], &denali_phy[90]); |
| 2308 | |
| 2309 | writel(denali_phy_params[215], &denali_phy[215]); |
| 2310 | writel(denali_phy_params[216], &denali_phy[216]); |
| 2311 | writel(denali_phy_params[217], &denali_phy[217]); |
| 2312 | writel(denali_phy_params[218], &denali_phy[218]); |
| 2313 | |
| 2314 | writel(denali_phy_params[343], &denali_phy[343]); |
| 2315 | writel(denali_phy_params[344], &denali_phy[344]); |
| 2316 | writel(denali_phy_params[345], &denali_phy[345]); |
| 2317 | writel(denali_phy_params[346], &denali_phy[346]); |
| 2318 | |
| 2319 | writel(denali_phy_params[471], &denali_phy[471]); |
| 2320 | writel(denali_phy_params[472], &denali_phy[472]); |
| 2321 | writel(denali_phy_params[473], &denali_phy[473]); |
| 2322 | writel(denali_phy_params[474], &denali_phy[474]); |
| 2323 | |
| 2324 | /* |
| 2325 | * phy_gtlvl_lat_adj_start_x |
| 2326 | * phy_gtlvl_rddqs_slv_dly_start_x |
| 2327 | * phy_rdlvl_rddqs_dq_slv_dly_start_x |
| 2328 | * phy_wdqlvl_dqdm_slv_dly_start_x |
| 2329 | */ |
| 2330 | writel(denali_phy_params[80], &denali_phy[80]); |
| 2331 | writel(denali_phy_params[81], &denali_phy[81]); |
| 2332 | |
| 2333 | writel(denali_phy_params[208], &denali_phy[208]); |
| 2334 | writel(denali_phy_params[209], &denali_phy[209]); |
| 2335 | |
| 2336 | writel(denali_phy_params[336], &denali_phy[336]); |
| 2337 | writel(denali_phy_params[337], &denali_phy[337]); |
| 2338 | |
| 2339 | writel(denali_phy_params[464], &denali_phy[464]); |
| 2340 | writel(denali_phy_params[465], &denali_phy[465]); |
| 2341 | |
| 2342 | /* |
| 2343 | * phy_master_delay_start_x |
| 2344 | * phy_sw_master_mode_x |
| 2345 | * phy_rddata_en_tsel_dly_x |
| 2346 | */ |
| 2347 | writel(denali_phy_params[86], &denali_phy[86]); |
| 2348 | writel(denali_phy_params[214], &denali_phy[214]); |
| 2349 | writel(denali_phy_params[342], &denali_phy[342]); |
| 2350 | writel(denali_phy_params[470], &denali_phy[470]); |
| 2351 | |
| 2352 | /* |
| 2353 | * phy_rddqz_slave_delay_x |
| 2354 | * phy_rddqs_dqz_fall_slave_delay_x |
| 2355 | * phy_rddqs_dqz_rise_slave_delay_x |
| 2356 | * phy_rddqs_dm_fall_slave_delay_x |
| 2357 | * phy_rddqs_dm_rise_slave_delay_x |
| 2358 | * phy_rddqs_gate_slave_delay_x |
| 2359 | * phy_wrlvl_delay_early_threshold_x |
| 2360 | * phy_write_path_lat_add_x |
| 2361 | * phy_rddqs_latency_adjust_x |
| 2362 | * phy_wrlvl_delay_period_threshold_x |
| 2363 | * phy_wrlvl_early_force_zero_x |
| 2364 | */ |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 2365 | sdram_copy_to_reg((u32 *)&denali_phy[64], |
| 2366 | (u32 *)&denali_phy_params[64], (67 - 63) * 4); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2367 | clrsetbits_le32(&denali_phy[68], 0xfffffc00, |
| 2368 | denali_phy_params[68] & 0xfffffc00); |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 2369 | sdram_copy_to_reg((u32 *)&denali_phy[69], |
| 2370 | (u32 *)&denali_phy_params[69], (79 - 68) * 4); |
| 2371 | sdram_copy_to_reg((u32 *)&denali_phy[192], |
| 2372 | (u32 *)&denali_phy_params[192], (195 - 191) * 4); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2373 | clrsetbits_le32(&denali_phy[196], 0xfffffc00, |
| 2374 | denali_phy_params[196] & 0xfffffc00); |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 2375 | sdram_copy_to_reg((u32 *)&denali_phy[197], |
| 2376 | (u32 *)&denali_phy_params[197], (207 - 196) * 4); |
| 2377 | sdram_copy_to_reg((u32 *)&denali_phy[320], |
| 2378 | (u32 *)&denali_phy_params[320], (323 - 319) * 4); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2379 | clrsetbits_le32(&denali_phy[324], 0xfffffc00, |
| 2380 | denali_phy_params[324] & 0xfffffc00); |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 2381 | sdram_copy_to_reg((u32 *)&denali_phy[325], |
| 2382 | (u32 *)&denali_phy_params[325], (335 - 324) * 4); |
| 2383 | sdram_copy_to_reg((u32 *)&denali_phy[448], |
| 2384 | (u32 *)&denali_phy_params[448], (451 - 447) * 4); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2385 | clrsetbits_le32(&denali_phy[452], 0xfffffc00, |
| 2386 | denali_phy_params[452] & 0xfffffc00); |
YouMin Chen | 23ae72e | 2019-11-15 11:04:45 +0800 | [diff] [blame] | 2387 | sdram_copy_to_reg((u32 *)&denali_phy[453], |
| 2388 | (u32 *)&denali_phy_params[453], (463 - 452) * 4); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2389 | |
| 2390 | /* phy_two_cyc_preamble_x */ |
| 2391 | clrsetbits_le32(&denali_phy[7], 0x3 << 24, |
| 2392 | denali_phy_params[7] & (0x3 << 24)); |
| 2393 | clrsetbits_le32(&denali_phy[135], 0x3 << 24, |
| 2394 | denali_phy_params[135] & (0x3 << 24)); |
| 2395 | clrsetbits_le32(&denali_phy[263], 0x3 << 24, |
| 2396 | denali_phy_params[263] & (0x3 << 24)); |
| 2397 | clrsetbits_le32(&denali_phy[391], 0x3 << 24, |
| 2398 | denali_phy_params[391] & (0x3 << 24)); |
| 2399 | |
| 2400 | /* speed */ |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2401 | if (params_cfg->base.ddr_freq < 400) |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2402 | speed = 0x0; |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2403 | else if (params_cfg->base.ddr_freq < 800) |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2404 | speed = 0x1; |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2405 | else if (params_cfg->base.ddr_freq < 1200) |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2406 | speed = 0x2; |
| 2407 | |
| 2408 | /* phy_924 phy_pad_fdbk_drive */ |
| 2409 | clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); |
| 2410 | /* phy_926 phy_pad_data_drive */ |
| 2411 | clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); |
| 2412 | /* phy_927 phy_pad_dqs_drive */ |
| 2413 | clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); |
| 2414 | /* phy_928 phy_pad_addr_drive */ |
| 2415 | clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); |
| 2416 | /* phy_929 phy_pad_clk_drive */ |
| 2417 | clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); |
| 2418 | /* phy_935 phy_pad_cke_drive */ |
| 2419 | clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); |
| 2420 | /* phy_937 phy_pad_rst_drive */ |
| 2421 | clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); |
| 2422 | /* phy_939 phy_pad_cs_drive */ |
| 2423 | clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); |
| 2424 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 2425 | if (params_cfg->base.dramtype == LPDDR4) { |
| 2426 | read_mr(dram->chan[channel].pctl, 1, 5, &mr5); |
| 2427 | set_ds_odt(&dram->chan[channel], params_cfg, true, mr5); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2428 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 2429 | ctl_fn = lpddr4_get_ctl_fn(params_cfg, phy_fn); |
| 2430 | set_lpddr4_dq_odt(&dram->chan[channel], params_cfg, |
| 2431 | ctl_fn, true, true, mr5); |
| 2432 | set_lpddr4_ca_odt(&dram->chan[channel], params_cfg, |
| 2433 | ctl_fn, true, true, mr5); |
| 2434 | set_lpddr4_MR3(&dram->chan[channel], params_cfg, |
| 2435 | ctl_fn, true, mr5); |
| 2436 | set_lpddr4_MR12(&dram->chan[channel], params_cfg, |
| 2437 | ctl_fn, true, mr5); |
| 2438 | set_lpddr4_MR14(&dram->chan[channel], params_cfg, |
| 2439 | ctl_fn, true, mr5); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2440 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 2441 | /* |
| 2442 | * if phy_sw_master_mode_x not bypass mode, |
| 2443 | * clear phy_slice_pwr_rdc_disable. |
| 2444 | * note: need use timings, not ddr_publ_regs |
| 2445 | */ |
| 2446 | if (!((denali_phy_params[86] >> 8) & (1 << 2))) { |
| 2447 | clrbits_le32(&denali_phy[10], 1 << 16); |
| 2448 | clrbits_le32(&denali_phy[138], 1 << 16); |
| 2449 | clrbits_le32(&denali_phy[266], 1 << 16); |
| 2450 | clrbits_le32(&denali_phy[394], 1 << 16); |
| 2451 | } |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2452 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 2453 | /* |
| 2454 | * when PHY_PER_CS_TRAINING_EN=1, W2W_DIFFCS_DLY_Fx can't |
| 2455 | * smaller than 8 |
| 2456 | * NOTE: need use timings, not ddr_publ_regs |
| 2457 | */ |
| 2458 | if ((denali_phy_params[84] >> 16) & 1) { |
| 2459 | if (((readl(&denali_ctl[217 + ctl_fn]) >> |
| 2460 | 16) & 0x1f) < 8) |
| 2461 | clrsetbits_le32(&denali_ctl[217 + ctl_fn], |
| 2462 | 0x1f << 16, |
| 2463 | 8 << 16); |
| 2464 | } |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2465 | } |
| 2466 | } |
| 2467 | |
| 2468 | static void lpddr4_set_phy(struct dram_info *dram, |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2469 | struct rk3399_sdram_params *params, u32 phy_fn, |
| 2470 | struct rk3399_sdram_params *params_cfg) |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2471 | { |
| 2472 | u32 channel; |
| 2473 | |
| 2474 | for (channel = 0; channel < 2; channel++) |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2475 | lpddr4_copy_phy(dram, params, phy_fn, params_cfg, |
| 2476 | channel); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2477 | } |
| 2478 | |
| 2479 | static int lpddr4_set_ctl(struct dram_info *dram, |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2480 | struct rk3399_sdram_params *params, |
| 2481 | u32 fn, u32 hz) |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2482 | { |
| 2483 | u32 channel; |
| 2484 | int ret_clk, ret; |
| 2485 | |
| 2486 | /* cci idle req stall */ |
| 2487 | writel(0x70007, &dram->grf->soc_con0); |
| 2488 | |
| 2489 | /* enable all clk */ |
| 2490 | setbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7)); |
| 2491 | |
| 2492 | /* idle */ |
| 2493 | setbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18)); |
| 2494 | while ((readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18)) |
| 2495 | != (0x3 << 18)) |
| 2496 | ; |
| 2497 | |
| 2498 | /* change freq */ |
| 2499 | writel((((0x3 << 4) | (1 << 2) | 1) << 16) | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2500 | (fn << 4) | (1 << 2) | 1, &dram->cic->cic_ctrl0); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2501 | while (!(readl(&dram->cic->cic_status0) & (1 << 2))) |
| 2502 | ; |
| 2503 | |
| 2504 | ret_clk = clk_set_rate(&dram->ddr_clk, hz); |
| 2505 | if (ret_clk < 0) { |
| 2506 | printf("%s clk set failed %d\n", __func__, ret_clk); |
| 2507 | return ret_clk; |
| 2508 | } |
| 2509 | |
| 2510 | writel(0x20002, &dram->cic->cic_ctrl0); |
| 2511 | while (!(readl(&dram->cic->cic_status0) & (1 << 0))) |
| 2512 | ; |
| 2513 | |
| 2514 | /* deidle */ |
| 2515 | clrbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18)); |
| 2516 | while (readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18)) |
| 2517 | ; |
| 2518 | |
| 2519 | /* clear enable all clk */ |
| 2520 | clrbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7)); |
| 2521 | |
| 2522 | /* lpddr4 ctl2 can not do training, all training will fail */ |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2523 | if (!(params->base.dramtype == LPDDR4 && fn == 2)) { |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2524 | for (channel = 0; channel < 2; channel++) { |
| 2525 | if (!(params->ch[channel].cap_info.col)) |
| 2526 | continue; |
| 2527 | ret = data_training(dram, channel, params, |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2528 | PI_FULL_TRAINING); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2529 | if (ret) |
| 2530 | printf("%s: channel %d training failed!\n", |
| 2531 | __func__, channel); |
| 2532 | else |
| 2533 | debug("%s: channel %d training pass\n", |
| 2534 | __func__, channel); |
| 2535 | } |
| 2536 | } |
| 2537 | |
| 2538 | return 0; |
| 2539 | } |
| 2540 | |
| 2541 | static int lpddr4_set_rate(struct dram_info *dram, |
| 2542 | struct rk3399_sdram_params *params) |
| 2543 | { |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2544 | u32 ctl_fn; |
| 2545 | u32 phy_fn; |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2546 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2547 | for (ctl_fn = 0; ctl_fn < 2; ctl_fn++) { |
| 2548 | phy_fn = lpddr4_get_phy_fn(params, ctl_fn); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2549 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2550 | lpddr4_set_phy(dram, params, phy_fn, &dfs_cfgs_lpddr4[ctl_fn]); |
| 2551 | lpddr4_set_ctl(dram, params, ctl_fn, |
| 2552 | dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2553 | |
Jagan Teki | 57bd887 | 2020-07-14 01:36:34 +0530 | [diff] [blame] | 2554 | if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) |
| 2555 | printf("%s: change freq to %d mhz %d, %d\n", __func__, |
| 2556 | dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq, |
| 2557 | ctl_fn, phy_fn); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 2558 | } |
| 2559 | |
| 2560 | return 0; |
| 2561 | } |
Jagan Teki | cc117bb | 2019-07-16 17:27:31 +0530 | [diff] [blame] | 2562 | #endif /* CONFIG_RAM_RK3399_LPDDR4 */ |
| 2563 | |
YouMin Chen | 6ba388f | 2019-11-15 11:04:49 +0800 | [diff] [blame] | 2564 | /* CS0,n=1 |
| 2565 | * CS1,n=2 |
| 2566 | * CS0 & CS1, n=3 |
| 2567 | * cs0_cap: MB unit |
| 2568 | */ |
| 2569 | static void dram_set_cs(const struct chan_info *chan, u32 cs_map, u32 cs0_cap, |
| 2570 | unsigned char dramtype) |
| 2571 | { |
| 2572 | u32 *denali_ctl = chan->pctl->denali_ctl; |
| 2573 | u32 *denali_pi = chan->pi->denali_pi; |
| 2574 | struct msch_regs *ddr_msch_regs = chan->msch; |
| 2575 | |
| 2576 | clrsetbits_le32(&denali_ctl[196], 0x3, cs_map); |
| 2577 | writel((cs0_cap / 32) | (((4096 - cs0_cap) / 32) << 8), |
| 2578 | &ddr_msch_regs->ddrsize); |
| 2579 | if (dramtype == LPDDR4) { |
| 2580 | if (cs_map == 1) |
| 2581 | cs_map = 0x5; |
| 2582 | else if (cs_map == 2) |
| 2583 | cs_map = 0xa; |
| 2584 | else |
| 2585 | cs_map = 0xF; |
| 2586 | } |
| 2587 | /*PI_41 PI_CS_MAP:RW:24:4*/ |
| 2588 | clrsetbits_le32(&denali_pi[41], |
| 2589 | 0xf << 24, cs_map << 24); |
| 2590 | if (cs_map == 1 && dramtype == DDR3) |
| 2591 | writel(0x2EC7FFFF, &denali_pi[34]); |
| 2592 | } |
| 2593 | |
| 2594 | static void dram_set_bw(const struct chan_info *chan, u32 bw) |
| 2595 | { |
| 2596 | u32 *denali_ctl = chan->pctl->denali_ctl; |
| 2597 | |
| 2598 | if (bw == 2) |
| 2599 | clrbits_le32(&denali_ctl[196], 1 << 16); |
| 2600 | else |
| 2601 | setbits_le32(&denali_ctl[196], 1 << 16); |
| 2602 | } |
| 2603 | |
| 2604 | static void dram_set_max_col(const struct chan_info *chan, u32 bw, u32 *pcol) |
| 2605 | { |
| 2606 | u32 *denali_ctl = chan->pctl->denali_ctl; |
| 2607 | struct msch_regs *ddr_msch_regs = chan->msch; |
| 2608 | u32 *denali_pi = chan->pi->denali_pi; |
| 2609 | u32 ddrconfig; |
| 2610 | |
| 2611 | clrbits_le32(&denali_ctl[191], 0xf); |
| 2612 | clrsetbits_le32(&denali_ctl[190], |
| 2613 | (7 << 24), |
| 2614 | ((16 - ((bw == 2) ? 14 : 15)) << 24)); |
| 2615 | /*PI_199 PI_COL_DIFF:RW:0:4*/ |
| 2616 | clrbits_le32(&denali_pi[199], 0xf); |
| 2617 | /*PI_155 PI_ROW_DIFF:RW:24:3*/ |
| 2618 | clrsetbits_le32(&denali_pi[155], |
| 2619 | (7 << 24), |
| 2620 | ((16 - 12) << 24)); |
| 2621 | ddrconfig = (bw == 2) ? 3 : 2; |
| 2622 | writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf); |
| 2623 | /* set max cs0 size */ |
| 2624 | writel((4096 / 32) | ((0 / 32) << 8), |
| 2625 | &ddr_msch_regs->ddrsize); |
| 2626 | |
| 2627 | *pcol = 12; |
| 2628 | } |
| 2629 | |
| 2630 | static void dram_set_max_bank(const struct chan_info *chan, u32 bw, u32 *pbank, |
| 2631 | u32 *pcol) |
| 2632 | { |
| 2633 | u32 *denali_ctl = chan->pctl->denali_ctl; |
| 2634 | u32 *denali_pi = chan->pi->denali_pi; |
| 2635 | |
| 2636 | clrbits_le32(&denali_ctl[191], 0xf); |
| 2637 | clrbits_le32(&denali_ctl[190], (3 << 16)); |
| 2638 | /*PI_199 PI_COL_DIFF:RW:0:4*/ |
| 2639 | clrbits_le32(&denali_pi[199], 0xf); |
| 2640 | /*PI_155 PI_BANK_DIFF:RW:16:2*/ |
| 2641 | clrbits_le32(&denali_pi[155], (3 << 16)); |
| 2642 | |
| 2643 | *pbank = 3; |
| 2644 | *pcol = 12; |
| 2645 | } |
| 2646 | |
| 2647 | static void dram_set_max_row(const struct chan_info *chan, u32 bw, u32 *prow, |
| 2648 | u32 *pbank, u32 *pcol) |
| 2649 | { |
| 2650 | u32 *denali_ctl = chan->pctl->denali_ctl; |
| 2651 | u32 *denali_pi = chan->pi->denali_pi; |
| 2652 | struct msch_regs *ddr_msch_regs = chan->msch; |
| 2653 | |
| 2654 | clrsetbits_le32(&denali_ctl[191], 0xf, 12 - 10); |
| 2655 | clrbits_le32(&denali_ctl[190], |
| 2656 | (0x3 << 16) | (0x7 << 24)); |
| 2657 | /*PI_199 PI_COL_DIFF:RW:0:4*/ |
| 2658 | clrsetbits_le32(&denali_pi[199], 0xf, 12 - 10); |
| 2659 | /*PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2*/ |
| 2660 | clrbits_le32(&denali_pi[155], |
| 2661 | (0x3 << 16) | (0x7 << 24)); |
| 2662 | writel(1 | (1 << 8), &ddr_msch_regs->ddrconf); |
| 2663 | /* set max cs0 size */ |
| 2664 | writel((4096 / 32) | ((0 / 32) << 8), |
| 2665 | &ddr_msch_regs->ddrsize); |
| 2666 | |
| 2667 | *prow = 16; |
| 2668 | *pbank = 3; |
| 2669 | *pcol = (bw == 2) ? 10 : 11; |
| 2670 | } |
| 2671 | |
| 2672 | static u64 dram_detect_cap(struct dram_info *dram, |
| 2673 | struct rk3399_sdram_params *params, |
| 2674 | unsigned char channel) |
| 2675 | { |
| 2676 | const struct chan_info *chan = &dram->chan[channel]; |
| 2677 | struct sdram_cap_info *cap_info = ¶ms->ch[channel].cap_info; |
| 2678 | u32 bw; |
| 2679 | u32 col_tmp; |
| 2680 | u32 bk_tmp; |
| 2681 | u32 row_tmp; |
| 2682 | u32 cs0_cap; |
| 2683 | u32 training_flag; |
| 2684 | u32 ddrconfig; |
| 2685 | |
| 2686 | /* detect bw */ |
| 2687 | bw = 2; |
| 2688 | if (params->base.dramtype != LPDDR4) { |
| 2689 | dram_set_bw(chan, bw); |
| 2690 | cap_info->bw = bw; |
| 2691 | if (data_training(dram, channel, params, |
| 2692 | PI_READ_GATE_TRAINING)) { |
| 2693 | bw = 1; |
| 2694 | dram_set_bw(chan, 1); |
| 2695 | cap_info->bw = bw; |
| 2696 | if (data_training(dram, channel, params, |
| 2697 | PI_READ_GATE_TRAINING)) { |
| 2698 | printf("16bit error!!!\n"); |
| 2699 | goto error; |
| 2700 | } |
| 2701 | } |
| 2702 | } |
| 2703 | /* |
| 2704 | * LPDDR3 CA training msut be trigger before other training. |
| 2705 | * DDR3 is not have CA training. |
| 2706 | */ |
| 2707 | if (params->base.dramtype == LPDDR3) |
| 2708 | training_flag = PI_WRITE_LEVELING; |
| 2709 | else |
| 2710 | training_flag = PI_FULL_TRAINING; |
| 2711 | |
| 2712 | if (params->base.dramtype != LPDDR4) { |
| 2713 | if (data_training(dram, channel, params, training_flag)) { |
| 2714 | printf("full training error!!!\n"); |
| 2715 | goto error; |
| 2716 | } |
| 2717 | } |
| 2718 | |
| 2719 | /* detect col */ |
| 2720 | dram_set_max_col(chan, bw, &col_tmp); |
| 2721 | if (sdram_detect_col(cap_info, col_tmp) != 0) |
| 2722 | goto error; |
| 2723 | |
| 2724 | /* detect bank */ |
| 2725 | dram_set_max_bank(chan, bw, &bk_tmp, &col_tmp); |
| 2726 | sdram_detect_bank(cap_info, col_tmp, bk_tmp); |
| 2727 | |
| 2728 | /* detect row */ |
| 2729 | dram_set_max_row(chan, bw, &row_tmp, &bk_tmp, &col_tmp); |
| 2730 | if (sdram_detect_row(cap_info, col_tmp, bk_tmp, row_tmp) != 0) |
| 2731 | goto error; |
| 2732 | |
| 2733 | /* detect row_3_4 */ |
| 2734 | sdram_detect_row_3_4(cap_info, col_tmp, bk_tmp); |
| 2735 | |
| 2736 | /* set ddrconfig */ |
| 2737 | cs0_cap = (1 << (cap_info->cs0_row + cap_info->col + cap_info->bk + |
| 2738 | cap_info->bw - 20)); |
| 2739 | if (cap_info->row_3_4) |
| 2740 | cs0_cap = cs0_cap * 3 / 4; |
| 2741 | |
| 2742 | cap_info->cs1_row = cap_info->cs0_row; |
| 2743 | set_memory_map(chan, channel, params); |
| 2744 | ddrconfig = calculate_ddrconfig(params, channel); |
| 2745 | if (-1 == ddrconfig) |
| 2746 | goto error; |
| 2747 | set_ddrconfig(chan, params, channel, |
| 2748 | cap_info->ddrconfig); |
| 2749 | |
| 2750 | /* detect cs1 row */ |
| 2751 | sdram_detect_cs1_row(cap_info, params->base.dramtype); |
| 2752 | |
| 2753 | /* detect die bw */ |
| 2754 | sdram_detect_dbw(cap_info, params->base.dramtype); |
| 2755 | |
| 2756 | return 0; |
| 2757 | error: |
| 2758 | return (-1); |
| 2759 | } |
| 2760 | |
Jagan Teki | 2525fae | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 2761 | static unsigned char calculate_stride(struct rk3399_sdram_params *params) |
| 2762 | { |
Kever Yang | e2b64fd | 2019-11-15 11:04:52 +0800 | [diff] [blame] | 2763 | unsigned int gstride_type; |
| 2764 | unsigned int channel; |
| 2765 | unsigned int chinfo = 0; |
| 2766 | unsigned int cap = 0; |
| 2767 | unsigned int stride = -1; |
Jagan Teki | 2525fae | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 2768 | unsigned int ch_cap[2] = {0, 0}; |
Kever Yang | e2b64fd | 2019-11-15 11:04:52 +0800 | [diff] [blame] | 2769 | |
| 2770 | gstride_type = STRIDE_256B; |
Jagan Teki | 2525fae | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 2771 | |
| 2772 | for (channel = 0; channel < 2; channel++) { |
| 2773 | unsigned int cs0_cap = 0; |
| 2774 | unsigned int cs1_cap = 0; |
Kever Yang | e2b64fd | 2019-11-15 11:04:52 +0800 | [diff] [blame] | 2775 | struct sdram_cap_info *cap_info = |
| 2776 | ¶ms->ch[channel].cap_info; |
Jagan Teki | 2525fae | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 2777 | |
| 2778 | if (cap_info->col == 0) |
| 2779 | continue; |
| 2780 | |
| 2781 | cs0_cap = (1 << (cap_info->cs0_row + cap_info->col + |
| 2782 | cap_info->bk + cap_info->bw - 20)); |
| 2783 | if (cap_info->rank > 1) |
| 2784 | cs1_cap = cs0_cap >> (cap_info->cs0_row |
| 2785 | - cap_info->cs1_row); |
| 2786 | if (cap_info->row_3_4) { |
| 2787 | cs0_cap = cs0_cap * 3 / 4; |
| 2788 | cs1_cap = cs1_cap * 3 / 4; |
| 2789 | } |
| 2790 | ch_cap[channel] = cs0_cap + cs1_cap; |
| 2791 | chinfo |= 1 << channel; |
| 2792 | } |
| 2793 | |
Kever Yang | e2b64fd | 2019-11-15 11:04:52 +0800 | [diff] [blame] | 2794 | cap = ch_cap[0] + ch_cap[1]; |
| 2795 | if (params->base.num_channels == 1) { |
| 2796 | if (chinfo & 1) /* channel a only */ |
| 2797 | stride = 0x17; |
| 2798 | else /* channel b only */ |
| 2799 | stride = 0x18; |
| 2800 | } else {/* 2 channel */ |
| 2801 | if (ch_cap[0] == ch_cap[1]) { |
| 2802 | /* interleaved */ |
| 2803 | if (gstride_type == PART_STRIDE) { |
| 2804 | /* |
| 2805 | * first 64MB no interleaved other 256B interleaved |
| 2806 | * if 786M+768M.useful space from 0-1280MB and |
| 2807 | * 1536MB-1792MB |
| 2808 | * if 1.5G+1.5G(continuous).useful space from 0-2560MB |
| 2809 | * and 3072MB-3584MB |
| 2810 | */ |
| 2811 | stride = 0x1F; |
| 2812 | } else { |
| 2813 | switch (cap) { |
| 2814 | /* 512MB */ |
| 2815 | case 512: |
| 2816 | stride = 0; |
| 2817 | break; |
| 2818 | /* 1GB unstride or 256B stride*/ |
| 2819 | case 1024: |
| 2820 | stride = (gstride_type == UN_STRIDE) ? |
| 2821 | 0x1 : 0x5; |
| 2822 | break; |
| 2823 | /* |
| 2824 | * 768MB + 768MB same as total 2GB memory |
| 2825 | * useful space: 0-768MB 1GB-1792MB |
| 2826 | */ |
| 2827 | case 1536: |
| 2828 | /* 2GB unstride or 256B or 512B stride */ |
| 2829 | case 2048: |
| 2830 | stride = (gstride_type == UN_STRIDE) ? |
| 2831 | 0x2 : |
| 2832 | ((gstride_type == STRIDE_512B) ? |
| 2833 | 0xA : 0x9); |
| 2834 | break; |
| 2835 | /* 1536MB + 1536MB */ |
| 2836 | case 3072: |
| 2837 | stride = (gstride_type == UN_STRIDE) ? |
| 2838 | 0x3 : |
| 2839 | ((gstride_type == STRIDE_512B) ? |
| 2840 | 0x12 : 0x11); |
| 2841 | break; |
| 2842 | /* 4GB unstride or 128B,256B,512B,4KB stride */ |
| 2843 | case 4096: |
| 2844 | stride = (gstride_type == UN_STRIDE) ? |
| 2845 | 0x3 : (0xC + gstride_type); |
| 2846 | break; |
| 2847 | } |
| 2848 | } |
| 2849 | } |
| 2850 | if (ch_cap[0] == 2048 && ch_cap[1] == 1024) { |
| 2851 | /* 2GB + 1GB */ |
| 2852 | stride = (gstride_type == UN_STRIDE) ? 0x3 : 0x19; |
| 2853 | } |
Jagan Teki | 2525fae | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 2854 | /* |
Kever Yang | e2b64fd | 2019-11-15 11:04:52 +0800 | [diff] [blame] | 2855 | * remain two channel capability not equal OR capability |
| 2856 | * power function of 2 |
Jagan Teki | 2525fae | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 2857 | */ |
Kever Yang | e2b64fd | 2019-11-15 11:04:52 +0800 | [diff] [blame] | 2858 | if (stride == (-1)) { |
| 2859 | switch ((ch_cap[0] > ch_cap[1]) ? |
| 2860 | ch_cap[0] : ch_cap[1]) { |
| 2861 | case 256: /* 256MB + 128MB */ |
| 2862 | stride = 0; |
| 2863 | break; |
| 2864 | case 512: /* 512MB + 256MB */ |
| 2865 | stride = 1; |
| 2866 | break; |
| 2867 | case 1024:/* 1GB + 128MB/256MB/384MB/512MB/768MB */ |
| 2868 | stride = 2; |
| 2869 | break; |
| 2870 | case 2048: /* 2GB + 128MB/256MB/384MB/512MB/768MB/1GB */ |
| 2871 | stride = 3; |
| 2872 | break; |
| 2873 | default: |
| 2874 | break; |
| 2875 | } |
Jagan Teki | 2525fae | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 2876 | } |
Kever Yang | e2b64fd | 2019-11-15 11:04:52 +0800 | [diff] [blame] | 2877 | if (stride == (-1)) |
| 2878 | goto error; |
| 2879 | } |
Jagan Teki | 2525fae | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 2880 | |
Jagan Teki | 8eed4a4 | 2019-07-15 23:58:55 +0530 | [diff] [blame] | 2881 | sdram_print_stride(stride); |
| 2882 | |
Jagan Teki | 2525fae | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 2883 | return stride; |
Kever Yang | e2b64fd | 2019-11-15 11:04:52 +0800 | [diff] [blame] | 2884 | error: |
| 2885 | printf("Cap not support!\n"); |
| 2886 | return (-1); |
Jagan Teki | 2525fae | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 2887 | } |
| 2888 | |
Jagan Teki | 43485e1 | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 2889 | static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel) |
| 2890 | { |
| 2891 | params->ch[channel].cap_info.rank = 0; |
| 2892 | params->ch[channel].cap_info.col = 0; |
| 2893 | params->ch[channel].cap_info.bk = 0; |
| 2894 | params->ch[channel].cap_info.bw = 32; |
| 2895 | params->ch[channel].cap_info.dbw = 32; |
| 2896 | params->ch[channel].cap_info.row_3_4 = 0; |
| 2897 | params->ch[channel].cap_info.cs0_row = 0; |
| 2898 | params->ch[channel].cap_info.cs1_row = 0; |
| 2899 | params->ch[channel].cap_info.ddrconfig = 0; |
| 2900 | } |
| 2901 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 2902 | static int sdram_init(struct dram_info *dram, |
Jagan Teki | 2525fae | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 2903 | struct rk3399_sdram_params *params) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 2904 | { |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 2905 | unsigned char dramtype = params->base.dramtype; |
| 2906 | unsigned int ddr_freq = params->base.ddr_freq; |
Jagan Teki | 43485e1 | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 2907 | int channel, ch, rank; |
YouMin Chen | 6ba388f | 2019-11-15 11:04:49 +0800 | [diff] [blame] | 2908 | u32 tmp, ret; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 2909 | |
| 2910 | debug("Starting SDRAM initialization...\n"); |
| 2911 | |
Philipp Tomsich | 39dce4a | 2017-05-31 18:16:35 +0200 | [diff] [blame] | 2912 | if ((dramtype == DDR3 && ddr_freq > 933) || |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 2913 | (dramtype == LPDDR3 && ddr_freq > 933) || |
| 2914 | (dramtype == LPDDR4 && ddr_freq > 800)) { |
| 2915 | debug("SDRAM frequency is to high!"); |
| 2916 | return -E2BIG; |
| 2917 | } |
| 2918 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 2919 | /* detect rank */ |
Jagan Teki | 43485e1 | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 2920 | for (ch = 0; ch < 2; ch++) { |
| 2921 | params->ch[ch].cap_info.rank = 2; |
| 2922 | for (rank = 2; rank != 0; rank--) { |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 2923 | for (channel = 0; channel < 2; channel++) { |
| 2924 | const struct chan_info *chan = |
| 2925 | &dram->chan[channel]; |
Jagan Teki | 783acfd | 2020-01-09 14:22:17 +0530 | [diff] [blame] | 2926 | struct rockchip_cru *cru = dram->cru; |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 2927 | struct rk3399_ddr_publ_regs *publ = chan->publ; |
| 2928 | |
| 2929 | phy_pctrl_reset(cru, channel); |
| 2930 | phy_dll_bypass_set(publ, ddr_freq); |
| 2931 | pctl_cfg(dram, chan, channel, params); |
Jagan Teki | 43485e1 | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 2932 | } |
| 2933 | |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 2934 | /* start to trigger initialization */ |
| 2935 | pctl_start(dram, params, 3); |
| 2936 | |
Jagan Teki | 43485e1 | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 2937 | /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ |
| 2938 | if (dramtype == LPDDR3) |
| 2939 | udelay(10); |
| 2940 | |
YouMin Chen | 6ba388f | 2019-11-15 11:04:49 +0800 | [diff] [blame] | 2941 | tmp = (rank == 2) ? 3 : 1; |
| 2942 | dram_set_cs(&dram->chan[ch], tmp, 2048, |
| 2943 | params->base.dramtype); |
Jagan Teki | 43485e1 | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 2944 | params->ch[ch].cap_info.rank = rank; |
| 2945 | |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 2946 | ret = dram->ops->data_training_first(dram, ch, |
| 2947 | rank, params); |
Jagan Teki | 9eb935a | 2019-07-16 17:27:30 +0530 | [diff] [blame] | 2948 | if (!ret) { |
| 2949 | debug("%s: data trained for rank %d, ch %d\n", |
| 2950 | __func__, rank, ch); |
Jagan Teki | 43485e1 | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 2951 | break; |
Jagan Teki | 9eb935a | 2019-07-16 17:27:30 +0530 | [diff] [blame] | 2952 | } |
Jagan Teki | 43485e1 | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 2953 | } |
| 2954 | /* Computed rank with associated channel number */ |
| 2955 | params->ch[ch].cap_info.rank = rank; |
| 2956 | } |
| 2957 | |
| 2958 | params->base.num_channels = 0; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 2959 | for (channel = 0; channel < 2; channel++) { |
| 2960 | const struct chan_info *chan = &dram->chan[channel]; |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 2961 | struct sdram_cap_info *cap_info = |
| 2962 | ¶ms->ch[channel].cap_info; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 2963 | |
Jagan Teki | 43485e1 | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 2964 | if (cap_info->rank == 0) { |
YouMin Chen | 6ba388f | 2019-11-15 11:04:49 +0800 | [diff] [blame] | 2965 | clear_channel_params(params, 1); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 2966 | continue; |
Jagan Teki | 43485e1 | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 2967 | } else { |
| 2968 | params->base.num_channels++; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 2969 | } |
| 2970 | |
Jagan Teki | 57bd887 | 2020-07-14 01:36:34 +0530 | [diff] [blame] | 2971 | if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) { |
| 2972 | printf("Channel "); |
| 2973 | printf(channel ? "1: " : "0: "); |
| 2974 | } |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 2975 | |
YouMin Chen | 6ba388f | 2019-11-15 11:04:49 +0800 | [diff] [blame] | 2976 | if (channel == 0) |
| 2977 | set_ddr_stride(dram->pmusgrf, 0x17); |
| 2978 | else |
| 2979 | set_ddr_stride(dram->pmusgrf, 0x18); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 2980 | |
YouMin Chen | 6ba388f | 2019-11-15 11:04:49 +0800 | [diff] [blame] | 2981 | if (dram_detect_cap(dram, params, channel)) { |
| 2982 | printf("Cap error!\n"); |
| 2983 | continue; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 2984 | } |
| 2985 | |
Jagan Teki | 8eed4a4 | 2019-07-15 23:58:55 +0530 | [diff] [blame] | 2986 | sdram_print_ddr_info(cap_info, ¶ms->base); |
Kever Yang | e723a55 | 2019-08-12 20:02:29 +0800 | [diff] [blame] | 2987 | set_memory_map(chan, channel, params); |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 2988 | cap_info->ddrconfig = |
| 2989 | calculate_ddrconfig(params, channel); |
| 2990 | if (-1 == cap_info->ddrconfig) { |
| 2991 | printf("no ddrconfig find, Cap not support!\n"); |
| 2992 | continue; |
| 2993 | } |
Jagan Teki | 43485e1 | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 2994 | set_ddrconfig(chan, params, channel, cap_info->ddrconfig); |
Kever Yang | e723a55 | 2019-08-12 20:02:29 +0800 | [diff] [blame] | 2995 | set_cap_relate_config(chan, params, channel); |
Jagan Teki | 43485e1 | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 2996 | } |
| 2997 | |
| 2998 | if (params->base.num_channels == 0) { |
| 2999 | printf("%s: ", __func__); |
Jagan Teki | 8eed4a4 | 2019-07-15 23:58:55 +0530 | [diff] [blame] | 3000 | sdram_print_dram_type(params->base.dramtype); |
Jagan Teki | 43485e1 | 2019-07-15 23:58:54 +0530 | [diff] [blame] | 3001 | printf(" - %dMHz failed!\n", params->base.ddr_freq); |
| 3002 | return -EINVAL; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3003 | } |
Jagan Teki | 2525fae | 2019-07-15 23:58:52 +0530 | [diff] [blame] | 3004 | |
| 3005 | params->base.stride = calculate_stride(params); |
Jagan Teki | a58ff79 | 2019-07-15 23:50:58 +0530 | [diff] [blame] | 3006 | dram_all_config(dram, params); |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 3007 | |
| 3008 | dram->ops->set_rate_index(dram, params); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3009 | |
| 3010 | debug("Finish SDRAM initialization...\n"); |
| 3011 | return 0; |
| 3012 | } |
| 3013 | |
| 3014 | static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev) |
| 3015 | { |
| 3016 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
| 3017 | struct rockchip_dmc_plat *plat = dev_get_platdata(dev); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3018 | int ret; |
| 3019 | |
Philipp Tomsich | 0250c23 | 2017-06-07 18:46:03 +0200 | [diff] [blame] | 3020 | ret = dev_read_u32_array(dev, "rockchip,sdram-params", |
| 3021 | (u32 *)&plat->sdram_params, |
| 3022 | sizeof(plat->sdram_params) / sizeof(u32)); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3023 | if (ret) { |
| 3024 | printf("%s: Cannot read rockchip,sdram-params %d\n", |
| 3025 | __func__, ret); |
| 3026 | return ret; |
| 3027 | } |
Masahiro Yamada | e4873e3 | 2018-04-19 12:14:03 +0900 | [diff] [blame] | 3028 | ret = regmap_init_mem(dev_ofnode(dev), &plat->map); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3029 | if (ret) |
| 3030 | printf("%s: regmap failed %d\n", __func__, ret); |
| 3031 | |
| 3032 | #endif |
| 3033 | return 0; |
| 3034 | } |
| 3035 | |
| 3036 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
| 3037 | static int conv_of_platdata(struct udevice *dev) |
| 3038 | { |
| 3039 | struct rockchip_dmc_plat *plat = dev_get_platdata(dev); |
| 3040 | struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; |
| 3041 | int ret; |
| 3042 | |
| 3043 | ret = regmap_init_mem_platdata(dev, dtplat->reg, |
Jagan Teki | f676c7c | 2019-07-15 23:50:56 +0530 | [diff] [blame] | 3044 | ARRAY_SIZE(dtplat->reg) / 2, |
| 3045 | &plat->map); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3046 | if (ret) |
| 3047 | return ret; |
| 3048 | |
| 3049 | return 0; |
| 3050 | } |
| 3051 | #endif |
| 3052 | |
Jagan Teki | 9eb935a | 2019-07-16 17:27:30 +0530 | [diff] [blame] | 3053 | static const struct sdram_rk3399_ops rk3399_ops = { |
Jagan Teki | cc117bb | 2019-07-16 17:27:31 +0530 | [diff] [blame] | 3054 | #if !defined(CONFIG_RAM_RK3399_LPDDR4) |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 3055 | .data_training_first = data_training_first, |
| 3056 | .set_rate_index = switch_to_phy_index1, |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 3057 | .modify_param = modify_param, |
| 3058 | .get_phy_index_params = get_phy_index_params, |
Jagan Teki | cc117bb | 2019-07-16 17:27:31 +0530 | [diff] [blame] | 3059 | #else |
YouMin Chen | de57fbf | 2019-11-15 11:04:46 +0800 | [diff] [blame] | 3060 | .data_training_first = lpddr4_mr_detect, |
| 3061 | .set_rate_index = lpddr4_set_rate, |
YouMin Chen | 9902737 | 2019-11-15 11:04:48 +0800 | [diff] [blame] | 3062 | .modify_param = lpddr4_modify_param, |
| 3063 | .get_phy_index_params = lpddr4_get_phy_index_params, |
Jagan Teki | cc117bb | 2019-07-16 17:27:31 +0530 | [diff] [blame] | 3064 | #endif |
Jagan Teki | 9eb935a | 2019-07-16 17:27:30 +0530 | [diff] [blame] | 3065 | }; |
| 3066 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3067 | static int rk3399_dmc_init(struct udevice *dev) |
| 3068 | { |
| 3069 | struct dram_info *priv = dev_get_priv(dev); |
| 3070 | struct rockchip_dmc_plat *plat = dev_get_platdata(dev); |
| 3071 | int ret; |
| 3072 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
| 3073 | struct rk3399_sdram_params *params = &plat->sdram_params; |
| 3074 | #else |
| 3075 | struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; |
| 3076 | struct rk3399_sdram_params *params = |
| 3077 | (void *)dtplat->rockchip_sdram_params; |
| 3078 | |
| 3079 | ret = conv_of_platdata(dev); |
| 3080 | if (ret) |
| 3081 | return ret; |
| 3082 | #endif |
| 3083 | |
Jagan Teki | 9eb935a | 2019-07-16 17:27:30 +0530 | [diff] [blame] | 3084 | priv->ops = &rk3399_ops; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3085 | priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC); |
Jagan Teki | c9151e2 | 2019-07-15 23:58:45 +0530 | [diff] [blame] | 3086 | priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 3087 | priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3088 | priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); |
| 3089 | priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); |
| 3090 | priv->pmucru = rockchip_get_pmucru(); |
| 3091 | priv->cru = rockchip_get_cru(); |
| 3092 | priv->chan[0].pctl = regmap_get_range(plat->map, 0); |
| 3093 | priv->chan[0].pi = regmap_get_range(plat->map, 1); |
| 3094 | priv->chan[0].publ = regmap_get_range(plat->map, 2); |
| 3095 | priv->chan[0].msch = regmap_get_range(plat->map, 3); |
| 3096 | priv->chan[1].pctl = regmap_get_range(plat->map, 4); |
| 3097 | priv->chan[1].pi = regmap_get_range(plat->map, 5); |
| 3098 | priv->chan[1].publ = regmap_get_range(plat->map, 6); |
| 3099 | priv->chan[1].msch = regmap_get_range(plat->map, 7); |
| 3100 | |
| 3101 | debug("con reg %p %p %p %p %p %p %p %p\n", |
| 3102 | priv->chan[0].pctl, priv->chan[0].pi, |
| 3103 | priv->chan[0].publ, priv->chan[0].msch, |
| 3104 | priv->chan[1].pctl, priv->chan[1].pi, |
| 3105 | priv->chan[1].publ, priv->chan[1].msch); |
Jagan Teki | 6ea8269 | 2019-07-16 17:27:40 +0530 | [diff] [blame] | 3106 | debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p, pmu %p\n", priv->cru, |
| 3107 | priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu); |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 3108 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3109 | #if CONFIG_IS_ENABLED(OF_PLATDATA) |
Walter Lozano | dc5b437 | 2020-06-25 01:10:13 -0300 | [diff] [blame] | 3110 | ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->ddr_clk); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3111 | #else |
| 3112 | ret = clk_get_by_index(dev, 0, &priv->ddr_clk); |
| 3113 | #endif |
| 3114 | if (ret) { |
| 3115 | printf("%s clk get failed %d\n", __func__, ret); |
| 3116 | return ret; |
| 3117 | } |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 3118 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3119 | ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz); |
| 3120 | if (ret < 0) { |
| 3121 | printf("%s clk set failed %d\n", __func__, ret); |
| 3122 | return ret; |
| 3123 | } |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 3124 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3125 | ret = sdram_init(priv, params); |
| 3126 | if (ret < 0) { |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 3127 | printf("%s DRAM init failed %d\n", __func__, ret); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3128 | return ret; |
| 3129 | } |
| 3130 | |
| 3131 | return 0; |
| 3132 | } |
| 3133 | #endif |
| 3134 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3135 | static int rk3399_dmc_probe(struct udevice *dev) |
| 3136 | { |
Kever Yang | 7f34784 | 2019-04-01 17:20:53 +0800 | [diff] [blame] | 3137 | #if defined(CONFIG_TPL_BUILD) || \ |
| 3138 | (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3139 | if (rk3399_dmc_init(dev)) |
| 3140 | return 0; |
| 3141 | #else |
| 3142 | struct dram_info *priv = dev_get_priv(dev); |
| 3143 | |
| 3144 | priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); |
Jagan Teki | acf8e0f | 2019-07-15 23:50:57 +0530 | [diff] [blame] | 3145 | debug("%s: pmugrf = %p\n", __func__, priv->pmugrf); |
Kever Yang | 6c15a54 | 2017-06-23 16:11:06 +0800 | [diff] [blame] | 3146 | priv->info.base = CONFIG_SYS_SDRAM_BASE; |
Jagan Teki | f676c7c | 2019-07-15 23:50:56 +0530 | [diff] [blame] | 3147 | priv->info.size = |
| 3148 | rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2); |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3149 | #endif |
| 3150 | return 0; |
| 3151 | } |
| 3152 | |
| 3153 | static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info) |
| 3154 | { |
| 3155 | struct dram_info *priv = dev_get_priv(dev); |
| 3156 | |
Kever Yang | ea61d14 | 2017-04-19 16:01:14 +0800 | [diff] [blame] | 3157 | *info = priv->info; |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3158 | |
| 3159 | return 0; |
| 3160 | } |
| 3161 | |
| 3162 | static struct ram_ops rk3399_dmc_ops = { |
| 3163 | .get_info = rk3399_dmc_get_info, |
| 3164 | }; |
| 3165 | |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3166 | static const struct udevice_id rk3399_dmc_ids[] = { |
| 3167 | { .compatible = "rockchip,rk3399-dmc" }, |
| 3168 | { } |
| 3169 | }; |
| 3170 | |
| 3171 | U_BOOT_DRIVER(dmc_rk3399) = { |
| 3172 | .name = "rockchip_rk3399_dmc", |
| 3173 | .id = UCLASS_RAM, |
| 3174 | .of_match = rk3399_dmc_ids, |
| 3175 | .ops = &rk3399_dmc_ops, |
Kever Yang | 7f34784 | 2019-04-01 17:20:53 +0800 | [diff] [blame] | 3176 | #if defined(CONFIG_TPL_BUILD) || \ |
| 3177 | (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3178 | .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata, |
| 3179 | #endif |
| 3180 | .probe = rk3399_dmc_probe, |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3181 | .priv_auto_alloc_size = sizeof(struct dram_info), |
Kever Yang | 7f34784 | 2019-04-01 17:20:53 +0800 | [diff] [blame] | 3182 | #if defined(CONFIG_TPL_BUILD) || \ |
| 3183 | (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) |
Kever Yang | 50fb998 | 2017-02-22 16:56:35 +0800 | [diff] [blame] | 3184 | .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat), |
| 3185 | #endif |
| 3186 | }; |