commit 9d8769c67c2e3128f54962e5720ca2925d77de5f
author Jagan Teki <jagan@amarulasolutions.com> Tue Jul 16 17:27:01 2019 +0530
committer Kever Yang <kever.yang@rock-chips.com> Sat Jul 20 23:59:44 2019 +0800
tree 02ae2d608cb709610b26a1e605285273c8d27cb3
parent 2d337120307ffcac84b2a34f89a482376646dabb

ram: rk3399: Introduce sys_reg3 for more capacity info

cs0_row, cs1_row and cs1_col needs more bits to show its
correct value, update to make use of both sys_reg2,
sys_reg3.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
(Squash similar patches into one patch)
Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>

drivers/ram/rockchip/sdram_rk3399.c

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 38ae6d1..fed9f94 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1074,6 +1074,7 @@
 			    const struct rk3399_sdram_params *params)
 {
 	u32 sys_reg2 = 0;
+	u32 sys_reg3 = 0;
 	unsigned int channel, idx;
 
 	sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);
@@ -1094,10 +1095,13 @@
 		sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
 		sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel);
 		sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
-		sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel);
-		sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel);
 		sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
 		sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
+		SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel);
+		if (info->cap_info.cs1_row)
+			SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
+					    sys_reg3, channel);
+		sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel);
 
 		ddr_msch_regs = dram->chan[channel].msch;
 		noc_timing = &params->ch[channel].noc_timings;
@@ -1119,6 +1123,7 @@
 	}
 
 	writel(sys_reg2, &dram->pmugrf->os_reg2);
+	writel(sys_reg3, &dram->pmugrf->os_reg3);
 	rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
 		     params->base.stride << 10);