arm: rockchip: Add common cru.h
Few of the rockchip family SoC atleast rk3288,
rk3399 are sharing some cru register bits so
adding common code between these SoC families
would require to include both cru include files
that indeed resulting function declarations error.
So, create a common cru include as cru.h then
include the rk3399 arch cru include file and move
the common cru register bit definitions into it.
The rest of rockchip cru files will add it in future.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 9c276e1..d69ef01 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -14,7 +14,7 @@
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3399.h>
+#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/pmu_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
@@ -66,7 +66,7 @@
u32 pwrup_srefresh_exit[2];
struct chan_info chan[2];
struct clk ddr_clk;
- struct rk3399_cru *cru;
+ struct rockchip_cru *cru;
struct rk3399_grf_regs *grf;
struct rk3399_pmu_regs *pmu;
struct rk3399_pmucru *pmucru;
@@ -228,7 +228,7 @@
return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc1_con0;
}
-static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
+static void rkclk_ddr_reset(struct rockchip_cru *cru, u32 channel, u32 ctl,
u32 phy)
{
channel &= 0x1;
@@ -239,7 +239,7 @@
&cru->softrst_con[4]);
}
-static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel)
+static void phy_pctrl_reset(struct rockchip_cru *cru, u32 channel)
{
rkclk_ddr_reset(cru, channel, 1, 1);
udelay(10);
@@ -2943,7 +2943,7 @@
for (channel = 0; channel < 2; channel++) {
const struct chan_info *chan =
&dram->chan[channel];
- struct rk3399_cru *cru = dram->cru;
+ struct rockchip_cru *cru = dram->cru;
struct rk3399_ddr_publ_regs *publ = chan->publ;
phy_pctrl_reset(cru, channel);