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York Sunb3d71642016-09-26 08:09:26 -07001config ARCH_LS1012A
York Sunfcd0e742016-10-04 14:31:47 -07002 bool
York Sun4dd8c612016-10-04 14:31:48 -07003 select FSL_LSCH2
York Sunb6fffd82016-10-04 18:03:08 -07004 select SYS_FSL_DDR_BE
York Sunb3d71642016-09-26 08:09:26 -07005 select SYS_FSL_MMDC
York Sun149eb332016-09-26 08:09:27 -07006 select SYS_FSL_ERRATUM_A010315
7
8config ARCH_LS1043A
York Sunfcd0e742016-10-04 14:31:47 -07009 bool
York Sun4dd8c612016-10-04 14:31:48 -070010 select FSL_LSCH2
York Sund297d392016-12-28 08:43:40 -080011 select SYS_FSL_DDR
York Sunb6fffd82016-10-04 18:03:08 -070012 select SYS_FSL_DDR_BE
13 select SYS_FSL_DDR_VER_50
York Sun1dc61ca2016-12-28 08:43:41 -080014 select SYS_FSL_ERRATUM_A008850
15 select SYS_FSL_ERRATUM_A009660
16 select SYS_FSL_ERRATUM_A009663
17 select SYS_FSL_ERRATUM_A009929
18 select SYS_FSL_ERRATUM_A009942
York Sun149eb332016-09-26 08:09:27 -070019 select SYS_FSL_ERRATUM_A010315
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +080020 select SYS_FSL_ERRATUM_A010539
York Sund297d392016-12-28 08:43:40 -080021 select SYS_FSL_HAS_DDR3
22 select SYS_FSL_HAS_DDR4
York Sunb3d71642016-09-26 08:09:26 -070023
York Sunbad49842016-09-26 08:09:24 -070024config ARCH_LS1046A
York Sunfcd0e742016-10-04 14:31:47 -070025 bool
York Sun4dd8c612016-10-04 14:31:48 -070026 select FSL_LSCH2
York Sund297d392016-12-28 08:43:40 -080027 select SYS_FSL_DDR
York Sunb6fffd82016-10-04 18:03:08 -070028 select SYS_FSL_DDR_BE
York Sunb6fffd82016-10-04 18:03:08 -070029 select SYS_FSL_DDR_VER_50
York Sun1dc61ca2016-12-28 08:43:41 -080030 select SYS_FSL_ERRATUM_A008511
31 select SYS_FSL_ERRATUM_A009801
32 select SYS_FSL_ERRATUM_A009803
33 select SYS_FSL_ERRATUM_A009942
34 select SYS_FSL_ERRATUM_A010165
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +080035 select SYS_FSL_ERRATUM_A010539
York Sund297d392016-12-28 08:43:40 -080036 select SYS_FSL_HAS_DDR4
York Sun6b62ef02016-10-04 18:01:34 -070037 select SYS_FSL_SRDS_2
York Sunb3d71642016-09-26 08:09:26 -070038
York Sunfcd0e742016-10-04 14:31:47 -070039config ARCH_LS2080A
40 bool
York Sun4dd8c612016-10-04 14:31:48 -070041 select FSL_LSCH3
York Sund297d392016-12-28 08:43:40 -080042 select SYS_FSL_DDR
York Sunb6fffd82016-10-04 18:03:08 -070043 select SYS_FSL_DDR_LE
44 select SYS_FSL_DDR_VER_50
York Sun6b62ef02016-10-04 18:01:34 -070045 select SYS_FSL_HAS_DP_DDR
York Sun92c36e22016-12-28 08:43:30 -080046 select SYS_FSL_HAS_SEC
York Sund297d392016-12-28 08:43:40 -080047 select SYS_FSL_HAS_DDR4
York Sun92c36e22016-12-28 08:43:30 -080048 select SYS_FSL_SEC_COMPAT_5
York Sunfa4199422016-12-28 08:43:31 -080049 select SYS_FSL_SEC_LE
York Sun6b62ef02016-10-04 18:01:34 -070050 select SYS_FSL_SRDS_2
York Sun1dc61ca2016-12-28 08:43:41 -080051 select SYS_FSL_ERRATUM_A008336
52 select SYS_FSL_ERRATUM_A008511
53 select SYS_FSL_ERRATUM_A008514
54 select SYS_FSL_ERRATUM_A008585
55 select SYS_FSL_ERRATUM_A009635
56 select SYS_FSL_ERRATUM_A009663
57 select SYS_FSL_ERRATUM_A009801
58 select SYS_FSL_ERRATUM_A009803
59 select SYS_FSL_ERRATUM_A009942
60 select SYS_FSL_ERRATUM_A010165
York Sun4dd8c612016-10-04 14:31:48 -070061
62config FSL_LSCH2
63 bool
York Sun92c36e22016-12-28 08:43:30 -080064 select SYS_FSL_HAS_SEC
65 select SYS_FSL_SEC_COMPAT_5
York Sunfa4199422016-12-28 08:43:31 -080066 select SYS_FSL_SEC_BE
York Sun6b62ef02016-10-04 18:01:34 -070067 select SYS_FSL_SRDS_1
68 select SYS_HAS_SERDES
York Sun4dd8c612016-10-04 14:31:48 -070069
70config FSL_LSCH3
71 bool
York Sun6b62ef02016-10-04 18:01:34 -070072 select SYS_FSL_SRDS_1
73 select SYS_HAS_SERDES
York Sun4dd8c612016-10-04 14:31:48 -070074
75menu "Layerscape architecture"
76 depends on FSL_LSCH2 || FSL_LSCH3
York Sunfcd0e742016-10-04 14:31:47 -070077
Hou Zhiqiangd553bf22016-12-13 14:54:24 +080078config FSL_PCIE_COMPAT
79 string "PCIe compatible of Kernel DT"
80 depends on PCIE_LAYERSCAPE
81 default "fsl,ls1012a-pcie" if ARCH_LS1012A
82 default "fsl,ls1043a-pcie" if ARCH_LS1043A
83 default "fsl,ls1046a-pcie" if ARCH_LS1046A
84 default "fsl,ls2080a-pcie" if ARCH_LS2080A
85 help
86 This compatible is used to find pci controller node in Kernel DT
87 to complete fixup.
88
macro.wave.z@gmail.comec2d7ed2016-12-08 11:58:21 +080089menu "Layerscape PPA"
90config FSL_LS_PPA
91 bool "FSL Layerscape PPA firmware support"
macro.wave.z@gmail.com01bd3342016-12-08 11:58:22 +080092 depends on !ARMV8_PSCI
macro.wave.z@gmail.comec2d7ed2016-12-08 11:58:21 +080093 depends on ARCH_LS1043A || ARCH_LS1046A
94 select FSL_PPA_ARMV8_PSCI
95 help
96 The FSL Primary Protected Application (PPA) is a software component
97 which is loaded during boot stage, and then remains resident in RAM
98 and runs in the TrustZone after boot.
99 Say y to enable it.
100
101config FSL_PPA_ARMV8_PSCI
102 bool "PSCI implementation in PPA firmware"
103 depends on FSL_LS_PPA
104 help
105 This config enables the ARMv8 PSCI implementation in PPA firmware.
106 This is a private PSCI implementation and different from those
107 implemented under the common ARMv8 PSCI framework.
108endmenu
109
York Sun149eb332016-09-26 08:09:27 -0700110config SYS_FSL_ERRATUM_A010315
111 bool "Workaround for PCIe erratum A010315"
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800112
113config SYS_FSL_ERRATUM_A010539
114 bool "Workaround for PIN MUX erratum A010539"
York Sun4dd8c612016-10-04 14:31:48 -0700115
York Sunf188d222016-10-04 14:45:01 -0700116config MAX_CPUS
117 int "Maximum number of CPUs permitted for Layerscape"
118 default 4 if ARCH_LS1043A
119 default 4 if ARCH_LS1046A
120 default 16 if ARCH_LS2080A
121 default 1
122 help
123 Set this number to the maximum number of possible CPUs in the SoC.
124 SoCs may have multiple clusters with each cluster may have multiple
125 ports. If some ports are reserved but higher ports are used for
126 cores, count the reserved ports. This will allocate enough memory
127 in spin table to properly handle all cores.
128
York Sun728e7002016-12-02 09:32:35 -0800129config SECURE_BOOT
130 bool
131 help
132 Enable Freescale Secure Boot feature
133
Yuan Yao52ae4fd2016-12-01 10:13:52 +0800134config QSPI_AHB_INIT
135 bool "Init the QSPI AHB bus"
136 help
137 The default setting for QSPI AHB bus just support 3bytes addressing.
138 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
139 bus for those flashes to support the full QSPI flash size.
140
York Sune7310a32016-10-04 14:45:54 -0700141config SYS_FSL_IFC_BANK_COUNT
142 int "Maximum banks of Integrated flash controller"
143 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
144 default 4 if ARCH_LS1043A
145 default 4 if ARCH_LS1046A
146 default 8 if ARCH_LS2080A
147
York Sun0dc9abb2016-10-04 14:46:50 -0700148config SYS_FSL_HAS_DP_DDR
149 bool
150
York Sun6b62ef02016-10-04 18:01:34 -0700151config SYS_FSL_SRDS_1
152 bool
153
154config SYS_FSL_SRDS_2
155 bool
156
157config SYS_HAS_SERDES
158 bool
159
York Sun4dd8c612016-10-04 14:31:48 -0700160endmenu
York Sun1dc61ca2016-12-28 08:43:41 -0800161
162config SYS_FSL_ERRATUM_A008336
163 bool
164
165config SYS_FSL_ERRATUM_A008514
166 bool
167
168config SYS_FSL_ERRATUM_A008585
169 bool
170
171config SYS_FSL_ERRATUM_A008850
172 bool
173
174config SYS_FSL_ERRATUM_A009635
175 bool
176
177config SYS_FSL_ERRATUM_A009660
178 bool
179
180config SYS_FSL_ERRATUM_A009929
181 bool