Masahiro Yamada | cc85b7b | 2015-07-26 02:46:26 +0900 | [diff] [blame] | 1 | # |
| 2 | # I2C subsystem configuration |
| 3 | # |
| 4 | |
| 5 | menu "I2C support" |
| 6 | |
Masahiro Yamada | cd5cf8e | 2015-01-13 12:44:35 +0900 | [diff] [blame] | 7 | config DM_I2C |
| 8 | bool "Enable Driver Model for I2C drivers" |
| 9 | depends on DM |
| 10 | help |
Przemyslaw Marczak | e5fa121 | 2015-03-31 18:57:17 +0200 | [diff] [blame] | 11 | Enable driver model for I2C. The I2C uclass interface: probe, read, |
| 12 | write and speed, is implemented with the bus drivers operations, |
| 13 | which provide methods for bus setting and data transfer. Each chip |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 14 | device (bus child) info is kept as parent plat. The interface |
Bartosz Golaszewski | 1e4450c | 2019-07-29 08:58:00 +0200 | [diff] [blame] | 15 | is defined in include/i2c.h. |
Simon Glass | e200ee2 | 2015-02-13 12:20:48 -0700 | [diff] [blame] | 16 | |
Simon Glass | 9ad07af | 2015-08-03 08:19:23 -0600 | [diff] [blame] | 17 | config I2C_CROS_EC_TUNNEL |
| 18 | tristate "Chrome OS EC tunnel I2C bus" |
| 19 | depends on CROS_EC |
| 20 | help |
| 21 | This provides an I2C bus that will tunnel i2c commands through to |
| 22 | the other side of the Chrome OS EC to the I2C bus connected there. |
| 23 | This will work whatever the interface used to talk to the EC (SPI, |
| 24 | I2C or LPC). Some Chromebooks use this when the hardware design |
| 25 | does not allow direct access to the main PMIC from the AP. |
| 26 | |
Simon Glass | eb2cc51 | 2015-08-03 08:19:24 -0600 | [diff] [blame] | 27 | config I2C_CROS_EC_LDO |
| 28 | bool "Provide access to LDOs on the Chrome OS EC" |
| 29 | depends on CROS_EC |
| 30 | ---help--- |
| 31 | On many Chromebooks the main PMIC is inaccessible to the AP. This is |
| 32 | often dealt with by using an I2C pass-through interface provided by |
| 33 | the EC. On some unfortunate models (e.g. Spring) the pass-through |
| 34 | is not available, and an LDO message is available instead. This |
| 35 | option enables a driver which provides very basic access to those |
| 36 | regulators, via the EC. We implement this as an I2C bus which |
| 37 | emulates just the TPS65090 messages we know about. This is done to |
| 38 | avoid duplicating the logic in the TPS65090 regulator driver for |
| 39 | enabling/disabling an LDO. |
Simon Glass | 9ad07af | 2015-08-03 08:19:23 -0600 | [diff] [blame] | 40 | |
Lukasz Majewski | 0a55627 | 2017-03-21 12:08:25 +0100 | [diff] [blame] | 41 | config I2C_SET_DEFAULT_BUS_NUM |
| 42 | bool "Set default I2C bus number" |
| 43 | depends on DM_I2C |
| 44 | help |
| 45 | Set default number of I2C bus to be accessed. This option provides |
| 46 | behaviour similar to old (i.e. pre DM) I2C bus driver. |
| 47 | |
| 48 | config I2C_DEFAULT_BUS_NUMBER |
| 49 | hex "I2C default bus number" |
| 50 | depends on I2C_SET_DEFAULT_BUS_NUM |
| 51 | default 0x0 |
| 52 | help |
| 53 | Number of default I2C bus to use |
| 54 | |
Przemyslaw Marczak | d3aa7e1 | 2015-03-31 18:57:18 +0200 | [diff] [blame] | 55 | config DM_I2C_GPIO |
| 56 | bool "Enable Driver Model for software emulated I2C bus driver" |
| 57 | depends on DM_I2C && DM_GPIO |
| 58 | help |
| 59 | Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO |
| 60 | configuration is given by the device tree. Kernel-style device tree |
| 61 | bindings are supported. |
| 62 | Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt |
| 63 | |
Songjun Wu | 26d8828 | 2016-06-20 13:22:38 +0800 | [diff] [blame] | 64 | config SYS_I2C_AT91 |
| 65 | bool "Atmel I2C driver" |
| 66 | depends on DM_I2C && ARCH_AT91 |
| 67 | help |
| 68 | Add support for the Atmel I2C driver. A serious problem is that there |
| 69 | is no documented way to issue repeated START conditions for more than |
| 70 | two messages, as needed to support combined I2C messages. Use the |
| 71 | i2c-gpio driver unless your system can cope with this limitation. |
| 72 | Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt |
| 73 | |
Rayagonda Kokatanur | d5dc36f | 2020-04-08 11:12:27 +0530 | [diff] [blame] | 74 | config SYS_I2C_IPROC |
| 75 | bool "Broadcom I2C driver" |
| 76 | depends on DM_I2C |
| 77 | help |
| 78 | Broadcom I2C driver. |
| 79 | Add support for Broadcom I2C driver. |
| 80 | Say yes here to to enable the Broadco I2C driver. |
| 81 | |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 82 | config SYS_I2C_FSL |
| 83 | bool "Freescale I2C bus driver" |
| 84 | depends on DM_I2C |
| 85 | help |
| 86 | Add support for Freescale I2C busses as used on MPC8240, MPC8245, and |
| 87 | MPC85xx processors. |
| 88 | |
Moritz Fischer | 0075dac | 2015-12-28 09:47:11 -0800 | [diff] [blame] | 89 | config SYS_I2C_CADENCE |
| 90 | tristate "Cadence I2C Controller" |
Michal Simek | c28665d | 2020-08-06 15:18:36 +0200 | [diff] [blame] | 91 | depends on DM_I2C |
Moritz Fischer | 0075dac | 2015-12-28 09:47:11 -0800 | [diff] [blame] | 92 | help |
| 93 | Say yes here to select Cadence I2C Host Controller. This controller is |
| 94 | e.g. used by Xilinx Zynq. |
| 95 | |
Arthur Li | fe661ba | 2020-06-01 12:56:31 -0700 | [diff] [blame] | 96 | config SYS_I2C_CA |
| 97 | tristate "Cortina-Access I2C Controller" |
| 98 | depends on DM_I2C && CORTINA_PLATFORM |
| 99 | default n |
| 100 | help |
| 101 | Add support for the Cortina Access I2C host controller. |
| 102 | Say yes here to select Cortina-Access I2C Host Controller. |
| 103 | |
Adam Ford | decc895 | 2018-08-10 05:05:22 -0500 | [diff] [blame] | 104 | config SYS_I2C_DAVINCI |
| 105 | bool "Davinci I2C Controller" |
| 106 | depends on (ARCH_KEYSTONE || ARCH_DAVINCI) |
| 107 | help |
| 108 | Say yes here to add support for Davinci and Keystone I2C controller |
| 109 | |
Stefan Roese | b71955f | 2016-04-28 09:47:17 +0200 | [diff] [blame] | 110 | config SYS_I2C_DW |
| 111 | bool "Designware I2C Controller" |
| 112 | default n |
| 113 | help |
| 114 | Say yes here to select the Designware I2C Host Controller. This |
| 115 | controller is used in various SoCs, e.g. the ST SPEAr, Altera |
| 116 | SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs. |
| 117 | |
Stefan Roese | 38fe7dc | 2016-04-28 09:47:19 +0200 | [diff] [blame] | 118 | config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED |
| 119 | bool "DW I2C Enable Status Register not supported" |
| 120 | depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \ |
| 121 | TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600) |
| 122 | default y |
| 123 | help |
| 124 | Some versions of the Designware I2C controller do not support the |
| 125 | enable status register. This config option can be enabled in such |
| 126 | cases. |
| 127 | |
maxims@google.com | 7f61331 | 2017-04-17 12:00:30 -0700 | [diff] [blame] | 128 | config SYS_I2C_ASPEED |
| 129 | bool "Aspeed I2C Controller" |
| 130 | depends on DM_I2C && ARCH_ASPEED |
| 131 | help |
| 132 | Say yes here to select Aspeed I2C Host Controller. The driver |
| 133 | supports AST2500 and AST2400 controllers, but is very limited. |
| 134 | Only single master mode is supported and only byte-by-byte |
| 135 | synchronous reads and writes are supported, no Pool Buffers or DMA. |
| 136 | |
Simon Glass | 5e66fdc | 2016-01-17 16:11:44 -0700 | [diff] [blame] | 137 | config SYS_I2C_INTEL |
| 138 | bool "Intel I2C/SMBUS driver" |
| 139 | depends on DM_I2C |
| 140 | help |
| 141 | Add support for the Intel SMBUS driver. So far this driver is just |
| 142 | a stub which perhaps some basic init. There is no implementation of |
| 143 | the I2C API meaning that any I2C operations will immediately fail |
| 144 | for now. |
| 145 | |
Peng Fan | d684adb | 2017-02-24 09:54:18 +0800 | [diff] [blame] | 146 | config SYS_I2C_IMX_LPI2C |
| 147 | bool "NXP i.MX LPI2C driver" |
Peng Fan | d684adb | 2017-02-24 09:54:18 +0800 | [diff] [blame] | 148 | help |
| 149 | Add support for the NXP i.MX LPI2C driver. |
| 150 | |
Beniamino Galvani | d5b199c | 2017-10-29 10:09:00 +0100 | [diff] [blame] | 151 | config SYS_I2C_MESON |
| 152 | bool "Amlogic Meson I2C driver" |
| 153 | depends on DM_I2C && ARCH_MESON |
| 154 | help |
Beniamino Galvani | 83b153d | 2017-11-26 17:40:54 +0100 | [diff] [blame] | 155 | Add support for the I2C controller available in Amlogic Meson |
| 156 | SoCs. The controller supports programmable bus speed including |
| 157 | standard (100kbits/s) and fast (400kbit/s) speed and allows the |
| 158 | software to define a flexible format of the bit streams. It has an |
| 159 | internal buffer holding up to 8 bytes for transfers and supports |
| 160 | both 7-bit and 10-bit addresses. |
Beniamino Galvani | d5b199c | 2017-10-29 10:09:00 +0100 | [diff] [blame] | 161 | |
Jagan Teki | 0aedd7f | 2016-12-06 00:00:57 +0100 | [diff] [blame] | 162 | config SYS_I2C_MXC |
Sriram Dash | 7122a0c | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 163 | bool "NXP MXC I2C driver" |
Jagan Teki | 0aedd7f | 2016-12-06 00:00:57 +0100 | [diff] [blame] | 164 | help |
Chris Packham | 94d0d3d | 2019-01-13 22:13:25 +1300 | [diff] [blame] | 165 | Add support for the NXP I2C driver. This supports up to four bus |
| 166 | channels and operating on standard mode up to 100 kbits/s and fast |
| 167 | mode up to 400 kbits/s. |
Jagan Teki | 0aedd7f | 2016-12-06 00:00:57 +0100 | [diff] [blame] | 168 | |
Trent Piepho | 92ebcba | 2019-05-08 23:30:06 +0000 | [diff] [blame] | 169 | # These settings are not used with DM_I2C, however SPL doesn't use |
| 170 | # DM_I2C even if DM_I2C is enabled, and so might use these settings even |
| 171 | # when main u-boot does not! |
| 172 | if SYS_I2C_MXC && (!DM_I2C || SPL) |
Sriram Dash | 7122a0c | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 173 | config SYS_I2C_MXC_I2C1 |
| 174 | bool "NXP MXC I2C1" |
| 175 | help |
| 176 | Add support for NXP MXC I2C Controller 1. |
| 177 | Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A |
| 178 | |
| 179 | config SYS_I2C_MXC_I2C2 |
| 180 | bool "NXP MXC I2C2" |
| 181 | help |
| 182 | Add support for NXP MXC I2C Controller 2. |
| 183 | Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A |
| 184 | |
| 185 | config SYS_I2C_MXC_I2C3 |
| 186 | bool "NXP MXC I2C3" |
| 187 | help |
| 188 | Add support for NXP MXC I2C Controller 3. |
| 189 | Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A |
| 190 | |
| 191 | config SYS_I2C_MXC_I2C4 |
| 192 | bool "NXP MXC I2C4" |
| 193 | help |
| 194 | Add support for NXP MXC I2C Controller 4. |
| 195 | Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A |
Sriram Dash | a64aa19 | 2018-02-06 11:26:31 +0530 | [diff] [blame] | 196 | |
| 197 | config SYS_I2C_MXC_I2C5 |
| 198 | bool "NXP MXC I2C5" |
| 199 | help |
| 200 | Add support for NXP MXC I2C Controller 5. |
| 201 | Required for SoCs which have I2C MXC controller 5 eg LX2160A |
| 202 | |
| 203 | config SYS_I2C_MXC_I2C6 |
| 204 | bool "NXP MXC I2C6" |
| 205 | help |
| 206 | Add support for NXP MXC I2C Controller 6. |
| 207 | Required for SoCs which have I2C MXC controller 6 eg LX2160A |
| 208 | |
| 209 | config SYS_I2C_MXC_I2C7 |
| 210 | bool "NXP MXC I2C7" |
| 211 | help |
| 212 | Add support for NXP MXC I2C Controller 7. |
| 213 | Required for SoCs which have I2C MXC controller 7 eg LX2160A |
| 214 | |
| 215 | config SYS_I2C_MXC_I2C8 |
| 216 | bool "NXP MXC I2C8" |
| 217 | help |
| 218 | Add support for NXP MXC I2C Controller 8. |
| 219 | Required for SoCs which have I2C MXC controller 8 eg LX2160A |
Sriram Dash | 7122a0c | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 220 | endif |
| 221 | |
| 222 | if SYS_I2C_MXC_I2C1 |
| 223 | config SYS_MXC_I2C1_SPEED |
| 224 | int "I2C Channel 1 speed" |
| 225 | default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU |
| 226 | default 100000 |
| 227 | help |
| 228 | MXC I2C Channel 1 speed |
| 229 | |
| 230 | config SYS_MXC_I2C1_SLAVE |
| 231 | int "I2C1 Slave" |
| 232 | default 0 |
| 233 | help |
| 234 | MXC I2C1 Slave |
| 235 | endif |
| 236 | |
| 237 | if SYS_I2C_MXC_I2C2 |
| 238 | config SYS_MXC_I2C2_SPEED |
| 239 | int "I2C Channel 2 speed" |
| 240 | default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU |
| 241 | default 100000 |
| 242 | help |
| 243 | MXC I2C Channel 2 speed |
| 244 | |
| 245 | config SYS_MXC_I2C2_SLAVE |
| 246 | int "I2C2 Slave" |
| 247 | default 0 |
| 248 | help |
| 249 | MXC I2C2 Slave |
| 250 | endif |
| 251 | |
| 252 | if SYS_I2C_MXC_I2C3 |
| 253 | config SYS_MXC_I2C3_SPEED |
| 254 | int "I2C Channel 3 speed" |
| 255 | default 100000 |
| 256 | help |
| 257 | MXC I2C Channel 3 speed |
| 258 | |
| 259 | config SYS_MXC_I2C3_SLAVE |
| 260 | int "I2C3 Slave" |
| 261 | default 0 |
| 262 | help |
| 263 | MXC I2C3 Slave |
| 264 | endif |
| 265 | |
| 266 | if SYS_I2C_MXC_I2C4 |
| 267 | config SYS_MXC_I2C4_SPEED |
| 268 | int "I2C Channel 4 speed" |
| 269 | default 100000 |
| 270 | help |
| 271 | MXC I2C Channel 4 speed |
| 272 | |
| 273 | config SYS_MXC_I2C4_SLAVE |
| 274 | int "I2C4 Slave" |
| 275 | default 0 |
| 276 | help |
| 277 | MXC I2C4 Slave |
| 278 | endif |
| 279 | |
Sriram Dash | a64aa19 | 2018-02-06 11:26:31 +0530 | [diff] [blame] | 280 | if SYS_I2C_MXC_I2C5 |
| 281 | config SYS_MXC_I2C5_SPEED |
| 282 | int "I2C Channel 5 speed" |
| 283 | default 100000 |
| 284 | help |
| 285 | MXC I2C Channel 5 speed |
| 286 | |
| 287 | config SYS_MXC_I2C5_SLAVE |
| 288 | int "I2C5 Slave" |
| 289 | default 0 |
| 290 | help |
| 291 | MXC I2C5 Slave |
| 292 | endif |
| 293 | |
| 294 | if SYS_I2C_MXC_I2C6 |
| 295 | config SYS_MXC_I2C6_SPEED |
| 296 | int "I2C Channel 6 speed" |
| 297 | default 100000 |
| 298 | help |
| 299 | MXC I2C Channel 6 speed |
| 300 | |
| 301 | config SYS_MXC_I2C6_SLAVE |
| 302 | int "I2C6 Slave" |
| 303 | default 0 |
| 304 | help |
| 305 | MXC I2C6 Slave |
| 306 | endif |
| 307 | |
| 308 | if SYS_I2C_MXC_I2C7 |
| 309 | config SYS_MXC_I2C7_SPEED |
| 310 | int "I2C Channel 7 speed" |
| 311 | default 100000 |
| 312 | help |
| 313 | MXC I2C Channel 7 speed |
| 314 | |
| 315 | config SYS_MXC_I2C7_SLAVE |
| 316 | int "I2C7 Slave" |
| 317 | default 0 |
| 318 | help |
| 319 | MXC I2C7 Slave |
| 320 | endif |
| 321 | |
| 322 | if SYS_I2C_MXC_I2C8 |
| 323 | config SYS_MXC_I2C8_SPEED |
| 324 | int "I2C Channel 8 speed" |
| 325 | default 100000 |
| 326 | help |
| 327 | MXC I2C Channel 8 speed |
| 328 | |
| 329 | config SYS_MXC_I2C8_SLAVE |
| 330 | int "I2C8 Slave" |
| 331 | default 0 |
| 332 | help |
| 333 | MXC I2C8 Slave |
| 334 | endif |
| 335 | |
Stefan Bosch | 9d85dfb | 2020-07-10 19:07:28 +0200 | [diff] [blame] | 336 | config SYS_I2C_NEXELL |
| 337 | bool "Nexell I2C driver" |
| 338 | depends on DM_I2C |
| 339 | help |
| 340 | Add support for the Nexell I2C driver. This is used with various |
| 341 | Nexell parts such as S5Pxx18 series SoCs. All chips |
| 342 | have several I2C ports and all are provided, controlled by the |
| 343 | device tree. |
| 344 | |
Pragnesh Patel | 1cfbd7a | 2020-11-14 14:42:34 +0530 | [diff] [blame] | 345 | config SYS_I2C_OCORES |
| 346 | bool "ocores I2C driver" |
| 347 | depends on DM_I2C |
| 348 | help |
| 349 | Add support for ocores I2C controller. For details see |
| 350 | https://opencores.org/projects/i2c |
| 351 | |
Adam Ford | 8590116 | 2017-08-07 13:11:34 -0500 | [diff] [blame] | 352 | config SYS_I2C_OMAP24XX |
| 353 | bool "TI OMAP2+ I2C driver" |
Vignesh R | 64d4f55 | 2019-06-04 18:08:11 -0500 | [diff] [blame] | 354 | depends on ARCH_OMAP2PLUS || ARCH_K3 |
Adam Ford | 8590116 | 2017-08-07 13:11:34 -0500 | [diff] [blame] | 355 | help |
| 356 | Add support for the OMAP2+ I2C driver. |
| 357 | |
Adam Ford | ed3b082 | 2018-01-24 15:21:21 -0600 | [diff] [blame] | 358 | if SYS_I2C_OMAP24XX |
| 359 | config SYS_OMAP24_I2C_SLAVE |
| 360 | int "I2C Slave addr channel 0" |
| 361 | default 1 |
| 362 | help |
| 363 | OMAP24xx I2C Slave address channel 0 |
| 364 | |
| 365 | config SYS_OMAP24_I2C_SPEED |
| 366 | int "I2C Slave channel 0 speed" |
| 367 | default 100000 |
| 368 | help |
| 369 | OMAP24xx Slave speed channel 0 |
| 370 | endif |
| 371 | |
Marek Vasut | 2716596 | 2018-04-21 18:57:28 +0200 | [diff] [blame] | 372 | config SYS_I2C_RCAR_I2C |
| 373 | bool "Renesas RCar I2C driver" |
| 374 | depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C |
| 375 | help |
| 376 | Support for Renesas RCar I2C controller. |
| 377 | |
Marek Vasut | 125d8df | 2017-11-28 08:02:27 +0100 | [diff] [blame] | 378 | config SYS_I2C_RCAR_IIC |
| 379 | bool "Renesas RCar Gen3 IIC driver" |
Marek Vasut | 4bc57a3 | 2018-02-17 02:17:40 +0100 | [diff] [blame] | 380 | depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C |
Marek Vasut | 125d8df | 2017-11-28 08:02:27 +0100 | [diff] [blame] | 381 | help |
| 382 | Support for Renesas RCar Gen3 IIC controller. |
| 383 | |
Simon Glass | 3595f95 | 2015-08-30 16:55:39 -0600 | [diff] [blame] | 384 | config SYS_I2C_ROCKCHIP |
| 385 | bool "Rockchip I2C driver" |
| 386 | depends on DM_I2C |
| 387 | help |
| 388 | Add support for the Rockchip I2C driver. This is used with various |
| 389 | Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips |
Chris Packham | 94d0d3d | 2019-01-13 22:13:25 +1300 | [diff] [blame] | 390 | have several I2C ports and all are provided, controlled by the |
Simon Glass | 3595f95 | 2015-08-30 16:55:39 -0600 | [diff] [blame] | 391 | device tree. |
| 392 | |
Simon Glass | 39bc3be | 2015-03-06 13:19:04 -0700 | [diff] [blame] | 393 | config SYS_I2C_SANDBOX |
| 394 | bool "Sandbox I2C driver" |
| 395 | depends on SANDBOX && DM_I2C |
| 396 | help |
| 397 | Enable I2C support for sandbox. This is an emulation of a real I2C |
| 398 | bus. Devices can be attached to the bus using the device tree |
Masahiro Yamada | 8d8371d | 2017-02-11 12:39:55 +0900 | [diff] [blame] | 399 | which specifies the driver to use. See sandbox.dts as an example. |
Simon Glass | 39bc3be | 2015-03-06 13:19:04 -0700 | [diff] [blame] | 400 | |
Suneel Garapati | c6baea2 | 2020-05-26 14:13:07 +0200 | [diff] [blame] | 401 | config SYS_I2C_OCTEON |
| 402 | bool "Octeon II/III/TX/TX2 I2C driver" |
| 403 | depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C |
| 404 | default y |
| 405 | help |
| 406 | Add support for the Marvell Octeon I2C driver. This is used with |
| 407 | various Octeon parts such as Octeon II/III and OcteonTX/TX2. All |
| 408 | chips have several I2C ports and all are provided, controlled by |
| 409 | the device tree. |
| 410 | |
Jaehoon Chung | f7e6a03 | 2017-01-09 14:47:52 +0900 | [diff] [blame] | 411 | config SYS_I2C_S3C24X0 |
| 412 | bool "Samsung I2C driver" |
| 413 | depends on ARCH_EXYNOS4 && DM_I2C |
| 414 | help |
| 415 | Support for Samsung I2C controller as Samsung SoCs. |
Simon Glass | 39bc3be | 2015-03-06 13:19:04 -0700 | [diff] [blame] | 416 | |
Patrice Chotard | ebf442d | 2017-08-09 14:45:27 +0200 | [diff] [blame] | 417 | config SYS_I2C_STM32F7 |
| 418 | bool "STMicroelectronics STM32F7 I2C support" |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 419 | depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C |
Patrice Chotard | ebf442d | 2017-08-09 14:45:27 +0200 | [diff] [blame] | 420 | help |
| 421 | Enable this option to add support for STM32 I2C controller |
| 422 | introduced with STM32F7/H7 SoCs. This I2C controller supports : |
| 423 | _ Slave and master modes |
| 424 | _ Multimaster capability |
| 425 | _ Standard-mode (up to 100 kHz) |
| 426 | _ Fast-mode (up to 400 kHz) |
| 427 | _ Fast-mode Plus (up to 1 MHz) |
| 428 | _ 7-bit and 10-bit addressing mode |
| 429 | _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) |
| 430 | _ All 7-bit addresses acknowledge mode |
| 431 | _ General call |
| 432 | _ Programmable setup and hold times |
| 433 | _ Easy to use event management |
| 434 | _ Optional clock stretching |
| 435 | _ Software reset |
| 436 | |
Peter Robinson | 12d37d8 | 2019-02-20 12:17:26 +0000 | [diff] [blame] | 437 | config SYS_I2C_TEGRA |
| 438 | bool "NVIDIA Tegra internal I2C controller" |
Trevor Woerner | 513f640 | 2020-05-06 08:02:41 -0400 | [diff] [blame] | 439 | depends on ARCH_TEGRA |
Peter Robinson | 12d37d8 | 2019-02-20 12:17:26 +0000 | [diff] [blame] | 440 | help |
| 441 | Support for NVIDIA I2C controller available in Tegra SoCs. |
| 442 | |
Masahiro Yamada | 96a42ed | 2015-01-13 12:44:36 +0900 | [diff] [blame] | 443 | config SYS_I2C_UNIPHIER |
| 444 | bool "UniPhier I2C driver" |
| 445 | depends on ARCH_UNIPHIER && DM_I2C |
| 446 | default y |
| 447 | help |
Masahiro Yamada | 563ee4c | 2015-05-29 17:30:01 +0900 | [diff] [blame] | 448 | Support for UniPhier I2C controller driver. This I2C controller |
| 449 | is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs. |
Masahiro Yamada | 4e82e5e | 2015-01-13 12:44:37 +0900 | [diff] [blame] | 450 | |
| 451 | config SYS_I2C_UNIPHIER_F |
| 452 | bool "UniPhier FIFO-builtin I2C driver" |
| 453 | depends on ARCH_UNIPHIER && DM_I2C |
| 454 | default y |
| 455 | help |
Masahiro Yamada | 563ee4c | 2015-05-29 17:30:01 +0900 | [diff] [blame] | 456 | Support for UniPhier FIFO-builtin I2C controller driver. |
Masahiro Yamada | 4e82e5e | 2015-01-13 12:44:37 +0900 | [diff] [blame] | 457 | This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. |
Simon Glass | 2a80c40 | 2015-08-03 08:19:21 -0600 | [diff] [blame] | 458 | |
Heiko Schocher | a37c196 | 2018-10-11 07:26:33 +0200 | [diff] [blame] | 459 | config SYS_I2C_VERSATILE |
| 460 | bool "Arm Ltd Versatile I2C bus driver" |
| 461 | depends on DM_I2C && (TARGET_VEXPRESS_CA15_TC2 || TARGET_VEXPRESS64_JUNO) |
| 462 | help |
| 463 | Add support for the Arm Ltd Versatile Express I2C driver. The I2C host |
| 464 | controller is present in the development boards manufactured by Arm Ltd. |
| 465 | |
mario.six@gdsys.cc | 355a127 | 2016-07-21 11:57:10 +0200 | [diff] [blame] | 466 | config SYS_I2C_MVTWSI |
| 467 | bool "Marvell I2C driver" |
| 468 | depends on DM_I2C |
| 469 | help |
| 470 | Support for Marvell I2C controllers as used on the orion5x and |
| 471 | kirkwood SoC families. |
| 472 | |
Stephen Warren | 67a8348 | 2016-08-08 11:28:27 -0600 | [diff] [blame] | 473 | config TEGRA186_BPMP_I2C |
| 474 | bool "Enable Tegra186 BPMP-based I2C driver" |
| 475 | depends on TEGRA186_BPMP |
| 476 | help |
| 477 | Support for Tegra I2C controllers managed by the BPMP (Boot and |
| 478 | Power Management Processor). On Tegra186, some I2C controllers are |
| 479 | directly controlled by the main CPU, whereas others are controlled |
| 480 | by the BPMP, and can only be accessed by the main CPU via IPC |
| 481 | requests to the BPMP. This driver covers the latter case. |
| 482 | |
Adam Ford | fa1dd3d | 2017-08-11 06:39:34 -0500 | [diff] [blame] | 483 | config SYS_I2C_BUS_MAX |
| 484 | int "Max I2C busses" |
| 485 | depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA |
| 486 | default 2 if TI816X |
| 487 | default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE |
| 488 | default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X |
| 489 | default 5 if OMAP54XX |
| 490 | help |
| 491 | Define the maximum number of available I2C buses. |
| 492 | |
Marek Vasut | 9de0e2a | 2018-12-19 12:26:27 +0100 | [diff] [blame] | 493 | config SYS_I2C_XILINX_XIIC |
| 494 | bool "Xilinx AXI I2C driver" |
| 495 | depends on DM_I2C |
| 496 | help |
| 497 | Support for Xilinx AXI I2C controller. |
| 498 | |
Mario Six | 3bb409c | 2018-01-15 11:08:11 +0100 | [diff] [blame] | 499 | config SYS_I2C_IHS |
| 500 | bool "gdsys IHS I2C driver" |
| 501 | depends on DM_I2C |
| 502 | help |
| 503 | Support for gdsys IHS I2C driver on FPGA bus. |
| 504 | |
Simon Glass | 2a80c40 | 2015-08-03 08:19:21 -0600 | [diff] [blame] | 505 | source "drivers/i2c/muxes/Kconfig" |
Masahiro Yamada | cc85b7b | 2015-07-26 02:46:26 +0900 | [diff] [blame] | 506 | |
| 507 | endmenu |