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git01.mediatek.com / filogic / uboot / 46f5a763136f33e038510956e36bee802c7f4787 / . / arch / arm / include / asm / arch-am33xx / ddr_defs.h
blob: 2278358ab200ecc26fc7500e01b11268fe7d43f5 [file] [log] [blame]
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]1/*
2 * ddr_defs.h
3 *
4 * ddr specific header
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]9 */
10
11#ifndef _DDR_DEFS_H
12#define _DDR_DEFS_H
13
14#include <asm/arch/hardware.h>
Tom Rinib668ae42012-07-24 14:55:38 -0700[diff] [blame]15#include <asm/emif.h>
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]16
17/* AM335X EMIF Register values */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]18#define VTP_CTRL_READY (0x1 << 5)
19#define VTP_CTRL_ENABLE (0x1 << 6)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]20#define VTP_CTRL_START_EN (0x1)
Tom Rinide3c5702012-07-24 14:03:24 -0700[diff] [blame]21#define DDR_CKE_CTRL_NORMAL 0x1
Vaibhav Hiremathc30d57b2013-03-14 21:11:16 +0000[diff] [blame]22#define PHY_EN_DYN_PWRDN (0x1 << 20)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]23
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]24/* Micron MT47H128M16RT-25E */
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]25#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
26#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
27#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
28#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
29#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
30#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]31#define MT47H128M16RT25E_RATIO 0x80
32#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
33#define MT47H128M16RT25E_RD_DQS 0x12
34#define MT47H128M16RT25E_WR_DQS 0x00
35#define MT47H128M16RT25E_PHY_WRLVL 0x00
36#define MT47H128M16RT25E_PHY_GATELVL 0x00
37#define MT47H128M16RT25E_PHY_WR_DATA 0x40
38#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]39#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]40
Tom Rini323315a2012-07-30 14:49:50 -0700[diff] [blame]41/* Micron MT41J128M16JT-125 */
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]42#define MT41J128MJT125_EMIF_READ_LATENCY 0x06
43#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
44#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
45#define MT41J128MJT125_EMIF_TIM3 0x501F830F
46#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
47#define MT41J128MJT125_EMIF_SDREF 0x0000093B
48#define MT41J128MJT125_ZQ_CFG 0x50074BE4
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]49#define MT41J128MJT125_RATIO 0x40
50#define MT41J128MJT125_INVERT_CLKOUT 0x1
51#define MT41J128MJT125_RD_DQS 0x3B
52#define MT41J128MJT125_WR_DQS 0x85
53#define MT41J128MJT125_PHY_WR_DATA 0xC1
54#define MT41J128MJT125_PHY_FIFO_WE 0x100
55#define MT41J128MJT125_IOCTRL_VALUE 0x18B
Tom Rini323315a2012-07-30 14:49:50 -0700[diff] [blame]56
Ilya Ledvich791ca182013-11-07 07:57:33 +0200[diff] [blame]57/* Micron MT41J64M16JT-125 */
58#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
59
60/* Micron MT41J256M16JT-125 */
61#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
62
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]63/* Micron MT41J256M8HX-15E */
64#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06
65#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
66#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
67#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
68#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
69#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
70#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]71#define MT41J256M8HX15E_RATIO 0x40
72#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
73#define MT41J256M8HX15E_RD_DQS 0x3B
74#define MT41J256M8HX15E_WR_DQS 0x85
75#define MT41J256M8HX15E_PHY_WR_DATA 0xC1
76#define MT41J256M8HX15E_PHY_FIFO_WE 0x100
77#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
78
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]79/* Micron MT41K256M16HA-125E */
Tom Rini8939ec32013-04-10 15:10:54 +0200[diff] [blame]80#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
81#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
Tom Rini05acd822013-04-12 12:38:16 -0400[diff] [blame]82#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
83#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
84#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
Tom Rini8939ec32013-04-10 15:10:54 +0200[diff] [blame]85#define MT41K256M16HA125E_EMIF_SDREF 0xC30
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]86#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
Tom Rini8939ec32013-04-10 15:10:54 +0200[diff] [blame]87#define MT41K256M16HA125E_RATIO 0x80
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]88#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
Tom Rini05acd822013-04-12 12:38:16 -0400[diff] [blame]89#define MT41K256M16HA125E_RD_DQS 0x38
90#define MT41K256M16HA125E_WR_DQS 0x44
91#define MT41K256M16HA125E_PHY_WR_DATA 0x7D
92#define MT41K256M16HA125E_PHY_FIFO_WE 0x94
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]93#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
94
Jeff Lance7c03a222013-01-14 05:32:20 +0000[diff] [blame]95/* Micron MT41J512M8RH-125 on EVM v1.5 */
96#define MT41J512M8RH125_EMIF_READ_LATENCY 0x06
97#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
98#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
99#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
100#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
101#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
102#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
Jeff Lance7c03a222013-01-14 05:32:20 +0000[diff] [blame]103#define MT41J512M8RH125_RATIO 0x80
104#define MT41J512M8RH125_INVERT_CLKOUT 0x0
105#define MT41J512M8RH125_RD_DQS 0x3B
106#define MT41J512M8RH125_WR_DQS 0x3C
107#define MT41J512M8RH125_PHY_FIFO_WE 0xA5
108#define MT41J512M8RH125_PHY_WR_DATA 0x74
109#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]110
Enric Balletbo i Serrad8efff12013-04-04 22:27:57 +0000[diff] [blame]111/* Samsung K4B2G1646E-BIH9 */
Enric Balletbo i Serra177db362013-09-10 11:12:26 +0200[diff] [blame]112#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x07
113#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
114#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
115#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
116#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
117#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
Enric Balletbo i Serrad8efff12013-04-04 22:27:57 +0000[diff] [blame]118#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
Enric Balletbo i Serra177db362013-09-10 11:12:26 +0200[diff] [blame]119#define K4B2G1646EBIH9_RATIO 0x80
120#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
121#define K4B2G1646EBIH9_RD_DQS 0x35
122#define K4B2G1646EBIH9_WR_DQS 0x3A
123#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97
124#define K4B2G1646EBIH9_PHY_WR_DATA 0x76
Enric Balletbo i Serrad8efff12013-04-04 22:27:57 +0000[diff] [blame]125#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
126
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]127/**
Matt Porter40355102013-03-15 10:07:07 +0000[diff] [blame]128 * Configure DMM
129 */
130void config_dmm(const struct dmm_lisa_map_regs *regs);
131
132/**
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]133 * Configure SDRAM
134 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]135void config_sdram(const struct emif_regs *regs, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]136
137/**
138 * Set SDRAM timings
139 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]140void set_sdram_timings(const struct emif_regs *regs, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]141
142/**
143 * Configure DDR PHY
144 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]145void config_ddr_phy(const struct emif_regs *regs, int nr);
146
147struct ddr_cmd_regs {
148 unsigned int resv0[7];
149 unsigned int cm0csratio; /* offset 0x01C */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]150 unsigned int resv1[3];
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]151 unsigned int cm0iclkout; /* offset 0x02C */
152 unsigned int resv2[8];
153 unsigned int cm1csratio; /* offset 0x050 */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]154 unsigned int resv3[3];
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]155 unsigned int cm1iclkout; /* offset 0x060 */
156 unsigned int resv4[8];
157 unsigned int cm2csratio; /* offset 0x084 */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]158 unsigned int resv5[3];
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]159 unsigned int cm2iclkout; /* offset 0x094 */
160 unsigned int resv6[3];
161};
162
163struct ddr_data_regs {
164 unsigned int dt0rdsratio0; /* offset 0x0C8 */
165 unsigned int resv1[4];
166 unsigned int dt0wdsratio0; /* offset 0x0DC */
167 unsigned int resv2[4];
168 unsigned int dt0wiratio0; /* offset 0x0F0 */
169 unsigned int resv3;
170 unsigned int dt0wimode0; /* offset 0x0F8 */
171 unsigned int dt0giratio0; /* offset 0x0FC */
172 unsigned int resv4;
173 unsigned int dt0gimode0; /* offset 0x104 */
174 unsigned int dt0fwsratio0; /* offset 0x108 */
175 unsigned int resv5[4];
176 unsigned int dt0dqoffset; /* offset 0x11C */
177 unsigned int dt0wrsratio0; /* offset 0x120 */
178 unsigned int resv6[4];
179 unsigned int dt0rdelays0; /* offset 0x134 */
180 unsigned int dt0dldiff0; /* offset 0x138 */
181 unsigned int resv7[12];
182};
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]183
184/**
185 * This structure represents the DDR registers on AM33XX devices.
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]186 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
187 * correspond to DATA1 registers defined here.
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]188 */
189struct ddr_regs {
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]190 unsigned int resv0[3];
191 unsigned int cm0config; /* offset 0x00C */
192 unsigned int cm0configclk; /* offset 0x010 */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]193 unsigned int resv1[2];
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]194 unsigned int cm0csratio; /* offset 0x01C */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]195 unsigned int resv2[3];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]196 unsigned int cm0iclkout; /* offset 0x02C */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]197 unsigned int resv3[4];
198 unsigned int cm1config; /* offset 0x040 */
199 unsigned int cm1configclk; /* offset 0x044 */
200 unsigned int resv4[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]201 unsigned int cm1csratio; /* offset 0x050 */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]202 unsigned int resv5[3];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]203 unsigned int cm1iclkout; /* offset 0x060 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]204 unsigned int resv6[4];
205 unsigned int cm2config; /* offset 0x074 */
206 unsigned int cm2configclk; /* offset 0x078 */
207 unsigned int resv7[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]208 unsigned int cm2csratio; /* offset 0x084 */
Tom Rinibcce2a02013-11-07 11:42:57 -0500[diff] [blame]209 unsigned int resv8[3];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]210 unsigned int cm2iclkout; /* offset 0x094 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]211 unsigned int resv9[12];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]212 unsigned int dt0rdsratio0; /* offset 0x0C8 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]213 unsigned int resv10[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]214 unsigned int dt0wdsratio0; /* offset 0x0DC */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]215 unsigned int resv11[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]216 unsigned int dt0wiratio0; /* offset 0x0F0 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]217 unsigned int resv12;
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]218 unsigned int dt0wimode0; /* offset 0x0F8 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]219 unsigned int dt0giratio0; /* offset 0x0FC */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]220 unsigned int resv13;
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]221 unsigned int dt0gimode0; /* offset 0x104 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]222 unsigned int dt0fwsratio0; /* offset 0x108 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]223 unsigned int resv14[4];
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]224 unsigned int dt0dqoffset; /* offset 0x11C */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]225 unsigned int dt0wrsratio0; /* offset 0x120 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]226 unsigned int resv15[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]227 unsigned int dt0rdelays0; /* offset 0x134 */
228 unsigned int dt0dldiff0; /* offset 0x138 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]229};
230
231/**
232 * Encapsulates DDR CMD control registers.
233 */
234struct cmd_control {
235 unsigned long cmd0csratio;
236 unsigned long cmd0csforce;
237 unsigned long cmd0csdelay;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]238 unsigned long cmd0iclkout;
239 unsigned long cmd1csratio;
240 unsigned long cmd1csforce;
241 unsigned long cmd1csdelay;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]242 unsigned long cmd1iclkout;
243 unsigned long cmd2csratio;
244 unsigned long cmd2csforce;
245 unsigned long cmd2csdelay;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]246 unsigned long cmd2iclkout;
247};
248
249/**
250 * Encapsulates DDR DATA registers.
251 */
252struct ddr_data {
253 unsigned long datardsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]254 unsigned long datawdsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]255 unsigned long datawiratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]256 unsigned long datagiratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]257 unsigned long datafwsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]258 unsigned long datawrsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]259};
260
261/**
262 * Configure DDR CMD control registers
263 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]264void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]265
266/**
267 * Configure DDR DATA registers
268 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]269void config_ddr_data(const struct ddr_data *data, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]270
271/**
272 * This structure represents the DDR io control on AM33XX devices.
273 */
274struct ddr_cmdtctrl {
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]275 unsigned int cm0ioctl;
276 unsigned int cm1ioctl;
277 unsigned int cm2ioctl;
278 unsigned int resv2[12];
279 unsigned int dt0ioctl;
280 unsigned int dt1ioctl;
281};
282
283/**
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]284 * Configure DDR io control registers
285 */
Tom Rinib239b3b2012-07-24 16:31:26 -0700[diff] [blame]286void config_io_ctrl(unsigned long val);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]287
288struct ddr_ctrl {
289 unsigned int ddrioctrl;
290 unsigned int resv1[325];
291 unsigned int ddrckectrl;
292};
293
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]294void config_ddr(unsigned int pll, unsigned int ioctrl,
295 const struct ddr_data *data, const struct cmd_control *ctrl,
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]296 const struct emif_regs *regs, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]297
298#endif /* _DDR_DEFS_H */