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git01.mediatek.com / filogic / uboot / 35c7e52280add598193ad953531d0f8198cfe963 / . / arch / arm / include / asm / arch-am33xx / ddr_defs.h
blob: 95f7a9ad41192ceafccc4d7d3d6fd45bb9570b82 [file] [log] [blame]
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]1/*
2 * ddr_defs.h
3 *
4 * ddr specific header
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]9 */
10
11#ifndef _DDR_DEFS_H
12#define _DDR_DEFS_H
13
14#include <asm/arch/hardware.h>
Tom Rinib668ae42012-07-24 14:55:38 -0700[diff] [blame]15#include <asm/emif.h>
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]16
17/* AM335X EMIF Register values */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]18#define VTP_CTRL_READY (0x1 << 5)
19#define VTP_CTRL_ENABLE (0x1 << 6)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]20#define VTP_CTRL_START_EN (0x1)
Tom Rinif4914f92012-07-24 13:05:10 -0700[diff] [blame]21#define PHY_DLL_LOCK_DIFF 0x0
Tom Rinide3c5702012-07-24 14:03:24 -0700[diff] [blame]22#define DDR_CKE_CTRL_NORMAL 0x1
Vaibhav Hiremathc30d57b2013-03-14 21:11:16 +0000[diff] [blame]23#define PHY_EN_DYN_PWRDN (0x1 << 20)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]24
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]25/* Micron MT47H128M16RT-25E */
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]26#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
27#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
28#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
29#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
30#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
31#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
32#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0
33#define MT47H128M16RT25E_RATIO 0x80
34#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
35#define MT47H128M16RT25E_RD_DQS 0x12
36#define MT47H128M16RT25E_WR_DQS 0x00
37#define MT47H128M16RT25E_PHY_WRLVL 0x00
38#define MT47H128M16RT25E_PHY_GATELVL 0x00
39#define MT47H128M16RT25E_PHY_WR_DATA 0x40
40#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
41#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1
42#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]43
Tom Rini323315a2012-07-30 14:49:50 -0700[diff] [blame]44/* Micron MT41J128M16JT-125 */
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]45#define MT41J128MJT125_EMIF_READ_LATENCY 0x06
46#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
47#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
48#define MT41J128MJT125_EMIF_TIM3 0x501F830F
49#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
50#define MT41J128MJT125_EMIF_SDREF 0x0000093B
51#define MT41J128MJT125_ZQ_CFG 0x50074BE4
52#define MT41J128MJT125_DLL_LOCK_DIFF 0x1
53#define MT41J128MJT125_RATIO 0x40
54#define MT41J128MJT125_INVERT_CLKOUT 0x1
55#define MT41J128MJT125_RD_DQS 0x3B
56#define MT41J128MJT125_WR_DQS 0x85
57#define MT41J128MJT125_PHY_WR_DATA 0xC1
58#define MT41J128MJT125_PHY_FIFO_WE 0x100
59#define MT41J128MJT125_IOCTRL_VALUE 0x18B
Tom Rini323315a2012-07-30 14:49:50 -0700[diff] [blame]60
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]61/* Micron MT41J256M8HX-15E */
62#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06
63#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
64#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
65#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
66#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
67#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
68#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
69#define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1
70#define MT41J256M8HX15E_RATIO 0x40
71#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
72#define MT41J256M8HX15E_RD_DQS 0x3B
73#define MT41J256M8HX15E_WR_DQS 0x85
74#define MT41J256M8HX15E_PHY_WR_DATA 0xC1
75#define MT41J256M8HX15E_PHY_FIFO_WE 0x100
76#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
77
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]78/* Micron MT41K256M16HA-125E */
Tom Rini8939ec32013-04-10 15:10:54 +0200[diff] [blame]79#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
80#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
Tom Rini05acd822013-04-12 12:38:16 -0400[diff] [blame]81#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
82#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
83#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
Tom Rini8939ec32013-04-10 15:10:54 +0200[diff] [blame]84#define MT41K256M16HA125E_EMIF_SDREF 0xC30
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]85#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
86#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
Tom Rini8939ec32013-04-10 15:10:54 +0200[diff] [blame]87#define MT41K256M16HA125E_RATIO 0x80
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]88#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
Tom Rini05acd822013-04-12 12:38:16 -0400[diff] [blame]89#define MT41K256M16HA125E_RD_DQS 0x38
90#define MT41K256M16HA125E_WR_DQS 0x44
91#define MT41K256M16HA125E_PHY_WR_DATA 0x7D
92#define MT41K256M16HA125E_PHY_FIFO_WE 0x94
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]93#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
94
Jeff Lance7c03a222013-01-14 05:32:20 +0000[diff] [blame]95/* Micron MT41J512M8RH-125 on EVM v1.5 */
96#define MT41J512M8RH125_EMIF_READ_LATENCY 0x06
97#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
98#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
99#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
100#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
101#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
102#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
103#define MT41J512M8RH125_DLL_LOCK_DIFF 0x1
104#define MT41J512M8RH125_RATIO 0x80
105#define MT41J512M8RH125_INVERT_CLKOUT 0x0
106#define MT41J512M8RH125_RD_DQS 0x3B
107#define MT41J512M8RH125_WR_DQS 0x3C
108#define MT41J512M8RH125_PHY_FIFO_WE 0xA5
109#define MT41J512M8RH125_PHY_WR_DATA 0x74
110#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]111
Enric Balletbo i Serrad8efff12013-04-04 22:27:57 +0000[diff] [blame]112/* Samsung K4B2G1646E-BIH9 */
113#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x06
114#define K4B2G1646EBIH9_EMIF_TIM1 0x0888A39B
115#define K4B2G1646EBIH9_EMIF_TIM2 0x2A04011A
116#define K4B2G1646EBIH9_EMIF_TIM3 0x501F820F
117#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C24AB2
118#define K4B2G1646EBIH9_EMIF_SDREF 0x0000093B
119#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
120#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1
121#define K4B2G1646EBIH9_RATIO 0x40
122#define K4B2G1646EBIH9_INVERT_CLKOUT 0x1
123#define K4B2G1646EBIH9_RD_DQS 0x3B
124#define K4B2G1646EBIH9_WR_DQS 0x85
125#define K4B2G1646EBIH9_PHY_FIFO_WE 0x100
126#define K4B2G1646EBIH9_PHY_WR_DATA 0xC1
127#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
128
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]129/**
Matt Porter40355102013-03-15 10:07:07 +0000[diff] [blame]130 * Configure DMM
131 */
132void config_dmm(const struct dmm_lisa_map_regs *regs);
133
134/**
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]135 * Configure SDRAM
136 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]137void config_sdram(const struct emif_regs *regs, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]138
139/**
140 * Set SDRAM timings
141 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]142void set_sdram_timings(const struct emif_regs *regs, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]143
144/**
145 * Configure DDR PHY
146 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]147void config_ddr_phy(const struct emif_regs *regs, int nr);
148
149struct ddr_cmd_regs {
150 unsigned int resv0[7];
151 unsigned int cm0csratio; /* offset 0x01C */
152 unsigned int resv1[2];
153 unsigned int cm0dldiff; /* offset 0x028 */
154 unsigned int cm0iclkout; /* offset 0x02C */
155 unsigned int resv2[8];
156 unsigned int cm1csratio; /* offset 0x050 */
157 unsigned int resv3[2];
158 unsigned int cm1dldiff; /* offset 0x05C */
159 unsigned int cm1iclkout; /* offset 0x060 */
160 unsigned int resv4[8];
161 unsigned int cm2csratio; /* offset 0x084 */
162 unsigned int resv5[2];
163 unsigned int cm2dldiff; /* offset 0x090 */
164 unsigned int cm2iclkout; /* offset 0x094 */
165 unsigned int resv6[3];
166};
167
168struct ddr_data_regs {
169 unsigned int dt0rdsratio0; /* offset 0x0C8 */
170 unsigned int resv1[4];
171 unsigned int dt0wdsratio0; /* offset 0x0DC */
172 unsigned int resv2[4];
173 unsigned int dt0wiratio0; /* offset 0x0F0 */
174 unsigned int resv3;
175 unsigned int dt0wimode0; /* offset 0x0F8 */
176 unsigned int dt0giratio0; /* offset 0x0FC */
177 unsigned int resv4;
178 unsigned int dt0gimode0; /* offset 0x104 */
179 unsigned int dt0fwsratio0; /* offset 0x108 */
180 unsigned int resv5[4];
181 unsigned int dt0dqoffset; /* offset 0x11C */
182 unsigned int dt0wrsratio0; /* offset 0x120 */
183 unsigned int resv6[4];
184 unsigned int dt0rdelays0; /* offset 0x134 */
185 unsigned int dt0dldiff0; /* offset 0x138 */
186 unsigned int resv7[12];
187};
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]188
189/**
190 * This structure represents the DDR registers on AM33XX devices.
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]191 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
192 * correspond to DATA1 registers defined here.
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]193 */
194struct ddr_regs {
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]195 unsigned int resv0[3];
196 unsigned int cm0config; /* offset 0x00C */
197 unsigned int cm0configclk; /* offset 0x010 */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]198 unsigned int resv1[2];
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]199 unsigned int cm0csratio; /* offset 0x01C */
200 unsigned int resv2[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]201 unsigned int cm0dldiff; /* offset 0x028 */
202 unsigned int cm0iclkout; /* offset 0x02C */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]203 unsigned int resv3[4];
204 unsigned int cm1config; /* offset 0x040 */
205 unsigned int cm1configclk; /* offset 0x044 */
206 unsigned int resv4[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]207 unsigned int cm1csratio; /* offset 0x050 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]208 unsigned int resv5[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]209 unsigned int cm1dldiff; /* offset 0x05C */
210 unsigned int cm1iclkout; /* offset 0x060 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]211 unsigned int resv6[4];
212 unsigned int cm2config; /* offset 0x074 */
213 unsigned int cm2configclk; /* offset 0x078 */
214 unsigned int resv7[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]215 unsigned int cm2csratio; /* offset 0x084 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]216 unsigned int resv8[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]217 unsigned int cm2dldiff; /* offset 0x090 */
218 unsigned int cm2iclkout; /* offset 0x094 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]219 unsigned int resv9[12];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]220 unsigned int dt0rdsratio0; /* offset 0x0C8 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]221 unsigned int resv10[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]222 unsigned int dt0wdsratio0; /* offset 0x0DC */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]223 unsigned int resv11[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]224 unsigned int dt0wiratio0; /* offset 0x0F0 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]225 unsigned int resv12;
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]226 unsigned int dt0wimode0; /* offset 0x0F8 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]227 unsigned int dt0giratio0; /* offset 0x0FC */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]228 unsigned int resv13;
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]229 unsigned int dt0gimode0; /* offset 0x104 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]230 unsigned int dt0fwsratio0; /* offset 0x108 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]231 unsigned int resv14[4];
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]232 unsigned int dt0dqoffset; /* offset 0x11C */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]233 unsigned int dt0wrsratio0; /* offset 0x120 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame^]234 unsigned int resv15[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]235 unsigned int dt0rdelays0; /* offset 0x134 */
236 unsigned int dt0dldiff0; /* offset 0x138 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]237};
238
239/**
240 * Encapsulates DDR CMD control registers.
241 */
242struct cmd_control {
243 unsigned long cmd0csratio;
244 unsigned long cmd0csforce;
245 unsigned long cmd0csdelay;
246 unsigned long cmd0dldiff;
247 unsigned long cmd0iclkout;
248 unsigned long cmd1csratio;
249 unsigned long cmd1csforce;
250 unsigned long cmd1csdelay;
251 unsigned long cmd1dldiff;
252 unsigned long cmd1iclkout;
253 unsigned long cmd2csratio;
254 unsigned long cmd2csforce;
255 unsigned long cmd2csdelay;
256 unsigned long cmd2dldiff;
257 unsigned long cmd2iclkout;
258};
259
260/**
261 * Encapsulates DDR DATA registers.
262 */
263struct ddr_data {
264 unsigned long datardsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]265 unsigned long datawdsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]266 unsigned long datawiratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]267 unsigned long datagiratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]268 unsigned long datafwsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]269 unsigned long datawrsratio0;
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]270 unsigned long datauserank0delay;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]271 unsigned long datadldiff0;
272};
273
274/**
275 * Configure DDR CMD control registers
276 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]277void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]278
279/**
280 * Configure DDR DATA registers
281 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]282void config_ddr_data(const struct ddr_data *data, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]283
284/**
285 * This structure represents the DDR io control on AM33XX devices.
286 */
287struct ddr_cmdtctrl {
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]288 unsigned int cm0ioctl;
289 unsigned int cm1ioctl;
290 unsigned int cm2ioctl;
291 unsigned int resv2[12];
292 unsigned int dt0ioctl;
293 unsigned int dt1ioctl;
294};
295
296/**
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]297 * Configure DDR io control registers
298 */
Tom Rinib239b3b2012-07-24 16:31:26 -0700[diff] [blame]299void config_io_ctrl(unsigned long val);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]300
301struct ddr_ctrl {
302 unsigned int ddrioctrl;
303 unsigned int resv1[325];
304 unsigned int ddrckectrl;
305};
306
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]307void config_ddr(unsigned int pll, unsigned int ioctrl,
308 const struct ddr_data *data, const struct cmd_control *ctrl,
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]309 const struct emif_regs *regs, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]310
311#endif /* _DDR_DEFS_H */