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git01.mediatek.com / filogic / uboot / 65991ec1039b50cc4b30986f9317b7940f49c769 / . / arch / arm / include / asm / arch-am33xx / ddr_defs.h
blob: 55c61e6598f149c1d1b272938ae9fbbb97f7a516 [file] [log] [blame]
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]1/*
2 * ddr_defs.h
3 *
4 * ddr specific header
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef _DDR_DEFS_H
20#define _DDR_DEFS_H
21
22#include <asm/arch/hardware.h>
Tom Rinib668ae42012-07-24 14:55:38 -0700[diff] [blame]23#include <asm/emif.h>
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]24
25/* AM335X EMIF Register values */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]26#define VTP_CTRL_READY (0x1 << 5)
27#define VTP_CTRL_ENABLE (0x1 << 6)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]28#define VTP_CTRL_START_EN (0x1)
Tom Rinif4914f92012-07-24 13:05:10 -0700[diff] [blame]29#define PHY_DLL_LOCK_DIFF 0x0
Tom Rinide3c5702012-07-24 14:03:24 -0700[diff] [blame]30#define DDR_CKE_CTRL_NORMAL 0x1
Vaibhav Hiremathc30d57b2013-03-14 21:11:16 +0000[diff] [blame]31#define PHY_EN_DYN_PWRDN (0x1 << 20)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]32
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]33/* Micron MT47H128M16RT-25E */
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]34#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
35#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
36#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
37#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
38#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
39#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
40#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0
41#define MT47H128M16RT25E_RATIO 0x80
42#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
43#define MT47H128M16RT25E_RD_DQS 0x12
44#define MT47H128M16RT25E_WR_DQS 0x00
45#define MT47H128M16RT25E_PHY_WRLVL 0x00
46#define MT47H128M16RT25E_PHY_GATELVL 0x00
47#define MT47H128M16RT25E_PHY_WR_DATA 0x40
48#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
49#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1
50#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]51
Tom Rini323315a2012-07-30 14:49:50 -0700[diff] [blame]52/* Micron MT41J128M16JT-125 */
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]53#define MT41J128MJT125_EMIF_READ_LATENCY 0x06
54#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
55#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
56#define MT41J128MJT125_EMIF_TIM3 0x501F830F
57#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
58#define MT41J128MJT125_EMIF_SDREF 0x0000093B
59#define MT41J128MJT125_ZQ_CFG 0x50074BE4
60#define MT41J128MJT125_DLL_LOCK_DIFF 0x1
61#define MT41J128MJT125_RATIO 0x40
62#define MT41J128MJT125_INVERT_CLKOUT 0x1
63#define MT41J128MJT125_RD_DQS 0x3B
64#define MT41J128MJT125_WR_DQS 0x85
65#define MT41J128MJT125_PHY_WR_DATA 0xC1
66#define MT41J128MJT125_PHY_FIFO_WE 0x100
67#define MT41J128MJT125_IOCTRL_VALUE 0x18B
Tom Rini323315a2012-07-30 14:49:50 -0700[diff] [blame]68
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]69/* Micron MT41J256M8HX-15E */
70#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06
71#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
72#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
73#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
74#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
75#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
76#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
77#define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1
78#define MT41J256M8HX15E_RATIO 0x40
79#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
80#define MT41J256M8HX15E_RD_DQS 0x3B
81#define MT41J256M8HX15E_WR_DQS 0x85
82#define MT41J256M8HX15E_PHY_WR_DATA 0xC1
83#define MT41J256M8HX15E_PHY_FIFO_WE 0x100
84#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
85
Jeff Lance7c03a222013-01-14 05:32:20 +0000[diff] [blame]86/* Micron MT41J512M8RH-125 on EVM v1.5 */
87#define MT41J512M8RH125_EMIF_READ_LATENCY 0x06
88#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
89#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
90#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
91#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
92#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
93#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
94#define MT41J512M8RH125_DLL_LOCK_DIFF 0x1
95#define MT41J512M8RH125_RATIO 0x80
96#define MT41J512M8RH125_INVERT_CLKOUT 0x0
97#define MT41J512M8RH125_RD_DQS 0x3B
98#define MT41J512M8RH125_WR_DQS 0x3C
99#define MT41J512M8RH125_PHY_FIFO_WE 0xA5
100#define MT41J512M8RH125_PHY_WR_DATA 0x74
101#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]102
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]103/**
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]104 * Configure SDRAM
105 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame^]106void config_sdram(const struct emif_regs *regs, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]107
108/**
109 * Set SDRAM timings
110 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame^]111void set_sdram_timings(const struct emif_regs *regs, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]112
113/**
114 * Configure DDR PHY
115 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame^]116void config_ddr_phy(const struct emif_regs *regs, int nr);
117
118struct ddr_cmd_regs {
119 unsigned int resv0[7];
120 unsigned int cm0csratio; /* offset 0x01C */
121 unsigned int resv1[2];
122 unsigned int cm0dldiff; /* offset 0x028 */
123 unsigned int cm0iclkout; /* offset 0x02C */
124 unsigned int resv2[8];
125 unsigned int cm1csratio; /* offset 0x050 */
126 unsigned int resv3[2];
127 unsigned int cm1dldiff; /* offset 0x05C */
128 unsigned int cm1iclkout; /* offset 0x060 */
129 unsigned int resv4[8];
130 unsigned int cm2csratio; /* offset 0x084 */
131 unsigned int resv5[2];
132 unsigned int cm2dldiff; /* offset 0x090 */
133 unsigned int cm2iclkout; /* offset 0x094 */
134 unsigned int resv6[3];
135};
136
137struct ddr_data_regs {
138 unsigned int dt0rdsratio0; /* offset 0x0C8 */
139 unsigned int resv1[4];
140 unsigned int dt0wdsratio0; /* offset 0x0DC */
141 unsigned int resv2[4];
142 unsigned int dt0wiratio0; /* offset 0x0F0 */
143 unsigned int resv3;
144 unsigned int dt0wimode0; /* offset 0x0F8 */
145 unsigned int dt0giratio0; /* offset 0x0FC */
146 unsigned int resv4;
147 unsigned int dt0gimode0; /* offset 0x104 */
148 unsigned int dt0fwsratio0; /* offset 0x108 */
149 unsigned int resv5[4];
150 unsigned int dt0dqoffset; /* offset 0x11C */
151 unsigned int dt0wrsratio0; /* offset 0x120 */
152 unsigned int resv6[4];
153 unsigned int dt0rdelays0; /* offset 0x134 */
154 unsigned int dt0dldiff0; /* offset 0x138 */
155 unsigned int resv7[12];
156};
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]157
158/**
159 * This structure represents the DDR registers on AM33XX devices.
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]160 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
161 * correspond to DATA1 registers defined here.
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]162 */
163struct ddr_regs {
164 unsigned int resv0[7];
165 unsigned int cm0csratio; /* offset 0x01C */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]166 unsigned int resv1[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]167 unsigned int cm0dldiff; /* offset 0x028 */
168 unsigned int cm0iclkout; /* offset 0x02C */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]169 unsigned int resv2[8];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]170 unsigned int cm1csratio; /* offset 0x050 */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]171 unsigned int resv3[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]172 unsigned int cm1dldiff; /* offset 0x05C */
173 unsigned int cm1iclkout; /* offset 0x060 */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]174 unsigned int resv4[8];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]175 unsigned int cm2csratio; /* offset 0x084 */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]176 unsigned int resv5[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]177 unsigned int cm2dldiff; /* offset 0x090 */
178 unsigned int cm2iclkout; /* offset 0x094 */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]179 unsigned int resv6[12];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]180 unsigned int dt0rdsratio0; /* offset 0x0C8 */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]181 unsigned int resv7[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]182 unsigned int dt0wdsratio0; /* offset 0x0DC */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]183 unsigned int resv8[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]184 unsigned int dt0wiratio0; /* offset 0x0F0 */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]185 unsigned int resv9;
186 unsigned int dt0wimode0; /* offset 0x0F8 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]187 unsigned int dt0giratio0; /* offset 0x0FC */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]188 unsigned int resv10;
189 unsigned int dt0gimode0; /* offset 0x104 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]190 unsigned int dt0fwsratio0; /* offset 0x108 */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]191 unsigned int resv11[4];
192 unsigned int dt0dqoffset; /* offset 0x11C */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]193 unsigned int dt0wrsratio0; /* offset 0x120 */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]194 unsigned int resv12[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]195 unsigned int dt0rdelays0; /* offset 0x134 */
196 unsigned int dt0dldiff0; /* offset 0x138 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]197};
198
199/**
200 * Encapsulates DDR CMD control registers.
201 */
202struct cmd_control {
203 unsigned long cmd0csratio;
204 unsigned long cmd0csforce;
205 unsigned long cmd0csdelay;
206 unsigned long cmd0dldiff;
207 unsigned long cmd0iclkout;
208 unsigned long cmd1csratio;
209 unsigned long cmd1csforce;
210 unsigned long cmd1csdelay;
211 unsigned long cmd1dldiff;
212 unsigned long cmd1iclkout;
213 unsigned long cmd2csratio;
214 unsigned long cmd2csforce;
215 unsigned long cmd2csdelay;
216 unsigned long cmd2dldiff;
217 unsigned long cmd2iclkout;
218};
219
220/**
221 * Encapsulates DDR DATA registers.
222 */
223struct ddr_data {
224 unsigned long datardsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]225 unsigned long datawdsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]226 unsigned long datawiratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]227 unsigned long datagiratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]228 unsigned long datafwsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]229 unsigned long datawrsratio0;
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]230 unsigned long datauserank0delay;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]231 unsigned long datadldiff0;
232};
233
234/**
235 * Configure DDR CMD control registers
236 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame^]237void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]238
239/**
240 * Configure DDR DATA registers
241 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame^]242void config_ddr_data(const struct ddr_data *data, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]243
244/**
245 * This structure represents the DDR io control on AM33XX devices.
246 */
247struct ddr_cmdtctrl {
248 unsigned int resv1[1];
249 unsigned int cm0ioctl;
250 unsigned int cm1ioctl;
251 unsigned int cm2ioctl;
252 unsigned int resv2[12];
253 unsigned int dt0ioctl;
254 unsigned int dt1ioctl;
255};
256
257/**
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]258 * Configure DDR io control registers
259 */
Tom Rinib239b3b2012-07-24 16:31:26 -0700[diff] [blame]260void config_io_ctrl(unsigned long val);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]261
262struct ddr_ctrl {
263 unsigned int ddrioctrl;
264 unsigned int resv1[325];
265 unsigned int ddrckectrl;
266};
267
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]268void config_ddr(unsigned int pll, unsigned int ioctrl,
269 const struct ddr_data *data, const struct cmd_control *ctrl,
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame^]270 const struct emif_regs *regs, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]271
272#endif /* _DDR_DEFS_H */