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git01.mediatek.com / filogic / uboot / b239b3bd24fa6273f8243403b4b0de60167f5e78 / . / arch / arm / include / asm / arch-am33xx / ddr_defs.h
blob: ebd3077f72ffe3ac98f1f63f8baab793025c2be9 [file] [log] [blame]
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]1/*
2 * ddr_defs.h
3 *
4 * ddr specific header
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef _DDR_DEFS_H
20#define _DDR_DEFS_H
21
22#include <asm/arch/hardware.h>
Tom Rinib668ae42012-07-24 14:55:38 -0700[diff] [blame]23#include <asm/emif.h>
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]24
25/* AM335X EMIF Register values */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]26#define VTP_CTRL_READY (0x1 << 5)
27#define VTP_CTRL_ENABLE (0x1 << 6)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]28#define VTP_CTRL_START_EN (0x1)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]29#define CMD_FORCE 0x00
30#define CMD_DELAY 0x00
Tom Rinif4914f92012-07-24 13:05:10 -0700[diff] [blame]31#define PHY_DLL_LOCK_DIFF 0x0
Tom Rinide3c5702012-07-24 14:03:24 -0700[diff] [blame]32#define DDR_CKE_CTRL_NORMAL 0x1
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]33
Vaibhav Bediaa1255122012-04-20 13:28:16 +0530[diff] [blame]34#define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */
35#define DDR2_EMIF_TIM1 0x0666B3C9
36#define DDR2_EMIF_TIM2 0x243631CA
37#define DDR2_EMIF_TIM3 0x0000033F
38#define DDR2_EMIF_SDCFG 0x41805332
Tom Rinif4914f92012-07-24 13:05:10 -0700[diff] [blame]39#define DDR2_EMIF_SDREF 0x0000081a
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]40#define DDR2_DLL_LOCK_DIFF 0x0
Tom Rinif4914f92012-07-24 13:05:10 -0700[diff] [blame]41#define DDR2_RATIO 0x80
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]42#define DDR2_INVERT_CLKOUT 0x00
Tom Rinif4914f92012-07-24 13:05:10 -0700[diff] [blame]43#define DDR2_RD_DQS 0x12
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]44#define DDR2_WR_DQS 0x00
45#define DDR2_PHY_WRLVL 0x00
46#define DDR2_PHY_GATELVL 0x00
47#define DDR2_PHY_WR_DATA 0x40
Tom Rinif4914f92012-07-24 13:05:10 -0700[diff] [blame]48#define DDR2_PHY_FIFO_WE 0x80
49#define DDR2_PHY_RANK0_DELAY 0x1
50#define DDR2_IOCTRL_VALUE 0x18B
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]51
52/**
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]53 * Configure SDRAM
54 */
Tom Rinib668ae42012-07-24 14:55:38 -0700[diff] [blame]55void config_sdram(const struct emif_regs *regs);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]56
57/**
58 * Set SDRAM timings
59 */
Tom Rinib668ae42012-07-24 14:55:38 -0700[diff] [blame]60void set_sdram_timings(const struct emif_regs *regs);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]61
62/**
63 * Configure DDR PHY
64 */
Tom Rinib668ae42012-07-24 14:55:38 -0700[diff] [blame]65void config_ddr_phy(const struct emif_regs *regs);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]66
67/**
68 * This structure represents the DDR registers on AM33XX devices.
69 */
70struct ddr_regs {
71 unsigned int resv0[7];
72 unsigned int cm0csratio; /* offset 0x01C */
73 unsigned int cm0csforce; /* offset 0x020 */
74 unsigned int cm0csdelay; /* offset 0x024 */
75 unsigned int cm0dldiff; /* offset 0x028 */
76 unsigned int cm0iclkout; /* offset 0x02C */
77 unsigned int resv1[8];
78 unsigned int cm1csratio; /* offset 0x050 */
79 unsigned int cm1csforce; /* offset 0x054 */
80 unsigned int cm1csdelay; /* offset 0x058 */
81 unsigned int cm1dldiff; /* offset 0x05C */
82 unsigned int cm1iclkout; /* offset 0x060 */
83 unsigned int resv2[8];
84 unsigned int cm2csratio; /* offset 0x084 */
85 unsigned int cm2csforce; /* offset 0x088 */
86 unsigned int cm2csdelay; /* offset 0x08C */
87 unsigned int cm2dldiff; /* offset 0x090 */
88 unsigned int cm2iclkout; /* offset 0x094 */
89 unsigned int resv3[12];
90 unsigned int dt0rdsratio0; /* offset 0x0C8 */
91 unsigned int dt0rdsratio1; /* offset 0x0CC */
92 unsigned int resv4[3];
93 unsigned int dt0wdsratio0; /* offset 0x0DC */
94 unsigned int dt0wdsratio1; /* offset 0x0E0 */
95 unsigned int resv5[3];
96 unsigned int dt0wiratio0; /* offset 0x0F0 */
97 unsigned int dt0wiratio1; /* offset 0x0F4 */
98 unsigned int dt0giratio0; /* offset 0x0FC */
99 unsigned int dt0giratio1; /* offset 0x100 */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]100 unsigned int resv6[1];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]101 unsigned int dt0fwsratio0; /* offset 0x108 */
102 unsigned int dt0fwsratio1; /* offset 0x10C */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]103 unsigned int resv7[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]104 unsigned int dt0wrsratio0; /* offset 0x120 */
105 unsigned int dt0wrsratio1; /* offset 0x124 */
106 unsigned int resv8[3];
107 unsigned int dt0rdelays0; /* offset 0x134 */
108 unsigned int dt0dldiff0; /* offset 0x138 */
109 unsigned int resv9[39];
110 unsigned int dt1rdelays0; /* offset 0x1D8 */
111};
112
113/**
114 * Encapsulates DDR CMD control registers.
115 */
116struct cmd_control {
117 unsigned long cmd0csratio;
118 unsigned long cmd0csforce;
119 unsigned long cmd0csdelay;
120 unsigned long cmd0dldiff;
121 unsigned long cmd0iclkout;
122 unsigned long cmd1csratio;
123 unsigned long cmd1csforce;
124 unsigned long cmd1csdelay;
125 unsigned long cmd1dldiff;
126 unsigned long cmd1iclkout;
127 unsigned long cmd2csratio;
128 unsigned long cmd2csforce;
129 unsigned long cmd2csdelay;
130 unsigned long cmd2dldiff;
131 unsigned long cmd2iclkout;
132};
133
134/**
135 * Encapsulates DDR DATA registers.
136 */
137struct ddr_data {
138 unsigned long datardsratio0;
139 unsigned long datardsratio1;
140 unsigned long datawdsratio0;
141 unsigned long datawdsratio1;
142 unsigned long datawiratio0;
143 unsigned long datawiratio1;
144 unsigned long datagiratio0;
145 unsigned long datagiratio1;
146 unsigned long datafwsratio0;
147 unsigned long datafwsratio1;
148 unsigned long datawrsratio0;
149 unsigned long datawrsratio1;
150 unsigned long datadldiff0;
151};
152
153/**
154 * Configure DDR CMD control registers
155 */
Tom Rini6f868cf2012-07-24 14:54:41 -0700[diff] [blame]156void config_cmd_ctrl(const struct cmd_control *cmd);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]157
158/**
159 * Configure DDR DATA registers
160 */
Tom Rini6f868cf2012-07-24 14:54:41 -0700[diff] [blame]161void config_ddr_data(int data_macrono, const struct ddr_data *data);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]162
163/**
164 * This structure represents the DDR io control on AM33XX devices.
165 */
166struct ddr_cmdtctrl {
167 unsigned int resv1[1];
168 unsigned int cm0ioctl;
169 unsigned int cm1ioctl;
170 unsigned int cm2ioctl;
171 unsigned int resv2[12];
172 unsigned int dt0ioctl;
173 unsigned int dt1ioctl;
174};
175
176/**
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]177 * Configure DDR io control registers
178 */
Tom Rinib239b3b2012-07-24 16:31:26 -0700[diff] [blame^]179void config_io_ctrl(unsigned long val);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]180
181struct ddr_ctrl {
182 unsigned int ddrioctrl;
183 unsigned int resv1[325];
184 unsigned int ddrckectrl;
185};
186
Tom Rini3fd44562012-07-03 08:51:34 -0700[diff] [blame]187void config_ddr(short ddr_type);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]188
189#endif /* _DDR_DEFS_H */