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git01.mediatek.com / filogic / uboot / 3fd44562b46b808dc0f28ae6bac1f30d036d50a3 / . / arch / arm / include / asm / arch-am33xx / ddr_defs.h
blob: 842e45f55955816912ae62613ef6ab5549e2ecdb [file] [log] [blame]
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]1/*
2 * ddr_defs.h
3 *
4 * ddr specific header
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef _DDR_DEFS_H
20#define _DDR_DEFS_H
21
22#include <asm/arch/hardware.h>
23
24/* AM335X EMIF Register values */
25#define EMIF_SDMGT 0x80000000
26#define EMIF_SDRAM 0x00004650
27#define EMIF_PHYCFG 0x2
28#define DDR_PHY_RESET (0x1 << 10)
29#define DDR_FUNCTIONAL_MODE_EN 0x1
30#define DDR_PHY_READY (0x1 << 2)
31#define VTP_CTRL_READY (0x1 << 5)
32#define VTP_CTRL_ENABLE (0x1 << 6)
33#define VTP_CTRL_LOCK_EN (0x1 << 4)
34#define VTP_CTRL_START_EN (0x1)
35#define DDR2_RATIO 0x80
36#define CMD_FORCE 0x00
37#define CMD_DELAY 0x00
38
Chase Maupin2cf9ba82012-02-13 05:57:27 +0000[diff] [blame]39#define EMIF_READ_LATENCY 0x05
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]40#define EMIF_TIM1 0x0666B3D6
41#define EMIF_TIM2 0x143731DA
42#define EMIF_TIM3 0x00000347
43#define EMIF_SDCFG 0x43805332
44#define EMIF_SDREF 0x0000081a
45#define DDR2_DLL_LOCK_DIFF 0x0
46#define DDR2_RD_DQS 0x12
47#define DDR2_PHY_FIFO_WE 0x80
48
49#define DDR2_INVERT_CLKOUT 0x00
50#define DDR2_WR_DQS 0x00
51#define DDR2_PHY_WRLVL 0x00
52#define DDR2_PHY_GATELVL 0x00
53#define DDR2_PHY_WR_DATA 0x40
54#define PHY_RANK0_DELAY 0x01
55#define PHY_DLL_LOCK_DIFF 0x0
56#define DDR_IOCTRL_VALUE 0x18B
57
58/**
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]59 * Encapsulates DDR PHY control and corresponding shadow registers.
60 */
61struct ddr_phy_control {
62 unsigned long reg;
63 unsigned long reg_sh;
64 unsigned long reg2;
65};
66
67/**
68 * Encapsulates SDRAM timing and corresponding shadow registers.
69 */
70struct sdram_timing {
71 unsigned long time1;
72 unsigned long time1_sh;
73 unsigned long time2;
74 unsigned long time2_sh;
75 unsigned long time3;
76 unsigned long time3_sh;
77};
78
79/**
80 * Encapsulates SDRAM configuration.
81 * (Includes refresh control registers) */
82struct sdram_config {
83 unsigned long sdrcr;
84 unsigned long sdrcr2;
85 unsigned long refresh;
86 unsigned long refresh_sh;
87};
88
89/**
90 * Configure SDRAM
91 */
92int config_sdram(struct sdram_config *cfg);
93
94/**
95 * Set SDRAM timings
96 */
97int set_sdram_timings(struct sdram_timing *val);
98
99/**
100 * Configure DDR PHY
101 */
102int config_ddr_phy(struct ddr_phy_control *cfg);
103
104/**
105 * This structure represents the DDR registers on AM33XX devices.
106 */
107struct ddr_regs {
108 unsigned int resv0[7];
109 unsigned int cm0csratio; /* offset 0x01C */
110 unsigned int cm0csforce; /* offset 0x020 */
111 unsigned int cm0csdelay; /* offset 0x024 */
112 unsigned int cm0dldiff; /* offset 0x028 */
113 unsigned int cm0iclkout; /* offset 0x02C */
114 unsigned int resv1[8];
115 unsigned int cm1csratio; /* offset 0x050 */
116 unsigned int cm1csforce; /* offset 0x054 */
117 unsigned int cm1csdelay; /* offset 0x058 */
118 unsigned int cm1dldiff; /* offset 0x05C */
119 unsigned int cm1iclkout; /* offset 0x060 */
120 unsigned int resv2[8];
121 unsigned int cm2csratio; /* offset 0x084 */
122 unsigned int cm2csforce; /* offset 0x088 */
123 unsigned int cm2csdelay; /* offset 0x08C */
124 unsigned int cm2dldiff; /* offset 0x090 */
125 unsigned int cm2iclkout; /* offset 0x094 */
126 unsigned int resv3[12];
127 unsigned int dt0rdsratio0; /* offset 0x0C8 */
128 unsigned int dt0rdsratio1; /* offset 0x0CC */
129 unsigned int resv4[3];
130 unsigned int dt0wdsratio0; /* offset 0x0DC */
131 unsigned int dt0wdsratio1; /* offset 0x0E0 */
132 unsigned int resv5[3];
133 unsigned int dt0wiratio0; /* offset 0x0F0 */
134 unsigned int dt0wiratio1; /* offset 0x0F4 */
135 unsigned int dt0giratio0; /* offset 0x0FC */
136 unsigned int dt0giratio1; /* offset 0x100 */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]137 unsigned int resv6[1];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]138 unsigned int dt0fwsratio0; /* offset 0x108 */
139 unsigned int dt0fwsratio1; /* offset 0x10C */
Chandan Nath5b5c2122012-01-09 20:38:56 +0000[diff] [blame]140 unsigned int resv7[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]141 unsigned int dt0wrsratio0; /* offset 0x120 */
142 unsigned int dt0wrsratio1; /* offset 0x124 */
143 unsigned int resv8[3];
144 unsigned int dt0rdelays0; /* offset 0x134 */
145 unsigned int dt0dldiff0; /* offset 0x138 */
146 unsigned int resv9[39];
147 unsigned int dt1rdelays0; /* offset 0x1D8 */
148};
149
150/**
151 * Encapsulates DDR CMD control registers.
152 */
153struct cmd_control {
154 unsigned long cmd0csratio;
155 unsigned long cmd0csforce;
156 unsigned long cmd0csdelay;
157 unsigned long cmd0dldiff;
158 unsigned long cmd0iclkout;
159 unsigned long cmd1csratio;
160 unsigned long cmd1csforce;
161 unsigned long cmd1csdelay;
162 unsigned long cmd1dldiff;
163 unsigned long cmd1iclkout;
164 unsigned long cmd2csratio;
165 unsigned long cmd2csforce;
166 unsigned long cmd2csdelay;
167 unsigned long cmd2dldiff;
168 unsigned long cmd2iclkout;
169};
170
171/**
172 * Encapsulates DDR DATA registers.
173 */
174struct ddr_data {
175 unsigned long datardsratio0;
176 unsigned long datardsratio1;
177 unsigned long datawdsratio0;
178 unsigned long datawdsratio1;
179 unsigned long datawiratio0;
180 unsigned long datawiratio1;
181 unsigned long datagiratio0;
182 unsigned long datagiratio1;
183 unsigned long datafwsratio0;
184 unsigned long datafwsratio1;
185 unsigned long datawrsratio0;
186 unsigned long datawrsratio1;
187 unsigned long datadldiff0;
188};
189
190/**
191 * Configure DDR CMD control registers
192 */
Tom Rini1652dd52012-07-03 08:48:46 -0700[diff] [blame]193int config_cmd_ctrl(const struct cmd_control *cmd);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]194
195/**
196 * Configure DDR DATA registers
197 */
Tom Rini1652dd52012-07-03 08:48:46 -0700[diff] [blame]198int config_ddr_data(int data_macrono, const struct ddr_data *data);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]199
200/**
201 * This structure represents the DDR io control on AM33XX devices.
202 */
203struct ddr_cmdtctrl {
204 unsigned int resv1[1];
205 unsigned int cm0ioctl;
206 unsigned int cm1ioctl;
207 unsigned int cm2ioctl;
208 unsigned int resv2[12];
209 unsigned int dt0ioctl;
210 unsigned int dt1ioctl;
211};
212
213/**
214 * Encapsulates DDR CMD & DATA io control registers.
215 */
216struct ddr_ioctrl {
217 unsigned long cmd1ctl;
218 unsigned long cmd2ctl;
219 unsigned long cmd3ctl;
220 unsigned long data1ctl;
221 unsigned long data2ctl;
222};
223
224/**
225 * Configure DDR io control registers
226 */
227int config_io_ctrl(struct ddr_ioctrl *ioctrl);
228
229struct ddr_ctrl {
230 unsigned int ddrioctrl;
231 unsigned int resv1[325];
232 unsigned int ddrckectrl;
233};
234
Tom Rini3fd44562012-07-03 08:51:34 -0700[diff] [blame^]235void config_ddr(short ddr_type);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]236
237#endif /* _DDR_DEFS_H */