Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 1 | menu "MediaTek MIPS platforms" |
developer | 89f051b | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 2 | depends on ARCH_MTMIPS |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 3 | |
Guillaume La Roque | a24e1cf | 2021-09-10 10:21:06 +0200 | [diff] [blame] | 4 | config SYS_VENDOR |
| 5 | default "mediatek" if BOARD_MT7628_RFB || BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB |
| 6 | |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 7 | config SYS_MALLOC_F_LEN |
| 8 | default 0x1000 |
| 9 | |
| 10 | config SYS_SOC |
developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 11 | default "mt7620" if SOC_MT7620 |
developer | 89f051b | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 12 | default "mt7628" if SOC_MT7628 |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 13 | |
developer | 26f763e | 2020-04-21 09:28:26 +0200 | [diff] [blame] | 14 | config SYS_DCACHE_SIZE |
| 15 | default 32768 |
| 16 | |
| 17 | config SYS_DCACHE_LINE_SIZE |
| 18 | default 32 |
| 19 | |
| 20 | config SYS_ICACHE_SIZE |
| 21 | default 65536 |
| 22 | |
| 23 | config SYS_ICACHE_LINE_SIZE |
| 24 | default 32 |
| 25 | |
developer | 29b37c5 | 2020-04-21 09:28:34 +0200 | [diff] [blame] | 26 | config SYS_TEXT_BASE |
developer | 19d572e | 2020-04-21 09:28:47 +0200 | [diff] [blame] | 27 | default 0x9c000000 if !SPL |
| 28 | default 0x80200000 if SPL |
| 29 | |
| 30 | config SPL_TEXT_BASE |
developer | 29b37c5 | 2020-04-21 09:28:34 +0200 | [diff] [blame] | 31 | default 0x9c000000 |
| 32 | |
developer | 19d572e | 2020-04-21 09:28:47 +0200 | [diff] [blame] | 33 | config SPL_PAYLOAD |
| 34 | default "u-boot-lzma.img" if SPL_LZMA |
| 35 | |
| 36 | config BUILD_TARGET |
| 37 | default "u-boot-with-spl.bin" if SPL |
developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 38 | default "u-boot.bin" |
developer | 19d572e | 2020-04-21 09:28:47 +0200 | [diff] [blame] | 39 | |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 40 | choice |
| 41 | prompt "MediaTek MIPS SoC select" |
| 42 | |
developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 43 | config SOC_MT7620 |
| 44 | bool "MT7620" |
Tom Rini | 3ef67ae | 2021-08-26 11:47:59 -0400 | [diff] [blame] | 45 | select SYS_CACHE_SHIFT_5 |
developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 46 | select SYS_MIPS_CACHE_INIT_RAM_LOAD |
| 47 | select PINCTRL_MT7620 |
| 48 | select MT7620_SERIAL |
| 49 | select MISC |
| 50 | select SPL_SEPARATE_BSS if SPL |
| 51 | select SPL_LOADER_SUPPORT if SPL |
| 52 | select SPL_OF_CONTROL if SPL_DM |
| 53 | select SPL_OF_PLATDATA if SPL_DM |
| 54 | select SPL_DM_SERIAL if SPL_DM |
| 55 | help |
| 56 | This supports MediaTek MT7620. |
| 57 | |
developer | 89f051b | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 58 | config SOC_MT7628 |
| 59 | bool "MT7628" |
Tom Rini | 3ef67ae | 2021-08-26 11:47:59 -0400 | [diff] [blame] | 60 | select SYS_CACHE_SHIFT_5 |
developer | 29b37c5 | 2020-04-21 09:28:34 +0200 | [diff] [blame] | 61 | select MIPS_INIT_STACK_IN_SRAM |
| 62 | select MIPS_SRAM_INIT |
| 63 | select SYS_MIPS_CACHE_INIT_RAM_LOAD |
developer | 591826e | 2019-09-25 17:45:43 +0800 | [diff] [blame] | 64 | select PINCTRL_MT7628 |
| 65 | select MTK_SERIAL |
developer | 93f7400 | 2020-11-12 16:35:28 +0800 | [diff] [blame] | 66 | select SYSRESET |
developer | 3b3015f | 2020-04-21 09:28:30 +0200 | [diff] [blame] | 67 | select SYSRESET_RESETCTL |
developer | 19d572e | 2020-04-21 09:28:47 +0200 | [diff] [blame] | 68 | select SPL_SEPARATE_BSS if SPL |
| 69 | select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL |
| 70 | select SPL_LOADER_SUPPORT if SPL |
| 71 | select SPL_OF_CONTROL if SPL_DM |
| 72 | select SPL_SIMPLE_BUS if SPL_DM |
| 73 | select SPL_DM_SERIAL if SPL_DM |
Simon Glass | f4d6039 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 74 | select SPL_CLK if SPL_DM && SPL_SERIAL |
developer | 19d572e | 2020-04-21 09:28:47 +0200 | [diff] [blame] | 75 | select SPL_SYSRESET if SPL_DM |
| 76 | select SPL_OF_LIBFDT if SPL_OF_CONTROL |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 77 | help |
developer | 89f051b | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 78 | This supports MediaTek MT7628/MT7688. |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 79 | |
| 80 | endchoice |
| 81 | |
developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 82 | source "arch/mips/mach-mtmips/mt7620/Kconfig" |
developer | 37e34ba | 2020-11-12 16:35:23 +0800 | [diff] [blame] | 83 | source "arch/mips/mach-mtmips/mt7628/Kconfig" |
Stefan Roese | 2052a93 | 2018-08-16 15:27:30 +0200 | [diff] [blame] | 84 | |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 85 | endmenu |