blob: a504a0ea462a1c34d3bd7cede7285895457b07f4 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
York Sune12abcb2015-03-20 19:28:24 -07002/*
Yangbo Lubb32e682021-06-03 10:51:19 +08003 * Copyright 2017, 2019-2021 NXP
York Sune12abcb2015-03-20 19:28:24 -07004 * Copyright 2015 Freescale Semiconductor
York Sune12abcb2015-03-20 19:28:24 -07005 */
6
7#ifndef __LS2_RDB_H
8#define __LS2_RDB_H
9
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +053010#include "ls2080a_common.h"
York Sune12abcb2015-03-20 19:28:24 -070011
Rai Harninder6aa1f3b2016-03-23 17:04:38 +053012#define I2C_MUX_CH_VOL_MONITOR 0xa
13#define I2C_VOL_MONITOR_ADDR 0x38
Rai Harninder6aa1f3b2016-03-23 17:04:38 +053014
Rai Harninder6aa1f3b2016-03-23 17:04:38 +053015/* step the IR regulator in 5mV increments */
16#define IR_VDD_STEP_DOWN 5
17#define IR_VDD_STEP_UP 5
18/* The lowest and highest voltage allowed for LS2080ARDB */
19#define VDD_MV_MIN 819
20#define VDD_MV_MAX 1212
21
Tom Rini8c70baa2021-12-14 13:36:40 -050022#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
York Sune12abcb2015-03-20 19:28:24 -070023
York Sune12abcb2015-03-20 19:28:24 -070024#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
25#define SPD_EEPROM_ADDRESS1 0x51
26#define SPD_EEPROM_ADDRESS2 0x52
York Sunac192a92015-05-28 14:54:09 +053027#define SPD_EEPROM_ADDRESS3 0x53
28#define SPD_EEPROM_ADDRESS4 0x54
York Sune12abcb2015-03-20 19:28:24 -070029#define SPD_EEPROM_ADDRESS5 0x55
30#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
31#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
York Sune12abcb2015-03-20 19:28:24 -070032
Rajesh Bhagatd5691be2018-12-27 04:37:59 +000033#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
York Sune12abcb2015-03-20 19:28:24 -070034
35#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
36#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
37#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
38
39#define CONFIG_SYS_NOR0_CSPR \
40 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
41 CSPR_PORT_SIZE_16 | \
42 CSPR_MSEL_NOR | \
43 CSPR_V)
44#define CONFIG_SYS_NOR0_CSPR_EARLY \
45 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
46 CSPR_PORT_SIZE_16 | \
47 CSPR_MSEL_NOR | \
48 CSPR_V)
49#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
50#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
51 FTIM0_NOR_TEADC(0x5) | \
52 FTIM0_NOR_TEAHC(0x5))
53#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
54 FTIM1_NOR_TRAD_NOR(0x1a) |\
55 FTIM1_NOR_TSEQRAD_NOR(0x13))
56#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
57 FTIM2_NOR_TCH(0x4) | \
58 FTIM2_NOR_TWPH(0x0E) | \
59 FTIM2_NOR_TWP(0x1c))
60#define CONFIG_SYS_NOR_FTIM3 0x04000000
61#define CONFIG_SYS_IFC_CCR 0x01000000
62
Masahiro Yamada8cea9b52017-02-11 22:43:54 +090063#ifdef CONFIG_MTD_NOR_FLASH
York Sune12abcb2015-03-20 19:28:24 -070064#define CONFIG_SYS_FLASH_QUIET_TEST
65#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
66
York Sune12abcb2015-03-20 19:28:24 -070067#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
68#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
69#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
70
71#define CONFIG_SYS_FLASH_EMPTY_INFO
72#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
73 CONFIG_SYS_FLASH_BASE + 0x40000000}
74#endif
75
York Sune12abcb2015-03-20 19:28:24 -070076#define CONFIG_SYS_NAND_MAX_ECCPOS 256
77#define CONFIG_SYS_NAND_MAX_OOBFREE 2
78
York Sune12abcb2015-03-20 19:28:24 -070079#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
80#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
81 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
82 | CSPR_MSEL_NAND /* MSEL = NAND */ \
83 | CSPR_V)
84#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
85
86#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
87 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
88 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
89 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
90 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
91 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
92 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
93
York Sune12abcb2015-03-20 19:28:24 -070094/* ONFI NAND Flash mode0 Timing Params */
95#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
96 FTIM0_NAND_TWP(0x30) | \
97 FTIM0_NAND_TWCHT(0x0e) | \
98 FTIM0_NAND_TWH(0x14))
99#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
100 FTIM1_NAND_TWBE(0xab) | \
101 FTIM1_NAND_TRR(0x1c) | \
102 FTIM1_NAND_TRP(0x30))
103#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
104 FTIM2_NAND_TREH(0x14) | \
105 FTIM2_NAND_TWHRE(0x3c))
106#define CONFIG_SYS_NAND_FTIM3 0x0
107
108#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
109#define CONFIG_SYS_MAX_NAND_DEVICE 1
110#define CONFIG_MTD_NAND_VERIFY_WRITE
York Sune12abcb2015-03-20 19:28:24 -0700111
York Sune12abcb2015-03-20 19:28:24 -0700112#define QIXIS_LBMAP_SWITCH 0x06
113#define QIXIS_LBMAP_MASK 0x0f
114#define QIXIS_LBMAP_SHIFT 0
115#define QIXIS_LBMAP_DFLTBANK 0x00
116#define QIXIS_LBMAP_ALTBANK 0x04
Scott Wood212b8d82015-03-24 13:25:03 -0700117#define QIXIS_LBMAP_NAND 0x09
York Sune12abcb2015-03-20 19:28:24 -0700118#define QIXIS_RST_CTL_RESET 0x31
119#define QIXIS_RST_CTL_RESET_EN 0x30
120#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
121#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
122#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Scott Wood212b8d82015-03-24 13:25:03 -0700123#define QIXIS_RCW_SRC_NAND 0x119
York Sune12abcb2015-03-20 19:28:24 -0700124#define QIXIS_RST_FORCE_MEM 0x01
125
126#define CONFIG_SYS_CSPR3_EXT (0x0)
127#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
128 | CSPR_PORT_SIZE_8 \
129 | CSPR_MSEL_GPCM \
130 | CSPR_V)
131#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
132 | CSPR_PORT_SIZE_8 \
133 | CSPR_MSEL_GPCM \
134 | CSPR_V)
135
136#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
137#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
138/* QIXIS Timing parameters for IFC CS3 */
139#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
140 FTIM0_GPCM_TEADC(0x0e) | \
141 FTIM0_GPCM_TEAHC(0x0e))
142#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
143 FTIM1_GPCM_TRAD(0x3f))
144#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
145 FTIM2_GPCM_TCH(0xf) | \
146 FTIM2_GPCM_TWP(0x3E))
147#define CONFIG_SYS_CS3_FTIM3 0x0
148
Miquel Raynald0935362019-10-03 19:50:03 +0200149#if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
Scott Wood212b8d82015-03-24 13:25:03 -0700150#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
151#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
152#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
153#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
154#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
155#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
156#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
157#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
158#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
159#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
160#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
161#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
162#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
163#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
164#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
165#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
166#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
167
Scott Wood212b8d82015-03-24 13:25:03 -0700168#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
169#else
York Sune12abcb2015-03-20 19:28:24 -0700170#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
171#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
172#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
173#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
174#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
175#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
176#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
177#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
178#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
179#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
180#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
181#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
182#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
183#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
184#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
185#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
186#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000187#endif
Scott Wood212b8d82015-03-24 13:25:03 -0700188
York Sune12abcb2015-03-20 19:28:24 -0700189/* Debug Server firmware */
190#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
191#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
Priyanka Jain7d05b992017-04-28 10:41:35 +0530192#endif
York Sune12abcb2015-03-20 19:28:24 -0700193#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
194
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530195#ifdef CONFIG_TARGET_LS2081ARDB
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530196#define QIXIS_QMAP_MASK 0x07
197#define QIXIS_QMAP_SHIFT 5
198#define QIXIS_LBMAP_DFLTBANK 0x00
199#define QIXIS_LBMAP_QSPI 0x00
200#define QIXIS_RCW_SRC_QSPI 0x62
201#define QIXIS_LBMAP_ALTBANK 0x20
202#define QIXIS_RST_CTL_RESET 0x31
203#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
204#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
205#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
206#define QIXIS_LBMAP_MASK 0x0f
207#define QIXIS_RST_CTL_RESET_EN 0x30
208#endif
209
York Sune12abcb2015-03-20 19:28:24 -0700210/*
211 * I2C
212 */
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530213#ifdef CONFIG_TARGET_LS2081ARDB
214#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
215#endif
Prabhakar Kushwahad561e2d2015-05-28 14:54:01 +0530216#define I2C_MUX_PCA_ADDR 0x75
217#define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
York Sune12abcb2015-03-20 19:28:24 -0700218
219/* I2C bus multiplexer */
220#define I2C_MUX_CH_DEFAULT 0x8
221
Haikun Wang7e3180d2015-07-03 16:51:35 +0800222/* SPI */
Haikun Wang7e3180d2015-07-03 16:51:35 +0800223
York Sune12abcb2015-03-20 19:28:24 -0700224/*
225 * RTC configuration
226 */
227#define RTC
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530228#ifdef CONFIG_TARGET_LS2081ARDB
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530229#define CONFIG_SYS_I2C_RTC_ADDR 0x51
230#else
York Sune12abcb2015-03-20 19:28:24 -0700231#define CONFIG_RTC_DS3231 1
232#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Priyanka Jain75cd67f2017-04-27 15:08:07 +0530233#endif
York Sune12abcb2015-03-20 19:28:24 -0700234
235/* EEPROM */
York Sune12abcb2015-03-20 19:28:24 -0700236#define CONFIG_SYS_I2C_EEPROM_NXID
237#define CONFIG_SYS_EEPROM_BUS_NUM 0
York Sune12abcb2015-03-20 19:28:24 -0700238
York Sune12abcb2015-03-20 19:28:24 -0700239#define CONFIG_FSL_MEMAC
York Sune12abcb2015-03-20 19:28:24 -0700240
Alexander Graf39e4f242016-11-17 01:03:02 +0100241#define BOOT_TARGET_DEVICES(func) \
242 func(USB, usb, 0) \
243 func(MMC, mmc, 0) \
Mian Yousaf Kaukabcedf23f2019-01-29 16:38:34 +0100244 func(SCSI, scsi, 0) \
245 func(DHCP, dhcp, na)
Alexander Graf39e4f242016-11-17 01:03:02 +0100246#include <config_distro_bootcmd.h>
247
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000248#ifdef CONFIG_TFABOOT
Kuldeep Singh73129d22020-02-07 22:09:09 +0530249#define QSPI_MC_INIT_CMD \
250 "sf probe 0:0; " \
251 "sf read 0x80640000 0x640000 0x80000; " \
252 "env exists secureboot && " \
253 "esbc_validate 0x80640000 && " \
254 "esbc_validate 0x80680000; " \
Priyanka Jaind0f94bb2021-07-19 15:07:49 +0530255 "sf read 0x80a00000 0xa00000 0x200000; " \
Kuldeep Singh73129d22020-02-07 22:09:09 +0530256 "sf read 0x80e00000 0xe00000 0x100000; " \
257 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000258#define SD_MC_INIT_CMD \
Priyanka Jaind0f94bb2021-07-19 15:07:49 +0530259 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
Wasim Khan01ae4352019-06-10 10:17:29 +0000260 "mmc read 0x80e00000 0x7000 0x800;" \
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000261 "env exists secureboot && " \
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000262 "mmc read 0x80640000 0x3200 0x20 && " \
263 "mmc read 0x80680000 0x3400 0x20 && " \
264 "esbc_validate 0x80640000 && " \
265 "esbc_validate 0x80680000 ;" \
Wasim Khan01ae4352019-06-10 10:17:29 +0000266 "fsl_mc start mc 0x80a00000 0x80e00000\0"
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000267#define IFC_MC_INIT_CMD \
268 "env exists secureboot && " \
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000269 "esbc_validate 0x580640000 && " \
270 "esbc_validate 0x580680000; " \
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000271 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
272#else
VINITHA PILLAI6c98ff82017-06-12 09:43:45 +0530273#ifdef CONFIG_QSPI_BOOT
Kuldeep Singh73129d22020-02-07 22:09:09 +0530274#define MC_INIT_CMD \
275 "mcinitcmd=sf probe 0:0; " \
276 "sf read 0x80640000 0x640000 0x80000; " \
277 "env exists secureboot && " \
278 "esbc_validate 0x80640000 && " \
279 "esbc_validate 0x80680000; " \
Priyanka Jaind0f94bb2021-07-19 15:07:49 +0530280 "sf read 0x80a00000 0xa00000 0x200000; " \
Kuldeep Singh73129d22020-02-07 22:09:09 +0530281 "sf read 0x80e00000 0xe00000 0x100000; " \
282 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
Shengzhou Liu184d7ca2017-11-09 17:57:58 +0800283#elif defined(CONFIG_SD_BOOT)
284#define MC_INIT_CMD \
Priyanka Jaind0f94bb2021-07-19 15:07:49 +0530285 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
286 "mmc read 0x80e00000 0x7000 0x800;" \
Shengzhou Liu184d7ca2017-11-09 17:57:58 +0800287 "env exists secureboot && " \
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000288 "mmc read 0x80640000 0x3200 0x20 && " \
289 "mmc read 0x80680000 0x3400 0x20 && " \
290 "esbc_validate 0x80640000 && " \
291 "esbc_validate 0x80680000 ;" \
Priyanka Jaind0f94bb2021-07-19 15:07:49 +0530292 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
Shengzhou Liu184d7ca2017-11-09 17:57:58 +0800293 "mcmemsize=0x70000000\0"
VINITHA PILLAI6c98ff82017-06-12 09:43:45 +0530294#else
295#define MC_INIT_CMD \
296 "mcinitcmd=env exists secureboot && " \
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000297 "esbc_validate 0x580640000 && " \
298 "esbc_validate 0x580680000; " \
VINITHA PILLAI6c98ff82017-06-12 09:43:45 +0530299 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
300#endif
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000301#endif
VINITHA PILLAI6c98ff82017-06-12 09:43:45 +0530302
York Sune12abcb2015-03-20 19:28:24 -0700303/* Initial environment variables */
304#undef CONFIG_EXTRA_ENV_SETTINGS
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000305#ifdef CONFIG_TFABOOT
306#define CONFIG_EXTRA_ENV_SETTINGS \
307 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
308 "ramdisk_addr=0x800000\0" \
309 "ramdisk_size=0x2000000\0" \
310 "fdt_high=0xa0000000\0" \
311 "initrd_high=0xffffffffffffffff\0" \
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000312 "kernel_addr=0x581000000\0" \
313 "kernel_start=0x1000000\0" \
314 "kernelheader_start=0x800000\0" \
315 "scriptaddr=0x80000000\0" \
316 "scripthdraddr=0x80080000\0" \
317 "fdtheader_addr_r=0x80100000\0" \
318 "kernelheader_addr_r=0x80200000\0" \
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000319 "kernelheader_addr=0x580600000\0" \
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000320 "kernel_addr_r=0x81000000\0" \
321 "kernelheader_size=0x40000\0" \
322 "fdt_addr_r=0x90000000\0" \
323 "load_addr=0xa0000000\0" \
324 "kernel_size=0x2800000\0" \
325 "kernel_addr_sd=0x8000\0" \
326 "kernel_size_sd=0x14000\0" \
327 "console=ttyAMA0,38400n8\0" \
328 "mcmemsize=0x70000000\0" \
329 "sd_bootcmd=echo Trying load from SD ..;" \
330 "mmcinfo; mmc read $load_addr " \
331 "$kernel_addr_sd $kernel_size_sd && " \
332 "bootm $load_addr#$board\0" \
333 QSPI_MC_INIT_CMD \
334 BOOTENV \
335 "boot_scripts=ls2088ardb_boot.scr\0" \
336 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
337 "scan_dev_for_boot_part=" \
338 "part list ${devtype} ${devnum} devplist; " \
339 "env exists devplist || setenv devplist 1; " \
340 "for distro_bootpart in ${devplist}; do " \
341 "if fstype ${devtype} " \
342 "${devnum}:${distro_bootpart} " \
343 "bootfstype; then " \
344 "run scan_dev_for_boot; " \
345 "fi; " \
346 "done\0" \
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000347 "boot_a_script=" \
348 "load ${devtype} ${devnum}:${distro_bootpart} " \
349 "${scriptaddr} ${prefix}${script}; " \
350 "env exists secureboot && load ${devtype} " \
351 "${devnum}:${distro_bootpart} " \
352 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
353 "&& esbc_validate ${scripthdraddr};" \
354 "source ${scriptaddr}\0" \
355 "qspi_bootcmd=echo Trying load from qspi..;" \
356 "sf probe && sf read $load_addr " \
357 "$kernel_start $kernel_size ; env exists secureboot &&" \
358 "sf read $kernelheader_addr_r $kernelheader_start " \
359 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
360 " bootm $load_addr#$board\0" \
361 "nor_bootcmd=echo Trying load from nor..;" \
362 "cp.b $kernel_addr $load_addr " \
363 "$kernel_size ; env exists secureboot && " \
364 "cp.b $kernelheader_addr $kernelheader_addr_r " \
365 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
366 "bootm $load_addr#$board\0"
367#else
York Sune12abcb2015-03-20 19:28:24 -0700368#define CONFIG_EXTRA_ENV_SETTINGS \
369 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
York Sune12abcb2015-03-20 19:28:24 -0700370 "ramdisk_addr=0x800000\0" \
371 "ramdisk_size=0x2000000\0" \
372 "fdt_high=0xa0000000\0" \
373 "initrd_high=0xffffffffffffffff\0" \
Vinitha V Pillai9d97f502018-02-27 12:57:31 +0530374 "kernel_addr=0x581000000\0" \
VINITHA PILLAI6c98ff82017-06-12 09:43:45 +0530375 "kernel_start=0x1000000\0" \
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000376 "kernelheader_start=0x600000\0" \
Zhang Ying-22455876c7fe2017-06-05 11:07:18 +0800377 "scriptaddr=0x80000000\0" \
VINITHA PILLAI6c98ff82017-06-12 09:43:45 +0530378 "scripthdraddr=0x80080000\0" \
Zhang Ying-22455876c7fe2017-06-05 11:07:18 +0800379 "fdtheader_addr_r=0x80100000\0" \
380 "kernelheader_addr_r=0x80200000\0" \
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000381 "kernelheader_addr=0x580600000\0" \
Zhang Ying-22455876c7fe2017-06-05 11:07:18 +0800382 "kernel_addr_r=0x81000000\0" \
VINITHA PILLAI6c98ff82017-06-12 09:43:45 +0530383 "kernelheader_size=0x40000\0" \
Zhang Ying-22455876c7fe2017-06-05 11:07:18 +0800384 "fdt_addr_r=0x90000000\0" \
385 "load_addr=0xa0000000\0" \
Prabhakar Kushwahaae193f92016-02-03 17:03:51 +0530386 "kernel_size=0x2800000\0" \
Shengzhou Liu184d7ca2017-11-09 17:57:58 +0800387 "kernel_addr_sd=0x8000\0" \
388 "kernel_size_sd=0x14000\0" \
Zhang Ying-22455876c7fe2017-06-05 11:07:18 +0800389 "console=ttyAMA0,38400n8\0" \
Priyanka Jainabac14e2017-08-29 15:20:37 +0530390 "mcmemsize=0x70000000\0" \
Shengzhou Liu184d7ca2017-11-09 17:57:58 +0800391 "sd_bootcmd=echo Trying load from SD ..;" \
392 "mmcinfo; mmc read $load_addr " \
393 "$kernel_addr_sd $kernel_size_sd && " \
394 "bootm $load_addr#$board\0" \
VINITHA PILLAI6c98ff82017-06-12 09:43:45 +0530395 MC_INIT_CMD \
Zhang Ying-22455876c7fe2017-06-05 11:07:18 +0800396 BOOTENV \
397 "boot_scripts=ls2088ardb_boot.scr\0" \
VINITHA PILLAI6c98ff82017-06-12 09:43:45 +0530398 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
Zhang Ying-22455876c7fe2017-06-05 11:07:18 +0800399 "scan_dev_for_boot_part=" \
400 "part list ${devtype} ${devnum} devplist; " \
401 "env exists devplist || setenv devplist 1; " \
402 "for distro_bootpart in ${devplist}; do " \
403 "if fstype ${devtype} " \
404 "${devnum}:${distro_bootpart} " \
405 "bootfstype; then " \
406 "run scan_dev_for_boot; " \
407 "fi; " \
408 "done\0" \
VINITHA PILLAI6c98ff82017-06-12 09:43:45 +0530409 "boot_a_script=" \
410 "load ${devtype} ${devnum}:${distro_bootpart} " \
411 "${scriptaddr} ${prefix}${script}; " \
412 "env exists secureboot && load ${devtype} " \
413 "${devnum}:${distro_bootpart} " \
Vinitha V Pillai25355ec2019-04-23 05:52:17 +0000414 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
415 "env exists secureboot " \
VINITHA PILLAI6c98ff82017-06-12 09:43:45 +0530416 "&& esbc_validate ${scripthdraddr};" \
417 "source ${scriptaddr}\0" \
Zhang Ying-22455876c7fe2017-06-05 11:07:18 +0800418 "qspi_bootcmd=echo Trying load from qspi..;" \
419 "sf probe && sf read $load_addr " \
VINITHA PILLAI6c98ff82017-06-12 09:43:45 +0530420 "$kernel_start $kernel_size ; env exists secureboot &&" \
421 "sf read $kernelheader_addr_r $kernelheader_start " \
422 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
Zhang Ying-22455876c7fe2017-06-05 11:07:18 +0800423 " bootm $load_addr#$board\0" \
424 "nor_bootcmd=echo Trying load from nor..;" \
425 "cp.b $kernel_addr $load_addr " \
VINITHA PILLAI6c98ff82017-06-12 09:43:45 +0530426 "$kernel_size ; env exists secureboot && " \
427 "cp.b $kernelheader_addr $kernelheader_addr_r " \
428 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
429 "bootm $load_addr#$board\0"
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000430#endif
431
432#ifdef CONFIG_TFABOOT
433#define QSPI_NOR_BOOTCOMMAND \
Kuldeep Singh95018ef2020-02-07 22:15:18 +0530434 "sf probe 0:0; " \
435 "sf read 0x806c0000 0x6c0000 0x40000; " \
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000436 "env exists mcinitcmd && env exists secureboot "\
Kuldeep Singh95018ef2020-02-07 22:15:18 +0530437 "&& esbc_validate 0x806c0000; " \
438 "sf read 0x80d00000 0xd00000 0x100000; " \
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000439 "env exists mcinitcmd && " \
Kuldeep Singh95018ef2020-02-07 22:15:18 +0530440 "fsl_mc lazyapply dpl 0x80d00000; " \
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000441 "run distro_bootcmd;run qspi_bootcmd; " \
442 "env exists secureboot && esbc_halt;"
443
444/* Try to boot an on-SD kernel first, then do normal distro boot */
445#define SD_BOOTCOMMAND \
446 "env exists mcinitcmd && env exists secureboot "\
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000447 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000448 "&& esbc_validate $load_addr; " \
449 "env exists mcinitcmd && run mcinitcmd " \
Wasim Khan01ae4352019-06-10 10:17:29 +0000450 "&& mmc read 0x80d00000 0x6800 0x800 " \
451 "&& fsl_mc lazyapply dpl 0x80d00000; " \
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000452 "run distro_bootcmd;run sd_bootcmd; " \
453 "env exists secureboot && esbc_halt;"
Prabhakar Kushwahaf4392592015-08-02 09:11:44 +0530454
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000455/* Try to boot an on-NOR kernel first, then do normal distro boot */
456#define IFC_NOR_BOOTCOMMAND \
457 "env exists mcinitcmd && env exists secureboot "\
Priyanka Singh7cef8b62020-01-22 10:32:38 +0000458 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000459 "&& fsl_mc lazyapply dpl 0x580d00000;" \
460 "run distro_bootcmd;run nor_bootcmd; " \
461 "env exists secureboot && esbc_halt;"
462#else
York Sune12abcb2015-03-20 19:28:24 -0700463#ifdef CONFIG_QSPI_BOOT
Priyanka Jain7d05b992017-04-28 10:41:35 +0530464/* Try to boot an on-QSPI kernel first, then do normal distro boot */
Shengzhou Liu184d7ca2017-11-09 17:57:58 +0800465#elif defined(CONFIG_SD_BOOT)
466/* Try to boot an on-SD kernel first, then do normal distro boot */
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530467#else
Alexander Graf39e4f242016-11-17 01:03:02 +0100468/* Try to boot an on-NOR kernel first, then do normal distro boot */
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530469#endif
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000470#endif
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530471
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530472/* MAC/PHY configuration */
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530473#define CORTINA_PHY_ADDR1 0x10
474#define CORTINA_PHY_ADDR2 0x11
475#define CORTINA_PHY_ADDR3 0x12
476#define CORTINA_PHY_ADDR4 0x13
477#define AQ_PHY_ADDR1 0x00
478#define AQ_PHY_ADDR2 0x01
479#define AQ_PHY_ADDR3 0x02
480#define AQ_PHY_ADDR4 0x03
Shaohui Xie8c7ce822016-01-28 15:38:15 +0800481#define AQR405_IRQ_MASK 0x36
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530482
Saksham Jainc0c38d22016-03-23 16:24:35 +0530483#include <asm/fsl_secure_boot.h>
484
York Sune12abcb2015-03-20 19:28:24 -0700485#endif /* __LS2_RDB_H */