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Ian Campbelld8e69e02014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Hans de Goedef07872b2015-04-06 20:33:34 +02003# Note only one of these may be selected at a time! But hidden choices are
4# not supported by Kconfig
5config SUNXI_GEN_SUN4I
6 bool
7 ---help---
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
10
11config SUNXI_GEN_SUN6I
12 bool
13 ---help---
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
16 watchdog, etc.
17
18
Ian Campbelld8e69e02014-10-24 21:20:44 +010019choice
20 prompt "Sunxi SoC Variant"
Joe Hershbergerf0699602015-05-12 14:46:23 -050021 optional
Ian Campbelld8e69e02014-10-24 21:20:44 +010022
Ian Campbell4a24a1c2014-10-24 21:20:45 +010023config MACH_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010024 bool "sun4i (Allwinner A10)"
25 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020026 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010027 select SUPPORT_SPL
28
Ian Campbell4a24a1c2014-10-24 21:20:45 +010029config MACH_SUN5I
Ian Campbelld8e69e02014-10-24 21:20:44 +010030 bool "sun5i (Allwinner A13)"
31 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020032 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010033 select SUPPORT_SPL
34
Ian Campbell4a24a1c2014-10-24 21:20:45 +010035config MACH_SUN6I
Ian Campbelld8e69e02014-10-24 21:20:44 +010036 bool "sun6i (Allwinner A31)"
37 select CPU_V7
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080038 select CPU_V7_HAS_NONSEC
39 select CPU_V7_HAS_VIRT
Hans de Goedef07872b2015-04-06 20:33:34 +020040 select SUNXI_GEN_SUN6I
Hans de Goedea5403b92014-10-25 20:18:10 +020041 select SUPPORT_SPL
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080042 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010043
Ian Campbell4a24a1c2014-10-24 21:20:45 +010044config MACH_SUN7I
Ian Campbelld8e69e02014-10-24 21:20:44 +010045 bool "sun7i (Allwinner A20)"
46 select CPU_V7
Hans de Goede85437352014-11-14 09:34:30 +010047 select CPU_V7_HAS_NONSEC
48 select CPU_V7_HAS_VIRT
Hans de Goedef07872b2015-04-06 20:33:34 +020049 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010050 select SUPPORT_SPL
Hans de Goedea5636382014-10-24 20:12:04 +020051 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010052
Hans de Goedef055ed62015-04-06 20:55:39 +020053config MACH_SUN8I_A23
Ian Campbelld8e69e02014-10-24 21:20:44 +010054 bool "sun8i (Allwinner A23)"
55 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080056 select CPU_V7_HAS_NONSEC
57 select CPU_V7_HAS_VIRT
Hans de Goedef07872b2015-04-06 20:33:34 +020058 select SUNXI_GEN_SUN6I
Hans de Goede966d2392014-12-07 14:34:27 +010059 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080060 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010061
Vishnu Patekar3702f142015-03-01 23:47:48 +053062config MACH_SUN8I_A33
63 bool "sun8i (Allwinner A33)"
64 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080065 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
Vishnu Patekar3702f142015-03-01 23:47:48 +053067 select SUNXI_GEN_SUN6I
68 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080069 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar3702f142015-03-01 23:47:48 +053070
Hans de Goede7bfe2bb2015-01-13 19:25:06 +010071config MACH_SUN9I
72 bool "sun9i (Allwinner A80)"
73 select CPU_V7
74 select SUNXI_GEN_SUN6I
75
Ian Campbelld8e69e02014-10-24 21:20:44 +010076endchoice
Maxime Ripard2c519412014-10-03 20:16:29 +080077
Hans de Goedef055ed62015-04-06 20:55:39 +020078# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
79config MACH_SUN8I
80 bool
81 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33
82
83
Hans de Goede3aeaa282014-11-15 19:46:39 +010084config DRAM_CLK
Hans de Goede59d9fc72015-01-17 14:24:55 +010085 int "sunxi dram clock speed"
86 default 312 if MACH_SUN6I || MACH_SUN8I
87 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +010088 ---help---
89 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goede06ddc452015-01-25 11:29:27 +010090 of 24.
Hans de Goede3aeaa282014-11-15 19:46:39 +010091
Siarhei Siamashka47359bb2015-02-01 00:27:06 +020092if MACH_SUN5I || MACH_SUN7I
93config DRAM_MBUS_CLK
94 int "sunxi mbus clock speed"
95 default 300
96 ---help---
97 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
98
99endif
100
Hans de Goede3aeaa282014-11-15 19:46:39 +0100101config DRAM_ZQ
Hans de Goede59d9fc72015-01-17 14:24:55 +0100102 int "sunxi dram zq value"
103 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
104 default 127 if MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100105 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100106 Set the dram zq value.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100107
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200108config DRAM_ODT_EN
109 bool "sunxi dram odt enable"
110 default n if !MACH_SUN8I_A23
111 default y if MACH_SUN8I_A23
112 ---help---
113 Select this to enable dram odt (on die termination).
114
Hans de Goede59d9fc72015-01-17 14:24:55 +0100115if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
116config DRAM_EMR1
117 int "sunxi dram emr1 value"
118 default 0 if MACH_SUN4I
119 default 4 if MACH_SUN5I || MACH_SUN7I
120 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100121 Set the dram controller emr1 value.
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200122
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200123config DRAM_TPR3
124 hex "sunxi dram tpr3 value"
125 default 0
126 ---help---
127 Set the dram controller tpr3 parameter. This parameter configures
128 the delay on the command lane and also phase shifts, which are
129 applied for sampling incoming read data. The default value 0
130 means that no phase/delay adjustments are necessary. Properly
131 configuring this parameter increases reliability at high DRAM
132 clock speeds.
133
134config DRAM_DQS_GATING_DELAY
135 hex "sunxi dram dqs_gating_delay value"
136 default 0
137 ---help---
138 Set the dram controller dqs_gating_delay parmeter. Each byte
139 encodes the DQS gating delay for each byte lane. The delay
140 granularity is 1/4 cycle. For example, the value 0x05060606
141 means that the delay is 5 quarter-cycles for one lane (1.25
142 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
143 The default value 0 means autodetection. The results of hardware
144 autodetection are not very reliable and depend on the chip
145 temperature (sometimes producing different results on cold start
146 and warm reboot). But the accuracy of hardware autodetection
147 is usually good enough, unless running at really high DRAM
148 clocks speeds (up to 600MHz). If unsure, keep as 0.
149
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200150choice
151 prompt "sunxi dram timings"
152 default DRAM_TIMINGS_VENDOR_MAGIC
153 ---help---
154 Select the timings of the DDR3 chips.
155
156config DRAM_TIMINGS_VENDOR_MAGIC
157 bool "Magic vendor timings from Android"
158 ---help---
159 The same DRAM timings as in the Allwinner boot0 bootloader.
160
161config DRAM_TIMINGS_DDR3_1066F_1333H
162 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
163 ---help---
164 Use the timings of the standard JEDEC DDR3-1066F speed bin for
165 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
166 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
167 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
168 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
169 that down binning to DDR3-1066F is supported (because DDR3-1066F
170 uses a bit faster timings than DDR3-1333H).
171
172config DRAM_TIMINGS_DDR3_800E_1066G_1333J
173 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
174 ---help---
175 Use the timings of the slowest possible JEDEC speed bin for the
176 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
177 DDR3-800E, DDR3-1066G or DDR3-1333J.
178
179endchoice
180
Hans de Goede3aeaa282014-11-15 19:46:39 +0100181endif
182
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200183if MACH_SUN8I_A23
184config DRAM_ODT_CORRECTION
185 int "sunxi dram odt correction value"
186 default 0
187 ---help---
188 Set the dram odt correction value (range -255 - 255). In allwinner
189 fex files, this option is found in bits 8-15 of the u32 odt_en variable
190 in the [dram] section. When bit 31 of the odt_en variable is set
191 then the correction is negative. Usually the value for this is 0.
192endif
193
Iain Paton630df142015-03-28 10:26:38 +0000194config SYS_CLK_FREQ
195 default 912000000 if MACH_SUN7I
196 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
197
Maxime Ripard2c519412014-10-03 20:16:29 +0800198config SYS_CONFIG_NAME
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100199 default "sun4i" if MACH_SUN4I
200 default "sun5i" if MACH_SUN5I
201 default "sun6i" if MACH_SUN6I
202 default "sun7i" if MACH_SUN7I
203 default "sun8i" if MACH_SUN8I
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100204 default "sun9i" if MACH_SUN9I
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900205
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900206config SYS_BOARD
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900207 default "sunxi"
208
209config SYS_SOC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900210 default "sunxi"
211
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200212config UART0_PORT_F
213 bool "UART0 on MicroSD breakout board"
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200214 default n
215 ---help---
216 Repurpose the SD card slot for getting access to the UART0 serial
217 console. Primarily useful only for low level u-boot debugging on
218 tablets, where normal UART0 is difficult to access and requires
219 device disassembly and/or soldering. As the SD card can't be used
220 at the same time, the system can be only booted in the FEL mode.
221 Only enable this if you really know what you are doing.
222
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200223config OLD_SUNXI_KERNEL_COMPAT
224 boolean "Enable workarounds for booting old kernels"
225 default n
226 ---help---
227 Set this to enable various workarounds for old kernels, this results in
228 sub-optimal settings for newer kernels, only enable if needed.
229
Hans de Goede7412ef82014-10-02 20:29:26 +0200230config MMC0_CD_PIN
231 string "Card detect pin for mmc0"
232 default ""
233 ---help---
234 Set the card detect pin for mmc0, leave empty to not use cd. This
235 takes a string in the format understood by sunxi_name_to_gpio, e.g.
236 PH1 for pin 1 of port H.
237
238config MMC1_CD_PIN
239 string "Card detect pin for mmc1"
240 default ""
241 ---help---
242 See MMC0_CD_PIN help text.
243
244config MMC2_CD_PIN
245 string "Card detect pin for mmc2"
246 default ""
247 ---help---
248 See MMC0_CD_PIN help text.
249
250config MMC3_CD_PIN
251 string "Card detect pin for mmc3"
252 default ""
253 ---help---
254 See MMC0_CD_PIN help text.
255
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100256config MMC1_PINS
257 string "Pins for mmc1"
258 default ""
259 ---help---
260 Set the pins used for mmc1, when applicable. This takes a string in the
261 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
262
263config MMC2_PINS
264 string "Pins for mmc2"
265 default ""
266 ---help---
267 See MMC1_PINS help text.
268
269config MMC3_PINS
270 string "Pins for mmc3"
271 default ""
272 ---help---
273 See MMC1_PINS help text.
274
Hans de Goedeaf593e42014-10-02 20:43:50 +0200275config MMC_SUNXI_SLOT_EXTRA
276 int "mmc extra slot number"
277 default -1
278 ---help---
279 sunxi builds always enable mmc0, some boards also have a second sdcard
280 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
281 support for this.
282
Hans de Goedee7b852a2015-01-07 15:26:06 +0100283config USB0_VBUS_PIN
284 string "Vbus enable pin for usb0 (otg)"
285 default ""
286 ---help---
287 Set the Vbus enable pin for usb0 (otg). This takes a string in the
288 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
289
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100290config USB0_VBUS_DET
291 string "Vbus detect pin for usb0 (otg)"
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100292 default ""
293 ---help---
294 Set the Vbus detect pin for usb0 (otg). This takes a string in the
295 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
296
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100297config USB1_VBUS_PIN
298 string "Vbus enable pin for usb1 (ehci0)"
299 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100300 default "PH27" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100301 ---help---
302 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
303 a string in the format understood by sunxi_name_to_gpio, e.g.
304 PH1 for pin 1 of port H.
305
306config USB2_VBUS_PIN
307 string "Vbus enable pin for usb2 (ehci1)"
308 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100309 default "PH24" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100310 ---help---
311 See USB1_VBUS_PIN help text.
312
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200313config I2C0_ENABLE
314 bool "Enable I2C/TWI controller 0"
315 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
316 default n if MACH_SUN6I || MACH_SUN8I
317 ---help---
318 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
319 its clock and setting up the bus. This is especially useful on devices
320 with slaves connected to the bus or with pins exposed through e.g. an
321 expansion port/header.
322
323config I2C1_ENABLE
324 bool "Enable I2C/TWI controller 1"
325 default n
326 ---help---
327 See I2C0_ENABLE help text.
328
329config I2C2_ENABLE
330 bool "Enable I2C/TWI controller 2"
331 default n
332 ---help---
333 See I2C0_ENABLE help text.
334
335if MACH_SUN6I || MACH_SUN7I
336config I2C3_ENABLE
337 bool "Enable I2C/TWI controller 3"
338 default n
339 ---help---
340 See I2C0_ENABLE help text.
341endif
342
343if MACH_SUN7I
344config I2C4_ENABLE
345 bool "Enable I2C/TWI controller 4"
346 default n
347 ---help---
348 See I2C0_ENABLE help text.
349endif
350
Hans de Goede3ae1d132015-04-25 17:25:14 +0200351config AXP_GPIO
352 boolean "Enable support for gpio-s on axp PMICs"
353 default n
354 ---help---
355 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
356
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200357config VIDEO
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100358 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200359 default y
360 ---help---
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100361 Say Y here to add support for using a cfb console on the HDMI, LCD
362 or VGA output found on most sunxi devices. See doc/README.video for
363 info on how to select the video output and mode.
364
Hans de Goedee9544592014-12-23 23:04:35 +0100365config VIDEO_HDMI
366 boolean "HDMI output support"
367 depends on VIDEO && !MACH_SUN8I
368 default y
369 ---help---
370 Say Y here to add support for outputting video over HDMI.
371
Hans de Goede260f5202014-12-25 13:58:06 +0100372config VIDEO_VGA
373 boolean "VGA output support"
374 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
375 default n
376 ---help---
377 Say Y here to add support for outputting video over VGA.
378
Hans de Goedeac1633c2014-12-24 12:17:07 +0100379config VIDEO_VGA_VIA_LCD
380 boolean "VGA via LCD controller support"
Chen-Yu Tsai39ca4c12015-01-12 18:02:10 +0800381 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedeac1633c2014-12-24 12:17:07 +0100382 default n
383 ---help---
384 Say Y here to add support for external DACs connected to the parallel
385 LCD interface driving a VGA connector, such as found on the
386 Olimex A13 boards.
387
Hans de Goede18366f72015-01-25 15:33:07 +0100388config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
389 boolean "Force sync active high for VGA via LCD controller support"
390 depends on VIDEO_VGA_VIA_LCD
391 default n
392 ---help---
393 Say Y here if you've a board which uses opendrain drivers for the vga
394 hsync and vsync signals. Opendrain drivers cannot generate steep enough
395 positive edges for a stable video output, so on boards with opendrain
396 drivers the sync signals must always be active high.
397
Chen-Yu Tsai9ed19522015-01-12 18:02:11 +0800398config VIDEO_VGA_EXTERNAL_DAC_EN
399 string "LCD panel power enable pin"
400 depends on VIDEO_VGA_VIA_LCD
401 default ""
402 ---help---
403 Set the enable pin for the external VGA DAC. This takes a string in the
404 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
405
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100406config VIDEO_LCD_MODE
407 string "LCD panel timing details"
408 depends on VIDEO
409 default ""
410 ---help---
411 LCD panel timing details string, leave empty if there is no LCD panel.
412 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
413 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
414
Hans de Goede481b6642015-01-13 13:21:46 +0100415config VIDEO_LCD_DCLK_PHASE
416 int "LCD panel display clock phase"
417 depends on VIDEO
418 default 1
419 ---help---
420 Select LCD panel display clock phase shift, range 0-3.
421
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100422config VIDEO_LCD_POWER
423 string "LCD panel power enable pin"
424 depends on VIDEO
425 default ""
426 ---help---
427 Set the power enable pin for the LCD panel. This takes a string in the
428 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
429
Hans de Goedece9e3322015-02-16 17:26:41 +0100430config VIDEO_LCD_RESET
431 string "LCD panel reset pin"
432 depends on VIDEO
433 default ""
434 ---help---
435 Set the reset pin for the LCD panel. This takes a string in the format
436 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
437
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100438config VIDEO_LCD_BL_EN
439 string "LCD panel backlight enable pin"
440 depends on VIDEO
441 default ""
442 ---help---
443 Set the backlight enable pin for the LCD panel. This takes a string in the
444 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
445 port H.
446
447config VIDEO_LCD_BL_PWM
448 string "LCD panel backlight pwm pin"
449 depends on VIDEO
450 default ""
451 ---help---
452 Set the backlight pwm pin for the LCD panel. This takes a string in the
453 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200454
Hans de Goede2d5d3022015-01-22 21:02:42 +0100455config VIDEO_LCD_BL_PWM_ACTIVE_LOW
456 bool "LCD panel backlight pwm is inverted"
457 depends on VIDEO
458 default y
459 ---help---
460 Set this if the backlight pwm output is active low.
461
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100462config VIDEO_LCD_PANEL_I2C
463 bool "LCD panel needs to be configured via i2c"
464 depends on VIDEO
Hans de Goede6de9f762015-03-07 12:00:02 +0100465 default n
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100466 ---help---
467 Say y here if the LCD panel needs to be configured via i2c. This
468 will add a bitbang i2c controller using gpios to talk to the LCD.
469
470config VIDEO_LCD_PANEL_I2C_SDA
471 string "LCD panel i2c interface SDA pin"
472 depends on VIDEO_LCD_PANEL_I2C
473 default "PG12"
474 ---help---
475 Set the SDA pin for the LCD i2c interface. This takes a string in the
476 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
477
478config VIDEO_LCD_PANEL_I2C_SCL
479 string "LCD panel i2c interface SCL pin"
480 depends on VIDEO_LCD_PANEL_I2C
481 default "PG10"
482 ---help---
483 Set the SCL pin for the LCD i2c interface. This takes a string in the
484 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
485
Hans de Goede797a0f52015-01-01 22:04:34 +0100486
487# Note only one of these may be selected at a time! But hidden choices are
488# not supported by Kconfig
489config VIDEO_LCD_IF_PARALLEL
490 bool
491
492config VIDEO_LCD_IF_LVDS
493 bool
494
495
496choice
497 prompt "LCD panel support"
498 depends on VIDEO
499 ---help---
500 Select which type of LCD panel to support.
501
502config VIDEO_LCD_PANEL_PARALLEL
503 bool "Generic parallel interface LCD panel"
504 select VIDEO_LCD_IF_PARALLEL
505
506config VIDEO_LCD_PANEL_LVDS
507 bool "Generic lvds interface LCD panel"
508 select VIDEO_LCD_IF_LVDS
509
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200510config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
511 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
512 select VIDEO_LCD_SSD2828
513 select VIDEO_LCD_IF_PARALLEL
514 ---help---
515 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
516
Hans de Goede743fb9552015-01-20 09:23:36 +0100517config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
518 bool "Hitachi tx18d42vm LCD panel"
519 select VIDEO_LCD_HITACHI_TX18D42VM
520 select VIDEO_LCD_IF_LVDS
521 ---help---
522 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
523
Hans de Goede613dade2015-02-16 17:49:47 +0100524config VIDEO_LCD_TL059WV5C0
525 bool "tl059wv5c0 LCD panel"
526 select VIDEO_LCD_PANEL_I2C
527 select VIDEO_LCD_IF_PARALLEL
528 ---help---
529 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
530 Aigo M60/M608/M606 tablets.
531
Hans de Goede797a0f52015-01-01 22:04:34 +0100532endchoice
533
534
Hans de Goedef494cad2015-01-11 17:17:00 +0100535config USB_MUSB_SUNXI
536 bool "Enable sunxi OTG / DRC USB controller in host mode"
537 default n
538 ---help---
539 Say y here to enable support for the sunxi OTG / DRC USB controller
540 used on almost all sunxi boards. Note currently u-boot can only have
541 one usb host controller enabled at a time, so enabling this on boards
542 which also use the ehci host controller will result in build errors.
543
Hans de Goede16030822014-09-18 21:03:34 +0200544config USB_KEYBOARD
545 boolean "Enable USB keyboard support"
546 default y
547 ---help---
548 Say Y here to add support for using a USB keyboard (typically used
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100549 in combination with a graphical console).
Hans de Goede16030822014-09-18 21:03:34 +0200550
Hans de Goedebf880fe2015-01-25 12:10:48 +0100551config GMAC_TX_DELAY
552 int "GMAC Transmit Clock Delay Chain"
553 default 0
554 ---help---
555 Set the GMAC Transmit Clock Delay Chain value.
556
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900557endif