Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Scott Wood | f64c98c | 2015-03-20 19:28:12 -0700 | [diff] [blame] | 2 | /* |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 3 | * Copyright 2014-2015 Freescale Semiconductor |
Ran Wang | 13a84a5 | 2021-06-16 17:53:19 +0530 | [diff] [blame] | 4 | * Copyright 2019-2021 NXP |
Scott Wood | f64c98c | 2015-03-20 19:28:12 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | 85d6531 | 2019-12-28 10:44:58 -0700 | [diff] [blame] | 8 | #include <clock_legacy.h> |
Hou Zhiqiang | 031bb87 | 2020-04-28 10:19:32 +0800 | [diff] [blame] | 9 | #include <cpu_func.h> |
Simon Glass | 5e6201b | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 10 | #include <env.h> |
Ashish Kumar | 1123406 | 2017-08-11 11:09:14 +0530 | [diff] [blame] | 11 | #include <fsl_immap.h> |
Scott Wood | f64c98c | 2015-03-20 19:28:12 -0700 | [diff] [blame] | 12 | #include <fsl_ifc.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 13 | #include <init.h> |
Hou Zhiqiang | 031bb87 | 2020-04-28 10:19:32 +0800 | [diff] [blame] | 14 | #include <linux/sizes.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 15 | #include <log.h> |
Hou Zhiqiang | 4b23ca8 | 2016-08-02 19:03:27 +0800 | [diff] [blame] | 16 | #include <asm/arch/fsl_serdes.h> |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 17 | #include <asm/arch/soc.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 18 | #include <asm/cache.h> |
Scott Wood | ae1df32 | 2015-03-20 19:28:13 -0700 | [diff] [blame] | 19 | #include <asm/io.h> |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 20 | #include <asm/global_data.h> |
Prabhakar Kushwaha | 22cfe96 | 2015-11-05 12:00:14 +0530 | [diff] [blame] | 21 | #include <asm/arch-fsl-layerscape/config.h> |
Ran Wang | 4e7cdcf | 2018-08-10 15:00:00 +0800 | [diff] [blame] | 22 | #include <asm/arch-fsl-layerscape/ns_access.h> |
Laurentiu Tudor | 512d13e | 2018-08-09 15:19:46 +0300 | [diff] [blame] | 23 | #include <asm/arch-fsl-layerscape/fsl_icid.h> |
Hou Zhiqiang | 031bb87 | 2020-04-28 10:19:32 +0800 | [diff] [blame] | 24 | #include <asm/gic-v3.h> |
Hou Zhiqiang | 4b23ca8 | 2016-08-02 19:03:27 +0800 | [diff] [blame] | 25 | #ifdef CONFIG_LAYERSCAPE_NS_ACCESS |
Hou Zhiqiang | 5ac9a5c | 2016-08-02 19:03:23 +0800 | [diff] [blame] | 26 | #include <fsl_csu.h> |
Hou Zhiqiang | 4b23ca8 | 2016-08-02 19:03:27 +0800 | [diff] [blame] | 27 | #endif |
Prabhakar Kushwaha | d169ebe | 2016-06-03 18:41:31 +0530 | [diff] [blame] | 28 | #ifdef CONFIG_SYS_FSL_DDR |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 29 | #include <fsl_ddr_sdram.h> |
| 30 | #include <fsl_ddr.h> |
Prabhakar Kushwaha | d169ebe | 2016-06-03 18:41:31 +0530 | [diff] [blame] | 31 | #endif |
Aneesh Bansal | 39d5b3b | 2016-01-22 16:37:26 +0530 | [diff] [blame] | 32 | #ifdef CONFIG_CHAIN_OF_TRUST |
| 33 | #include <fsl_validate.h> |
| 34 | #endif |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 35 | #include <fsl_immap.h> |
Ran Wang | ba7cd0f | 2020-08-05 15:07:27 +0800 | [diff] [blame] | 36 | #include <dm.h> |
Tom Rini | fb6abdd | 2020-10-15 21:44:15 -0400 | [diff] [blame] | 37 | #include <dm/device_compat.h> |
Ran Wang | ba7cd0f | 2020-08-05 15:07:27 +0800 | [diff] [blame] | 38 | #include <linux/err.h> |
Alban Bedel | 0b8932f | 2020-11-17 16:20:04 +0100 | [diff] [blame] | 39 | #ifdef CONFIG_GIC_V3_ITS |
Pankit Garg | bdbf84f | 2018-11-05 18:01:52 +0000 | [diff] [blame] | 40 | DECLARE_GLOBAL_DATA_PTR; |
| 41 | #endif |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 42 | |
Hou Zhiqiang | 031bb87 | 2020-04-28 10:19:32 +0800 | [diff] [blame] | 43 | #ifdef CONFIG_GIC_V3_ITS |
Hou Zhiqiang | 031bb87 | 2020-04-28 10:19:32 +0800 | [diff] [blame] | 44 | int ls_gic_rd_tables_init(void *blob) |
| 45 | { |
Hou Zhiqiang | 14fa6b7 | 2020-08-06 14:38:19 +0800 | [diff] [blame] | 46 | struct fdt_memory lpi_base; |
| 47 | fdt_addr_t addr; |
| 48 | fdt_size_t size; |
| 49 | int offset, ret; |
| 50 | |
| 51 | offset = fdt_path_offset(gd->fdt_blob, "/syscon@0x80000000"); |
| 52 | addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, offset, "reg", |
| 53 | 0, &size, false); |
| 54 | |
| 55 | lpi_base.start = addr; |
| 56 | lpi_base.end = addr + size - 1; |
Thierry Reding | 5e33691 | 2021-09-03 15:16:19 +0200 | [diff] [blame] | 57 | ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, |
Tom Rini | 2106a84 | 2021-10-15 15:58:16 -0400 | [diff] [blame] | 58 | 0, NULL, 0); |
Hou Zhiqiang | 14fa6b7 | 2020-08-06 14:38:19 +0800 | [diff] [blame] | 59 | if (ret) { |
| 60 | debug("%s: failed to add reserved memory\n", __func__); |
| 61 | return ret; |
| 62 | } |
Hou Zhiqiang | 031bb87 | 2020-04-28 10:19:32 +0800 | [diff] [blame] | 63 | |
Rayagonda Kokatanur | 158c16e | 2020-07-26 22:37:33 +0530 | [diff] [blame] | 64 | ret = gic_lpi_tables_init(); |
Hou Zhiqiang | 031bb87 | 2020-04-28 10:19:32 +0800 | [diff] [blame] | 65 | if (ret) |
| 66 | debug("%s: failed to init gic-lpi-tables\n", __func__); |
| 67 | |
| 68 | return ret; |
| 69 | } |
| 70 | #endif |
| 71 | |
York Sun | cbe8e1c | 2016-04-04 11:41:26 -0700 | [diff] [blame] | 72 | bool soc_has_dp_ddr(void) |
| 73 | { |
| 74 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 75 | u32 svr = gur_in32(&gur->svr); |
| 76 | |
Priyanka Jain | 4a6f173 | 2016-11-17 12:29:55 +0530 | [diff] [blame] | 77 | /* LS2085A, LS2088A, LS2048A has DP_DDR */ |
| 78 | if ((SVR_SOC_VER(svr) == SVR_LS2085A) || |
| 79 | (SVR_SOC_VER(svr) == SVR_LS2088A) || |
| 80 | (SVR_SOC_VER(svr) == SVR_LS2048A)) |
York Sun | cbe8e1c | 2016-04-04 11:41:26 -0700 | [diff] [blame] | 81 | return true; |
| 82 | |
| 83 | return false; |
| 84 | } |
| 85 | |
| 86 | bool soc_has_aiop(void) |
| 87 | { |
| 88 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 89 | u32 svr = gur_in32(&gur->svr); |
| 90 | |
| 91 | /* LS2085A has AIOP */ |
Prabhakar Kushwaha | ac7f242 | 2016-06-24 13:48:13 +0530 | [diff] [blame] | 92 | if (SVR_SOC_VER(svr) == SVR_LS2085A) |
York Sun | cbe8e1c | 2016-04-04 11:41:26 -0700 | [diff] [blame] | 93 | return true; |
| 94 | |
| 95 | return false; |
| 96 | } |
| 97 | |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 98 | static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset) |
| 99 | { |
| 100 | scfg_clrsetbits32(scfg + offset / 4, |
| 101 | 0xF << 6, |
| 102 | SCFG_USB_TXVREFTUNE << 6); |
| 103 | } |
| 104 | |
| 105 | static void erratum_a009008(void) |
| 106 | { |
| 107 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009008 |
| 108 | u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 109 | |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 110 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ |
| 111 | defined(CONFIG_ARCH_LS1012A) |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 112 | set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1); |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 113 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 114 | set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2); |
| 115 | set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3); |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 116 | #endif |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 117 | #elif defined(CONFIG_ARCH_LS2080A) |
| 118 | set_usb_txvreftune(scfg, SCFG_USB3PRM1CR); |
| 119 | #endif |
| 120 | #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ |
| 121 | } |
| 122 | |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 123 | static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset) |
| 124 | { |
| 125 | scfg_clrbits32(scfg + offset / 4, |
| 126 | SCFG_USB_SQRXTUNE_MASK << 23); |
| 127 | } |
| 128 | |
| 129 | static void erratum_a009798(void) |
| 130 | { |
| 131 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009798 |
| 132 | u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; |
| 133 | |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 134 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ |
| 135 | defined(CONFIG_ARCH_LS1012A) |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 136 | set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1); |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 137 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 138 | set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2); |
| 139 | set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3); |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 140 | #endif |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 141 | #elif defined(CONFIG_ARCH_LS2080A) |
| 142 | set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR); |
| 143 | #endif |
| 144 | #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ |
| 145 | } |
| 146 | |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 147 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ |
| 148 | defined(CONFIG_ARCH_LS1012A) |
Ran Wang | e64f747 | 2017-09-04 18:46:50 +0800 | [diff] [blame] | 149 | static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset) |
| 150 | { |
| 151 | scfg_clrsetbits32(scfg + offset / 4, |
| 152 | 0x7F << 9, |
| 153 | SCFG_USB_PCSTXSWINGFULL << 9); |
| 154 | } |
| 155 | #endif |
| 156 | |
| 157 | static void erratum_a008997(void) |
| 158 | { |
| 159 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008997 |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 160 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ |
| 161 | defined(CONFIG_ARCH_LS1012A) |
Ran Wang | e64f747 | 2017-09-04 18:46:50 +0800 | [diff] [blame] | 162 | u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; |
| 163 | |
| 164 | set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1); |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 165 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) |
Ran Wang | e64f747 | 2017-09-04 18:46:50 +0800 | [diff] [blame] | 166 | set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2); |
| 167 | set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3); |
| 168 | #endif |
Ran Wang | e118acb | 2019-05-14 17:34:56 +0800 | [diff] [blame] | 169 | #elif defined(CONFIG_ARCH_LS1028A) |
| 170 | clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1, |
| 171 | 0x7F << 11, |
| 172 | DCSR_USB_PCSTXSWINGFULL << 11); |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 173 | #endif |
Ran Wang | e64f747 | 2017-09-04 18:46:50 +0800 | [diff] [blame] | 174 | #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ |
| 175 | } |
| 176 | |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 177 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ |
| 178 | defined(CONFIG_ARCH_LS1012A) |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 179 | |
| 180 | #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ |
| 181 | out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ |
| 182 | out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \ |
| 183 | out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ |
| 184 | out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) |
| 185 | |
Yinbo Zhu | 5c3767e | 2019-05-14 17:34:57 +0800 | [diff] [blame] | 186 | #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ |
Meenakshi Aggarwal | ccb5d5d | 2020-10-29 19:16:16 +0530 | [diff] [blame] | 187 | defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) || \ |
| 188 | defined(CONFIG_ARCH_LX2162A) |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 189 | |
| 190 | #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ |
| 191 | out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ |
| 192 | out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \ |
| 193 | out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ |
| 194 | out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) |
| 195 | |
| 196 | #endif |
| 197 | |
| 198 | static void erratum_a009007(void) |
| 199 | { |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 200 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ |
| 201 | defined(CONFIG_ARCH_LS1012A) |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 202 | void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1; |
| 203 | |
| 204 | PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 205 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 206 | usb_phy = (void __iomem *)SCFG_USB_PHY2; |
| 207 | PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); |
| 208 | |
| 209 | usb_phy = (void __iomem *)SCFG_USB_PHY3; |
| 210 | PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 211 | #endif |
Yinbo Zhu | 5c3767e | 2019-05-14 17:34:57 +0800 | [diff] [blame] | 212 | #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ |
| 213 | defined(CONFIG_ARCH_LS1028A) |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 214 | void __iomem *dcsr = (void __iomem *)DCSR_BASE; |
| 215 | |
| 216 | PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1); |
| 217 | PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2); |
| 218 | #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ |
| 219 | } |
| 220 | |
Shengzhou Liu | a3117ee | 2016-11-11 18:11:05 +0800 | [diff] [blame] | 221 | #if defined(CONFIG_FSL_LSCH3) |
Ran Wang | 13a84a5 | 2021-06-16 17:53:19 +0530 | [diff] [blame] | 222 | static void erratum_a050204(void) |
Ran Wang | d0270dc | 2019-11-26 11:40:40 +0800 | [diff] [blame] | 223 | { |
Meenakshi Aggarwal | ccb5d5d | 2020-10-29 19:16:16 +0530 | [diff] [blame] | 224 | #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) |
Ran Wang | d0270dc | 2019-11-26 11:40:40 +0800 | [diff] [blame] | 225 | void __iomem *dcsr = (void __iomem *)DCSR_BASE; |
| 226 | |
| 227 | PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1); |
| 228 | PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2); |
| 229 | #endif |
| 230 | } |
Yao Yuan | fae8805 | 2015-12-05 14:59:14 +0800 | [diff] [blame] | 231 | /* |
| 232 | * This erratum requires setting a value to eddrtqcr1 to |
| 233 | * optimal the DDR performance. |
| 234 | */ |
| 235 | static void erratum_a008336(void) |
| 236 | { |
Shengzhou Liu | a3117ee | 2016-11-11 18:11:05 +0800 | [diff] [blame] | 237 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 |
Yao Yuan | fae8805 | 2015-12-05 14:59:14 +0800 | [diff] [blame] | 238 | u32 *eddrtqcr1; |
| 239 | |
Yao Yuan | fae8805 | 2015-12-05 14:59:14 +0800 | [diff] [blame] | 240 | #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR |
| 241 | eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; |
Shengzhou Liu | 7beb0c4 | 2016-08-26 18:30:38 +0800 | [diff] [blame] | 242 | if (fsl_ddr_get_version(0) == 0x50200) |
| 243 | out_le32(eddrtqcr1, 0x63b30002); |
Yao Yuan | fae8805 | 2015-12-05 14:59:14 +0800 | [diff] [blame] | 244 | #endif |
| 245 | #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR |
| 246 | eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; |
Shengzhou Liu | 7beb0c4 | 2016-08-26 18:30:38 +0800 | [diff] [blame] | 247 | if (fsl_ddr_get_version(0) == 0x50200) |
| 248 | out_le32(eddrtqcr1, 0x63b30002); |
Yao Yuan | fae8805 | 2015-12-05 14:59:14 +0800 | [diff] [blame] | 249 | #endif |
| 250 | #endif |
| 251 | } |
| 252 | |
| 253 | /* |
| 254 | * This erratum requires a register write before being Memory |
| 255 | * controller 3 being enabled. |
| 256 | */ |
| 257 | static void erratum_a008514(void) |
| 258 | { |
Shengzhou Liu | a3117ee | 2016-11-11 18:11:05 +0800 | [diff] [blame] | 259 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 |
Yao Yuan | fae8805 | 2015-12-05 14:59:14 +0800 | [diff] [blame] | 260 | u32 *eddrtqcr1; |
| 261 | |
Yao Yuan | fae8805 | 2015-12-05 14:59:14 +0800 | [diff] [blame] | 262 | #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR |
| 263 | eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; |
| 264 | out_le32(eddrtqcr1, 0x63b20002); |
| 265 | #endif |
| 266 | #endif |
| 267 | } |
Prabhakar Kushwaha | 22cfe96 | 2015-11-05 12:00:14 +0530 | [diff] [blame] | 268 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 |
| 269 | #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" |
| 270 | |
| 271 | static unsigned long get_internval_val_mhz(void) |
| 272 | { |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 273 | char *interval = env_get(PLATFORM_CYCLE_ENV_VAR); |
Prabhakar Kushwaha | 22cfe96 | 2015-11-05 12:00:14 +0530 | [diff] [blame] | 274 | /* |
| 275 | * interval is the number of platform cycles(MHz) between |
| 276 | * wake up events generated by EPU. |
| 277 | */ |
| 278 | ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); |
| 279 | |
| 280 | if (interval) |
Simon Glass | ff9b903 | 2021-07-24 09:03:30 -0600 | [diff] [blame] | 281 | interval_mhz = dectoul(interval, NULL); |
Prabhakar Kushwaha | 22cfe96 | 2015-11-05 12:00:14 +0530 | [diff] [blame] | 282 | |
| 283 | return interval_mhz; |
| 284 | } |
| 285 | |
| 286 | void erratum_a009635(void) |
| 287 | { |
| 288 | u32 val; |
| 289 | unsigned long interval_mhz = get_internval_val_mhz(); |
| 290 | |
| 291 | if (!interval_mhz) |
| 292 | return; |
| 293 | |
| 294 | val = in_le32(DCSR_CGACRE5); |
| 295 | writel(val | 0x00000200, DCSR_CGACRE5); |
| 296 | |
| 297 | val = in_le32(EPU_EPCMPR5); |
| 298 | writel(interval_mhz, EPU_EPCMPR5); |
| 299 | val = in_le32(EPU_EPCCR5); |
| 300 | writel(val | 0x82820000, EPU_EPCCR5); |
| 301 | val = in_le32(EPU_EPSMCR5); |
| 302 | writel(val | 0x002f0000, EPU_EPSMCR5); |
| 303 | val = in_le32(EPU_EPECR5); |
| 304 | writel(val | 0x20000000, EPU_EPECR5); |
| 305 | val = in_le32(EPU_EPGCR); |
| 306 | writel(val | 0x80000000, EPU_EPGCR); |
| 307 | } |
| 308 | #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ |
| 309 | |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 310 | static void erratum_rcw_src(void) |
| 311 | { |
Santan Kumar | 9913648 | 2017-05-05 15:42:28 +0530 | [diff] [blame] | 312 | #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT) |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 313 | u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; |
| 314 | u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; |
| 315 | u32 val; |
| 316 | |
| 317 | val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); |
| 318 | val &= ~DCFG_PORSR1_RCW_SRC; |
| 319 | val |= DCFG_PORSR1_RCW_SRC_NOR; |
| 320 | out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); |
| 321 | #endif |
| 322 | } |
| 323 | |
York Sun | 0404a39 | 2015-03-23 10:41:35 -0700 | [diff] [blame] | 324 | #define I2C_DEBUG_REG 0x6 |
| 325 | #define I2C_GLITCH_EN 0x8 |
| 326 | /* |
| 327 | * This erratum requires setting glitch_en bit to enable |
| 328 | * digital glitch filter to improve clock stability. |
| 329 | */ |
Ashish kumar | 3b52a23 | 2017-02-23 16:03:57 +0530 | [diff] [blame] | 330 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 |
York Sun | 0404a39 | 2015-03-23 10:41:35 -0700 | [diff] [blame] | 331 | static void erratum_a009203(void) |
| 332 | { |
Tom Rini | 52b2e26 | 2021-08-18 23:12:24 -0400 | [diff] [blame] | 333 | #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) |
Sriram Dash | afa125b | 2017-09-04 15:45:02 +0530 | [diff] [blame] | 334 | u8 __iomem *ptr; |
York Sun | 0404a39 | 2015-03-23 10:41:35 -0700 | [diff] [blame] | 335 | #ifdef I2C1_BASE_ADDR |
| 336 | ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); |
| 337 | |
| 338 | writeb(I2C_GLITCH_EN, ptr); |
| 339 | #endif |
| 340 | #ifdef I2C2_BASE_ADDR |
| 341 | ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); |
| 342 | |
| 343 | writeb(I2C_GLITCH_EN, ptr); |
| 344 | #endif |
| 345 | #ifdef I2C3_BASE_ADDR |
| 346 | ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); |
| 347 | |
| 348 | writeb(I2C_GLITCH_EN, ptr); |
| 349 | #endif |
| 350 | #ifdef I2C4_BASE_ADDR |
| 351 | ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); |
| 352 | |
| 353 | writeb(I2C_GLITCH_EN, ptr); |
| 354 | #endif |
| 355 | #endif |
| 356 | } |
Ashish kumar | 3b52a23 | 2017-02-23 16:03:57 +0530 | [diff] [blame] | 357 | #endif |
Shengzhou Liu | a3117ee | 2016-11-11 18:11:05 +0800 | [diff] [blame] | 358 | |
Saksham Jain | 5d8ffe1 | 2016-03-23 16:24:40 +0530 | [diff] [blame] | 359 | void bypass_smmu(void) |
| 360 | { |
| 361 | u32 val; |
| 362 | val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); |
| 363 | out_le32(SMMU_SCR0, val); |
| 364 | val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); |
| 365 | out_le32(SMMU_NSCR0, val); |
| 366 | } |
Scott Wood | f64c98c | 2015-03-20 19:28:12 -0700 | [diff] [blame] | 367 | void fsl_lsch3_early_init_f(void) |
| 368 | { |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 369 | erratum_rcw_src(); |
Sriram Dash | 36a4a34 | 2017-09-04 15:44:05 +0530 | [diff] [blame] | 370 | #ifdef CONFIG_FSL_IFC |
Scott Wood | f64c98c | 2015-03-20 19:28:12 -0700 | [diff] [blame] | 371 | init_early_memctl_regs(); /* tighten IFC timing */ |
Sriram Dash | 36a4a34 | 2017-09-04 15:44:05 +0530 | [diff] [blame] | 372 | #endif |
Ashish kumar | 3b52a23 | 2017-02-23 16:03:57 +0530 | [diff] [blame] | 373 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 |
York Sun | 0404a39 | 2015-03-23 10:41:35 -0700 | [diff] [blame] | 374 | erratum_a009203(); |
Ashish kumar | 3b52a23 | 2017-02-23 16:03:57 +0530 | [diff] [blame] | 375 | #endif |
Yao Yuan | fae8805 | 2015-12-05 14:59:14 +0800 | [diff] [blame] | 376 | erratum_a008514(); |
| 377 | erratum_a008336(); |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 378 | erratum_a009008(); |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 379 | erratum_a009798(); |
Ran Wang | e64f747 | 2017-09-04 18:46:50 +0800 | [diff] [blame] | 380 | erratum_a008997(); |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 381 | erratum_a009007(); |
Ran Wang | 13a84a5 | 2021-06-16 17:53:19 +0530 | [diff] [blame] | 382 | erratum_a050204(); |
Saksham Jain | 5d8ffe1 | 2016-03-23 16:24:40 +0530 | [diff] [blame] | 383 | #ifdef CONFIG_CHAIN_OF_TRUST |
| 384 | /* In case of Secure Boot, the IBR configures the SMMU |
| 385 | * to allow only Secure transactions. |
| 386 | * SMMU must be reset in bypass mode. |
| 387 | * Set the ClientPD bit and Clear the USFCFG Bit |
| 388 | */ |
| 389 | if (fsl_check_boot_mode_secure() == 1) |
| 390 | bypass_smmu(); |
| 391 | #endif |
Laurentiu Tudor | 7690ea7 | 2019-07-30 17:29:58 +0300 | [diff] [blame] | 392 | |
Laurentiu Tudor | 4adff39 | 2019-10-18 09:01:54 +0000 | [diff] [blame] | 393 | #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \ |
Meenakshi Aggarwal | ccb5d5d | 2020-10-29 19:16:16 +0530 | [diff] [blame] | 394 | defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \ |
| 395 | defined(CONFIG_ARCH_LX2162A) |
Laurentiu Tudor | 7690ea7 | 2019-07-30 17:29:58 +0300 | [diff] [blame] | 396 | set_icids(); |
| 397 | #endif |
Scott Wood | f64c98c | 2015-03-20 19:28:12 -0700 | [diff] [blame] | 398 | } |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 399 | |
Rajesh Bhagat | 814e077 | 2018-01-17 16:13:00 +0530 | [diff] [blame] | 400 | /* Get VDD in the unit mV from voltage ID */ |
| 401 | int get_core_volt_from_fuse(void) |
| 402 | { |
| 403 | struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 404 | int vdd; |
| 405 | u32 fusesr; |
| 406 | u8 vid; |
| 407 | |
| 408 | /* get the voltage ID from fuse status register */ |
| 409 | fusesr = in_le32(&gur->dcfg_fusesr); |
| 410 | debug("%s: fusesr = 0x%x\n", __func__, fusesr); |
| 411 | vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & |
| 412 | FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; |
| 413 | if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { |
| 414 | vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & |
| 415 | FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; |
| 416 | } |
| 417 | debug("%s: VID = 0x%x\n", __func__, vid); |
| 418 | switch (vid) { |
| 419 | case 0x00: /* VID isn't supported */ |
| 420 | vdd = -EINVAL; |
| 421 | debug("%s: The VID feature is not supported\n", __func__); |
| 422 | break; |
| 423 | case 0x08: /* 0.9V silicon */ |
| 424 | vdd = 900; |
| 425 | break; |
| 426 | case 0x10: /* 1.0V silicon */ |
| 427 | vdd = 1000; |
| 428 | break; |
| 429 | default: /* Other core voltage */ |
| 430 | vdd = -EINVAL; |
| 431 | debug("%s: The VID(%x) isn't supported\n", __func__, vid); |
| 432 | break; |
| 433 | } |
| 434 | debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd); |
| 435 | |
| 436 | return vdd; |
| 437 | } |
| 438 | |
Prabhakar Kushwaha | 1966d01 | 2016-06-03 18:41:27 +0530 | [diff] [blame] | 439 | #elif defined(CONFIG_FSL_LSCH2) |
Mingkai Hu | 172081c | 2016-02-02 11:28:03 +0800 | [diff] [blame] | 440 | /* |
| 441 | * This erratum requires setting a value to eddrtqcr1 to optimal |
| 442 | * the DDR performance. The eddrtqcr1 register is in SCFG space |
| 443 | * of LS1043A and the offset is 0x157_020c. |
| 444 | */ |
| 445 | #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \ |
| 446 | && defined(CONFIG_SYS_FSL_ERRATUM_A008514) |
| 447 | #error A009660 and A008514 can not be both enabled. |
| 448 | #endif |
| 449 | |
| 450 | static void erratum_a009660(void) |
| 451 | { |
| 452 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009660 |
| 453 | u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; |
| 454 | out_be32(eddrtqcr1, 0x63b20042); |
| 455 | #endif |
| 456 | } |
| 457 | |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 458 | static void erratum_a008850_early(void) |
| 459 | { |
| 460 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 |
| 461 | /* part 1 of 2 */ |
Ashish Kumar | 1123406 | 2017-08-11 11:09:14 +0530 | [diff] [blame] | 462 | struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + |
| 463 | CONFIG_SYS_CCI400_OFFSET); |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 464 | struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; |
| 465 | |
York Sun | e6b871e | 2017-05-15 08:51:59 -0700 | [diff] [blame] | 466 | /* Skip if running at lower exception level */ |
| 467 | if (current_el() < 3) |
| 468 | return; |
| 469 | |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 470 | /* disables propagation of barrier transactions to DDRC from CCI400 */ |
| 471 | out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); |
| 472 | |
| 473 | /* disable the re-ordering in DDRC */ |
| 474 | ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); |
| 475 | #endif |
| 476 | } |
| 477 | |
| 478 | void erratum_a008850_post(void) |
| 479 | { |
| 480 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 |
| 481 | /* part 2 of 2 */ |
Ashish Kumar | 1123406 | 2017-08-11 11:09:14 +0530 | [diff] [blame] | 482 | struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + |
| 483 | CONFIG_SYS_CCI400_OFFSET); |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 484 | struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; |
| 485 | u32 tmp; |
| 486 | |
York Sun | e6b871e | 2017-05-15 08:51:59 -0700 | [diff] [blame] | 487 | /* Skip if running at lower exception level */ |
| 488 | if (current_el() < 3) |
| 489 | return; |
| 490 | |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 491 | /* enable propagation of barrier transactions to DDRC from CCI400 */ |
| 492 | out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); |
| 493 | |
| 494 | /* enable the re-ordering in DDRC */ |
| 495 | tmp = ddr_in32(&ddr->eor); |
| 496 | tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); |
| 497 | ddr_out32(&ddr->eor, tmp); |
| 498 | #endif |
| 499 | } |
Hou Zhiqiang | 4b23ca8 | 2016-08-02 19:03:27 +0800 | [diff] [blame] | 500 | |
| 501 | #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 |
| 502 | void erratum_a010315(void) |
| 503 | { |
| 504 | int i; |
| 505 | |
| 506 | for (i = PCIE1; i <= PCIE4; i++) |
| 507 | if (!is_serdes_configured(i)) { |
| 508 | debug("PCIe%d: disabled all R/W permission!\n", i); |
| 509 | set_pcie_ns_access(i, 0); |
| 510 | } |
| 511 | } |
| 512 | #endif |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 513 | |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 514 | static void erratum_a010539(void) |
| 515 | { |
| 516 | #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT) |
| 517 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 518 | u32 porsr1; |
| 519 | |
| 520 | porsr1 = in_be32(&gur->porsr1); |
| 521 | porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; |
| 522 | out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), |
| 523 | porsr1); |
Hou Zhiqiang | 653793a | 2018-04-25 14:25:42 +0800 | [diff] [blame] | 524 | out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff); |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 525 | #endif |
| 526 | } |
| 527 | |
Hou Zhiqiang | 4ad5999 | 2016-12-09 16:09:00 +0800 | [diff] [blame] | 528 | /* Get VDD in the unit mV from voltage ID */ |
| 529 | int get_core_volt_from_fuse(void) |
| 530 | { |
| 531 | struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 532 | int vdd; |
| 533 | u32 fusesr; |
| 534 | u8 vid; |
| 535 | |
| 536 | fusesr = in_be32(&gur->dcfg_fusesr); |
| 537 | debug("%s: fusesr = 0x%x\n", __func__, fusesr); |
| 538 | vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & |
| 539 | FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; |
| 540 | if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { |
| 541 | vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & |
| 542 | FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; |
| 543 | } |
| 544 | debug("%s: VID = 0x%x\n", __func__, vid); |
| 545 | switch (vid) { |
| 546 | case 0x00: /* VID isn't supported */ |
| 547 | vdd = -EINVAL; |
| 548 | debug("%s: The VID feature is not supported\n", __func__); |
| 549 | break; |
| 550 | case 0x08: /* 0.9V silicon */ |
| 551 | vdd = 900; |
| 552 | break; |
| 553 | case 0x10: /* 1.0V silicon */ |
| 554 | vdd = 1000; |
| 555 | break; |
| 556 | default: /* Other core voltage */ |
| 557 | vdd = -EINVAL; |
| 558 | printf("%s: The VID(%x) isn't supported\n", __func__, vid); |
| 559 | break; |
| 560 | } |
| 561 | debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd); |
| 562 | |
| 563 | return vdd; |
| 564 | } |
| 565 | |
| 566 | __weak int board_switch_core_volt(u32 vdd) |
| 567 | { |
| 568 | return 0; |
| 569 | } |
| 570 | |
| 571 | static int setup_core_volt(u32 vdd) |
| 572 | { |
| 573 | return board_setup_core_volt(vdd); |
| 574 | } |
| 575 | |
| 576 | #ifdef CONFIG_SYS_FSL_DDR |
| 577 | static void ddr_enable_0v9_volt(bool en) |
| 578 | { |
| 579 | struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; |
| 580 | u32 tmp; |
| 581 | |
| 582 | tmp = ddr_in32(&ddr->ddr_cdr1); |
| 583 | |
| 584 | if (en) |
| 585 | tmp |= DDR_CDR1_V0PT9_EN; |
| 586 | else |
| 587 | tmp &= ~DDR_CDR1_V0PT9_EN; |
| 588 | |
| 589 | ddr_out32(&ddr->ddr_cdr1, tmp); |
| 590 | } |
| 591 | #endif |
| 592 | |
| 593 | int setup_chip_volt(void) |
| 594 | { |
| 595 | int vdd; |
| 596 | |
| 597 | vdd = get_core_volt_from_fuse(); |
| 598 | /* Nothing to do for silicons doesn't support VID */ |
| 599 | if (vdd < 0) |
| 600 | return vdd; |
| 601 | |
| 602 | if (setup_core_volt(vdd)) |
| 603 | printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd); |
| 604 | #ifdef CONFIG_SYS_HAS_SERDES |
| 605 | if (setup_serdes_volt(vdd)) |
| 606 | printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd); |
| 607 | #endif |
| 608 | |
| 609 | #ifdef CONFIG_SYS_FSL_DDR |
| 610 | if (vdd == 900) |
| 611 | ddr_enable_0v9_volt(true); |
| 612 | #endif |
| 613 | |
| 614 | return 0; |
| 615 | } |
| 616 | |
Calvin Johnson | 6d6ef01 | 2018-03-08 15:30:33 +0530 | [diff] [blame] | 617 | #ifdef CONFIG_FSL_PFE |
| 618 | void init_pfe_scfg_dcfg_regs(void) |
| 619 | { |
| 620 | struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; |
| 621 | u32 ecccr2; |
| 622 | |
| 623 | out_be32(&scfg->pfeasbcr, |
| 624 | in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0); |
| 625 | out_be32(&scfg->pfebsbcr, |
| 626 | in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0); |
| 627 | |
| 628 | /* CCI-400 QoS settings for PFE */ |
| 629 | out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS |
| 630 | | SCFG_WR_QOS1_PFE2_QOS)); |
| 631 | out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS |
| 632 | | SCFG_RD_QOS1_PFE2_QOS)); |
| 633 | |
| 634 | ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2); |
| 635 | out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2, |
| 636 | ecccr2 | (unsigned int)DISABLE_PFE_ECC); |
| 637 | } |
| 638 | #endif |
| 639 | |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 640 | void fsl_lsch2_early_init_f(void) |
| 641 | { |
Ashish Kumar | 1123406 | 2017-08-11 11:09:14 +0530 | [diff] [blame] | 642 | struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + |
| 643 | CONFIG_SYS_CCI400_OFFSET); |
Aneesh Bansal | 13d984d | 2015-12-08 13:54:27 +0530 | [diff] [blame] | 644 | struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; |
Pankit Garg | 41bde72 | 2019-05-29 12:12:36 +0000 | [diff] [blame] | 645 | #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT) |
| 646 | enum boot_src src; |
| 647 | #endif |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 648 | |
Hou Zhiqiang | 5ac9a5c | 2016-08-02 19:03:23 +0800 | [diff] [blame] | 649 | #ifdef CONFIG_LAYERSCAPE_NS_ACCESS |
| 650 | enable_layerscape_ns_access(); |
| 651 | #endif |
| 652 | |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 653 | #ifdef CONFIG_FSL_IFC |
| 654 | init_early_memctl_regs(); /* tighten IFC timing */ |
| 655 | #endif |
| 656 | |
Pankit Garg | 41bde72 | 2019-05-29 12:12:36 +0000 | [diff] [blame] | 657 | #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT) |
| 658 | src = get_boot_src(); |
| 659 | if (src != BOOT_SOURCE_QSPI_NOR) |
| 660 | out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); |
| 661 | #else |
Qianyu Gong | 5ab2d0a | 2016-03-16 18:01:52 +0800 | [diff] [blame] | 662 | #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) |
Gong Qianyu | 760df89 | 2016-01-25 15:16:06 +0800 | [diff] [blame] | 663 | out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); |
| 664 | #endif |
Pankit Garg | 41bde72 | 2019-05-29 12:12:36 +0000 | [diff] [blame] | 665 | #endif |
Aneesh Bansal | 13d984d | 2015-12-08 13:54:27 +0530 | [diff] [blame] | 666 | /* Make SEC reads and writes snoopable */ |
Ran Wang | c75026e | 2019-09-20 17:34:29 +0800 | [diff] [blame] | 667 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) |
| 668 | setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | |
| 669 | SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP | |
| 670 | SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP | |
| 671 | SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP | |
| 672 | SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP | |
| 673 | SCFG_SNPCNFGCR_SATAWRSNP); |
Ran Wang | a757669 | 2019-12-26 18:11:17 +0800 | [diff] [blame] | 674 | #elif defined(CONFIG_ARCH_LS1012A) |
| 675 | setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | |
| 676 | SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP | |
| 677 | SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP | |
| 678 | SCFG_SNPCNFGCR_SATAWRSNP); |
Ran Wang | c75026e | 2019-09-20 17:34:29 +0800 | [diff] [blame] | 679 | #else |
Aneesh Bansal | 13d984d | 2015-12-08 13:54:27 +0530 | [diff] [blame] | 680 | setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | |
Tang Yuantian | 2945ae0 | 2016-08-08 15:07:20 +0800 | [diff] [blame] | 681 | SCFG_SNPCNFGCR_SECWRSNP | |
| 682 | SCFG_SNPCNFGCR_SATARDSNP | |
| 683 | SCFG_SNPCNFGCR_SATAWRSNP); |
Ran Wang | c75026e | 2019-09-20 17:34:29 +0800 | [diff] [blame] | 684 | #endif |
Aneesh Bansal | 13d984d | 2015-12-08 13:54:27 +0530 | [diff] [blame] | 685 | |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 686 | /* |
| 687 | * Enable snoop requests and DVM message requests for |
| 688 | * Slave insterface S4 (A53 core cluster) |
| 689 | */ |
York Sun | e6b871e | 2017-05-15 08:51:59 -0700 | [diff] [blame] | 690 | if (current_el() == 3) { |
| 691 | out_le32(&cci->slave[4].snoop_ctrl, |
| 692 | CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); |
| 693 | } |
Mingkai Hu | 8beb075 | 2015-12-07 16:58:54 +0800 | [diff] [blame] | 694 | |
Ran Wang | 4e7cdcf | 2018-08-10 15:00:00 +0800 | [diff] [blame] | 695 | /* |
| 696 | * Program Central Security Unit (CSU) to grant access |
| 697 | * permission for USB 2.0 controller |
| 698 | */ |
| 699 | #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL) |
| 700 | if (current_el() == 3) |
| 701 | set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW); |
| 702 | #endif |
Mingkai Hu | 8beb075 | 2015-12-07 16:58:54 +0800 | [diff] [blame] | 703 | /* Erratum */ |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 704 | erratum_a008850_early(); /* part 1 of 2 */ |
Mingkai Hu | 172081c | 2016-02-02 11:28:03 +0800 | [diff] [blame] | 705 | erratum_a009660(); |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 706 | erratum_a010539(); |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 707 | erratum_a009008(); |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 708 | erratum_a009798(); |
Ran Wang | e64f747 | 2017-09-04 18:46:50 +0800 | [diff] [blame] | 709 | erratum_a008997(); |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 710 | erratum_a009007(); |
Laurentiu Tudor | 512d13e | 2018-08-09 15:19:46 +0300 | [diff] [blame] | 711 | |
Laurentiu Tudor | 22012d5 | 2018-08-27 17:33:59 +0300 | [diff] [blame] | 712 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) |
Laurentiu Tudor | 512d13e | 2018-08-09 15:19:46 +0300 | [diff] [blame] | 713 | set_icids(); |
| 714 | #endif |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 715 | } |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 716 | #endif |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 717 | |
Kuldeep Singh | 34aafb0 | 2019-11-21 17:15:17 +0530 | [diff] [blame] | 718 | #ifdef CONFIG_FSPI_AHB_EN_4BYTE |
| 719 | int fspi_ahb_init(void) |
| 720 | { |
| 721 | /* Enable 4bytes address support and fast read */ |
| 722 | u32 *fspi_lut, lut_key, *fspi_key; |
| 723 | |
| 724 | fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR; |
| 725 | fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR; |
| 726 | |
| 727 | lut_key = in_be32(fspi_key); |
| 728 | |
| 729 | if (lut_key == SYS_NXP_FSPI_LUTKEY) { |
| 730 | /* That means the register is BE */ |
| 731 | out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY); |
| 732 | /* Unlock the lut table */ |
| 733 | out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK); |
| 734 | /* Create READ LUT */ |
| 735 | out_be32(fspi_lut, 0x0820040c); |
| 736 | out_be32(fspi_lut + 1, 0x24003008); |
| 737 | out_be32(fspi_lut + 2, 0x00000000); |
| 738 | /* Lock the lut table */ |
| 739 | out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY); |
| 740 | out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK); |
| 741 | } else { |
| 742 | /* That means the register is LE */ |
| 743 | out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY); |
| 744 | /* Unlock the lut table */ |
| 745 | out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK); |
| 746 | /* Create READ LUT */ |
| 747 | out_le32(fspi_lut, 0x0820040c); |
| 748 | out_le32(fspi_lut + 1, 0x24003008); |
| 749 | out_le32(fspi_lut + 2, 0x00000000); |
| 750 | /* Lock the lut table */ |
| 751 | out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY); |
| 752 | out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK); |
| 753 | } |
| 754 | |
| 755 | return 0; |
| 756 | } |
| 757 | #endif |
| 758 | |
Yuan Yao | 52ae4fd | 2016-12-01 10:13:52 +0800 | [diff] [blame] | 759 | #ifdef CONFIG_QSPI_AHB_INIT |
| 760 | /* Enable 4bytes address support and fast read */ |
| 761 | int qspi_ahb_init(void) |
| 762 | { |
| 763 | u32 *qspi_lut, lut_key, *qspi_key; |
| 764 | |
| 765 | qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300; |
| 766 | qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310; |
| 767 | |
| 768 | lut_key = in_be32(qspi_key); |
| 769 | |
| 770 | if (lut_key == 0x5af05af0) { |
| 771 | /* That means the register is BE */ |
| 772 | out_be32(qspi_key, 0x5af05af0); |
| 773 | /* Unlock the lut table */ |
| 774 | out_be32(qspi_key + 1, 0x00000002); |
| 775 | out_be32(qspi_lut, 0x0820040c); |
| 776 | out_be32(qspi_lut + 1, 0x1c080c08); |
| 777 | out_be32(qspi_lut + 2, 0x00002400); |
| 778 | /* Lock the lut table */ |
| 779 | out_be32(qspi_key, 0x5af05af0); |
| 780 | out_be32(qspi_key + 1, 0x00000001); |
| 781 | } else { |
| 782 | /* That means the register is LE */ |
| 783 | out_le32(qspi_key, 0x5af05af0); |
| 784 | /* Unlock the lut table */ |
| 785 | out_le32(qspi_key + 1, 0x00000002); |
| 786 | out_le32(qspi_lut, 0x0820040c); |
| 787 | out_le32(qspi_lut + 1, 0x1c080c08); |
| 788 | out_le32(qspi_lut + 2, 0x00002400); |
| 789 | /* Lock the lut table */ |
| 790 | out_le32(qspi_key, 0x5af05af0); |
| 791 | out_le32(qspi_key + 1, 0x00000001); |
| 792 | } |
| 793 | |
Pankit Garg | bdbf84f | 2018-11-05 18:01:52 +0000 | [diff] [blame] | 794 | return 0; |
| 795 | } |
| 796 | #endif |
| 797 | |
| 798 | #ifdef CONFIG_TFABOOT |
Rajesh Bhagat | 5b73c90 | 2018-12-27 04:37:49 +0000 | [diff] [blame] | 799 | #define MAX_BOOTCMD_SIZE 512 |
Pankit Garg | bdbf84f | 2018-11-05 18:01:52 +0000 | [diff] [blame] | 800 | |
| 801 | int fsl_setenv_bootcmd(void) |
| 802 | { |
| 803 | int ret; |
| 804 | enum boot_src src = get_boot_src(); |
| 805 | char bootcmd_str[MAX_BOOTCMD_SIZE]; |
| 806 | |
| 807 | switch (src) { |
| 808 | #ifdef IFC_NOR_BOOTCOMMAND |
| 809 | case BOOT_SOURCE_IFC_NOR: |
| 810 | sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND); |
| 811 | break; |
| 812 | #endif |
| 813 | #ifdef QSPI_NOR_BOOTCOMMAND |
| 814 | case BOOT_SOURCE_QSPI_NOR: |
| 815 | sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND); |
| 816 | break; |
| 817 | #endif |
| 818 | #ifdef XSPI_NOR_BOOTCOMMAND |
| 819 | case BOOT_SOURCE_XSPI_NOR: |
| 820 | sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND); |
| 821 | break; |
| 822 | #endif |
| 823 | #ifdef IFC_NAND_BOOTCOMMAND |
| 824 | case BOOT_SOURCE_IFC_NAND: |
| 825 | sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND); |
| 826 | break; |
| 827 | #endif |
| 828 | #ifdef QSPI_NAND_BOOTCOMMAND |
| 829 | case BOOT_SOURCE_QSPI_NAND: |
| 830 | sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND); |
| 831 | break; |
| 832 | #endif |
| 833 | #ifdef XSPI_NAND_BOOTCOMMAND |
| 834 | case BOOT_SOURCE_XSPI_NAND: |
| 835 | sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND); |
| 836 | break; |
| 837 | #endif |
| 838 | #ifdef SD_BOOTCOMMAND |
| 839 | case BOOT_SOURCE_SD_MMC: |
| 840 | sprintf(bootcmd_str, SD_BOOTCOMMAND); |
| 841 | break; |
| 842 | #endif |
| 843 | #ifdef SD2_BOOTCOMMAND |
| 844 | case BOOT_SOURCE_SD_MMC2: |
| 845 | sprintf(bootcmd_str, SD2_BOOTCOMMAND); |
| 846 | break; |
| 847 | #endif |
| 848 | default: |
| 849 | #ifdef QSPI_NOR_BOOTCOMMAND |
| 850 | sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND); |
| 851 | #endif |
| 852 | break; |
| 853 | } |
| 854 | |
| 855 | ret = env_set("bootcmd", bootcmd_str); |
| 856 | if (ret) { |
| 857 | printf("Failed to set bootcmd: ret = %d\n", ret); |
| 858 | return ret; |
| 859 | } |
Yuan Yao | 52ae4fd | 2016-12-01 10:13:52 +0800 | [diff] [blame] | 860 | return 0; |
| 861 | } |
Pankit Garg | 82fcc46 | 2018-11-05 18:02:31 +0000 | [diff] [blame] | 862 | |
| 863 | int fsl_setenv_mcinitcmd(void) |
| 864 | { |
| 865 | int ret = 0; |
| 866 | enum boot_src src = get_boot_src(); |
| 867 | |
| 868 | switch (src) { |
| 869 | #ifdef IFC_MC_INIT_CMD |
| 870 | case BOOT_SOURCE_IFC_NAND: |
| 871 | case BOOT_SOURCE_IFC_NOR: |
| 872 | ret = env_set("mcinitcmd", IFC_MC_INIT_CMD); |
| 873 | break; |
| 874 | #endif |
| 875 | #ifdef QSPI_MC_INIT_CMD |
| 876 | case BOOT_SOURCE_QSPI_NAND: |
| 877 | case BOOT_SOURCE_QSPI_NOR: |
| 878 | ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD); |
| 879 | break; |
| 880 | #endif |
| 881 | #ifdef XSPI_MC_INIT_CMD |
| 882 | case BOOT_SOURCE_XSPI_NAND: |
| 883 | case BOOT_SOURCE_XSPI_NOR: |
| 884 | ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD); |
| 885 | break; |
| 886 | #endif |
| 887 | #ifdef SD_MC_INIT_CMD |
| 888 | case BOOT_SOURCE_SD_MMC: |
| 889 | ret = env_set("mcinitcmd", SD_MC_INIT_CMD); |
| 890 | break; |
| 891 | #endif |
| 892 | #ifdef SD2_MC_INIT_CMD |
| 893 | case BOOT_SOURCE_SD_MMC2: |
| 894 | ret = env_set("mcinitcmd", SD2_MC_INIT_CMD); |
| 895 | break; |
| 896 | #endif |
| 897 | default: |
| 898 | #ifdef QSPI_MC_INIT_CMD |
| 899 | ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD); |
| 900 | #endif |
| 901 | break; |
| 902 | } |
| 903 | |
| 904 | if (ret) { |
| 905 | printf("Failed to set mcinitcmd: ret = %d\n", ret); |
| 906 | return ret; |
| 907 | } |
| 908 | return 0; |
| 909 | } |
Yuan Yao | 52ae4fd | 2016-12-01 10:13:52 +0800 | [diff] [blame] | 910 | #endif |
| 911 | |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 912 | #ifdef CONFIG_BOARD_LATE_INIT |
Michael Walle | fc667ea | 2019-10-21 22:37:45 +0200 | [diff] [blame] | 913 | __weak int fsl_board_late_init(void) |
| 914 | { |
| 915 | return 0; |
| 916 | } |
| 917 | |
Ran Wang | ba7cd0f | 2020-08-05 15:07:27 +0800 | [diff] [blame] | 918 | #define DWC3_GSBUSCFG0 0xc100 |
| 919 | #define DWC3_GSBUSCFG0_CACHETYPE_SHIFT 16 |
| 920 | #define DWC3_GSBUSCFG0_CACHETYPE(n) (((n) & 0xffff) \ |
| 921 | << DWC3_GSBUSCFG0_CACHETYPE_SHIFT) |
| 922 | |
| 923 | void enable_dwc3_snooping(void) |
| 924 | { |
| 925 | int ret; |
| 926 | u32 val; |
| 927 | struct udevice *bus; |
| 928 | struct uclass *uc; |
| 929 | fdt_addr_t dwc3_base; |
| 930 | |
| 931 | ret = uclass_get(UCLASS_USB, &uc); |
| 932 | if (ret) |
| 933 | return; |
| 934 | |
| 935 | uclass_foreach_dev(bus, uc) { |
| 936 | if (!strcmp(bus->driver->of_match->compatible, "fsl,layerscape-dwc3")) { |
| 937 | dwc3_base = devfdt_get_addr(bus); |
| 938 | if (dwc3_base == FDT_ADDR_T_NONE) { |
| 939 | dev_err(bus, "dwc3 regs missing\n"); |
| 940 | continue; |
| 941 | } |
| 942 | val = in_le32(dwc3_base + DWC3_GSBUSCFG0); |
| 943 | val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0); |
| 944 | val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222); |
| 945 | writel(val, dwc3_base + DWC3_GSBUSCFG0); |
| 946 | } |
| 947 | } |
| 948 | } |
| 949 | |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 950 | int board_late_init(void) |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 951 | { |
Aneesh Bansal | 39d5b3b | 2016-01-22 16:37:26 +0530 | [diff] [blame] | 952 | #ifdef CONFIG_CHAIN_OF_TRUST |
| 953 | fsl_setenv_chain_of_trust(); |
| 954 | #endif |
Pankit Garg | bdbf84f | 2018-11-05 18:01:52 +0000 | [diff] [blame] | 955 | #ifdef CONFIG_TFABOOT |
| 956 | /* |
Wasim Khan | 5f74514 | 2021-08-02 10:34:52 +0200 | [diff] [blame] | 957 | * Set bootcmd and mcinitcmd if "fsl_bootcmd_mcinitcmd_set" does |
| 958 | * not exists in env |
Rajesh Bhagat | 5b73c90 | 2018-12-27 04:37:49 +0000 | [diff] [blame] | 959 | */ |
Wasim Khan | 5f74514 | 2021-08-02 10:34:52 +0200 | [diff] [blame] | 960 | if (env_get_yesno("fsl_bootcmd_mcinitcmd_set") <= 0) { |
| 961 | // Set bootcmd and mcinitcmd as per boot source |
Rajesh Bhagat | 5b73c90 | 2018-12-27 04:37:49 +0000 | [diff] [blame] | 962 | fsl_setenv_bootcmd(); |
| 963 | fsl_setenv_mcinitcmd(); |
Wasim Khan | 5f74514 | 2021-08-02 10:34:52 +0200 | [diff] [blame] | 964 | env_set("fsl_bootcmd_mcinitcmd_set", "y"); |
| 965 | } |
Pankit Garg | bdbf84f | 2018-11-05 18:01:52 +0000 | [diff] [blame] | 966 | #endif |
Yuan Yao | 52ae4fd | 2016-12-01 10:13:52 +0800 | [diff] [blame] | 967 | #ifdef CONFIG_QSPI_AHB_INIT |
| 968 | qspi_ahb_init(); |
| 969 | #endif |
Kuldeep Singh | 34aafb0 | 2019-11-21 17:15:17 +0530 | [diff] [blame] | 970 | #ifdef CONFIG_FSPI_AHB_EN_4BYTE |
| 971 | fspi_ahb_init(); |
| 972 | #endif |
Tang Yuantian | 57894be | 2015-12-09 15:32:18 +0800 | [diff] [blame] | 973 | |
Ran Wang | ba7cd0f | 2020-08-05 15:07:27 +0800 | [diff] [blame] | 974 | if (IS_ENABLED(CONFIG_DM)) |
| 975 | enable_dwc3_snooping(); |
| 976 | |
Michael Walle | fc667ea | 2019-10-21 22:37:45 +0200 | [diff] [blame] | 977 | return fsl_board_late_init(); |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 978 | } |
| 979 | #endif |