armv8: Add workaround for USB erratum A-009798
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.
Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index b9e3a20..d9d6e4f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -65,6 +65,7 @@
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
@@ -75,6 +76,27 @@
#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
}
+static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
+{
+ scfg_clrbits32(scfg + offset / 4,
+ SCFG_USB_SQRXTUNE_MASK << 23);
+}
+
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+ set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
+ set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
+ set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
+#elif defined(CONFIG_ARCH_LS2080A)
+ set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
#if defined(CONFIG_FSL_LSCH3)
/*
* This erratum requires setting a value to eddrtqcr1 to
@@ -222,6 +244,7 @@
erratum_a008514();
erratum_a008336();
erratum_a009008();
+ erratum_a009798();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -501,6 +524,7 @@
erratum_a009660();
erratum_a010539();
erratum_a009008();
+ erratum_a009798();
}
#endif