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git01.mediatek.com / filogic / uboot / 26d8b99753d9c55b5e11b4a294728dd877199af9 / . / arch / arm / mach-omap2 / omap5 / Kconfig
blob: a7132dae09eee87d2a5f0e55e7ebacecd2615ffe [file] [log] [blame]
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]1if OMAP54XX
2
Uri Mashiache47ae872017-02-23 15:39:35 +0200[diff] [blame]3config DRA7XX
4 bool
5 help
6 DRA7xx is an OMAP based SOC with Dual Core A-15s.
7
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]8choice
9 prompt "OMAP5 board select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500[diff] [blame]10 optional
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]11
12config TARGET_CM_T54
13 bool "CompuLab CM-T54"
14
15config TARGET_OMAP5_UEVM
16 bool "TI OMAP5 uEVM board"
17
18config TARGET_DRA7XX_EVM
19 bool "TI DRA7XX"
Tom Rini22d567e2017-01-22 19:43:11 -0500[diff] [blame]20 select BOARD_LATE_INIT
Uri Mashiache47ae872017-02-23 15:39:35 +0200[diff] [blame]21 select DRA7XX
Masahiro Yamada653e9fe2016-07-25 19:56:03 +0900[diff] [blame]22 select PHYS_64BIT
Michal Simek7e7ba3b2018-07-23 15:55:15 +0200[diff] [blame]23 select TI_I2C_BOARD_DETECT
Lokesh Vutla68ad5062017-08-21 12:50:51 +0530[diff] [blame]24 imply DM_PMIC
Lokesh Vutla68ad5062017-08-21 12:50:51 +0530[diff] [blame]25 imply DM_REGULATOR
26 imply DM_REGULATOR_LP87565
Faiz Abbas6c198d72017-11-14 16:12:33 +0530[diff] [blame]27 imply DM_THERMAL
Michal Simek7e7ba3b2018-07-23 15:55:15 +0200[diff] [blame]28 imply PMIC_LP87565
29 imply SCSI
30 imply SPL_THERMAL
Faiz Abbas6c198d72017-11-14 16:12:33 +0530[diff] [blame]31 imply TI_DRA7_THERMAL
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]32
Lokesh Vutla6c2cfdd2016-06-10 09:35:42 +0530[diff] [blame]33config TARGET_AM57XX_EVM
34 bool "AM57XX"
Tom Rini22d567e2017-01-22 19:43:11 -0500[diff] [blame]35 select BOARD_LATE_INIT
Michal Simek7e7ba3b2018-07-23 15:55:15 +0200[diff] [blame]36 select CMD_DDR3
Uri Mashiache47ae872017-02-23 15:39:35 +0200[diff] [blame]37 select DRA7XX
Kipisz, Steven161f1382016-02-24 12:30:58 -0600[diff] [blame]38 select TI_I2C_BOARD_DETECT
Michal Simek7e7ba3b2018-07-23 15:55:15 +0200[diff] [blame]39 imply DM_THERMAL
Simon Glass0e5faf02017-06-14 21:28:21 -0600[diff] [blame]40 imply SCSI
Faiz Abbas6c198d72017-11-14 16:12:33 +0530[diff] [blame]41 imply SPL_THERMAL
Faiz Abbas6c198d72017-11-14 16:12:33 +0530[diff] [blame]42 imply TI_DRA7_THERMAL
Felipe Balbi4750eb62014-11-10 14:02:44 -0600[diff] [blame]43
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]44endchoice
45
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]46config SYS_SOC
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]47 default "omap5"
48
Tom Rini50e221a2017-05-12 22:33:17 -0400[diff] [blame]49config OMAP_PLATFORM_RESET_TIME_MAX_USEC
50 int "Something"
51 range 0 31219
52 default 31219
53 help
54 Most OMAPs' provide a way to specify the time for which the reset
55 should be held low while the voltages and Oscillator outputs
56 stabilize.
57 This time is mostly board and PMIC dependent. Hence the boards are
58 expected to specify a pre-computed time using the above option.
59 This value can be computed using a summation of the below 3
60 parameters
61 1: Time taken by the Osciallator to stop and restart
62 2: PMIC OTP time
63 3: Voltage ramp time, which can be derived using the PMIC slew rate
64 and value of voltage ramp needed.
65
Suman Annaf28b26c2016-11-23 12:54:40 +0530[diff] [blame]66if TARGET_DRA7XX_EVM || TARGET_AM57XX_EVM
67menu "Voltage Domain OPP selections"
68
69choice
70 prompt "MPU Voltage Domain"
71 default DRA7_MPU_OPP_NOM
72 help
73 Select the Operating Performance Point(OPP) for the MPU voltage
74 domain on DRA7xx & AM57xx SoCs.
75
76config DRA7_MPU_OPP_NOM
77 bool "OPP NOM"
78 help
79 This config option enables Normal OPP for MPU. This is the safest
80 option for booting.
81
82endchoice
83
84choice
85 prompt "DSPEVE Voltage Domain"
86 help
87 Select the Operating Performance Point(OPP) for the DSPEVE voltage
88 domain on DRA7xx & AM57xx SoCs.
89
90config DRA7_DSPEVE_OPP_NOM
91 bool "OPP NOM"
92 help
93 This config option enables Normal OPP for DSPEVE. This is the safest
94 option for booting and choose this when unsure about other OPPs .
95
96config DRA7_DSPEVE_OPP_OD
97 bool "OPP OD"
98 help
99 This config option enables Over drive OPP for DSPEVE.
100
101config DRA7_DSPEVE_OPP_HIGH
102 bool "OPP HIGH"
103 help
104 This config option enables High OPP for DSPEVE.
105
106endchoice
107
108choice
109 prompt "IVA Voltage Domain"
110 help
111 Select the Operating Performance Point(OPP) for the IVA voltage
112 domain on DRA7xx & AM57xx SoCs.
113
114config DRA7_IVA_OPP_NOM
115 bool "OPP NOM"
116 help
117 This config option enables Normal OPP for IVA. This is the safest
118 option for booting and choose this when unsure about other OPPs .
119
120config DRA7_IVA_OPP_OD
121 bool "OPP OD"
122 help
123 This config option enables Over drive OPP for IVA.
124
125config DRA7_IVA_OPP_HIGH
126 bool "OPP HIGH"
127 help
128 This config option enables High OPP for IVA.
129
130endchoice
131
132choice
133 prompt "GPU Voltage Domain"
134 help
135 Select the Operating Performance Point(OPP) for the GPU voltage
136 domain on DRA7xx & AM57xx SoCs.
137
138config DRA7_GPU_OPP_NOM
139 bool "OPP NOM"
140 help
141 This config option enables Normal OPP for GPU. This is the safest
142 option for booting and choose this when unsure about other OPPs .
143
144config DRA7_GPU_OPP_OD
145 bool "OPP OD"
146 help
147 This config option enables Over drive OPP for GPU.
148
149config DRA7_GPU_OPP_HIGH
150 bool "OPP HIGH"
151 help
152 This config option enables High OPP for GPU.
153
154endchoice
155
156endmenu
157endif
158
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]159source "board/ti/omap5_uevm/Kconfig"
160source "board/ti/dra7xx/Kconfig"
Kipisz, Steven1dacd0d2015-10-29 16:50:43 -0500[diff] [blame]161source "board/ti/am57xx/Kconfig"
Masahiro Yamada420b8162014-08-31 07:11:04 +0900[diff] [blame]162
163endif