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wdenk9c53f402003-10-15 23:53:47 +00001/*
Kumar Gala8aa8cdd2009-09-11 13:41:49 -05002 * Copyright 2007-2009 Freescale Semiconductor, Inc.
Ed Swarthoutdd93d8f2007-07-27 01:50:47 -05003 *
wdenk9c53f402003-10-15 23:53:47 +00004 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <watchdog.h>
31#include <asm/processor.h>
32#include <ioports.h>
33#include <asm/io.h>
Kumar Gala9772ee72008-01-16 22:38:34 -060034#include <asm/mmu.h>
Kumar Gala95fd2f62008-01-16 01:13:58 -060035#include <asm/fsl_law.h>
Kumar Gala36d6b3f2008-01-17 16:48:33 -060036#include "mp.h"
wdenk9c53f402003-10-15 23:53:47 +000037
Wolfgang Denk6405a152006-03-31 18:32:53 +020038DECLARE_GLOBAL_DATA_PTR;
39
Kumar Galacd777282008-08-12 11:14:19 -050040#ifdef CONFIG_MPC8536
41extern void fsl_serdes_init(void);
42#endif
43
Andy Flemingee0e9172007-08-14 00:14:25 -050044#ifdef CONFIG_QE
45extern qe_iop_conf_t qe_iop_conf_tab[];
46extern void qe_config_iopin(u8 port, u8 pin, int dir,
47 int open_drain, int assign);
48extern void qe_init(uint qe_base);
49extern void qe_reset(void);
50
51static void config_qe_ioports(void)
52{
53 u8 port, pin;
54 int dir, open_drain, assign;
55 int i;
56
57 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
58 port = qe_iop_conf_tab[i].port;
59 pin = qe_iop_conf_tab[i].pin;
60 dir = qe_iop_conf_tab[i].dir;
61 open_drain = qe_iop_conf_tab[i].open_drain;
62 assign = qe_iop_conf_tab[i].assign;
63 qe_config_iopin(port, pin, dir, open_drain, assign);
64 }
65}
66#endif
Matthew McClintock148e26a2006-06-28 10:43:36 -050067
Jon Loeligerf5ad3782005-07-23 10:37:35 -050068#ifdef CONFIG_CPM2
Kumar Galacd113a02007-11-28 00:36:33 -060069void config_8560_ioports (volatile ccsr_cpm_t * cpm)
wdenk9c53f402003-10-15 23:53:47 +000070{
71 int portnum;
72
73 for (portnum = 0; portnum < 4; portnum++) {
74 uint pmsk = 0,
75 ppar = 0,
76 psor = 0,
77 pdir = 0,
78 podr = 0,
79 pdat = 0;
80 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
81 iop_conf_t *eiopc = iopc + 32;
82 uint msk = 1;
83
84 /*
85 * NOTE:
86 * index 0 refers to pin 31,
87 * index 31 refers to pin 0
88 */
89 while (iopc < eiopc) {
90 if (iopc->conf) {
91 pmsk |= msk;
92 if (iopc->ppar)
93 ppar |= msk;
94 if (iopc->psor)
95 psor |= msk;
96 if (iopc->pdir)
97 pdir |= msk;
98 if (iopc->podr)
99 podr |= msk;
100 if (iopc->pdat)
101 pdat |= msk;
102 }
103
104 msk <<= 1;
105 iopc++;
106 }
107
108 if (pmsk != 0) {
Kumar Galacd113a02007-11-28 00:36:33 -0600109 volatile ioport_t *iop = ioport_addr (cpm, portnum);
wdenk9c53f402003-10-15 23:53:47 +0000110 uint tpmsk = ~pmsk;
111
112 /*
113 * the (somewhat confused) paragraph at the
114 * bottom of page 35-5 warns that there might
115 * be "unknown behaviour" when programming
116 * PSORx and PDIRx, if PPARx = 1, so I
117 * decided this meant I had to disable the
118 * dedicated function first, and enable it
119 * last.
120 */
121 iop->ppar &= tpmsk;
122 iop->psor = (iop->psor & tpmsk) | psor;
123 iop->podr = (iop->podr & tpmsk) | podr;
124 iop->pdat = (iop->pdat & tpmsk) | pdat;
125 iop->pdir = (iop->pdir & tpmsk) | pdir;
126 iop->ppar |= ppar;
127 }
128 }
129}
130#endif
131
132/*
133 * Breathe some life into the CPU...
134 *
135 * Set up the memory map
136 * initialize a bunch of registers
137 */
138
Kumar Gala24f86a82009-09-17 01:52:37 -0500139#ifdef CONFIG_FSL_CORENET
140static void corenet_tb_init(void)
141{
142 volatile ccsr_rcpm_t *rcpm =
143 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
144 volatile ccsr_pic_t *pic =
145 (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
146 u32 whoami = in_be32(&pic->whoami);
147
148 /* Enable the timebase register for this core */
149 out_be32(&rcpm->ctbenrl, (1 << whoami));
150}
151#endif
152
wdenk9c53f402003-10-15 23:53:47 +0000153void cpu_init_f (void)
154{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155 volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
wdenk9c53f402003-10-15 23:53:47 +0000156 extern void m8560_cpm_reset (void);
Peter Tyser30103c62008-11-11 10:17:10 -0600157#ifdef CONFIG_MPC8548
158 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
159 uint svr = get_svr();
160
161 /*
162 * CPU2 errata workaround: A core hang possible while executing
163 * a msync instruction and a snoopable transaction from an I/O
164 * master tagged to make quick forward progress is present.
165 * Fixed in silicon rev 2.1.
166 */
167 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
168 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
169#endif
wdenk9c53f402003-10-15 23:53:47 +0000170
Kumar Gala9772ee72008-01-16 22:38:34 -0600171 disable_tlb(14);
172 disable_tlb(15);
173
Jon Loeligerf5ad3782005-07-23 10:37:35 -0500174#ifdef CONFIG_CPM2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
wdenk9c53f402003-10-15 23:53:47 +0000176#endif
177
178 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
179 * addresses - these have to be modified later when FLASH size
180 * has been determined
181 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182#if defined(CONFIG_SYS_OR0_REMAP)
Kumar Gala2f1d2d22010-04-13 23:56:23 -0500183 out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP);
wdenk9c53f402003-10-15 23:53:47 +0000184#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185#if defined(CONFIG_SYS_OR1_REMAP)
Kumar Gala2f1d2d22010-04-13 23:56:23 -0500186 out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP);
wdenk9c53f402003-10-15 23:53:47 +0000187#endif
188
189 /* now restrict to preliminary range */
Ed Swarthoutdd93d8f2007-07-27 01:50:47 -0500190 /* if cs1 is already set via debugger, leave cs0/cs1 alone */
191 if (! memctl->br1 & 1) {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
Kumar Gala2f1d2d22010-04-13 23:56:23 -0500193 out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM);
194 out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM);
wdenk9c53f402003-10-15 23:53:47 +0000195#endif
196
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200197#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
Kumar Gala2f1d2d22010-04-13 23:56:23 -0500198 out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM);
199 out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM);
wdenk9c53f402003-10-15 23:53:47 +0000200#endif
Ed Swarthoutdd93d8f2007-07-27 01:50:47 -0500201 }
wdenk9c53f402003-10-15 23:53:47 +0000202
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200203#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
Kumar Gala2f1d2d22010-04-13 23:56:23 -0500204 out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM);
205 out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM);
wdenk9c53f402003-10-15 23:53:47 +0000206#endif
wdenk9c53f402003-10-15 23:53:47 +0000207
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
Kumar Gala2f1d2d22010-04-13 23:56:23 -0500209 out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM);
210 out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM);
wdenk9c53f402003-10-15 23:53:47 +0000211#endif
212
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200213#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
Kumar Gala2f1d2d22010-04-13 23:56:23 -0500214 out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM);
215 out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM);
wdenk9c53f402003-10-15 23:53:47 +0000216#endif
217
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
Kumar Gala2f1d2d22010-04-13 23:56:23 -0500219 out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM);
220 out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM);
wdenk9c53f402003-10-15 23:53:47 +0000221#endif
222
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200223#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
Kumar Gala2f1d2d22010-04-13 23:56:23 -0500224 out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM);
225 out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM);
wdenk9c53f402003-10-15 23:53:47 +0000226#endif
227
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
Kumar Gala2f1d2d22010-04-13 23:56:23 -0500229 out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM);
230 out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM);
wdenk9c53f402003-10-15 23:53:47 +0000231#endif
232
Jon Loeligerf5ad3782005-07-23 10:37:35 -0500233#if defined(CONFIG_CPM2)
wdenk9c53f402003-10-15 23:53:47 +0000234 m8560_cpm_reset();
235#endif
Andy Flemingee0e9172007-08-14 00:14:25 -0500236#ifdef CONFIG_QE
237 /* Config QE ioports */
238 config_qe_ioports();
239#endif
Kumar Galacd777282008-08-12 11:14:19 -0500240#if defined(CONFIG_MPC8536)
241 fsl_serdes_init();
242#endif
Peter Tysera9af1dc2009-06-30 17:15:47 -0500243#if defined(CONFIG_FSL_DMA)
244 dma_init();
245#endif
Kumar Gala24f86a82009-09-17 01:52:37 -0500246#ifdef CONFIG_FSL_CORENET
247 corenet_tb_init();
248#endif
Kumar Gala42f99182009-11-12 10:26:16 -0600249 init_used_tlb_cams();
wdenk9c53f402003-10-15 23:53:47 +0000250}
251
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500252
wdenk9c53f402003-10-15 23:53:47 +0000253/*
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500254 * Initialize L2 as cache.
255 *
256 * The newer 8548, etc, parts have twice as much cache, but
257 * use the same bit-encoding as the older 8555, etc, parts.
258 *
wdenk9c53f402003-10-15 23:53:47 +0000259 */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500260
261int cpu_init_r(void)
wdenk9c53f402003-10-15 23:53:47 +0000262{
Lan Chunhee0ef7322010-04-21 07:40:50 -0500263#ifdef CONFIG_SYS_LBC_LCRR
264 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
265#endif
266
Wolfgang Grandegger09cb1202008-06-05 13:11:59 +0200267 puts ("L2: ");
268
wdenk9c53f402003-10-15 23:53:47 +0000269#if defined(CONFIG_L2_CACHE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200270 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500271 volatile uint cache_ctl;
272 uint svr, ver;
Ed Swarthoutdd93d8f2007-07-27 01:50:47 -0500273 uint l2srbar;
Kumar Gala20119972008-07-14 14:07:00 -0500274 u32 l2siz_field;
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500275
276 svr = get_svr();
Kumar Gala1f109fd2008-04-08 10:45:50 -0500277 ver = SVR_SOC_VER(svr);
wdenk9c53f402003-10-15 23:53:47 +0000278
279 asm("msync;isync");
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500280 cache_ctl = l2cache->l2ctl;
Mingkai Hu0255cd72009-09-11 14:19:10 +0800281
282#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
283 if (cache_ctl & MPC85xx_L2CTL_L2E) {
284 /* Clear L2 SRAM memory-mapped base address */
285 out_be32(&l2cache->l2srbar0, 0x0);
286 out_be32(&l2cache->l2srbar1, 0x0);
287
288 /* set MBECCDIS=0, SBECCDIS=0 */
289 clrbits_be32(&l2cache->l2errdis,
290 (MPC85xx_L2ERRDIS_MBECC |
291 MPC85xx_L2ERRDIS_SBECC));
292
293 /* set L2E=0, L2SRAM=0 */
294 clrbits_be32(&l2cache->l2ctl,
295 (MPC85xx_L2CTL_L2E |
296 MPC85xx_L2CTL_L2SRAM_ENTIRE));
297 }
298#endif
299
Kumar Gala20119972008-07-14 14:07:00 -0500300 l2siz_field = (cache_ctl >> 28) & 0x3;
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500301
Kumar Gala20119972008-07-14 14:07:00 -0500302 switch (l2siz_field) {
303 case 0x0:
304 printf(" unknown size (0x%08x)\n", cache_ctl);
305 return -1;
306 break;
307 case 0x1:
308 if (ver == SVR_8540 || ver == SVR_8560 ||
309 ver == SVR_8541 || ver == SVR_8541_E ||
310 ver == SVR_8555 || ver == SVR_8555_E) {
311 puts("128 KB ");
312 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
313 cache_ctl = 0xc4000000;
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500314 } else {
Wolfgang Grandegger09cb1202008-06-05 13:11:59 +0200315 puts("256 KB ");
Kumar Gala20119972008-07-14 14:07:00 -0500316 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
317 }
318 break;
319 case 0x2:
320 if (ver == SVR_8540 || ver == SVR_8560 ||
321 ver == SVR_8541 || ver == SVR_8541_E ||
322 ver == SVR_8555 || ver == SVR_8555_E) {
323 puts("256 KB ");
Ed Swarthoutdd93d8f2007-07-27 01:50:47 -0500324 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
325 cache_ctl = 0xc8000000;
Kumar Gala20119972008-07-14 14:07:00 -0500326 } else {
327 puts ("512 KB ");
328 /* set L2E=1, L2I=1, & L2SRAM=0 */
329 cache_ctl = 0xc0000000;
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500330 }
Jon Loeliger4fc25e42005-07-25 10:58:39 -0500331 break;
Kumar Gala20119972008-07-14 14:07:00 -0500332 case 0x3:
333 puts("1024 KB ");
334 /* set L2E=1, L2I=1, & L2SRAM=0 */
335 cache_ctl = 0xc0000000;
Ed Swarthoutdd93d8f2007-07-27 01:50:47 -0500336 break;
Jon Loeliger4fc25e42005-07-25 10:58:39 -0500337 }
338
Mingkai Hud2088e02009-08-18 15:37:15 +0800339 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
Wolfgang Grandegger09cb1202008-06-05 13:11:59 +0200340 puts("already enabled");
Ed Swarthoutdd93d8f2007-07-27 01:50:47 -0500341 l2srbar = l2cache->l2srbar0;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200342#ifdef CONFIG_SYS_INIT_L2_ADDR
Mingkai Hud2088e02009-08-18 15:37:15 +0800343 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
344 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200345 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
Ed Swarthoutdd93d8f2007-07-27 01:50:47 -0500346 l2cache->l2srbar0 = l2srbar;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200347 printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
Ed Swarthoutdd93d8f2007-07-27 01:50:47 -0500348 }
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200349#endif /* CONFIG_SYS_INIT_L2_ADDR */
Ed Swarthoutdd93d8f2007-07-27 01:50:47 -0500350 puts("\n");
351 } else {
352 asm("msync;isync");
353 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
354 asm("msync;isync");
Wolfgang Grandegger09cb1202008-06-05 13:11:59 +0200355 puts("enabled\n");
Ed Swarthoutdd93d8f2007-07-27 01:50:47 -0500356 }
Kumar Galae56f2c52009-03-19 09:16:10 -0500357#elif defined(CONFIG_BACKSIDE_L2_CACHE)
358 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
359
360 /* invalidate the L2 cache */
Kumar Galab6a40902009-09-22 15:45:44 -0500361 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
362 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
Kumar Galae56f2c52009-03-19 09:16:10 -0500363 ;
364
Kumar Gala8d2817c2009-03-19 02:53:01 -0500365#ifdef CONFIG_SYS_CACHE_STASHING
366 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
367 mtspr(SPRN_L2CSR1, (32 + 1));
368#endif
369
Kumar Galae56f2c52009-03-19 09:16:10 -0500370 /* enable the cache */
371 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
372
Dave Liu17218192009-10-22 00:10:23 -0500373 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
374 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
375 ;
Kumar Galae56f2c52009-03-19 09:16:10 -0500376 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
Dave Liu17218192009-10-22 00:10:23 -0500377 }
wdenk9c53f402003-10-15 23:53:47 +0000378#else
Wolfgang Grandegger09cb1202008-06-05 13:11:59 +0200379 puts("disabled\n");
wdenk9c53f402003-10-15 23:53:47 +0000380#endif
Andy Flemingee0e9172007-08-14 00:14:25 -0500381#ifdef CONFIG_QE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200382 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
Andy Flemingee0e9172007-08-14 00:14:25 -0500383 qe_init(qe_base);
384 qe_reset();
385#endif
wdenk9c53f402003-10-15 23:53:47 +0000386
Kumar Gala36d6b3f2008-01-17 16:48:33 -0600387#if defined(CONFIG_MP)
388 setup_mp();
389#endif
Lan Chunhee0ef7322010-04-21 07:40:50 -0500390
391#ifdef CONFIG_SYS_LBC_LCRR
392 /*
393 * Modify the CLKDIV field of LCRR register to improve the writing
394 * speed for NOR flash.
395 */
396 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
397 __raw_readl(&lbc->lcrr);
398 isync();
399#endif
400
wdenk9c53f402003-10-15 23:53:47 +0000401 return 0;
402}
Kumar Galac24a9052009-08-14 13:37:54 -0500403
404extern void setup_ivors(void);
405
406void arch_preboot_os(void)
407{
Kumar Gala9faa23a2009-09-11 15:28:41 -0500408 u32 msr;
409
410 /*
411 * We are changing interrupt offsets and are about to boot the OS so
412 * we need to make sure we disable all async interrupts. EE is already
413 * disabled by the time we get called.
414 */
415 msr = mfmsr();
416 msr &= ~(MSR_ME|MSR_CE|MSR_DE);
417 mtmsr(msr);
418
Kumar Galac24a9052009-08-14 13:37:54 -0500419 setup_ivors();
420}