| commit | 30103c610a8b3e1ea3f6b1476ae30a40f5995801 | [log] [tgz] |
|---|---|---|
| author | Peter Tyser <ptyser@xes-inc.com> | Tue Nov 11 10:17:10 2008 -0600 |
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | Wed Dec 03 22:46:42 2008 -0600 |
| tree | a8064eb08a501fdecadfb50af56f646c90be0f3a | |
| parent | 83d43d2f6ab29e02a16b46b915390726f5252966 [diff] |
85xx: Add CPU 2 errata workaround to all 8548 boards All mpc8548-based boards should implement the suggested workaround to CPU 2 errata. Without the workaround, its possible for the 8548's core to hang while executing a msync or mbar 0 instruction and a snoopable transaction from an I/O master tagged to make quick forward progress is present. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Andy Fleming <afleming@freescale.com>