blob: ee5851c376c13e73a5463d1dbda8bef2f46a2762 [file] [log] [blame]
developerb0c86782023-10-27 15:40:47 +08001From 09961de38c33d2cf5ba12679862726e6937e5c58 Mon Sep 17 00:00:00 2001
developeraace7f52022-06-24 13:40:42 +08002From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Wed, 22 Jun 2022 10:39:47 +0800
developer36fe7092023-09-27 12:24:47 +08004Subject: [PATCH] wifi: mt76: mt7915: add mtk internal debug tools for mt76
developer3fa816c2022-04-19 10:21:20 +08005
6---
developerf3f5d9b2023-02-07 15:24:34 +08007 mt76_connac_mcu.h | 6 +
developer27b55252022-09-05 19:09:45 +08008 mt7915/Makefile | 2 +-
developerd5789dc2023-03-27 11:22:06 +08009 mt7915/debugfs.c | 89 +-
developer27b55252022-09-05 19:09:45 +080010 mt7915/mac.c | 14 +
developer36fe7092023-09-27 12:24:47 +080011 mt7915/main.c | 5 +
developerf3f5d9b2023-02-07 15:24:34 +080012 mt7915/mcu.c | 48 +-
developer27b55252022-09-05 19:09:45 +080013 mt7915/mcu.h | 4 +
developer5eddc512023-02-13 16:01:56 +080014 mt7915/mt7915.h | 43 +
developera43cc482023-04-17 15:57:28 +080015 mt7915/mt7915_debug.h | 1418 ++++++++++++++++
developerdfb50982023-09-11 13:34:36 +080016 mt7915/mtk_debugfs.c | 3622 +++++++++++++++++++++++++++++++++++++++++
developer27b55252022-09-05 19:09:45 +080017 mt7915/mtk_mcu.c | 51 +
18 tools/fwlog.c | 44 +-
developer36fe7092023-09-27 12:24:47 +080019 12 files changed, 5327 insertions(+), 19 deletions(-)
developer27b55252022-09-05 19:09:45 +080020 create mode 100644 mt7915/mt7915_debug.h
21 create mode 100644 mt7915/mtk_debugfs.c
22 create mode 100644 mt7915/mtk_mcu.c
developer3fa816c2022-04-19 10:21:20 +080023
24diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
developere35b8e42023-10-16 11:04:00 +080025index ddf901ae..8b3b7c0b 100644
developer3fa816c2022-04-19 10:21:20 +080026--- a/mt76_connac_mcu.h
27+++ b/mt76_connac_mcu.h
developere35b8e42023-10-16 11:04:00 +080028@@ -1162,6 +1162,7 @@ enum {
developer9e5bcc52022-09-27 10:30:15 +080029 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
30 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
31 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
32+ MCU_EXT_CMD_MEC_CTRL = 0x1f,
33 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
34 MCU_EXT_CMD_THERMAL_PROT = 0x23,
35 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
developere35b8e42023-10-16 11:04:00 +080036@@ -1185,6 +1186,11 @@ enum {
developer3fa816c2022-04-19 10:21:20 +080037 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
38 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
39 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
40+#ifdef MTK_DEBUG
developer3fa816c2022-04-19 10:21:20 +080041+ MCU_EXT_CMD_RED_SHOW_STA = 0x69,
42+ MCU_EXT_CMD_RED_TARGET_DELAY = 0x6A,
43+ MCU_EXT_CMD_RED_TX_RPT = 0x6B,
44+#endif
45 MCU_EXT_CMD_TXDPD_CAL = 0x60,
46 MCU_EXT_CMD_CAL_CACHE = 0x67,
developerf3f5d9b2023-02-07 15:24:34 +080047 MCU_EXT_CMD_RED_ENABLE = 0x68,
developer3fa816c2022-04-19 10:21:20 +080048diff --git a/mt7915/Makefile b/mt7915/Makefile
developer36fe7092023-09-27 12:24:47 +080049index c4dca9c1..fd711416 100644
developer3fa816c2022-04-19 10:21:20 +080050--- a/mt7915/Makefile
51+++ b/mt7915/Makefile
developerf3f5d9b2023-02-07 15:24:34 +080052@@ -4,7 +4,7 @@ EXTRA_CFLAGS += -DCONFIG_MT76_LEDS
developer3fa816c2022-04-19 10:21:20 +080053 obj-$(CONFIG_MT7915E) += mt7915e.o
54
55 mt7915e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
56- debugfs.o mmio.o
57+ debugfs.o mmio.o mtk_debugfs.o mtk_mcu.o
58
59 mt7915e-$(CONFIG_NL80211_TESTMODE) += testmode.o
developerad9333b2023-05-22 15:16:16 +080060 mt7915e-$(CONFIG_MT798X_WMAC) += soc.o
developer3fa816c2022-04-19 10:21:20 +080061diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c
developer36fe7092023-09-27 12:24:47 +080062index 93e549c3..f1813776 100644
developer3fa816c2022-04-19 10:21:20 +080063--- a/mt7915/debugfs.c
64+++ b/mt7915/debugfs.c
65@@ -8,6 +8,9 @@
66 #include "mac.h"
67
68 #define FW_BIN_LOG_MAGIC 0x44e98caf
69+#ifdef MTK_DEBUG
70+#define FW_BIN_LOG_MAGIC_V2 0x44d9c99a
71+#endif
72
73 /** global debugfs **/
74
developer004e50c2023-06-29 20:33:22 +080075@@ -496,6 +499,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080076 int ret;
77
developer42b63282022-06-16 13:33:13 +080078 dev->fw.debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
developer3fa816c2022-04-19 10:21:20 +080079+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +080080+ dev->fw.debug_wm = val;
developer3fa816c2022-04-19 10:21:20 +080081+#endif
82
developer42b63282022-06-16 13:33:13 +080083 if (dev->fw.debug_bin)
developer3fa816c2022-04-19 10:21:20 +080084 val = 16;
developer004e50c2023-06-29 20:33:22 +080085@@ -520,6 +526,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080086 if (ret)
developer42b63282022-06-16 13:33:13 +080087 goto out;
developer3fa816c2022-04-19 10:21:20 +080088 }
89+#ifdef MTK_DEBUG
90+ mt7915_mcu_fw_dbg_ctrl(dev, 68, !!val);
91+#endif
92
93 /* WM CPU info record control */
94 mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0));
developer004e50c2023-06-29 20:33:22 +080095@@ -527,6 +536,12 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080096 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5));
97 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5));
98
99+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +0800100+ if (dev->fw.debug_bin & BIT(3))
developer3fa816c2022-04-19 10:21:20 +0800101+ /* use bit 7 to indicate v2 magic number */
developer42b63282022-06-16 13:33:13 +0800102+ dev->fw.debug_wm |= BIT(7);
developer3fa816c2022-04-19 10:21:20 +0800103+#endif
104+
developer42b63282022-06-16 13:33:13 +0800105 out:
106 if (ret)
107 dev->fw.debug_wm = 0;
developer004e50c2023-06-29 20:33:22 +0800108@@ -539,7 +554,11 @@ mt7915_fw_debug_wm_get(void *data, u64 *val)
developer3fa816c2022-04-19 10:21:20 +0800109 {
110 struct mt7915_dev *dev = data;
111
developer42b63282022-06-16 13:33:13 +0800112- *val = dev->fw.debug_wm;
developer3fa816c2022-04-19 10:21:20 +0800113+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +0800114+ *val = dev->fw.debug_wm & ~BIT(7);
developer3fa816c2022-04-19 10:21:20 +0800115+#else
developer42b63282022-06-16 13:33:13 +0800116+ val = dev->fw.debug_wm;
developer3fa816c2022-04-19 10:21:20 +0800117+#endif
118
119 return 0;
120 }
developer004e50c2023-06-29 20:33:22 +0800121@@ -614,16 +633,30 @@ mt7915_fw_debug_bin_set(void *data, u64 val)
developerd5789dc2023-03-27 11:22:06 +0800122 };
123 struct mt7915_dev *dev = data;
124
125- if (!dev->relay_fwlog)
126+ if (!dev->relay_fwlog && val) {
127 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir,
128 1500, 512, &relay_cb, NULL);
129- if (!dev->relay_fwlog)
130- return -ENOMEM;
131+ if (!dev->relay_fwlog)
132+ return -ENOMEM;
133+ }
134
135 dev->fw.debug_bin = val;
developer3fa816c2022-04-19 10:21:20 +0800136
137 relay_reset(dev->relay_fwlog);
138
139+#ifdef MTK_DEBUG
140+ dev->dbg.dump_mcu_pkt = val & BIT(4) ? true : false;
141+ dev->dbg.dump_txd = val & BIT(5) ? true : false;
142+ dev->dbg.dump_tx_pkt = val & BIT(6) ? true : false;
143+ dev->dbg.dump_rx_pkt = val & BIT(7) ? true : false;
144+ dev->dbg.dump_rx_raw = val & BIT(8) ? true : false;
developer3fa816c2022-04-19 10:21:20 +0800145+#endif
146+
developerd5789dc2023-03-27 11:22:06 +0800147+ if (dev->relay_fwlog && !val) {
148+ relay_close(dev->relay_fwlog);
149+ dev->relay_fwlog = NULL;
150+ }
developer42b63282022-06-16 13:33:13 +0800151+
152 return mt7915_fw_debug_wm_set(dev, dev->fw.debug_wm);
developer3fa816c2022-04-19 10:21:20 +0800153 }
154
developer2b96a9e2023-08-09 10:28:15 +0800155@@ -1253,6 +1286,11 @@ int mt7915_init_debugfs(struct mt7915_phy *phy)
developer3fa816c2022-04-19 10:21:20 +0800156 if (!ext_phy)
157 dev->debugfs_dir = dir;
158
159+#ifdef MTK_DEBUG
160+ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
161+ mt7915_mtk_init_debugfs(phy, dir);
162+#endif
163+
164 return 0;
165 }
166
developer2b96a9e2023-08-09 10:28:15 +0800167@@ -1265,6 +1303,12 @@ mt7915_debugfs_write_fwlog(struct mt7915_dev *dev, const void *hdr, int hdrlen,
developerd5789dc2023-03-27 11:22:06 +0800168 void *dest;
169
170 spin_lock_irqsave(&lock, flags);
171+
172+ if (!dev->relay_fwlog) {
173+ spin_unlock_irqrestore(&lock, flags);
174+ return;
175+ }
176+
177 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4);
178 if (dest) {
179 *(u32 *)dest = hdrlen + len;
developer2b96a9e2023-08-09 10:28:15 +0800180@@ -1293,17 +1337,50 @@ void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int
developer3fa816c2022-04-19 10:21:20 +0800181 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),
182 };
183
developerd5789dc2023-03-27 11:22:06 +0800184- if (!dev->relay_fwlog)
185- return;
developer3fa816c2022-04-19 10:21:20 +0800186+#ifdef MTK_DEBUG
187+ struct {
188+ __le32 magic;
189+ u8 version;
190+ u8 _rsv;
191+ __le16 serial_id;
192+ __le32 timestamp;
193+ __le16 msg_type;
194+ __le16 len;
195+ } hdr2 = {
196+ .version = 0x1,
197+ .magic = cpu_to_le32(FW_BIN_LOG_MAGIC_V2),
198+ .msg_type = PKT_TYPE_RX_FW_MONITOR,
199+ };
200+#endif
developer3fa816c2022-04-19 10:21:20 +0800201
202+#ifdef MTK_DEBUG
203+ /* old magic num */
developer42b63282022-06-16 13:33:13 +0800204+ if (!(dev->fw.debug_wm & BIT(7))) {
developer3fa816c2022-04-19 10:21:20 +0800205+ hdr.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
206+ hdr.len = *(__le16 *)data;
207+ mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
208+ } else {
209+ hdr2.serial_id = dev->dbg.fwlog_seq++;
210+ hdr2.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
211+ hdr2.len = *(__le16 *)data;
212+ mt7915_debugfs_write_fwlog(dev, &hdr2, sizeof(hdr2), data, len);
213+ }
214+#else
215 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
216 hdr.len = *(__le16 *)data;
217 mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
218+#endif
219 }
220
221 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len)
222 {
223+#ifdef MTK_DEBUG
224+ if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC &&
225+ get_unaligned_le32(data) != FW_BIN_LOG_MAGIC_V2 &&
226+ get_unaligned_le32(data) != PKT_BIN_DEBUG_MAGIC)
227+#else
228 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC)
229+#endif
230 return false;
231
232 if (dev->relay_fwlog)
233diff --git a/mt7915/mac.c b/mt7915/mac.c
developere35b8e42023-10-16 11:04:00 +0800234index a9bdb653..2650b875 100644
developer3fa816c2022-04-19 10:21:20 +0800235--- a/mt7915/mac.c
236+++ b/mt7915/mac.c
developerad9333b2023-05-22 15:16:16 +0800237@@ -275,6 +275,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb,
developer3fa816c2022-04-19 10:21:20 +0800238 __le16 fc = 0;
239 int idx;
240
241+#ifdef MTK_DEBUG
242+ if (dev->dbg.dump_rx_raw)
243+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX_RAW, 0);
244+#endif
245 memset(status, 0, sizeof(*status));
246
developer2458e702022-12-13 15:52:04 +0800247 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->mt76->band_idx) {
developer004e50c2023-06-29 20:33:22 +0800248@@ -459,6 +463,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb,
developer3fa816c2022-04-19 10:21:20 +0800249 }
250
251 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
252+#ifdef MTK_DEBUG
253+ if (dev->dbg.dump_rx_pkt)
254+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX, hdr_gap);
255+#endif
256 if (hdr_trans && ieee80211_has_morefrags(fc)) {
developeraace7f52022-06-24 13:40:42 +0800257 struct ieee80211_vif *vif;
258 int err;
developer004e50c2023-06-29 20:33:22 +0800259@@ -796,6 +804,12 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developer3fa816c2022-04-19 10:21:20 +0800260 tx_info->buf[1].skip_unmap = true;
261 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
262
263+#ifdef MTK_DEBUG
264+ if (dev->dbg.dump_txd)
265+ mt7915_packet_log_to_host(dev, txwi, MT_TXD_SIZE, PKT_BIN_DEBUG_TXD, 0);
266+ if (dev->dbg.dump_tx_pkt)
267+ mt7915_packet_log_to_host(dev, t->skb->data, t->skb->len, PKT_BIN_DEBUG_TX, 0);
268+#endif
269 return 0;
270 }
271
developeraace7f52022-06-24 13:40:42 +0800272diff --git a/mt7915/main.c b/mt7915/main.c
developere35b8e42023-10-16 11:04:00 +0800273index 95ad05dd..b19aa635 100644
developeraace7f52022-06-24 13:40:42 +0800274--- a/mt7915/main.c
275+++ b/mt7915/main.c
developer2aa1e642022-12-19 11:33:22 +0800276@@ -73,7 +73,11 @@ int mt7915_run(struct ieee80211_hw *hw)
developeraace7f52022-06-24 13:40:42 +0800277 if (ret)
278 goto out;
279
280+#ifdef MTK_DEBUG
281+ ret = mt7915_mcu_set_sku_en(phy, !dev->dbg.sku_disable);
282+#else
283 ret = mt7915_mcu_set_sku_en(phy, true);
284+#endif
285 if (ret)
286 goto out;
287
developere35b8e42023-10-16 11:04:00 +0800288@@ -254,6 +258,7 @@ static int mt7915_add_interface(struct ieee80211_hw *hw,
developer36fe7092023-09-27 12:24:47 +0800289 mvif->sta.wcid.hw_key_idx = -1;
290 mvif->sta.wcid.tx_info |= MT_WCID_TX_INFO_SET;
developere35b8e42023-10-16 11:04:00 +0800291 mt76_wcid_init(&mvif->sta.wcid);
developer36fe7092023-09-27 12:24:47 +0800292+ mvif->sta.vif = mvif;
developer36fe7092023-09-27 12:24:47 +0800293
294 mt7915_mac_wtbl_update(dev, idx,
developere35b8e42023-10-16 11:04:00 +0800295 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
developer3fa816c2022-04-19 10:21:20 +0800296diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developere35b8e42023-10-16 11:04:00 +0800297index e9d7f20b..47e178fd 100644
developer3fa816c2022-04-19 10:21:20 +0800298--- a/mt7915/mcu.c
299+++ b/mt7915/mcu.c
developer004e50c2023-06-29 20:33:22 +0800300@@ -205,6 +205,11 @@ mt7915_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
developeraace7f52022-06-24 13:40:42 +0800301 else
302 qid = MT_MCUQ_WM;
developer3fa816c2022-04-19 10:21:20 +0800303
developer3fa816c2022-04-19 10:21:20 +0800304+#ifdef MTK_DEBUG
305+ if (dev->dbg.dump_mcu_pkt)
306+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_MCU, 0);
307+#endif
developeraace7f52022-06-24 13:40:42 +0800308+
309 return mt76_tx_queue_skb_raw(dev, mdev->q_mcu[qid], skb, 0);
310 }
311
developere35b8e42023-10-16 11:04:00 +0800312@@ -2297,7 +2302,10 @@ static int mt7915_red_set_watermark(struct mt7915_dev *dev)
developerf3f5d9b2023-02-07 15:24:34 +0800313 sizeof(req), false);
314 }
315
316-static int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled)
317+#ifndef MTK_DEBUG
318+static
319+#endif
320+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled)
321 {
322 #define RED_DISABLE 0
323 #define RED_BY_WA_ENABLE 2
developere35b8e42023-10-16 11:04:00 +0800324@@ -3360,6 +3368,8 @@ int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable)
developeraace7f52022-06-24 13:40:42 +0800325 .sku_enable = enable,
326 };
developer3fa816c2022-04-19 10:21:20 +0800327
developeraace7f52022-06-24 13:40:42 +0800328+ pr_info("%s: enable = %d\n", __func__, enable);
329+
330 return mt76_mcu_send_msg(&dev->mt76,
331 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
332 sizeof(req), true);
developere35b8e42023-10-16 11:04:00 +0800333@@ -4014,6 +4024,23 @@ out:
developer004e50c2023-06-29 20:33:22 +0800334 return ret;
developer3fa816c2022-04-19 10:21:20 +0800335 }
developer1eeb8e82022-05-03 14:10:10 +0800336
developer3fa816c2022-04-19 10:21:20 +0800337+#ifdef MTK_DEBUG
338+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp)
339+{
340+ struct {
341+ __le32 args[3];
342+ } req = {
343+ .args = {
344+ cpu_to_le32(a1),
345+ cpu_to_le32(a2),
346+ cpu_to_le32(a3),
347+ },
348+ };
349+
350+ return mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), wait_resp);
351+}
developer3fa816c2022-04-19 10:21:20 +0800352+#endif
developer1eeb8e82022-05-03 14:10:10 +0800353+
354 int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set)
355 {
356 struct {
developere35b8e42023-10-16 11:04:00 +0800357@@ -4042,3 +4069,22 @@ int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set)
developer9e5bcc52022-09-27 10:30:15 +0800358
359 return 0;
360 }
361+
362+#ifdef MTK_DEBUG
363+int mt7915_mcu_set_amsdu_algo(struct mt7915_dev *dev, u16 wcid, u8 enable)
364+{
365+ struct {
366+ u16 action;
367+ u8 _rsv1[2];
368+ u16 wcid;
369+ u8 enable;
370+ u8 _rsv2[5];
371+ } __packed req = {
372+ .action = cpu_to_le16(1),
373+ .wcid = cpu_to_le16(wcid),
374+ .enable = enable,
375+ };
376+
377+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MEC_CTRL), &req, sizeof(req), true);
378+}
379+#endif
developer3fa816c2022-04-19 10:21:20 +0800380diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developer36fe7092023-09-27 12:24:47 +0800381index 8f365461..dd3b5062 100644
developer3fa816c2022-04-19 10:21:20 +0800382--- a/mt7915/mcu.h
383+++ b/mt7915/mcu.h
developerad9333b2023-05-22 15:16:16 +0800384@@ -333,6 +333,10 @@ enum {
developer3fa816c2022-04-19 10:21:20 +0800385 MCU_WA_PARAM_PDMA_RX = 0x04,
386 MCU_WA_PARAM_CPU_UTIL = 0x0b,
387 MCU_WA_PARAM_RED = 0x0e,
388+#ifdef MTK_DEBUG
389+ MCU_WA_PARAM_RED_SHOW_STA = 0xf,
390+ MCU_WA_PARAM_RED_TARGET_DELAY = 0x10,
391+#endif
developerf3f5d9b2023-02-07 15:24:34 +0800392 MCU_WA_PARAM_RED_SETTING = 0x40,
developer3fa816c2022-04-19 10:21:20 +0800393 };
394
developer3fa816c2022-04-19 10:21:20 +0800395diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developere35b8e42023-10-16 11:04:00 +0800396index 35458ec9..887c4a56 100644
developer3fa816c2022-04-19 10:21:20 +0800397--- a/mt7915/mt7915.h
398+++ b/mt7915/mt7915.h
399@@ -9,6 +9,7 @@
400 #include "../mt76_connac.h"
401 #include "regs.h"
402
403+#define MTK_DEBUG 1
404 #define MT7915_MAX_INTERFACES 19
developer3fa816c2022-04-19 10:21:20 +0800405 #define MT7915_WTBL_SIZE 288
developeraace7f52022-06-24 13:40:42 +0800406 #define MT7916_WTBL_SIZE 544
developere35b8e42023-10-16 11:04:00 +0800407@@ -322,6 +323,28 @@ struct mt7915_dev {
developer3fa816c2022-04-19 10:21:20 +0800408 struct reset_control *rstc;
409 void __iomem *dcm;
410 void __iomem *sku;
411+
412+#ifdef MTK_DEBUG
413+ u16 wlan_idx;
414+ struct {
415+ u32 fixed_rate;
416+ u32 l1debugfs_reg;
417+ u32 l2debugfs_reg;
418+ u32 mac_reg;
419+ u32 fw_dbg_module;
420+ u8 fw_dbg_lv;
421+ u32 bcn_total_cnt[2];
422+ u16 fwlog_seq;
423+ bool dump_mcu_pkt;
424+ bool dump_txd;
425+ bool dump_tx_pkt;
426+ bool dump_rx_pkt;
427+ bool dump_rx_raw;
428+ u32 token_idx;
developeraace7f52022-06-24 13:40:42 +0800429+ u8 sku_disable;
developer3fa816c2022-04-19 10:21:20 +0800430+ } dbg;
431+ const struct mt7915_dbg_reg_desc *dbg_reg;
432+#endif
433 };
434
435 enum {
developere35b8e42023-10-16 11:04:00 +0800436@@ -601,4 +624,24 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developerf1313102022-10-11 11:02:55 +0800437 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
438 bool pci, int *irq);
developer3fa816c2022-04-19 10:21:20 +0800439
440+#ifdef MTK_DEBUG
441+int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir);
442+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp);
443+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled);
444+void mt7915_dump_tmac_info(u8 *tmac_info);
445+int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level);
446+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len);
developer9e5bcc52022-09-27 10:30:15 +0800447+int mt7915_mcu_set_amsdu_algo(struct mt7915_dev *dev, u16 wcid, u8 enable);
developer3fa816c2022-04-19 10:21:20 +0800448+
449+#define PKT_BIN_DEBUG_MAGIC 0xc8763123
450+enum {
451+ PKT_BIN_DEBUG_MCU,
452+ PKT_BIN_DEBUG_TXD,
453+ PKT_BIN_DEBUG_TX,
454+ PKT_BIN_DEBUG_RX,
455+ PKT_BIN_DEBUG_RX_RAW,
456+};
457+
458+#endif
459+
460 #endif
461diff --git a/mt7915/mt7915_debug.h b/mt7915/mt7915_debug.h
462new file mode 100644
developerbf0f2d62023-11-14 17:01:47 +0800463index 0000000..4ab113e
developer3fa816c2022-04-19 10:21:20 +0800464--- /dev/null
465+++ b/mt7915/mt7915_debug.h
developerbf0f2d62023-11-14 17:01:47 +0800466@@ -0,0 +1,1432 @@
developer3fa816c2022-04-19 10:21:20 +0800467+#ifndef __MT7915_DEBUG_H
468+#define __MT7915_DEBUG_H
469+
470+#ifdef MTK_DEBUG
471+
472+#define DBG_INVALID_BASE 0xffffffff
473+#define DBG_INVALID_OFFSET 0x0
474+
475+struct __dbg_map {
476+ u32 phys;
477+ u32 maps;
478+ u32 size;
479+};
480+
481+struct __dbg_reg {
482+ u32 base;
483+ u32 offs;
484+};
485+
486+struct __dbg_mask {
487+ u32 end;
488+ u32 start;
489+};
490+
491+enum dbg_base_rev {
492+ MT_DBG_WFDMA0_BASE,
493+ MT_DBG_WFDMA1_BASE,
494+ MT_DBG_WFDMA0_PCIE1_BASE,
495+ MT_DBG_WFDMA1_PCIE1_BASE,
496+ MT_DBG_WFDMA_EXT_CSR_BASE,
497+ MT_DBG_SWDEF_BASE,
498+ __MT_DBG_BASE_REV_MAX,
499+};
500+
501+enum dbg_reg_rev {
502+ DBG_INT_SOURCE_CSR,
503+ DBG_INT_MASK_CSR,
504+ DBG_INT1_SOURCE_CSR,
505+ DBG_INT1_MASK_CSR,
506+ DBG_TX_RING_BASE,
507+ DBG_RX_EVENT_RING_BASE,
508+ DBG_RX_STS_RING_BASE,
509+ DBG_RX_DATA_RING_BASE,
510+ DBG_DMA_ICSC_FR0,
511+ DBG_DMA_ICSC_FR1,
512+ DBG_TMAC_ICSCR0,
513+ DBG_RMAC_RXICSRPT,
514+ DBG_MIB_M0SDR0,
515+ DBG_MIB_M0SDR3,
516+ DBG_MIB_M0SDR4,
517+ DBG_MIB_M0SDR5,
518+ DBG_MIB_M0SDR7,
519+ DBG_MIB_M0SDR8,
520+ DBG_MIB_M0SDR9,
521+ DBG_MIB_M0SDR10,
522+ DBG_MIB_M0SDR11,
523+ DBG_MIB_M0SDR12,
524+ DBG_MIB_M0SDR14,
525+ DBG_MIB_M0SDR15,
526+ DBG_MIB_M0SDR16,
527+ DBG_MIB_M0SDR17,
528+ DBG_MIB_M0SDR18,
529+ DBG_MIB_M0SDR19,
530+ DBG_MIB_M0SDR20,
531+ DBG_MIB_M0SDR21,
532+ DBG_MIB_M0SDR22,
533+ DBG_MIB_M0SDR23,
534+ DBG_MIB_M0DR0,
535+ DBG_MIB_M0DR1,
536+ DBG_MIB_MUBF,
537+ DBG_MIB_M0DR6,
538+ DBG_MIB_M0DR7,
539+ DBG_MIB_M0DR8,
540+ DBG_MIB_M0DR9,
541+ DBG_MIB_M0DR10,
542+ DBG_MIB_M0DR11,
543+ DBG_MIB_M0DR12,
544+ DBG_WTBLON_WDUCR,
545+ DBG_UWTBL_WDUCR,
546+ DBG_PLE_DRR_TABLE_CTRL,
547+ DBG_PLE_DRR_TABLE_RDATA,
548+ DBG_PLE_PBUF_CTRL,
549+ DBG_PLE_QUEUE_EMPTY,
550+ DBG_PLE_FREEPG_CNT,
551+ DBG_PLE_FREEPG_HEAD_TAIL,
552+ DBG_PLE_PG_HIF_GROUP,
553+ DBG_PLE_HIF_PG_INFO,
554+ DBG_PLE_PG_HIF_TXCMD_GROUP,
555+ DBG_PLE_HIF_TXCMD_PG_INFO,
556+ DBG_PLE_PG_CPU_GROUP,
557+ DBG_PLE_CPU_PG_INFO,
558+ DBG_PLE_FL_QUE_CTRL,
559+ DBG_PLE_NATIVE_TXCMD_Q_EMPTY,
560+ DBG_PLE_TXCMD_Q_EMPTY,
561+ DBG_PLE_AC_QEMPTY,
562+ DBG_PLE_AC_OFFSET,
563+ DBG_PLE_STATION_PAUSE,
564+ DBG_PLE_DIS_STA_MAP,
565+ DBG_PSE_PBUF_CTRL,
566+ DBG_PSE_FREEPG_CNT,
567+ DBG_PSE_FREEPG_HEAD_TAIL,
568+ DBG_PSE_HIF0_PG_INFO,
569+ DBG_PSE_PG_HIF1_GROUP,
570+ DBG_PSE_HIF1_PG_INFO,
571+ DBG_PSE_PG_CPU_GROUP,
572+ DBG_PSE_CPU_PG_INFO,
573+ DBG_PSE_PG_PLE_GROUP,
574+ DBG_PSE_PLE_PG_INFO,
575+ DBG_PSE_PG_LMAC0_GROUP,
576+ DBG_PSE_LMAC0_PG_INFO,
577+ DBG_PSE_PG_LMAC1_GROUP,
578+ DBG_PSE_LMAC1_PG_INFO,
579+ DBG_PSE_PG_LMAC2_GROUP,
580+ DBG_PSE_LMAC2_PG_INFO,
581+ DBG_PSE_PG_LMAC3_GROUP,
582+ DBG_PSE_LMAC3_PG_INFO,
583+ DBG_PSE_PG_MDP_GROUP,
584+ DBG_PSE_MDP_PG_INFO,
585+ DBG_PSE_PG_PLE1_GROUP,
586+ DBG_PSE_PLE1_PG_INFO,
587+ DBG_AGG_AALCR0,
588+ DBG_AGG_AALCR1,
589+ DBG_AGG_AALCR2,
590+ DBG_AGG_AALCR3,
591+ DBG_AGG_AALCR4,
592+ DBG_AGG_B0BRR0,
593+ DBG_AGG_B1BRR0,
594+ DBG_AGG_B2BRR0,
595+ DBG_AGG_B3BRR0,
596+ DBG_AGG_AWSCR0,
597+ DBG_AGG_PCR0,
598+ DBG_AGG_TTCR0,
599+ DBG_MIB_M0ARNG0,
600+ DBG_MIB_M0DR2,
601+ DBG_MIB_M0DR13,
developer79a21a22023-01-09 13:57:39 +0800602+ DBG_WFDMA_WED_TX_CTRL,
603+ DBG_WFDMA_WED_RX_CTRL,
developer3fa816c2022-04-19 10:21:20 +0800604+ __MT_DBG_REG_REV_MAX,
605+};
606+
607+enum dbg_mask_rev {
608+ DBG_MIB_M0SDR10_RX_MDRDY_COUNT,
609+ DBG_MIB_M0SDR14_AMPDU,
610+ DBG_MIB_M0SDR15_AMPDU_ACKED,
611+ DBG_MIB_RX_FCS_ERROR_COUNT,
612+ __MT_DBG_MASK_REV_MAX,
613+};
614+
615+enum dbg_bit_rev {
616+ __MT_DBG_BIT_REV_MAX,
617+};
618+
619+static const u32 mt7915_dbg_base[] = {
620+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
621+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
622+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
623+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
624+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
625+ [MT_DBG_SWDEF_BASE] = 0x41f200,
626+};
627+
628+static const u32 mt7916_dbg_base[] = {
629+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
630+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
631+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
632+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
633+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
634+ [MT_DBG_SWDEF_BASE] = 0x411400,
635+};
636+
developerbf0f2d62023-11-14 17:01:47 +0800637+static const u32 mt7981_dbg_base[] = {
638+ [MT_DBG_WFDMA0_BASE] = 0x24000,
639+ [MT_DBG_WFDMA1_BASE] = 0x25000,
640+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0x28000,
641+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0x29000,
642+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0x27000,
643+ [MT_DBG_SWDEF_BASE] = 0x411400,
644+};
645+
developer3fa816c2022-04-19 10:21:20 +0800646+static const u32 mt7986_dbg_base[] = {
647+ [MT_DBG_WFDMA0_BASE] = 0x24000,
648+ [MT_DBG_WFDMA1_BASE] = 0x25000,
649+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0x28000,
650+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0x29000,
651+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0x27000,
652+ [MT_DBG_SWDEF_BASE] = 0x411400,
653+};
654+
655+/* mt7915 regs with different base and offset */
656+static const struct __dbg_reg mt7915_dbg_reg[] = {
developer79a21a22023-01-09 13:57:39 +0800657+ [DBG_WFDMA_WED_TX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x300 },
658+ [DBG_WFDMA_WED_RX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x400 },
developer3fa816c2022-04-19 10:21:20 +0800659+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x10 },
660+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x14 },
661+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x88 },
662+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x8c },
663+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x400 },
664+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x500 },
665+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x510 },
666+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
667+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x0f0 },
668+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x0f4 },
669+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x200 },
670+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0x618},
671+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x010},
672+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x014},
673+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x018},
674+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x01c},
675+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x024},
676+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x028},
677+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x02C},
678+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x030},
679+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x034},
680+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x038},
681+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x040},
682+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x044},
683+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x048},
684+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x04c},
685+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x050},
686+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x054},
687+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x058},
688+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x05c},
689+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x060},
690+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x064},
691+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x0a0},
692+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x0a4},
693+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x090},
694+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x0b8},
695+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x0bc},
696+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x0c0},
697+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x0c4},
698+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x0c8},
699+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x0cc},
700+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x160},
701+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x0},
702+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x0},
703+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x388},
704+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x350},
705+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
706+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x0b0},
707+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
708+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
709+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x110},
710+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x114},
711+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x120},
712+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x124},
713+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
714+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
715+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x1b0},
716+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x22c},
717+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x230},
718+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x500},
719+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x040},
720+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x400},
721+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x440},
developerf32dabf2022-06-01 10:59:24 +0800722+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
developer3fa816c2022-04-19 10:21:20 +0800723+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
724+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
725+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x114},
726+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x118},
727+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x11c},
728+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
729+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
730+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x160},
731+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x164},
732+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x170},
733+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x174},
734+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x178},
735+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
736+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x180},
737+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x184},
738+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x188},
739+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x18c},
740+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x198},
741+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x19c},
742+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x168},
743+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
744+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x048},
745+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x04c},
746+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x050},
747+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x054},
748+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x058},
749+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x100},
750+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x104},
751+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x108},
752+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x10c},
753+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x030},
754+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x040},
755+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x04c},
756+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x4b8},
757+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x0a8},
758+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x164},
759+};
760+
761+/* mt7986/mt7916 regs with different base and offset */
762+static const struct __dbg_reg mt7916_dbg_reg[] = {
developer79a21a22023-01-09 13:57:39 +0800763+ [DBG_WFDMA_WED_TX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x300 },
764+ [DBG_WFDMA_WED_RX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x400 },
developer3fa816c2022-04-19 10:21:20 +0800765+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA0_BASE, 0x200 },
766+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA0_BASE, 0x204 },
767+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x200 },
768+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x204 },
769+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x400 },
770+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
771+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x520 },
772+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x540 },
773+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x05c },
774+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x060 },
775+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x120 },
776+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0xd0 },
777+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x7d8},
778+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x698},
779+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x788},
780+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x780},
781+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x5a8},
782+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x78c},
783+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x024},
784+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x76c},
785+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x790},
786+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x558},
787+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x564},
788+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x564},
789+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x7fc},
790+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x800},
791+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x030},
792+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x5ac},
793+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x5b0},
794+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x5b4},
795+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x770},
796+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x774},
797+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x594},
798+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x598},
799+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x7ac},
800+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x658},
801+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x65c},
802+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x56c},
803+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x570},
804+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x578},
805+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x574},
806+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x654},
807+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x200},
808+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x094},
809+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x490},
810+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x470},
811+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
812+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x360},
813+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
814+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
815+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x00c},
816+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x388},
817+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x014},
818+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x390},
819+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x018},
820+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x394},
821+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x3e0},
822+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x370},
developerf32dabf2022-06-01 10:59:24 +0800823+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x36c},
developer3fa816c2022-04-19 10:21:20 +0800824+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x600},
825+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x080},
826+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x100},
827+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x180},
828+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
829+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
830+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
831+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x150},
832+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x154},
833+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
834+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x118},
835+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x158},
836+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x11c},
837+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x15c},
838+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x124},
839+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x164},
840+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x128},
841+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x168},
842+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x12c},
843+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
844+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x130},
845+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
846+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x134},
847+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x174},
848+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x120},
849+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
850+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x028},
851+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x144},
852+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x14c},
853+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x154},
854+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x02c},
855+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x08c},
856+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x148},
857+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x150},
858+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x158},
859+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x05c},
860+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x06c},
861+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x07c},
862+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x0b0},
863+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x7dc},
864+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x7ec},
865+};
866+
867+static const struct __dbg_mask mt7915_dbg_mask[] = {
868+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {25, 0},
869+ [DBG_MIB_M0SDR14_AMPDU] = {23, 0},
870+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {23, 0},
871+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {15, 0},
872+};
873+
874+static const struct __dbg_mask mt7916_dbg_mask[] = {
875+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {31, 0},
876+ [DBG_MIB_M0SDR14_AMPDU] = {31, 0},
877+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {31, 0},
878+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {31, 16},
879+};
880+
881+/* used to differentiate between generations */
882+struct mt7915_dbg_reg_desc {
883+ const u32 id;
884+ const u32 *base_rev;
885+ const struct __dbg_reg *reg_rev;
886+ const struct __dbg_mask *mask_rev;
887+};
888+
889+static const struct mt7915_dbg_reg_desc dbg_reg_s[] = {
890+ { 0x7915,
891+ mt7915_dbg_base,
892+ mt7915_dbg_reg,
893+ mt7915_dbg_mask
894+ },
895+ { 0x7906,
896+ mt7916_dbg_base,
897+ mt7916_dbg_reg,
898+ mt7916_dbg_mask
899+ },
developerbf0f2d62023-11-14 17:01:47 +0800900+ { 0x7981,
901+ mt7981_dbg_base,
902+ mt7916_dbg_reg,
903+ mt7916_dbg_mask
904+ },
developer3fa816c2022-04-19 10:21:20 +0800905+ { 0x7986,
906+ mt7986_dbg_base,
907+ mt7916_dbg_reg,
908+ mt7916_dbg_mask
909+ },
910+};
911+
912+struct bin_debug_hdr {
913+ __le32 magic_num;
914+ __le16 serial_id;
915+ __le16 msg_type;
916+ __le16 len;
917+ __le16 des_len; /* descriptor len for rxd */
918+} __packed;
919+
developera43cc482023-04-17 15:57:28 +0800920+/* fw wm info related strcture */
921+struct cos_msg_trace_t {
922+ u32 dest_id;
923+ u8 msg_id;
924+ u32 pcount;
925+ u32 qread;
926+ u32 ts_enq;
927+ u32 ts_deq;
928+ u32 ts_finshq;
929+};
930+
931+struct cos_task_info_struct {
932+ u32 task_name_ptr;
933+ u32 task_qname_ptr;
934+ u32 task_priority;
935+ u16 task_stack_size;
936+ u8 task_ext_qsize;
937+ u32 task_id;
938+ u32 task_ext_qid;
939+ u32 task_main_func;
940+ u32 task_init_func;
941+};
942+
943+struct cos_program_trace_t{
944+ u32 dest_id;
945+ u32 msg_id;
946+ u32 msg_sn;
947+ u32 ts_gpt2;
948+ u32 LP;
949+ char name[12];
950+} ;
951+
952+struct cos_msg_type {
953+ u32 finish_cnt;
954+ u32 exe_time;
955+ u32 exe_peak;
956+};
957+
958+struct cos_task_type{
959+ u32 tc_stack_start;
960+ u32 tc_stack_end;
961+ u32 tc_stack_pointer;
962+ u32 tc_stack_size;
963+ u32 tc_schedule_count;
964+ u8 tc_status;
965+ u8 tc_priority;
966+ u8 tc_weight;
967+ u8 RSVD[28];
968+ u32 tc_entry_func;
969+ u32 tc_exe_start;
970+ u32 tc_exe_time;
971+ u32 tc_exe_peak;
972+ u32 tc_pcount;
973+};
974+
developer3fa816c2022-04-19 10:21:20 +0800975+#define __DBG_REG_MAP(_dev, id, ofs) ((_dev)->dbg_reg->base_rev[(id)] + (ofs))
976+#define __DBG_REG_BASE(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].base)
977+#define __DBG_REG_OFFS(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].offs)
978+
979+#define __DBG_MASK(_dev, id) GENMASK((_dev)->dbg_reg->mask_rev[(id)].end, \
980+ (_dev)->dbg_reg->mask_rev[(id)].start)
981+#define __DBG_REG(_dev, id) __DBG_REG_MAP((_dev), __DBG_REG_BASE((_dev), (id)), \
982+ __DBG_REG_OFFS((_dev), (id)))
983+
984+#define __DBG_FIELD_GET(id, _reg) (((_reg) & __DBG_MASK(dev, (id))) >> \
985+ dev->dbg_reg->mask_rev[(id)].start)
986+#define __DBG_FIELD_PREP(id, _reg) (((_reg) << dev->dbg_reg->mask_rev[(id)].start) & \
987+ __DBG_MASK(dev, (id)))
988+
989+
990+#define MT_DBG_TX_RING_BASE __DBG_REG(dev, DBG_TX_RING_BASE)
991+#define MT_DBG_RX_EVENT_RING_BASE __DBG_REG(dev, DBG_RX_EVENT_RING_BASE)
992+#define MT_DBG_RX_STS_RING_BASE __DBG_REG(dev, DBG_RX_STS_RING_BASE)
993+#define MT_DBG_RX_DATA_RING_BASE __DBG_REG(dev, DBG_RX_DATA_RING_BASE)
developer79a21a22023-01-09 13:57:39 +0800994+#define MT_DBG_WFDMA_WED_TX_CTRL_BASE __DBG_REG(dev, DBG_WFDMA_WED_TX_CTRL)
995+#define MT_DBG_WFDMA_WED_RX_CTRL_BASE __DBG_REG(dev, DBG_WFDMA_WED_RX_CTRL)
developer3fa816c2022-04-19 10:21:20 +0800996+
997+#define MT_DBG_TX_RING_CTRL(n) (MT_DBG_TX_RING_BASE + (0x10 * (n)))
998+#define MT_DBG_RX_DATA_RING_CTRL(n) (MT_DBG_RX_DATA_RING_BASE + (0x10 * (n)))
999+#define MT_DBG_RX_EVENT_RING_CTRL(n) (MT_DBG_RX_EVENT_RING_BASE + (0x10 * (n)))
1000+
developer79a21a22023-01-09 13:57:39 +08001001+#define MT_DBG_WFDMA_WED_TX_CTRL(n) (MT_DBG_WFDMA_WED_TX_CTRL_BASE + (0x10 * (n)))
1002+#define MT_DBG_WFDMA_WED_RX_CTRL(n) (MT_DBG_WFDMA_WED_RX_CTRL_BASE + (0x10 * (n)))
developer3fa816c2022-04-19 10:21:20 +08001003+/* WFDMA COMMON */
1004+#define MT_DBG_INT_SOURCE_CSR __DBG_REG(dev, DBG_INT_SOURCE_CSR)
1005+#define MT_DBG_INT_MASK_CSR __DBG_REG(dev, DBG_INT_MASK_CSR)
1006+#define MT_DBG_INT1_SOURCE_CSR __DBG_REG(dev, DBG_INT1_SOURCE_CSR)
1007+#define MT_DBG_INT1_MASK_CSR __DBG_REG(dev, DBG_INT1_MASK_CSR)
1008+
1009+/* WFDMA0 */
1010+#define MT_DBG_WFDMA0(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_BASE, (_ofs))
1011+
1012+#define MT_DBG_WFDMA0_INT_SOURCE_CSR MT_DBG_WFDMA0(0x200)
1013+#define MT_DBG_WFDMA0_INT_MASK_CSR MT_DBG_WFDMA0(0x204)
1014+
1015+#define MT_DBG_WFDMA0_GLO_CFG MT_DBG_WFDMA0(0x208)
1016+#define MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
1017+#define MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
1018+#define MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK BIT(1)
1019+#define MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK BIT(3)
1020+
1021+
1022+/* WFDMA1 */
1023+#define MT_DBG_WFDMA1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_BASE, (_ofs))
1024+#define MT_DBG_WFDMA1_INT_SOURCE_CSR MT_DBG_WFDMA1(0x200)
1025+#define MT_DBG_WFDMA1_INT_MASK_CSR MT_DBG_WFDMA1(0x204)
1026+
1027+#define MT_DBG_WFDMA1_GLO_CFG MT_DBG_WFDMA1(0x208)
1028+
1029+#define MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
1030+#define MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
1031+#define MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK BIT(1)
1032+#define MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK BIT(3)
1033+
1034+/* WFDMA0 PCIE1 */
1035+#define MT_DBG_WFDMA0_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_PCIE1_BASE, (_ofs))
1036+
1037+#define MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA0_PCIE1(0x200)
1038+#define MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR MT_DBG_WFDMA0_PCIE1(0x204)
1039+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG MT_DBG_WFDMA0_PCIE1(0x208)
1040+#define MT_DBG_WFDMA0_PCIE1_RX1_CTRL0 MT_DBG_WFDMA1_PCIE1(0x510)
1041+
1042+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
1043+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
1044+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
1045+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
1046+
1047+/* WFDMA1 PCIE1 */
1048+#define MT_DBG_WFDMA1_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_PCIE1_BASE, (_ofs))
1049+#define MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA1_PCIE1(0x200)
1050+#define MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR MT_DBG_WFDMA1_PCIE1(0x204)
1051+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG MT_DBG_WFDMA1_PCIE1(0x208)
1052+#define MT_DBG_WFDMA1_PCIE1_TX19_CTRL0 MT_DBG_WFDMA1_PCIE1(0x330)
1053+#define MT_DBG_WFDMA1_PCIE1_RX2_CTRL0 MT_DBG_WFDMA1_PCIE1(0x520)
1054+
1055+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
1056+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
1057+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
1058+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
1059+
1060+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK BIT(2)
1061+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK BIT(0)
1062+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK BIT(3)
1063+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK BIT(1)
1064+
1065+
1066+/* WF DMA TOP: band 0(0x820E7000),band 1(0x820F7000) */
1067+#define MT_DBG_WF_DMA_BASE(_band) ((_band) ? 0x820F7000 : 0x820E7000)
1068+#define MT_DBG_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
1069+
1070+#define MT_DBG_DMA_DCR0(_band) MT_DBG_WF_DMA((_band), 0x000)
1071+#define MT_DBG_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
1072+#define MT_DBG_DMA_DCR0_RXD_G5_EN BIT(23)
1073+
1074+#define MT_DBG_DMA_ICSC_FR0(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR0))
1075+#define MT_DBG_DMA_ICSC_FR0_RXBF_EN BIT(25)
1076+#define MT_DBG_DMA_ICSC_FR0_EN BIT(24)
1077+#define MT_DBG_DMA_ICSC_FR0_TOUT_MASK GENMASK(23, 16)
1078+#define MT_DBG_DMA_ICSC_FR0_PID_MASK GENMASK(9, 8)
1079+#define MT_DBG_DMA_ICSC_FR0_QID_MASK GENMASK(6, 0)
1080+
1081+#define MT_DBG_DMA_ICSC_FR1(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR1))
1082+#define MT_DBG_DMA_ICSC_FR1_AGG_SIZE_MASK GENMASK(26, 16)
1083+#define MT_DBG_DMA_ICSC_FR1_MAX_FRAME_SIZE_MASK GENMASK(10, 0)
1084+
1085+/* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
1086+#define MT_DBG_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
1087+#define MT_DBG_WF_TMAC(_band, ofs) (MT_DBG_WF_TMAC_BASE(_band) + (ofs))
1088+
1089+#define MT_DBG_TMAC_ICSCR0(_band) MT_DBG_WF_TMAC((_band), __DBG_REG_OFFS(dev, DBG_TMAC_ICSCR0))
1090+#define MT_DBG_TMAC_ICSCR0_ICSRPT_EN BIT(0)
1091+
1092+/* RMAC: band 0(0x820E5000), band 1(0x820f5000) */
1093+#define MT_DBG_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820E5000)
1094+#define MT_DBG_WF_RMAC(_band, ofs) (MT_DBG_WF_RMAC_BASE(_band) + (ofs))
1095+
1096+#define MT_DBG_RMAC_RXICSRPT(_band) MT_DBG_WF_RMAC((_band), __DBG_REG_OFFS(dev, DBG_RMAC_RXICSRPT))
1097+#define MT_DBG_RMAC_RXICSRPT_ICSRPT_EN BIT(0)
1098+
1099+/* MIB: band 0(0x820ed000), band 1(0x820fd000) */
1100+#define MT_DBG_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
1101+#define MT_DBG_MIB(_band, ofs) (MT_DBG_MIB_BASE(_band) + (ofs))
1102+
1103+
1104+#define MT_DBG_MIB_M0SCR0(_band) MT_DBG_MIB((_band), 0x00)
1105+#define MT_DBG_MIB_M0PBSCR(_band) MT_DBG_MIB((_band), 0x04)
1106+
1107+#define MT_DBG_MIB_M0SDR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR0))
1108+#define MT_DBG_MIB_M0SDR3(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR3))
1109+#define MT_DBG_MIB_RX_FCS_ERROR_COUNT_MASK __DBG_MASK(dev, DBG_MIB_RX_FCS_ERROR_COUNT)
1110+#define MT_DBG_MIB_M0SDR4(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR4))
1111+#define MT_DBG_MIB_M0SDR5(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR5))
1112+#define MT_DBG_MIB_M0SDR6(_band) MT_DBG_MIB((_band), 0x20)
1113+#define MT_DBG_MIB_M0SDR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR7))
1114+#define MT_DBG_MIB_M0SDR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR8))
1115+#define MT_DBG_MIB_M0SDR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR9))
1116+#define MT_DBG_MIB_M0SDR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR10))
1117+#define MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK __DBG_MASK(dev, DBG_MIB_M0SDR10_RX_MDRDY_COUNT)
1118+#define MT_DBG_MIB_M0SDR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR11))
1119+
1120+#define MT_DBG_MIB_M0SDR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR12))
1121+
1122+#define MT_DBG_MIB_M0SDR14(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR14))
1123+#define MT_DBG_MIB_M0SDR14_AMPDU_MASK __DBG_MASK(dev, DBG_MIB_M0SDR14_AMPDU)
1124+#define MT_DBG_MIB_M0SDR15(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR15))
1125+#define MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK __DBG_MASK(dev, DBG_MIB_M0SDR15_AMPDU_ACKED)
1126+#define MT_DBG_MIB_M0SDR16(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR16))
1127+#define MT_DBG_MIB_M0SDR17(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR17))
1128+#define MT_DBG_MIB_M0SDR18(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR18))
1129+#define MT_DBG_MIB_M0SDR19(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR19))
1130+#define MT_DBG_MIB_M0SDR20(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR20))
1131+#define MT_DBG_MIB_M0SDR21(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR21))
1132+#define MT_DBG_MIB_M0SDR22(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR22))
1133+#define MT_DBG_MIB_M0SDR23(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR23))
1134+#define MT_DBG_MIB_M0DR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR0))
1135+#define MT_DBG_MIB_M0DR1(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR1))
1136+
1137+#define MT_DBG_MIB_MUBF(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_MUBF))
1138+#define MT_DBG_MIB_M0DR6(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR6))
1139+#define MT_DBG_MIB_M0DR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR7))
1140+#define MT_DBG_MIB_M0DR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR8))
1141+#define MT_DBG_MIB_M0DR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR9))
1142+#define MT_DBG_MIB_M0DR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR10))
1143+#define MT_DBG_MIB_M0DR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR11))
1144+ #define MT_DBG_MIB_M0DR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR12))
1145+
1146+/* WTBLON TOP: 0x820D4000/pcie(0x34000) rbus(0x434000) */
1147+#define MT_DBG_WTBLON_TOP_BASE 0x820D4000
1148+#define MT_DBG_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
1149+#define MT_DBG_WTBLON_TOP_WDUCR MT_DBG_WTBLON_TOP(__DBG_REG_OFFS(dev, DBG_WTBLON_WDUCR))
1150+#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
1151+
1152+#define WF_WTBLON_TOP_B0BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1000) // 5000
1153+#define WF_WTBLON_TOP_B0BTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1010) // 5010
1154+#define WF_WTBLON_TOP_B0BRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1020) // 5020
1155+#define WF_WTBLON_TOP_B0BRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1030) // 5030
1156+#define WF_WTBLON_TOP_B0BTDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1040) // 5040
1157+#define WF_WTBLON_TOP_B0BRDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1050) // 5050
1158+#define WF_WTBLON_TOP_B0MBTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1100) // 5100
1159+#define WF_WTBLON_TOP_B0MBTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1140) // 5140
1160+#define WF_WTBLON_TOP_B0MBRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1180) // 5180
1161+#define WF_WTBLON_TOP_B0MBRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x11C0) // 51C0
1162+
1163+#define WF_WTBLON_TOP_B1BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1800) // 5800
1164+
1165+/* WTBLON TOP: 0x820C4000/pcie(0xa8000) rbus(0x4a8000) */
1166+#define MT_DBG_UWTBL_TOP_BASE 0x820C4000
1167+#define MT_DBG_UWTBL_TOP(ofs) (MT_DBG_UWTBL_TOP_BASE + (ofs))
1168+
developerf1313102022-10-11 11:02:55 +08001169+#define MT_DBG_UWTBL_TOP_WDUCR MT_DBG_UWTBL_TOP(__DBG_REG_OFFS(dev, DBG_UWTBL_WDUCR))
developer3fa816c2022-04-19 10:21:20 +08001170+
1171+#define MT_UWTBL_TOP_WDUCR_TARGET BIT(31)
1172+#define MT_UWTBL_TOP_WDUCR_GROUP GENMASK(3, 0)
1173+
1174+
1175+/* WTBL : 0x820D8000/pcie(0x38000) rbus(0x438000) */
1176+#define MT_DBG_WTBL_BASE 0x820D8000
1177+
1178+/* PLE related CRs. */
1179+#define MT_DBG_PLE_BASE 0x820C0000
1180+#define MT_DBG_PLE(ofs) (MT_DBG_PLE_BASE + (ofs))
1181+
1182+#define MT_DBG_PLE_DRR_TAB_CTRL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_CTRL))
1183+#define MT_DBG_PLE_DRR_TAB_RD_OFS __DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_RDATA)
1184+
1185+#define MT_DBG_PLE_DRR_TABLE_RDATA0 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x0)
1186+#define MT_DBG_PLE_DRR_TABLE_RDATA1 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x4)
1187+#define MT_DBG_PLE_DRR_TABLE_RDATA2 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x8)
1188+#define MT_DBG_PLE_DRR_TABLE_RDATA3 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0xc)
1189+#define MT_DBG_PLE_DRR_TABLE_RDATA4 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x10)
1190+#define MT_DBG_PLE_DRR_TABLE_RDATA5 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x14)
1191+#define MT_DBG_PLE_DRR_TABLE_RDATA6 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x18)
1192+#define MT_DBG_PLE_DRR_TABLE_RDATA7 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS+ 0x1c)
1193+
1194+#define MT_DBG_PLE_PBUF_CTRL_ADDR MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PBUF_CTRL))
1195+#define MT_DBG_PLE_QUEUE_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_QUEUE_EMPTY))
1196+#define MT_DBG_PLE_FREEPG_CNT MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_CNT))
1197+#define MT_DBG_PLE_FREEPG_HEAD_TAIL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_HEAD_TAIL))
1198+#define MT_DBG_PLE_PG_HIF_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_GROUP))
1199+#define MT_DBG_PLE_HIF_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_PG_INFO))
1200+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_TXCMD_GROUP))
1201+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_TXCMD_PG_INFO))
1202+#define MT_DBG_PLE_PG_CPU_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_CPU_GROUP))
1203+#define MT_DBG_PLE_CPU_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_CPU_PG_INFO))
1204+#define PLE_FL_QUE_CTRL_OFFSET __DBG_REG_OFFS(dev, DBG_PLE_FL_QUE_CTRL)
1205+#define MT_DBG_PLE_FL_QUE_CTRL0 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x0)
1206+#define MT_DBG_PLE_FL_QUE_CTRL1 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x4)
1207+#define MT_DBG_PLE_FL_QUE_CTRL2 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x8)
1208+#define MT_DBG_PLE_FL_QUE_CTRL3 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0xc)
1209+#define MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_NATIVE_TXCMD_Q_EMPTY))
1210+#define MT_DBG_PLE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_TXCMD_Q_EMPTY))
1211+
1212+#define MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK BIT(31)
1213+#define MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK GENMASK(25, 17)
1214+#define MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1215+
1216+#define MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1217+#define MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1218+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1219+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1220+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK GENMASK(27, 16)
1221+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK GENMASK(11, 0)
1222+
1223+#define MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK GENMASK(27, 16)
1224+#define MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK GENMASK(11, 0)
1225+
1226+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK GENMASK(27, 16)
1227+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK GENMASK(11, 0)
1228+
1229+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
1230+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
1231+
1232+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
1233+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
1234+
1235+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1236+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1237+
1238+#define MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1239+#define MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1240+
1241+#define MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK BIT(24)
1242+#define MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK BIT(31)
1243+#define MT_DBG_PLE_FL_QUE_CTRL0_Q_BUF_QID_MASK GENMASK(30, 24)
1244+
1245+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT 24
1246+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT 10
1247+
1248+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK GENMASK(27, 16)
1249+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK GENMASK(11, 0)
1250+#define MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK GENMASK(11, 0)
1251+
1252+#define MT_DBG_PLE_STATION_PAUSE(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_STATION_PAUSE) + ((n) << 2))
1253+#define MT_DBG_PLE_DIS_STA_MAP(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DIS_STA_MAP) + ((n) << 2))
1254+#define MT_DBG_PLE_AC_QEMPTY(ac, n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_AC_QEMPTY) + \
1255+ __DBG_REG_OFFS(dev, DBG_PLE_AC_OFFSET) * (ac) + ((n) << 2))
1256+
1257+#define MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(n) MT_DBG_PLE(0x10e0 + ((n) << 2))
1258+
1259+/* pseinfo related CRs. */
1260+#define MT_DBG_PSE_BASE 0x820C8000
1261+#define MT_DBG_PSE(ofs) (MT_DBG_PSE_BASE + (ofs))
1262+
developerf32dabf2022-06-01 10:59:24 +08001263+#define MT_DBG_PSE_PBUF_CTRL MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PBUF_CTRL))
1264+#define MT_DBG_PSE_QUEUE_EMPTY MT_DBG_PSE(0x0b0)
1265+#define MT_DBG_PSE_FREEPG_CNT MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_CNT))
1266+#define MT_DBG_PSE_FREEPG_HEAD_TAIL MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_HEAD_TAIL))
1267+#define MT_DBG_PSE_PG_HIF0_GROUP MT_DBG_PSE(0x110)
1268+#define MT_DBG_PSE_HIF0_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_HIF0_PG_INFO))
1269+#define MT_DBG_PSE_PG_HIF1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_HIF1_GROUP))
1270+#define MT_DBG_PSE_HIF1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_HIF1_PG_INFO))
1271+#define MT_DBG_PSE_PG_CPU_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_CPU_GROUP))
1272+#define MT_DBG_PSE_CPU_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_CPU_PG_INFO))
1273+#define MT_DBG_PSE_PG_LMAC0_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC0_GROUP))
1274+#define MT_DBG_PSE_LMAC0_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC0_PG_INFO))
1275+#define MT_DBG_PSE_PG_LMAC1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC1_GROUP))
1276+#define MT_DBG_PSE_LMAC1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC1_PG_INFO))
1277+#define MT_DBG_PSE_PG_LMAC2_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC2_GROUP))
1278+#define MT_DBG_PSE_LMAC2_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC2_PG_INFO))
1279+#define MT_DBG_PSE_PG_PLE_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE_GROUP))
1280+#define MT_DBG_PSE_PLE_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PLE_PG_INFO))
1281+#define MT_DBG_PSE_PG_LMAC3_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC3_GROUP))
1282+#define MT_DBG_PSE_LMAC3_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC3_PG_INFO))
1283+#define MT_DBG_PSE_PG_MDP_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_MDP_GROUP))
1284+#define MT_DBG_PSE_MDP_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_MDP_PG_INFO))
1285+#define MT_DBG_PSE_PG_PLE1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE1_GROUP))
1286+#define MT_DBG_PSE_PLE1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PLE1_PG_INFO))
developer3fa816c2022-04-19 10:21:20 +08001287+
1288+#define MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK BIT(31)
1289+#define MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK GENMASK(25, 17)
1290+#define MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1291+#define MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK BIT(31)
1292+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK BIT(23)
1293+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK BIT(22)
1294+#define MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK BIT(21)
1295+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT BIT(20)
1296+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK BIT(19)
1297+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK BIT(18)
1298+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK BIT(17)
1299+#define MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK BIT(16)
1300+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK BIT(13)
1301+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK BIT(12)
1302+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK BIT(11)
1303+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK BIT(10)
1304+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK BIT(9)
1305+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK BIT(8)
1306+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK BIT(3)
1307+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK BIT(2)
1308+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK BIT(1)
1309+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK BIT(0)
1310+#define MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1311+#define MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1312+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1313+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1314+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1315+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1316+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1317+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1318+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK GENMASK(27, 16)
1319+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK GENMASK(11, 0)
1320+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK GENMASK(27, 16)
1321+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK GENMASK(11, 0)
1322+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK GENMASK(27, 16)
1323+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK GENMASK(11, 0)
1324+#define MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1325+#define MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1326+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK GENMASK(27, 16)
1327+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK GENMASK(11, 0)
1328+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1329+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1330+#define MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK GENMASK(27, 16)
1331+#define MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK GENMASK(11, 0)
1332+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK GENMASK(27, 16)
1333+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK GENMASK(11, 0)
1334+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK GENMASK(27, 16)
1335+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK GENMASK(11, 0)
1336+#define MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK GENMASK(27, 16)
1337+#define MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK GENMASK(11, 0)
1338+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK GENMASK(27, 16)
1339+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK GENMASK(11, 0)
1340+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK GENMASK(27, 16)
1341+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK GENMASK(11, 0)
1342+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK GENMASK(27, 16)
1343+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK GENMASK(11, 0)
1344+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1345+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1346+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK GENMASK(27, 16)
1347+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK GENMASK(11, 0)
1348+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1349+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1350+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK GENMASK(27, 16)
1351+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK GENMASK(11, 0)
1352+#define MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK GENMASK(27, 16)
1353+#define MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK GENMASK(11, 0)
1354+
1355+#define MT_DBG_PSE_FL_QUE_CTRL_0_ADDR MT_DBG_PLE(0x1b0)
1356+#define MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK BIT(31)
1357+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24
1358+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT 10
1359+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK GENMASK(9, 0)
1360+
1361+#define MT_DBG_PSE_FL_QUE_CTRL_2_ADDR MT_DBG_PLE(0x1b8)
1362+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK GENMASK(27, 16)
1363+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK GENMASK(11, 0)
1364+
1365+#define MT_DBG_PSE_FL_QUE_CTRL_3_ADDR MT_DBG_PLE(0x1bc)
1366+#define MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK GENMASK(11, 0)
1367+
1368+
1369+/* AGG */
1370+#define MT_DBG_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
1371+#define MT_DBG_AGG(_band, ofs) (MT_DBG_AGG_BASE(_band) + (ofs))
1372+
1373+#define MT_DBG_AGG_AALCR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR0))
1374+#define MT_DBG_AGG_AALCR1(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR1))
1375+#define MT_DBG_AGG_AALCR2(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR2))
1376+#define MT_DBG_AGG_AALCR3(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR3))
1377+#define MT_DBG_AGG_AALCR4(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR4))
1378+#define MT_DBG_AGG_B0BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B0BRR0))
1379+#define MT_DBG_AGG_B1BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B1BRR0))
1380+#define MT_DBG_AGG_B2BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B2BRR0))
1381+#define MT_DBG_AGG_B3BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B3BRR0))
1382+#define MT_DBG_AGG_AWSCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AWSCR0) + ((n) << 2))
1383+#define MT_DBG_AGG_PCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_PCR0) + ((n) << 2))
1384+#define MT_DBG_AGG_TTCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_TTCR0) + ((n) << 2))
1385+#define MT_DBG_MIB_M0ARNG(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0ARNG0) + ((n) << 2))
1386+#define MT_DBG_MIB_M0DR2(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR2) + ((n) << 2))
1387+#define MT_DBG_MIB_M0DR13(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR13) + ((n) << 2))
1388+
1389+#define MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK GENMASK(31, 24)
1390+#define MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK GENMASK(23, 16)
1391+#define MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK GENMASK(15, 8)
1392+#define MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK GENMASK(7, 0)
1393+#define MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK GENMASK(7, 0)
1394+
1395+#define MT_DBG_AGG_AWSCR0_WINSIZE3_MASK GENMASK(31, 24)
1396+#define MT_DBG_AGG_AWSCR0_WINSIZE2_MASK GENMASK(23, 16)
1397+#define MT_DBG_AGG_AWSCR0_WINSIZE1_MASK GENMASK(15, 8)
1398+#define MT_DBG_AGG_AWSCR0_WINSIZE0_MASK GENMASK(7, 0)
1399+
1400+#define MT_DBG_AGG_AWSCR1_WINSIZE7_MASK GENMASK(31, 24)
1401+#define MT_DBG_AGG_AWSCR1_WINSIZE6_MASK GENMASK(23, 16)
1402+#define MT_DBG_AGG_AWSCR1_WINSIZE5_MASK GENMASK(15, 8)
1403+#define MT_DBG_AGG_AWSCR1_WINSIZE4_MASK GENMASK(7, 0)
1404+
1405+#define MT_DBG_AGG_AWSCR2_WINSIZEB_MASK GENMASK(31, 24)
1406+#define MT_DBG_AGG_AWSCR2_WINSIZEA_MASK GENMASK(23, 16)
1407+#define MT_DBG_AGG_AWSCR2_WINSIZE9_MASK GENMASK(15, 8)
1408+#define MT_DBG_AGG_AWSCR2_WINSIZE8_MASK GENMASK(7, 0)
1409+
1410+#define MT_DBG_AGG_AWSCR3_WINSIZEE_MASK GENMASK(23, 16)
1411+#define MT_DBG_AGG_AWSCR3_WINSIZED_MASK GENMASK(15, 8)
1412+#define MT_DBG_AGG_AWSCR3_WINSIZEC_MASK GENMASK(7, 0)
1413+
1414+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK GENMASK(31, 24)
1415+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK GENMASK(23, 16)
1416+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK GENMASK(15, 8)
1417+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK GENMASK(7, 0)
1418+
1419+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK GENMASK(31, 24)
1420+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK GENMASK(23, 16)
1421+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK GENMASK(15, 8)
1422+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK GENMASK(7, 0)
1423+
1424+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK GENMASK(31, 24)
1425+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK GENMASK(23, 16)
1426+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK GENMASK(15, 8)
1427+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK GENMASK(7, 0)
1428+
1429+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK GENMASK(23, 16)
1430+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK GENMASK(15, 8)
1431+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK GENMASK(7, 0)
1432+
1433+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK GENMASK(31, 16)
1434+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK GENMASK(15, 0)
1435+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK GENMASK(31, 16)
1436+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK GENMASK(15, 0)
1437+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK GENMASK(31, 16)
1438+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK GENMASK(15, 0)
1439+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK GENMASK(31, 16)
1440+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK GENMASK(15, 0)
1441+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK GENMASK(31, 16)
1442+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK GENMASK(15, 0)
1443+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK GENMASK(31, 16)
1444+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK GENMASK(15, 0)
1445+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK GENMASK(31, 16)
1446+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK GENMASK(15, 0)
1447+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK GENMASK(31, 16)
1448+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK GENMASK(15, 0)
1449+
1450+/* mt7915 host DMA*/
1451+#define MT_DBG_INT_DMA1_R0_DONE BIT(0)
1452+#define MT_DBG_INT_DMA1_R1_DONE BIT(1)
1453+#define MT_DBG_INT_DMA1_R2_DONE BIT(2)
1454+
1455+#define MT_DBG_INT_DMA1_T16_DONE BIT(26)
1456+#define MT_DBG_INT_DMA1_T17_DONE BIT(27)
1457+#define MT_DBG_INT_DMA1_T18_DONE BIT(30)
1458+#define MT_DBG_INT_DMA1_T19_DONE BIT(31)
1459+#define MT_DBG_INT_DMA1_T20_DONE BIT(15)
1460+
1461+#define MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE BIT(16)
1462+#define MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE BIT(17)
1463+
1464+/* mt7986 host DMA */
1465+#define MT_DBG_INT_DMA0_R0_DONE BIT(0)
1466+#define MT_DBG_INT_DMA0_R1_DONE BIT(1)
1467+#define MT_DBG_INT_DMA0_R2_DONE BIT(2)
1468+#define MT_DBG_INT_DMA0_R3_DONE BIT(3)
1469+#define MT_DBG_INT_DMA0_R4_DONE BIT(22)
1470+#define MT_DBG_INT_DMA0_R5_DONE BIT(23)
1471+
1472+#define MT_DBG_INT_DMA0_T16_DONE BIT(26)
1473+#define MT_DBG_INT_DMA0_T17_DONE BIT(27)
1474+#define MT_DBG_INT_DMA0_T18_DONE BIT(30)
1475+#define MT_DBG_INT_DMA0_T19_DONE BIT(31)
1476+#define MT_DBG_INT_DMA0_T20_DONE BIT(25)
1477+
1478+/* MCU DMA */
1479+#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
1480+#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
1481+#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
1482+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
1483+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1484+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1485+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1486+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1487+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1488+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1489+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1490+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1491+
1492+#define WF_WFDMA_MCU_DMA1_BASE 0x55000000
1493+#define WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x200) // 0200
1494+#define WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0X204) // 0204
1495+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x208) // 0208
1496+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1497+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1498+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1499+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1500+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1501+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1502+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1503+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1504+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x300) // 0300
1505+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x310) // 0310
1506+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x320) // 0320
1507+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x500) // 0500
1508+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x510) // 0510
1509+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x520) // 0520
1510+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x530) // 0530
1511+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x540) // 0540
1512+
1513+#define WF_WFDMA_MCU_DMA1_PCIE1_BASE 0x59000000
1514+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x200) // 0200
1515+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0X204) // 0204
1516+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x208) // 0208
1517+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1518+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1519+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1520+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1521+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1522+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1523+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1524+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1525+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x320) // 0320
1526+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x530) // 0530
1527+
1528+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
1529+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
1530+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
1531+/* mt7986 add */
1532+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330
1533+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340
1534+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350
1535+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360
1536+
1537+
1538+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
1539+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
1540+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
1541+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
1542+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
1543+
1544+/* mt7986 add */
1545+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550
1546+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560
1547+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570
1548+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580
1549+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590
1550+
1551+/* MEM DMA */
1552+#define WF_WFDMA_MEM_DMA_BASE 0x58000000
1553+#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
1554+#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
1555+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
1556+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1557+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1558+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1559+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1560+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1561+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1562+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1563+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1564+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
1565+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
1566+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
1567+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
1568+
1569+enum resource_attr {
1570+ HIF_TX_DATA,
1571+ HIF_TX_CMD,
1572+ HIF_TX_CMD_WM, /* direct path to WMCPU, only exist for WFDMA arch with 2 CPU */
1573+ HIF_TX_FWDL,
1574+ HIF_RX_DATA,
1575+ HIF_RX_EVENT,
1576+ RING_ATTR_NUM
1577+};
1578+
1579+struct hif_pci_tx_ring_desc {
1580+ u32 hw_int_mask;
1581+ u16 ring_size;
1582+ enum resource_attr ring_attr;
1583+ u8 band_idx;
1584+ char *const ring_info;
1585+};
1586+
1587+struct hif_pci_rx_ring_desc {
1588+ u32 hw_desc_base;
1589+ u32 hw_int_mask;
1590+ u16 ring_size;
1591+ enum resource_attr ring_attr;
1592+ u16 max_rx_process_cnt;
1593+ u16 max_sw_read_idx_inc;
1594+ char *const ring_info;
developer79a21a22023-01-09 13:57:39 +08001595+ bool flags;
developer3fa816c2022-04-19 10:21:20 +08001596+};
1597+
1598+const struct hif_pci_tx_ring_desc mt7915_tx_ring_layout[] = {
1599+ {
1600+ .hw_int_mask = MT_DBG_INT_DMA1_T16_DONE,
1601+ .ring_size = 128,
1602+ .ring_attr = HIF_TX_FWDL,
1603+ .ring_info = "FWDL"
1604+ },
1605+ {
1606+ .hw_int_mask = MT_DBG_INT_DMA1_T17_DONE,
1607+ .ring_size = 256,
1608+ .ring_attr = HIF_TX_CMD_WM,
1609+ .ring_info = "cmd to WM"
1610+ },
1611+ {
1612+ .hw_int_mask = MT_DBG_INT_DMA1_T18_DONE,
1613+ .ring_size = 2048,
1614+ .ring_attr = HIF_TX_DATA,
1615+ .ring_info = "band0 TXD"
1616+ },
1617+ {
1618+ .hw_int_mask = MT_DBG_INT_DMA1_T19_DONE,
1619+ .ring_size = 2048,
1620+ .ring_attr = HIF_TX_DATA,
1621+ .ring_info = "band1 TXD"
1622+ },
1623+ {
1624+ .hw_int_mask = MT_DBG_INT_DMA1_T20_DONE,
1625+ .ring_size = 256,
1626+ .ring_attr = HIF_TX_CMD,
1627+ .ring_info = "cmd to WA"
1628+ }
1629+};
1630+
1631+const struct hif_pci_rx_ring_desc mt7915_rx_ring_layout[] = {
1632+ {
1633+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE,
1634+ .ring_size = 1536,
1635+ .ring_attr = HIF_RX_DATA,
1636+ .ring_info = "band0 RX data"
1637+ },
1638+ {
1639+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE,
1640+ .ring_size = 1536,
1641+ .ring_attr = HIF_RX_DATA,
1642+ .ring_info = "band1 RX data"
1643+ },
1644+ {
1645+ .hw_int_mask = MT_DBG_INT_DMA1_R0_DONE,
1646+ .ring_size = 512,
1647+ .ring_attr = HIF_RX_EVENT,
1648+ .ring_info = "event from WM"
1649+ },
1650+ {
1651+ .hw_int_mask = MT_DBG_INT_DMA1_R1_DONE,
1652+ .ring_size = 1024,
1653+ .ring_attr = HIF_RX_EVENT,
developer79a21a22023-01-09 13:57:39 +08001654+ .ring_info = "event from WA band0",
1655+ .flags = true
developer3fa816c2022-04-19 10:21:20 +08001656+ },
1657+ {
1658+ .hw_int_mask = MT_DBG_INT_DMA1_R2_DONE,
1659+ .ring_size = 512,
1660+ .ring_attr = HIF_RX_EVENT,
1661+ .ring_info = "event from WA band1"
1662+ }
1663+};
1664+
1665+const struct hif_pci_tx_ring_desc mt7986_tx_ring_layout[] = {
1666+ {
1667+ .hw_int_mask = MT_DBG_INT_DMA0_T16_DONE,
1668+ .ring_size = 128,
1669+ .ring_attr = HIF_TX_FWDL,
1670+ .ring_info = "FWDL"
1671+ },
1672+ {
1673+ .hw_int_mask = MT_DBG_INT_DMA0_T17_DONE,
1674+ .ring_size = 256,
1675+ .ring_attr = HIF_TX_CMD_WM,
1676+ .ring_info = "cmd to WM"
1677+ },
1678+ {
1679+ .hw_int_mask = MT_DBG_INT_DMA0_T18_DONE,
1680+ .ring_size = 2048,
1681+ .ring_attr = HIF_TX_DATA,
1682+ .ring_info = "band0 TXD"
1683+ },
1684+ {
1685+ .hw_int_mask = MT_DBG_INT_DMA0_T19_DONE,
1686+ .ring_size = 2048,
1687+ .ring_attr = HIF_TX_DATA,
1688+ .ring_info = "band1 TXD"
1689+ },
1690+ {
1691+ .hw_int_mask = MT_DBG_INT_DMA0_T20_DONE,
1692+ .ring_size = 256,
1693+ .ring_attr = HIF_TX_CMD,
1694+ .ring_info = "cmd to WA"
1695+ }
1696+};
1697+
1698+const struct hif_pci_rx_ring_desc mt7986_rx_ring_layout[] = {
1699+ {
1700+ .hw_int_mask = MT_DBG_INT_DMA0_R4_DONE,
1701+ .ring_size = 1536,
1702+ .ring_attr = HIF_RX_DATA,
1703+ .ring_info = "band0 RX data"
1704+ },
1705+ {
1706+ .hw_int_mask = MT_DBG_INT_DMA0_R5_DONE,
1707+ .ring_size = 1536,
1708+ .ring_attr = HIF_RX_DATA,
1709+ .ring_info = "band1 RX data"
1710+ },
1711+ {
1712+ .hw_int_mask = MT_DBG_INT_DMA0_R0_DONE,
1713+ .ring_size = 512,
1714+ .ring_attr = HIF_RX_EVENT,
1715+ .ring_info = "event from WM"
1716+ },
1717+ {
1718+ .hw_int_mask = MT_DBG_INT_DMA0_R1_DONE,
1719+ .ring_size = 512,
1720+ .ring_attr = HIF_RX_EVENT,
1721+ .ring_info = "event from WA"
1722+ },
1723+ {
1724+ .hw_int_mask = MT_DBG_INT_DMA0_R2_DONE,
1725+ .ring_size = 1024,
1726+ .ring_attr = HIF_RX_EVENT,
developer79a21a22023-01-09 13:57:39 +08001727+ .ring_info = "STS WA band0",
1728+ .flags = true
developer3fa816c2022-04-19 10:21:20 +08001729+ },
1730+ {
1731+ .hw_int_mask = MT_DBG_INT_DMA0_R3_DONE,
1732+ .ring_size = 512,
1733+ .ring_attr = HIF_RX_EVENT,
1734+ .ring_info = "STS WA band1"
1735+ },
1736+};
1737+
1738+/* mibinfo related CRs. */
1739+#define BN0_WF_MIB_TOP_BASE 0x820ed000
1740+#define BN1_WF_MIB_TOP_BASE 0x820fd000
1741+
1742+#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400
1743+#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x428) // D428
1744+#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x4F0) // D4F0
1745+
1746+#define BN0_WF_MIB_TOP_BSDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x688) // D688
1747+#define BN0_WF_MIB_TOP_BSDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x690) // D690
1748+
1749+#define BN0_WF_MIB_TOP_BSDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x518) // D518
1750+#define BN0_WF_MIB_TOP_BSDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x520) // D520
1751+#define BN0_WF_MIB_TOP_BSDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x528) // D528
1752+#define BN0_WF_MIB_TOP_BSDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x530) // D530
1753+#define BN0_WF_MIB_TOP_BSDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x538) // D538
1754+
1755+#define BN0_WF_MIB_TOP_BROCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5B8) // D5B8
1756+#define BN0_WF_MIB_TOP_BRBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0
1757+#define BN0_WF_MIB_TOP_BRDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x630) // D630
1758+
1759+#define BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK 0x0000FFFF // BEACONTXCOUNT[15..0]
1760+
1761+#define BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK 0x0000FFFF // RX_FIFO_FULL_COUNT[15..0]
1762+
1763+#define BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
1764+
1765+#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
1766+
1767+#define BN1_WF_MIB_TOP_BTOCR_ADDR (BN1_WF_MIB_TOP_BASE + 0x400) // D400
1768+
1769+#define BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK 0x0000FFFF // VEC_MISS_COUNT[15..0]
1770+#define BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK 0x0000FFFF // DELIMITER_FAIL_COUNT[15..0]
1771+#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
1772+
1773+#define BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK 0x0000FFFF // RX_LEN_MISMATCH[15..0]
1774+
1775+#define BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK 0x00FFFFFF // P_CCA_TIME[23..0]
1776+#define BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK 0x00FFFFFF // S_CCA_TIME[23..0]
1777+#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
1778+#define BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK 0x00FFFFFF // CCK_MDRDY_TIME[23..0]
1779+#define BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[23..0]
1780+#define BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_GREEN_MDRDY_TIME[23..0]
1781+
1782+#define BN0_WF_MIB_TOP_M0SDR22_ADDR (BN0_WF_MIB_TOP_BASE + 0x60) // D060
1783+#define BN0_WF_MIB_TOP_M0SDR23_ADDR (BN0_WF_MIB_TOP_BASE + 0x64) // D064
1784+
1785+#define BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK 0x0000FFFF // MUBF_TX_COUNT[15..0]
1786+
1787+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK 0xFFFF0000 // TX_40MHZ_CNT[31..16]
1788+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT 16
1789+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK 0x0000FFFF // TX_20MHZ_CNT[15..0]
1790+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_SHFT 0
1791+
1792+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK 0xFFFF0000 // TX_160MHZ_CNT[31..16]
1793+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT 16
1794+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK 0x0000FFFF // TX_80MHZ_CNT[15..0]
1795+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_SHFT 0
1796+
1797+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG2_CNT[31..16]
1798+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT 16
1799+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG1_CNT[15..0]
1800+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_SHFT 0
1801+
1802+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG4_CNT[31..16]
1803+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT 16
1804+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG3_CNT[15..0]
1805+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_SHFT 0
1806+
1807+#define BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK 0x0000FFFF // MU_FAIL_PPDU_CNT[15..0]
1808+
1809+#define BN0_WF_MIB_TOP_M0B0SDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x100) // D100
1810+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK 0xFFFF0000 // RTSRETRYCOUNT[31..16]
1811+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT 16
1812+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK 0x0000FFFF // RTSTXCOUNT[15..0]
1813+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_SHFT 0
1814+#define BN0_WF_MIB_TOP_M0B0SDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x104) // D104
1815+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK 0xFFFF0000 // ACKFAILCOUNT[31..16]
1816+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT 16
1817+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK 0x0000FFFF // BAMISSCOUNT[15..0]
1818+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_SHFT 0
1819+#define BN0_WF_MIB_TOP_M0B0SDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x108) // D108
1820+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK 0xFFFF0000 // FRAMERETRY2COUNT[31..16]
1821+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT 16
1822+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK 0x0000FFFF // FRAMERETRYCOUNT[15..0]
1823+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_SHFT 0
1824+#define BN0_WF_MIB_TOP_M0B0SDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x10C) // D10C
1825+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK 0x0000FFFF // FRAMERETRY3COUNT[15..0]
1826+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_SHFT 0
1827+#define BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG0_CNT[15..0]
1828+
1829+
1830+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK 0xFFFF0000 // TX_OK_COUNT2np1[31..16]
1831+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT 16
1832+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK 0x0000FFFF // TX_OK_COUNT2n[15..0]
1833+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT 0
1834+
1835+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK 0xFFFF0000 // TX_DATA_COUNT2np1[31..16]
1836+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT 16
1837+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK 0x0000FFFF // TX_DATA_COUNT2n[15..0]
1838+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT 0
1839+
1840+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK 0xFFFF0000 // RX_OK_COUNT2np1[31..16]
1841+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT 16
1842+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK 0x0000FFFF // RX_OK_COUNT2n[15..0]
1843+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT 0
1844+
1845+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK 0xFFFF0000 // RX_DATA_COUNT2np1[31..16]
1846+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT 16
1847+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK 0x0000FFFF // RX_DATA_COUNT2n[15..0]
1848+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT 0
1849+
1850+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK 0xFFFF0000 // RTSTXCOUNT2np1[31..16]
1851+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT 16
1852+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK 0x0000FFFF // RTSTXCOUNT2n[15..0]
1853+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT 0
1854+
1855+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK 0xFFFF0000 // RTSRETRYCOUNT2np1[31..16]
1856+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT 16
1857+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK 0x0000FFFF // RTSRETRYCOUNT2n[15..0]
1858+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT 0
1859+
1860+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK 0xFFFF0000 // BAMISSCOUNT2np1[31..16]
1861+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT 16
1862+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK 0x0000FFFF // BAMISSCOUNT2n[15..0]
1863+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT 0
1864+
1865+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK 0xFFFF0000 // ACKFAILCOUNT2np1[31..16]
1866+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT 16
1867+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK 0x0000FFFF // ACKFAILCOUNT2n[15..0]
1868+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT 0
1869+
1870+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK 0xFFFF0000 // FRAMERETRYCOUNT2np1[31..16]
1871+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT 16
1872+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK 0x0000FFFF // FRAMERETRYCOUNT2n[15..0]
1873+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT 0
1874+
1875+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY2COUNT2np1[31..16]
1876+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT 16
1877+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK 0x0000FFFF // FRAMERETRY2COUNT2n[15..0]
1878+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT 0
1879+
1880+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY3COUNT2np1[31..16]
1881+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT 16
1882+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK 0x0000FFFF // FRAMERETRY3COUNT2n[15..0]
1883+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT 0
1884+/* TXD */
1885+
1886+#define MT_TXD1_ETYP BIT(15)
1887+#define MT_TXD1_VLAN BIT(14)
1888+#define MT_TXD1_RMVL BIT(13)
1889+#define MT_TXD1_AMS BIT(13)
1890+#define MT_TXD1_EOSP BIT(12)
1891+#define MT_TXD1_MRD BIT(11)
1892+
1893+#define MT_TXD7_CTXD BIT(26)
1894+#define MT_TXD7_CTXD_CNT GENMASK(25, 23)
1895+#define MT_TXD7_TAT GENMASK(9, 0)
1896+
1897+#endif
1898+#endif
1899diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c
1900new file mode 100644
developerb0c86782023-10-27 15:40:47 +08001901index 00000000..d7bbc598
developer3fa816c2022-04-19 10:21:20 +08001902--- /dev/null
1903+++ b/mt7915/mtk_debugfs.c
developerdfb50982023-09-11 13:34:36 +08001904@@ -0,0 +1,3622 @@
developer3fa816c2022-04-19 10:21:20 +08001905+#include<linux/inet.h>
1906+#include "mt7915.h"
1907+#include "mt7915_debug.h"
1908+#include "mac.h"
1909+#include "mcu.h"
1910+
1911+#ifdef MTK_DEBUG
1912+#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
1913+#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
1914+#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \
1915+ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
1916+ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
1917+
1918+#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
1919+#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
1920+#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1921+ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
1922+ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
1923+
1924+#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
1925+#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
1926+#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1927+ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
1928+ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
1929+
1930+enum mt7915_wtbl_type {
1931+ WTBL_TYPE_LMAC, /* WTBL in LMAC */
1932+ WTBL_TYPE_UMAC, /* WTBL in UMAC */
1933+ WTBL_TYPE_KEY, /* Key Table */
1934+ MAX_NUM_WTBL_TYPE
1935+};
1936+
1937+static int mt7915_wtbl_read_raw(struct mt7915_dev *dev, u16 idx,
1938+ enum mt7915_wtbl_type type, u16 start_dw,
1939+ u16 len, void *buf)
1940+{
1941+ u32 *dest_cpy = (u32 *)buf;
1942+ u32 size_dw = len;
1943+ u32 src = 0;
1944+
1945+ if (!buf)
1946+ return 0xFF;
1947+
1948+ if (type == WTBL_TYPE_LMAC) {
1949+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1950+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1951+ src = LWTBL_IDX2BASE(idx, start_dw);
1952+ } else if (type == WTBL_TYPE_UMAC) {
1953+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1954+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1955+ src = UWTBL_IDX2BASE(idx, start_dw);
1956+ } else if (type == WTBL_TYPE_KEY) {
1957+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1958+ MT_UWTBL_TOP_WDUCR_TARGET |
1959+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1960+ src = KEYTBL_IDX2BASE(idx, start_dw);
1961+ }
1962+
1963+ while (size_dw--) {
1964+ *dest_cpy++ = mt76_rr(dev, src);
1965+ src += 4;
1966+ };
1967+
1968+ return 0;
1969+}
1970+
1971+static int mt7915_wtbl_write_raw(struct mt7915_dev *dev, u16 idx,
1972+ enum mt7915_wtbl_type type, u16 start_dw,
1973+ u32 val)
1974+{
1975+ u32 addr = 0;
1976+
1977+ if (type == WTBL_TYPE_LMAC) {
1978+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1979+ FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1980+ addr = LWTBL_IDX2BASE(idx, start_dw);
1981+ } else if (type == WTBL_TYPE_UMAC) {
1982+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1983+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1984+ addr = UWTBL_IDX2BASE(idx, start_dw);
1985+ } else if (type == WTBL_TYPE_KEY) {
1986+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1987+ MT_UWTBL_TOP_WDUCR_TARGET |
1988+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1989+ addr = KEYTBL_IDX2BASE(idx, start_dw);
1990+ }
1991+
1992+ mt76_wr(dev, addr, val);
1993+
1994+ return 0;
1995+}
1996+
1997+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len)
1998+{
1999+ struct bin_debug_hdr *hdr;
2000+ char *buf;
2001+
2002+ if (len > 1500 - sizeof(*hdr))
2003+ len = 1500 - sizeof(*hdr);
2004+
2005+ buf = kzalloc(sizeof(*hdr) + len, GFP_KERNEL);
2006+ if (!buf)
2007+ return;
2008+
2009+ hdr = (struct bin_debug_hdr *)buf;
2010+ hdr->magic_num = cpu_to_le32(PKT_BIN_DEBUG_MAGIC);
2011+ hdr->serial_id = cpu_to_le16(dev->dbg.fwlog_seq++);
2012+ hdr->msg_type = cpu_to_le16(type);
2013+ hdr->len = cpu_to_le16(len);
2014+ hdr->des_len = cpu_to_le16(des_len);
2015+
2016+ memcpy(buf + sizeof(*hdr), data, len);
2017+
2018+ mt7915_debugfs_rx_log(dev, buf, sizeof(*hdr) + len);
2019+}
2020+
2021+static int
2022+mt7915_fw_debug_module_set(void *data, u64 module)
2023+{
2024+ struct mt7915_dev *dev = data;
2025+
2026+ dev->dbg.fw_dbg_module = module;
2027+ return 0;
2028+}
2029+
2030+static int
2031+mt7915_fw_debug_module_get(void *data, u64 *module)
2032+{
2033+ struct mt7915_dev *dev = data;
2034+
2035+ *module = dev->dbg.fw_dbg_module;
2036+ return 0;
2037+}
2038+
2039+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, mt7915_fw_debug_module_get,
2040+ mt7915_fw_debug_module_set, "%lld\n");
2041+
2042+static int
2043+mt7915_fw_debug_level_set(void *data, u64 level)
2044+{
2045+ struct mt7915_dev *dev = data;
2046+
2047+ dev->dbg.fw_dbg_lv = level;
2048+ mt7915_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv);
2049+ return 0;
2050+}
2051+
2052+static int
2053+mt7915_fw_debug_level_get(void *data, u64 *level)
2054+{
2055+ struct mt7915_dev *dev = data;
2056+
2057+ *level = dev->dbg.fw_dbg_lv;
2058+ return 0;
2059+}
2060+
2061+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, mt7915_fw_debug_level_get,
2062+ mt7915_fw_debug_level_set, "%lld\n");
2063+
2064+#define MAX_TX_MODE 12
2065+static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT",
2066+ "N/A", "N/A", "N/A", "HE_SU", "HE_EXT_SU",
2067+ "HE_TRIG", "HE_MU", "N/A"};
2068+static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong",
2069+ "N/A", "2Mshort", "5.5Mshort", "11Mshort",
2070+ "N/A"};
2071+static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M",
2072+ "48M", "54M", "N/A"};
2073+static char *fcap_str[] = {"20MHz", "20/40MHz", "20/40/80MHz",
2074+ "20/40/80/160/80+80MHz"};
2075+
2076+static char *hw_rate_ofdm_str(u16 ofdm_idx)
2077+{
2078+ switch (ofdm_idx) {
2079+ case 11: /* 6M */
2080+ return HW_TX_RATE_OFDM_STR[0];
2081+
2082+ case 15: /* 9M */
2083+ return HW_TX_RATE_OFDM_STR[1];
2084+
2085+ case 10: /* 12M */
2086+ return HW_TX_RATE_OFDM_STR[2];
2087+
2088+ case 14: /* 18M */
2089+ return HW_TX_RATE_OFDM_STR[3];
2090+
2091+ case 9: /* 24M */
2092+ return HW_TX_RATE_OFDM_STR[4];
2093+
2094+ case 13: /* 36M */
2095+ return HW_TX_RATE_OFDM_STR[5];
2096+
2097+ case 8: /* 48M */
2098+ return HW_TX_RATE_OFDM_STR[6];
2099+
2100+ case 12: /* 54M */
2101+ return HW_TX_RATE_OFDM_STR[7];
2102+
2103+ default:
2104+ return HW_TX_RATE_OFDM_STR[8];
2105+ }
2106+}
2107+
2108+static char *hw_rate_str(u8 mode, u16 rate_idx)
2109+{
2110+ if (mode == 0)
2111+ return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8];
2112+ else if (mode == 1)
2113+ return hw_rate_ofdm_str(rate_idx);
2114+ else
2115+ return "MCS";
2116+}
2117+
2118+static void parse_rate(struct seq_file *s, u16 rate_idx, u16 txrate)
2119+{
2120+ u16 txmode, mcs, nss, stbc;
2121+
2122+ txmode = FIELD_GET(GENMASK(9, 6), txrate);
2123+ mcs = FIELD_GET(GENMASK(5, 0), txrate);
2124+ nss = FIELD_GET(GENMASK(12, 10), txrate);
2125+ stbc = FIELD_GET(BIT(13), txrate);
2126+
2127+ seq_printf(s, "\tRate%d(0x%x):TxMode=%d(%s), TxRate=%d(%s), Nsts=%d, STBC=%d\n",
2128+ rate_idx + 1, txrate,
2129+ txmode, (txmode < MAX_TX_MODE ? HW_TX_MODE_STR[txmode] : HW_TX_MODE_STR[MAX_TX_MODE]),
2130+ mcs, hw_rate_str(txmode, mcs), nss, stbc);
2131+}
2132+
2133+#define LWTBL_LEN_IN_DW 32
2134+#define UWTBL_LEN_IN_DW 8
2135+#define ONE_KEY_ENTRY_LEN_IN_DW 8
developerf32dabf2022-06-01 10:59:24 +08002136+static int mt7915_sta_info(struct seq_file *s, void *data)
2137+{
2138+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2139+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
2140+ u16 i = 0;
2141+
2142+ for (i=0; i < mt7915_wtbl_size(dev); i++) {
2143+ mt7915_wtbl_read_raw(dev, i, WTBL_TYPE_LMAC, 0,
2144+ LWTBL_LEN_IN_DW, lwtbl);
2145+ if (lwtbl[4] || lwtbl[5] || lwtbl[6] || lwtbl[7] || lwtbl[0] || lwtbl[1])
2146+ seq_printf(s, "wcid:%d\tAddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
2147+ i, lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
2148+ }
2149+
2150+ return 0;
2151+}
2152+
developer3fa816c2022-04-19 10:21:20 +08002153+static int mt7915_wtbl_read(struct seq_file *s, void *data)
2154+{
2155+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2156+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
2157+ int x;
2158+ u32 *addr = 0;
2159+ u32 dw_value = 0;
2160+
2161+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_LMAC, 0,
2162+ LWTBL_LEN_IN_DW, lwtbl);
2163+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
2164+ seq_printf(s, "LMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2165+ MT_DBG_WTBLON_TOP_WDUCR,
2166+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2167+ LWTBL_IDX2BASE(dev->wlan_idx, 0));
2168+ for (x = 0; x < LWTBL_LEN_IN_DW; x++) {
2169+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2170+ x,
2171+ lwtbl[x * 4 + 3],
2172+ lwtbl[x * 4 + 2],
2173+ lwtbl[x * 4 + 1],
2174+ lwtbl[x * 4]);
2175+ }
2176+
2177+ seq_printf(s, "\n\tAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
2178+ lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
2179+
2180+ // DW0, DW1
2181+ seq_printf(s, "LWTBL DW 0/1\n\t");
2182+ addr = (u32 *)&(lwtbl[0]);
2183+ dw_value = *addr;
2184+ seq_printf(s, "MUAR_IDX:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
2185+ seq_printf(s, "RCA1:%ld/ ", FIELD_GET(BIT(22), dw_value));
2186+ seq_printf(s, "KID:%lu/ ", FIELD_GET(GENMASK(24, 23), dw_value));
2187+ seq_printf(s, "RCID:%ld/ ", FIELD_GET(BIT(25), dw_value));
2188+ seq_printf(s, "FROM_DS:%ld\n\t", FIELD_GET(BIT(26), dw_value));
2189+ seq_printf(s, "TO_DS:%ld/ ", FIELD_GET(BIT(27), dw_value));
2190+ seq_printf(s, "RV:%ld/ ", FIELD_GET(BIT(28), dw_value));
2191+ seq_printf(s, "RCA2:%ld/ ", FIELD_GET(BIT(29), dw_value));
2192+ seq_printf(s, "WPI_FLAG:%ld\n", FIELD_GET(BIT(30), dw_value));
2193+
2194+ // DW2
2195+ seq_printf(s, "LWTBL DW 2\n\t");
2196+ addr = (u32 *)&(lwtbl[2*4]);
2197+ dw_value = *addr;
2198+ seq_printf(s, "AID12:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
2199+ seq_printf(s, "SU:%ld/ ", FIELD_GET(BIT(12), dw_value));
2200+ seq_printf(s, "SPP_EN:%ld/ ", FIELD_GET(BIT(13), dw_value));
2201+ seq_printf(s, "WPI_EVEN:%ld\n\t",FIELD_GET(BIT(14), dw_value));
2202+ seq_printf(s, "CIPHER:%lu/ ", FIELD_GET(GENMASK(20, 16), dw_value));
2203+ seq_printf(s, "CIPHER_IGTK:%lu/ ",FIELD_GET(GENMASK(22, 21), dw_value));
2204+ seq_printf(s, "AAD_OM:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2205+ seq_printf(s, "SW:%ld/ ", FIELD_GET(BIT(24), dw_value));
2206+ seq_printf(s, "UL:%ld/ ", FIELD_GET(BIT(25), dw_value));
2207+ seq_printf(s, "TX_POWER_SAVE:%ld\n\t", FIELD_GET(BIT(26), dw_value));
2208+ seq_printf(s, "QOS:%ld/ ", FIELD_GET(BIT(27), dw_value));
2209+ seq_printf(s, "HT:%ld/ ", FIELD_GET(BIT(28), dw_value));
2210+ seq_printf(s, "VHT:%ld/ ", FIELD_GET(BIT(29), dw_value));
2211+ seq_printf(s, "HE:%ld/ ", FIELD_GET(BIT(30), dw_value));
2212+ seq_printf(s, "MESH:%ld\n", FIELD_GET(BIT(31), dw_value));
2213+
2214+ // DW3
2215+ seq_printf(s, "LWTBL DW 3\n\t");
2216+ addr = (u32 *)&(lwtbl[3*4]);
2217+ dw_value = *addr;
2218+ seq_printf(s, "WMM_Q:%lu/ ", FIELD_GET(GENMASK(1, 0), dw_value));
2219+ seq_printf(s, "RXD_DUP_MODE:%lu\n\t", FIELD_GET(GENMASK(3, 2), dw_value));
2220+ seq_printf(s, "VLAN2ETH:%ld/ ", FIELD_GET(BIT(4), dw_value));
2221+ seq_printf(s, "BEAM_CHG:%ld/ ", FIELD_GET(BIT(5), dw_value));
2222+ seq_printf(s, "DIS_BA256:%ld\n\t", FIELD_GET(BIT(6), dw_value));
2223+ seq_printf(s, "PFMU_IDX:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2224+ seq_printf(s, "ULPF_IDX:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
2225+ seq_printf(s, "RIBF:%ld/ ", FIELD_GET(BIT(24), dw_value));
2226+ seq_printf(s, "ULPF:%ld\n\t", FIELD_GET(BIT(25), dw_value));
2227+ seq_printf(s, "IGN_FBK:%ld/ ", FIELD_GET(BIT(26), dw_value));
2228+ seq_printf(s, "TBF:%ld/ ", FIELD_GET(BIT(29), dw_value));
2229+ seq_printf(s, "TBF_VHT:%ld/ ", FIELD_GET(BIT(30), dw_value));
2230+ seq_printf(s, "TBF_HE:%ld\n", FIELD_GET(BIT(31), dw_value));
2231+
2232+ // DW4
2233+ seq_printf(s, "LWTBL DW 4\n\t");
2234+ addr = (u32 *)&(lwtbl[4*4]);
2235+ dw_value = *addr;
2236+ seq_printf(s, "ANT_ID_STS0:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2237+ seq_printf(s, "STS1:%lu/ ", FIELD_GET(GENMASK(5, 3), dw_value));
2238+ seq_printf(s, "STS2:%lu/ ", FIELD_GET(GENMASK(8, 6), dw_value));
2239+ seq_printf(s, "STS3:%lu\n\t", FIELD_GET(GENMASK(11, 9), dw_value));
2240+ seq_printf(s, "ANT_ID_STS4:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
2241+ seq_printf(s, "STS5:%lu/ ", FIELD_GET(GENMASK(17, 15), dw_value));
2242+ seq_printf(s, "STS6:%ld/ ", FIELD_GET(GENMASK(20, 18), dw_value));
2243+ seq_printf(s, "STS7:%lu\n\t", FIELD_GET(GENMASK(23, 21), dw_value));
2244+ seq_printf(s, "CASCAD:%ld/ ", FIELD_GET(BIT(24), dw_value));
2245+ seq_printf(s, "LDPC_HT:%ld/ ", FIELD_GET(BIT(25), dw_value));
2246+ seq_printf(s, "LDPC_VHT:%ld/ ", FIELD_GET(BIT(26), dw_value));
2247+ seq_printf(s, "LDPC_HE:%ld\n\t", FIELD_GET(BIT(27), dw_value));
2248+ seq_printf(s, "DIS_RHTR:%ld/ ", FIELD_GET(BIT(28), dw_value));
2249+ seq_printf(s, "ALL_ACK:%ld/ ", FIELD_GET(BIT(29), dw_value));
2250+ seq_printf(s, "DROP:%ld/ ", FIELD_GET(BIT(30), dw_value));
2251+ seq_printf(s, "ACK_EN:%ld\n", FIELD_GET(BIT(31), dw_value));
2252+
2253+ // DW5
2254+ seq_printf(s, "LWTBL DW 5\n\t");
2255+ addr = (u32 *)&(lwtbl[5*4]);
2256+ dw_value = *addr;
2257+ seq_printf(s, "AF:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2258+ seq_printf(s, "AF_HE:%lu/ ", FIELD_GET(GENMASK(4, 3), dw_value));
2259+ seq_printf(s, "RTS:%ld/ ", FIELD_GET(BIT(5), dw_value));
2260+ seq_printf(s, "SMPS:%ld/ ", FIELD_GET(BIT(6), dw_value));
2261+ seq_printf(s, "DYN_BW:%ld\n\t", FIELD_GET(BIT(7), dw_value));
2262+ seq_printf(s, "MMSS:%lu/ ", FIELD_GET(GENMASK(10, 8), dw_value));
2263+ seq_printf(s, "USR:%ld/ ", FIELD_GET(BIT(11), dw_value));
2264+ seq_printf(s, "SR_RATE:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
2265+ seq_printf(s, "SR_ABORT:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2266+ seq_printf(s, "TX_POWER_OFFSET:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
2267+ seq_printf(s, "WTBL_MPDU_SIZE:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
2268+ seq_printf(s, "PE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
2269+ seq_printf(s, "DOPPL:%ld/ ", FIELD_GET(BIT(26), dw_value));
2270+ seq_printf(s, "TXOP_PS_CAP:%ld/ ", FIELD_GET(BIT(27), dw_value));
2271+ seq_printf(s, "DONOT_UPDATE_I_PSM:%ld\n\t", FIELD_GET(BIT(28), dw_value));
2272+ seq_printf(s, "I_PSM:%ld/ ", FIELD_GET(BIT(29), dw_value));
2273+ seq_printf(s, "PSM:%ld/ ", FIELD_GET(BIT(30), dw_value));
2274+ seq_printf(s, "SKIP_TX:%ld\n", FIELD_GET(BIT(31), dw_value));
2275+
2276+ // DW6
2277+ seq_printf(s, "LWTBL DW 6\n\t");
2278+ seq_printf(s, "TID 0/1/2/3/4/5/6/7 BA_WIN_SIZE:");
2279+ addr = (u32 *)&(lwtbl[6*4]);
2280+ dw_value = *addr;
2281+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(3, 0), dw_value));
2282+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(7, 4), dw_value));
2283+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(11, 8), dw_value));
2284+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(15, 12), dw_value));
2285+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(19, 16), dw_value));
2286+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(23, 20), dw_value));
2287+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(27, 24), dw_value));
2288+ seq_printf(s, "%lu\n", FIELD_GET(GENMASK(31, 28), dw_value));
2289+
2290+ // DW7
2291+ seq_printf(s, "LWTBL DW 7\n\t");
2292+ addr = (u32 *)&(lwtbl[7*4]);
2293+ dw_value = *addr;
2294+ seq_printf(s, "CBRN:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2295+ seq_printf(s, "DBNSS_EN:%ld/ ", FIELD_GET(BIT(3), dw_value));
2296+ seq_printf(s, "BAF_EN:%ld/ ", FIELD_GET(BIT(4), dw_value));
2297+ seq_printf(s, "RDGBA:%ld\n\t", FIELD_GET(BIT(5), dw_value));
2298+ seq_printf(s, "RDG:%ld/ ", FIELD_GET(BIT(6), dw_value));
2299+ seq_printf(s, "SPE_IDX:%lu/ ", FIELD_GET(GENMASK(11, 7), dw_value));
2300+ seq_printf(s, "G2:%ld/ ", FIELD_GET(BIT(12), dw_value));
2301+ seq_printf(s, "G4:%ld/ ", FIELD_GET(BIT(13), dw_value));
2302+ seq_printf(s, "G8:%ld/ ", FIELD_GET(BIT(14), dw_value));
2303+ seq_printf(s, "G16:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2304+ seq_printf(s, "G2_LTF:%lu/ ", FIELD_GET(GENMASK(17, 16), dw_value));
2305+ seq_printf(s, "G4_LTF:%lu/ ", FIELD_GET(GENMASK(19, 18), dw_value));
2306+ seq_printf(s, "G8_LTF:%lu/ ", FIELD_GET(GENMASK(21, 20), dw_value));
2307+ seq_printf(s, "G16_LTF:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
2308+ seq_printf(s, "G2_HE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
2309+ seq_printf(s, "G4_HE:%lu/ ", FIELD_GET(GENMASK(27, 27), dw_value));
2310+ seq_printf(s, "G8_HE:%lu/ ", FIELD_GET(GENMASK(29, 28), dw_value));
2311+ seq_printf(s, "G16_HE:%lu\n", FIELD_GET(GENMASK(31, 30), dw_value));
2312+
2313+ // DW8
2314+ seq_printf(s, "LWTBL DW 8\n\t");
2315+ addr = (u32 *)&(lwtbl[8*4]);
2316+ dw_value = *addr;
2317+ seq_printf(s, "FAIL_CNT_AC0:%lu/ ", FIELD_GET(GENMASK(4, 0), dw_value));
2318+ seq_printf(s, "AC1:%lu/ ", FIELD_GET(GENMASK(9, 5), dw_value));
2319+ seq_printf(s, "AC2:%lu/ ", FIELD_GET(GENMASK(14, 10), dw_value));
2320+ seq_printf(s, "AC3:%lu\n\t", FIELD_GET(GENMASK(19, 15), dw_value));
2321+ seq_printf(s, "PARTIAL_AID:%lu/ ", FIELD_GET(GENMASK(28, 20), dw_value));
2322+ seq_printf(s, "CHK_PER:%lu\n", FIELD_GET(BIT(31), dw_value));
2323+
2324+ // DW9
2325+ seq_printf(s, "LWTBL DW 9\n\t");
2326+ addr = (u32 *)&(lwtbl[9*4]);
2327+ dw_value = *addr;
2328+ seq_printf(s, "RX_AVG_MPDU:%lu/ ", FIELD_GET(GENMASK(13, 0), dw_value));
2329+ seq_printf(s, "PRITX_SW_MODE:%ld/ ", FIELD_GET(BIT(16), dw_value));
2330+ seq_printf(s, "PRITX_PLR:%ld\n\t", FIELD_GET(BIT(17), dw_value));
2331+ seq_printf(s, "PRITX_DCM:%ld/ ", FIELD_GET(BIT(18), dw_value));
2332+ seq_printf(s, "PRITX_ER160:%ld/ ", FIELD_GET(BIT(19), dw_value));
2333+ seq_printf(s, "PRITX_ERSU:%lu\n\t", FIELD_GET(BIT(20), dw_value));
2334+ seq_printf(s, "MPDU_FAIL_CNT:%lu/ ", FIELD_GET(GENMASK(25, 23), dw_value));
2335+ seq_printf(s, "MPDU_OK_CNT:%lu/ ", FIELD_GET(GENMASK(28, 26), dw_value));
2336+ seq_printf(s, "RATE_IDX:%lu\n\t", FIELD_GET(GENMASK(31, 29), dw_value));
2337+ seq_printf(s, "FCAP:%s\n", fcap_str[FIELD_GET(GENMASK(22, 21), dw_value)]);
2338+
2339+ // DW10
2340+ seq_printf(s, "LWTBL DW 10\n");
2341+ addr = (u32 *)&(lwtbl[10*4]);
2342+ dw_value = *addr;
2343+ parse_rate(s, 0, FIELD_GET(GENMASK(13, 0), dw_value));
2344+ parse_rate(s, 1, FIELD_GET(GENMASK(29, 16), dw_value));
2345+ // DW11
2346+ seq_printf(s, "LWTBL DW 11\n");
2347+ addr = (u32 *)&(lwtbl[11*4]);
2348+ dw_value = *addr;
2349+ parse_rate(s, 2, FIELD_GET(GENMASK(13, 0), dw_value));
2350+ parse_rate(s, 3, FIELD_GET(GENMASK(29, 16), dw_value));
2351+ // DW12
2352+ seq_printf(s, "LWTBL DW 12\n");
2353+ addr = (u32 *)&(lwtbl[12*4]);
2354+ dw_value = *addr;
2355+ parse_rate(s, 4, FIELD_GET(GENMASK(13, 0), dw_value));
2356+ parse_rate(s, 5, FIELD_GET(GENMASK(29, 16), dw_value));
2357+ // DW13
2358+ seq_printf(s, "LWTBL DW 13\n");
2359+ addr = (u32 *)&(lwtbl[13*4]);
2360+ dw_value = *addr;
2361+ parse_rate(s, 6, FIELD_GET(GENMASK(13, 0), dw_value));
2362+ parse_rate(s, 7, FIELD_GET(GENMASK(29, 16), dw_value));
2363+
2364+ //DW28
2365+ seq_printf(s, "LWTBL DW 28\n\t");
2366+ addr = (u32 *)&(lwtbl[28*4]);
2367+ dw_value = *addr;
2368+ seq_printf(s, "OM_INFO:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
2369+ seq_printf(s, "OM_RXD_DUP_MODE:%u\n\t", !!(dw_value & BIT(12)) );
2370+
2371+ //DW29
2372+ seq_printf(s, "LWTBL DW 29\n");
2373+ addr = (u32 *)&(lwtbl[29*4]);
2374+ dw_value = *addr;
2375+ seq_printf(s, "USER_RSSI:%lu/ ", FIELD_GET(GENMASK(8, 0), dw_value));
2376+ seq_printf(s, "USER_SNR:%lu/ ", FIELD_GET(GENMASK(14, 9), dw_value));
2377+ seq_printf(s, "RAPID_REACTION_RATE:%lu/ ", FIELD_GET(GENMASK(26, 16), dw_value));
2378+ seq_printf(s, "HT_AMSDU(Read Only):%u/ ", !!(dw_value & BIT(30)) );
2379+ seq_printf(s, "AMSDU_CROSS_LG(Read Only):%u\n\t ", !!(dw_value & BIT(31)));
2380+
2381+ //DW30
2382+ seq_printf(s, "LWTBL DW 30\n\t");
2383+ addr = (u32 *)&(lwtbl[30*4]);
2384+ dw_value = *addr;
2385+ seq_printf(s, "RCPI 0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2386+ seq_printf(s, "RCPI 1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2387+ seq_printf(s, "RCPI 2:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
2388+ seq_printf(s, "RCPI 3:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
2389+
2390+ //DW31
2391+ seq_printf(s, "LWTBL DW 31\n\t");
2392+ addr = (u32 *)&(lwtbl[31*4]);
2393+ dw_value = *addr;
2394+ seq_printf(s, "RCPI 4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2395+ seq_printf(s, "RCPI 5:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2396+ seq_printf(s, "RCPI 6:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
2397+ seq_printf(s, "RCPI 7:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
2398+
2399+ return 0;
2400+}
2401+
2402+static int mt7915_uwtbl_read(struct seq_file *s, void *data)
2403+{
2404+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2405+ u8 uwtbl[UWTBL_LEN_IN_DW * 4] = {0};
2406+ u8 keytbl[ONE_KEY_ENTRY_LEN_IN_DW*4] = {0};
2407+ int x;
2408+ u32 *addr = 0;
2409+ u32 dw_value = 0;
2410+ u32 amsdu_len = 0;
2411+ u32 u2SN = 0;
2412+ u16 keyloc0, keyloc1;
2413+
2414+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC, 0,
2415+ UWTBL_LEN_IN_DW, uwtbl);
2416+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
2417+ seq_printf(s, "UMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
developerb8853042023-02-17 11:50:45 +08002418+ MT_DBG_UWTBL_TOP_WDUCR,
2419+ mt76_rr(dev, MT_DBG_UWTBL_TOP_BASE),
developer3fa816c2022-04-19 10:21:20 +08002420+ UWTBL_IDX2BASE(dev->wlan_idx, 0));
2421+ for (x = 0; x < UWTBL_LEN_IN_DW; x++) {
2422+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2423+ x,
2424+ uwtbl[x * 4 + 3],
2425+ uwtbl[x * 4 + 2],
2426+ uwtbl[x * 4 + 1],
2427+ uwtbl[x * 4]);
2428+ }
2429+
2430+ /* UMAC WTBL DW 0 */
2431+ seq_printf(s, "\nUWTBL PN\n\t");
2432+ addr = (u32 *)&(uwtbl[0]);
2433+ dw_value = *addr;
2434+ seq_printf(s, "PN0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2435+ seq_printf(s, "PN1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2436+ seq_printf(s, "PN2:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
2437+ seq_printf(s, "PN3:%lu/ ", FIELD_GET(GENMASK(31, 24), dw_value));
2438+
2439+ addr = (u32 *)&(uwtbl[1 * 4]);
2440+ dw_value = *addr;
2441+ seq_printf(s, "PN4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2442+ seq_printf(s, "PN5:%lu\n", FIELD_GET(GENMASK(15, 8), dw_value));
2443+
2444+ /* UMAC WTBL DW SN part */
2445+ seq_printf(s, "\nUWTBL SN\n");
2446+ addr = (u32 *)&(uwtbl[2 * 4]);
2447+ dw_value = *addr;
2448+ seq_printf(s, "TID0_AC0_SN:%lu\n", FIELD_GET(GENMASK(11, 0), dw_value));
2449+ seq_printf(s, "TID1_AC1_SN:%lu\n", FIELD_GET(GENMASK(23, 12), dw_value));
2450+
2451+ u2SN = FIELD_GET(GENMASK(31, 24), dw_value);
2452+ addr = (u32 *)&(uwtbl[3 * 4]);
2453+ dw_value = *addr;
2454+ u2SN |= FIELD_GET(GENMASK(3, 0), dw_value);
2455+ seq_printf(s, "TID2_AC2_SN:%u\n", u2SN);
2456+ seq_printf(s, "TID3_AC3_SN:%lu\n", FIELD_GET(GENMASK(15, 4), dw_value));
2457+ seq_printf(s, "TID4_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
2458+
2459+ u2SN = FIELD_GET(GENMASK(31, 28), dw_value);
2460+ addr = (u32 *)&(uwtbl[4 * 4]);
2461+ dw_value = *addr;
2462+ u2SN |= FIELD_GET(GENMASK(7, 0), dw_value);
2463+ seq_printf(s, "TID5_SN:%u\n", u2SN);
2464+ seq_printf(s, "TID6_SN:%lu\n", FIELD_GET(GENMASK(19, 8), dw_value));
2465+ seq_printf(s, "TID7_SN:%lu\n", FIELD_GET(GENMASK(31, 20), dw_value));
2466+
2467+ addr = (u32 *)&(uwtbl[1 * 4]);
2468+ dw_value = *addr;
2469+ seq_printf(s, "COM_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
2470+
2471+ /* UMAC WTBL DW 0 */
2472+ seq_printf(s, "\nUWTBL others\n");
2473+
2474+ addr = (u32 *)&(uwtbl[5 * 4]);
2475+ dw_value = *addr;
2476+ keyloc0 = FIELD_GET(GENMASK(10, 0), dw_value);
2477+ keyloc1 = FIELD_GET(GENMASK(26, 16), dw_value);
2478+ seq_printf(s, "\tKey Loc 1/2:%lu/%lu\n",
2479+ FIELD_GET(GENMASK(10, 0), dw_value),
2480+ FIELD_GET(GENMASK(26, 16), dw_value));
2481+ seq_printf(s, "\tUWTBL_QOS:%lu\n", FIELD_GET(BIT(27), dw_value));
2482+ seq_printf(s, "\tUWTBL_HT_VHT_HE:%lu\n", FIELD_GET(BIT(28), dw_value));
2483+
2484+ addr = (u32 *)&(uwtbl[6*4]);
2485+ dw_value = *addr;
2486+ seq_printf(s, "\tHW AMSDU Enable:%lu\n", FIELD_GET(BIT(9), dw_value));
2487+
2488+ amsdu_len = FIELD_GET(GENMASK(5, 0), dw_value);
2489+ if (amsdu_len == 0)
2490+ seq_printf(s, "\tHW AMSDU Len:invalid (WTBL value=0x%x)\n", amsdu_len);
2491+ else if (amsdu_len == 1)
2492+ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
2493+ 1,
2494+ 255,
2495+ amsdu_len);
2496+ else
2497+ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
2498+ 256 * (amsdu_len - 1),
2499+ 256 * (amsdu_len - 1) + 255,
2500+ amsdu_len
2501+ );
2502+ seq_printf(s, "\tHW AMSDU Num:%lu (WTBL value=0x%lx)\n",
2503+ FIELD_GET(GENMASK(8, 6), dw_value) + 1,
2504+ FIELD_GET(GENMASK(8, 6), dw_value));
2505+
2506+ /* Parse KEY link */
2507+ seq_printf(s, "\n\tkeyloc0:%d\n", keyloc0);
2508+ if(keyloc0 != GENMASK(10, 0)) {
2509+ mt7915_wtbl_read_raw(dev, keyloc0, WTBL_TYPE_KEY,
2510+ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
2511+ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
developerb8853042023-02-17 11:50:45 +08002512+ MT_DBG_UWTBL_TOP_WDUCR,
2513+ mt76_rr(dev, MT_DBG_UWTBL_TOP_BASE),
developer3fa816c2022-04-19 10:21:20 +08002514+ KEYTBL_IDX2BASE(keyloc0, 0));
2515+
2516+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
2517+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2518+ x,
2519+ keytbl[x * 4 + 3],
2520+ keytbl[x * 4 + 2],
2521+ keytbl[x * 4 + 1],
2522+ keytbl[x * 4]);
2523+ }
2524+ }
2525+
2526+ seq_printf(s, "\n\tkeyloc1:%d\n", keyloc1);
2527+ if(keyloc1 != GENMASK(26, 16)) {
2528+ mt7915_wtbl_read_raw(dev, keyloc1, WTBL_TYPE_KEY,
2529+ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
2530+ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
developerb8853042023-02-17 11:50:45 +08002531+ MT_DBG_UWTBL_TOP_WDUCR,
2532+ mt76_rr(dev, MT_DBG_UWTBL_TOP_BASE),
developer3fa816c2022-04-19 10:21:20 +08002533+ KEYTBL_IDX2BASE(keyloc1, 0));
2534+
2535+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
2536+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2537+ x,
2538+ keytbl[x * 4 + 3],
2539+ keytbl[x * 4 + 2],
2540+ keytbl[x * 4 + 1],
2541+ keytbl[x * 4]);
2542+ }
2543+ }
2544+ return 0;
2545+}
2546+
2547+static void
2548+dump_dma_tx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
2549+{
2550+ u32 base, cnt, cidx, didx, queue_cnt;
2551+
2552+ base= mt76_rr(dev, ring_base);
2553+ cnt = mt76_rr(dev, ring_base + 4);
2554+ cidx = mt76_rr(dev, ring_base + 8);
2555+ didx = mt76_rr(dev, ring_base + 12);
2556+ queue_cnt = (cidx >= didx) ? (cidx - didx) : (cidx - didx + cnt);
2557+
2558+ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
2559+}
2560+
2561+static void
2562+dump_dma_rx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
2563+{
2564+ u32 base, cnt, cidx, didx, queue_cnt;
2565+
2566+ base= mt76_rr(dev, ring_base);
2567+ cnt = mt76_rr(dev, ring_base + 4);
2568+ cidx = mt76_rr(dev, ring_base + 8);
2569+ didx = mt76_rr(dev, ring_base + 12);
2570+ queue_cnt = (didx > cidx) ? (didx - cidx - 1) : (didx - cidx + cnt - 1);
2571+
2572+ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
2573+}
2574+
2575+static void
2576+mt7915_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2577+{
2578+ u32 sys_ctrl[10] = {};
2579+
2580+ /* HOST DMA */
2581+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
2582+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
2583+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
2584+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
2585+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_INT_SOURCE_CSR);
2586+ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_INT_MASK_CSR);
2587+ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
2588+ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_GLO_CFG);
2589+ seq_printf(s, "HOST_DMA Configuration\n");
2590+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2591+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2592+ seq_printf(s, "%10s %10x %10x\n",
2593+ "Merge", sys_ctrl[0], sys_ctrl[1]);
2594+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2595+ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
2596+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
2597+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
2598+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
2599+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
2600+
2601+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2602+ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
2603+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
2604+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
2605+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[7]),
2606+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[7]));
2607+
2608+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT1_SOURCE_CSR);
2609+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT1_MASK_CSR);
2610+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR);
2611+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR);
2612+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR);
2613+ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR);
2614+ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_GLO_CFG);
2615+ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_GLO_CFG);
2616+ seq_printf(s, "%10s %10x %10x\n",
2617+ "MergeP1", sys_ctrl[0], sys_ctrl[1]);
2618+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2619+ "DMA0P1", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
2620+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
2621+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
2622+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
2623+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
2624+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2625+ "DMA1P1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
2626+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
2627+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
2628+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[7]),
2629+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[7]));
2630+
2631+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2632+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2633+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2634+ dump_dma_rx_ring_info(s, dev, "R0:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2635+ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
2636+
2637+ seq_printf(s, "HOST_DMA0 PCIe 1 Ring Configuration\n");
2638+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2639+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2640+ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", MT_DBG_WFDMA0_PCIE1_RX1_CTRL0);
2641+
2642+ seq_printf(s, "HOST_DMA1 Ring Configuration\n");
2643+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2644+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2645+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
2646+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
developer79a21a22023-01-09 13:57:39 +08002647+ if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
2648+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(0));
2649+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(1));
2650+ } else {
2651+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
2652+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
2653+ }
developer3fa816c2022-04-19 10:21:20 +08002654+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
2655+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_EVENT_RING_CTRL(0));
developer79a21a22023-01-09 13:57:39 +08002656+ if (mtk_wed_device_active(&dev->mt76.mmio.wed))
2657+ dump_dma_rx_ring_info(s, dev, "R1:TxDone(WA2H)", MT_DBG_WFDMA_WED_RX_CTRL(1));
2658+ else
2659+ dump_dma_rx_ring_info(s, dev, "R1:Event0(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
developer3fa816c2022-04-19 10:21:20 +08002660+ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
2661+
2662+ seq_printf(s, "HOST_DMA1 PCIe 1 Ring Configuration\n");
2663+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2664+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2665+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA1_PCIE1_TX19_CTRL0);
2666+ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", MT_DBG_WFDMA1_PCIE1_RX2_CTRL0);
2667+}
2668+
2669+static void
2670+mt7915_show_mcu_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2671+{
2672+ u32 sys_ctrl[9] = {};
2673+
2674+ /* MCU DMA information */
2675+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2676+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2677+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2678+
2679+ sys_ctrl[3] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR);
2680+ sys_ctrl[4] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR);
2681+ sys_ctrl[5] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR);
2682+ sys_ctrl[6] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR);
2683+ sys_ctrl[7] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR);
2684+ sys_ctrl[8] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR);
2685+
2686+ seq_printf(s, "MCU_DMA Configuration\n");
2687+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2688+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2689+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2690+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2691+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2692+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2693+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2694+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2695+
2696+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2697+ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[3],
2698+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2699+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2700+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2701+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2702+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2703+ "DMA1P1", sys_ctrl[7], sys_ctrl[8], sys_ctrl[6],
2704+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2705+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2706+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2707+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2708+
2709+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2710+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2711+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2712+ dump_dma_tx_ring_info(s, dev, "T0:TXD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2713+ dump_dma_tx_ring_info(s, dev, "T1:TXCMD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2714+ dump_dma_tx_ring_info(s, dev, "T2:TXD(WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2715+ dump_dma_rx_ring_info(s, dev, "R0:Data(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2716+ dump_dma_rx_ring_info(s, dev, "R1:TxDone(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2717+ dump_dma_rx_ring_info(s, dev, "R2:SPL(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2718+ dump_dma_rx_ring_info(s, dev, "R3:TxDone(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2719+ dump_dma_rx_ring_info(s, dev, "R4:TXS(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2720+
2721+ seq_printf(s, "MCU_DMA1 Ring Configuration\n");
2722+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2723+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2724+ dump_dma_tx_ring_info(s, dev, "T0:Event(WM2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR);
2725+ dump_dma_tx_ring_info(s, dev, "T1:Event0(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR);
2726+ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR);
2727+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR);
2728+ dump_dma_rx_ring_info(s, dev, "R1:Cmd(H2WM)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR);
2729+ dump_dma_rx_ring_info(s, dev, "R2:TXD0(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR);
2730+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR);
2731+ dump_dma_rx_ring_info(s, dev, "R4:Cmd(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR);
2732+
2733+ seq_printf(s, "MCU_DMA1 PCIe 1 Ring Configuration\n");
2734+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2735+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2736+ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR);
2737+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR);
2738+}
2739+
2740+static void
2741+mt7986_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2742+{
2743+ u32 sys_ctrl[5] = {};
2744+
2745+ /* HOST DMA */
2746+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
2747+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
2748+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
2749+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
2750+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
2751+
2752+ seq_printf(s, "HOST_DMA Configuration\n");
2753+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2754+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2755+ seq_printf(s, "%10s %10x %10x\n",
2756+ "Merge", sys_ctrl[0], sys_ctrl[1]);
2757+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2758+ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[4],
2759+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK, sys_ctrl[4]),
2760+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK, sys_ctrl[4]),
2761+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK, sys_ctrl[4]),
2762+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK, sys_ctrl[4]));
2763+
2764+
2765+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2766+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2767+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2768+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
2769+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
developer79a21a22023-01-09 13:57:39 +08002770+
2771+ if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed)) {
2772+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(0));
2773+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(1));
2774+ } else {
2775+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
2776+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
2777+ }
2778+
developer3fa816c2022-04-19 10:21:20 +08002779+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
2780+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2781+ dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
developer79a21a22023-01-09 13:57:39 +08002782+ if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed))
2783+ dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_WFDMA_WED_RX_CTRL(1));
2784+ else
2785+ dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
developer3fa816c2022-04-19 10:21:20 +08002786+ dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(3));
2787+ dump_dma_rx_ring_info(s, dev, "R4:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2788+ dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
2789+}
2790+
2791+static void
2792+mt7986_show_mcu_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2793+{
2794+ u32 sys_ctrl[3] = {};
2795+
2796+ /* MCU DMA information */
2797+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2798+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2799+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2800+
2801+ seq_printf(s, "MCU_DMA Configuration\n");
2802+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2803+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2804+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2805+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2806+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2807+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2808+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2809+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2810+
2811+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2812+ seq_printf(s, "%22s %10s %10s %10s %10s %10s\n",
2813+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2814+ dump_dma_tx_ring_info(s, dev, "T0:Event (WM2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2815+ dump_dma_tx_ring_info(s, dev, "T1:Event (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2816+ dump_dma_tx_ring_info(s, dev, "T2:TxDone (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2817+ dump_dma_tx_ring_info(s, dev, "T3:TxDone1 (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR);
2818+ dump_dma_tx_ring_info(s, dev, "T4:TXD (WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR);
2819+ dump_dma_tx_ring_info(s, dev, "T5:TXCMD (WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR);
2820+ dump_dma_tx_ring_info(s, dev, "T6:TXD (WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR);
2821+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2822+ dump_dma_rx_ring_info(s, dev, "R1:Cmd (H2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2823+ dump_dma_rx_ring_info(s, dev, "R2:TXD (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2824+ dump_dma_rx_ring_info(s, dev, "R3:TXD1 (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2825+ dump_dma_rx_ring_info(s, dev, "R4:Cmd (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2826+ dump_dma_rx_ring_info(s, dev, "R5:Data (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR);
2827+ dump_dma_rx_ring_info(s, dev, "R6:TxDone/STS (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR);
2828+ dump_dma_rx_ring_info(s, dev, "R7:RPT (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR);
2829+ dump_dma_rx_ring_info(s, dev, "R8:TxDone/STS (MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR);
2830+ dump_dma_rx_ring_info(s, dev, "R9:Data1 (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR);
2831+
2832+}
2833+
2834+static void
2835+mt7915_show_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2836+{
2837+ u32 sys_ctrl[10] = {};
2838+
2839+ if(is_mt7915(&dev->mt76)) {
2840+ mt7915_show_host_dma_info(s, dev);
2841+ mt7915_show_mcu_dma_info(s, dev);
2842+ } else {
2843+ mt7986_show_host_dma_info(s, dev);
2844+ mt7986_show_mcu_dma_info(s, dev);
2845+ }
2846+
2847+ /* MEM DMA information */
2848+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR);
2849+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR);
2850+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR);
2851+
2852+ seq_printf(s, "MEM_DMA Configuration\n");
2853+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2854+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2855+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2856+ "MEM", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2857+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2858+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2859+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2860+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2861+
2862+ seq_printf(s, "MEM_DMA Ring Configuration\n");
2863+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2864+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2865+ dump_dma_tx_ring_info(s, dev, "T0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR);
2866+ dump_dma_tx_ring_info(s, dev, "T1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR);
2867+ dump_dma_rx_ring_info(s, dev, "R0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR);
2868+ dump_dma_rx_ring_info(s, dev, "R1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR);
2869+}
2870+
2871+static int mt7915_trinfo_read(struct seq_file *s, void *data)
2872+{
2873+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2874+ const struct hif_pci_tx_ring_desc *tx_ring_layout;
2875+ const struct hif_pci_rx_ring_desc *rx_ring_layout;
developer79a21a22023-01-09 13:57:39 +08002876+ struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
developer3fa816c2022-04-19 10:21:20 +08002877+ u32 tx_ring_num, rx_ring_num;
2878+ u32 tbase[5], tcnt[5];
2879+ u32 tcidx[5], tdidx[5];
2880+ u32 rbase[6], rcnt[6];
2881+ u32 rcidx[6], rdidx[6];
2882+ int idx;
developer79a21a22023-01-09 13:57:39 +08002883+ bool flags = false;
developer3fa816c2022-04-19 10:21:20 +08002884+
2885+ if(is_mt7915(&dev->mt76)) {
2886+ tx_ring_layout = &mt7915_tx_ring_layout[0];
2887+ rx_ring_layout = &mt7915_rx_ring_layout[0];
2888+ tx_ring_num = ARRAY_SIZE(mt7915_tx_ring_layout);
2889+ rx_ring_num = ARRAY_SIZE(mt7915_rx_ring_layout);
2890+ } else {
2891+ tx_ring_layout = &mt7986_tx_ring_layout[0];
2892+ rx_ring_layout = &mt7986_rx_ring_layout[0];
2893+ tx_ring_num = ARRAY_SIZE(mt7986_tx_ring_layout);
2894+ rx_ring_num = ARRAY_SIZE(mt7986_rx_ring_layout);
2895+ }
2896+
2897+ for (idx = 0; idx < tx_ring_num; idx++) {
developer79a21a22023-01-09 13:57:39 +08002898+ if (mtk_wed_device_active(wed) &&
2899+ (tx_ring_layout[idx].ring_attr == HIF_TX_DATA)) {
2900+ struct mt76_phy *phy = dev->mt76.phys[MT_BAND0];
2901+ struct mt76_phy *ext_phy = dev->mt76.phys[MT_BAND1];
2902+ struct mt76_queue *q;
2903+
2904+ tbase[idx] = tcnt[idx] = tcidx[idx] = tdidx[idx] = 0;
2905+
2906+ if (!phy)
2907+ continue;
2908+
2909+ if (flags && !ext_phy)
2910+ continue;
2911+
2912+ if (flags && ext_phy)
2913+ phy = ext_phy;
2914+
2915+ q = phy->q_tx[0];
2916+
2917+ if (q->wed_regs) {
2918+ tbase[idx] = mtk_wed_device_reg_read(wed, q->wed_regs);
2919+ tcnt[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x04);
2920+ tcidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x08);
2921+ tdidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x0c);
2922+ }
2923+
2924+ flags = true;
2925+ } else {
2926+ tbase[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx));
2927+ tcnt[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x04);
2928+ tcidx[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x08);
2929+ tdidx[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x0c);}
developer3fa816c2022-04-19 10:21:20 +08002930+ }
2931+
2932+ for (idx = 0; idx < rx_ring_num; idx++) {
developer79a21a22023-01-09 13:57:39 +08002933+ if (rx_ring_layout[idx].ring_attr == HIF_RX_DATA) {
2934+ if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) {
2935+ struct mt76_queue *q = &dev->mt76.q_rx[MT_RXQ_MAIN];
2936+
2937+ rbase[idx] = rcnt[idx] = rcidx[idx] = rdidx[idx] = 0;
2938+
2939+ if (idx == 1)
2940+ q = &dev->mt76.q_rx[MT_RXQ_BAND1];
2941+
2942+ if (q->wed_regs) {
2943+ rbase[idx] = mtk_wed_device_reg_read(wed, q->wed_regs);
2944+ rcnt[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x04);
2945+ rcidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x08);
2946+ rdidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x0c);
2947+ }
2948+ } else {
2949+ rbase[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx));
2950+ rcnt[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x04);
2951+ rcidx[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x08);
2952+ rdidx[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x0c);
2953+ }
developer3fa816c2022-04-19 10:21:20 +08002954+ } else {
developer79a21a22023-01-09 13:57:39 +08002955+ if (mtk_wed_device_active(wed) && rx_ring_layout[idx].flags) {
2956+ struct mt76_queue *q = &dev->mt76.q_rx[MT_RXQ_MAIN_WA];
2957+
2958+ if (is_mt7915(&dev->mt76))
2959+ q = &dev->mt76.q_rx[MT_RXQ_MCU_WA];
2960+
2961+ rbase[idx] = mtk_wed_device_reg_read(wed, q->wed_regs);
2962+ rcnt[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x04);
2963+ rcidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x08);
2964+ rdidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x0c);
2965+
2966+ } else {
2967+ rbase[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2));
2968+ rcnt[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x04);
2969+ rcidx[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x08);
2970+ rdidx[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x0c);
2971+ }
developer3fa816c2022-04-19 10:21:20 +08002972+ }
2973+ }
2974+
2975+ seq_printf(s, "=================================================\n");
2976+ seq_printf(s, "TxRing Configuration\n");
2977+ seq_printf(s, "%4s %10s %8s %1s %6s %6s %6s %6s\n",
2978+ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
2979+ "QCnt");
2980+ for (idx = 0; idx < tx_ring_num; idx++) {
2981+ u32 queue_cnt;
2982+
2983+ queue_cnt = (tcidx[idx] >= tdidx[idx]) ?
2984+ (tcidx[idx] - tdidx[idx]) :
2985+ (tcidx[idx] - tdidx[idx] + tcnt[idx]);
2986+ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
2987+ idx, tx_ring_layout[idx].ring_info,
2988+ MT_DBG_TX_RING_CTRL(idx), tbase[idx],
2989+ tcnt[idx], tcidx[idx], tdidx[idx], queue_cnt);
2990+ }
2991+
2992+ seq_printf(s, "RxRing Configuration\n");
2993+ seq_printf(s, "%4s %10s %8s %10s %6s %6s %6s %6s\n",
2994+ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
2995+ "QCnt");
2996+
2997+ for (idx = 0; idx < rx_ring_num; idx++) {
2998+ u32 queue_cnt;
2999+
3000+ queue_cnt = (rdidx[idx] > rcidx[idx]) ?
3001+ (rdidx[idx] - rcidx[idx] - 1) :
3002+ (rdidx[idx] - rcidx[idx] + rcnt[idx] - 1);
3003+ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
3004+ idx, rx_ring_layout[idx].ring_info,
3005+ (idx < 2) ? MT_DBG_RX_DATA_RING_CTRL(idx): MT_DBG_RX_EVENT_RING_CTRL(idx - 2),
3006+ rbase[idx], rcnt[idx], rcidx[idx], rdidx[idx], queue_cnt);
3007+ }
3008+
3009+ mt7915_show_dma_info(s, dev);
3010+ return 0;
3011+}
3012+
3013+static int mt7915_drr_info(struct seq_file *s, void *data)
3014+{
3015+#define DL_AC_START 0x00
3016+#define DL_AC_END 0x0F
3017+#define UL_AC_START 0x10
3018+#define UL_AC_END 0x1F
3019+
3020+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3021+ u32 drr_sta_status[16];
3022+ u32 drr_ctrl_def_val = 0x80220000, drr_ctrl_val = 0;
3023+ bool is_show = false;
3024+ int idx, sta_line = 0, sta_no = 0, max_sta_line = (mt7915_wtbl_size(dev) + 31) / 32;
3025+ seq_printf(s, "DRR Table STA Info:\n");
3026+
3027+ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
3028+ is_show = true;
3029+ drr_ctrl_val = (drr_ctrl_def_val | idx);
3030+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3031+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3032+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3033+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3034+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3035+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3036+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3037+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3038+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3039+
3040+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
3041+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1 << 10);
3042+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3043+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3044+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3045+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3046+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3047+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3048+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3049+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3050+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3051+ }
3052+ if (!is_mt7915(&dev->mt76))
3053+ max_sta_line = 8;
3054+
3055+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
3056+ if (drr_sta_status[sta_line] > 0) {
3057+ for (sta_no = 0; sta_no < 32; sta_no++) {
3058+ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
3059+ if (is_show) {
3060+ seq_printf(s, "\n DL AC%02d Queue Non-Empty STA:\n", idx);
3061+ is_show = false;
3062+ }
3063+ seq_printf(s, "%d ", sta_no + (sta_line * 32));
3064+ }
3065+ }
3066+ }
3067+ }
3068+ }
3069+
3070+ for (idx = UL_AC_START; idx <= UL_AC_END; idx++) {
3071+ is_show = true;
3072+ drr_ctrl_val = (drr_ctrl_def_val | idx);
3073+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3074+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3075+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3076+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3077+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3078+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3079+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3080+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3081+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3082+
3083+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
3084+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1 << 10);
3085+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3086+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3087+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3088+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3089+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3090+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3091+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3092+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3093+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3094+ }
3095+
3096+ if (!is_mt7915(&dev->mt76))
3097+ max_sta_line = 8;
3098+
3099+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
3100+ if (drr_sta_status[sta_line] > 0) {
3101+ for (sta_no = 0; sta_no < 32; sta_no++) {
3102+ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
3103+ if (is_show) {
3104+ seq_printf(s, "\n UL AC%02d Queue Non-Empty STA:\n", idx);
3105+ is_show = false;
3106+ }
3107+ seq_printf(s, "%d ", sta_no + (sta_line * 32));
3108+ }
3109+ }
3110+ }
3111+ }
3112+ }
3113+
3114+ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
3115+ drr_ctrl_def_val = 0x80420000;
3116+ drr_ctrl_val = (drr_ctrl_def_val | idx);
3117+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3118+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3119+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3120+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3121+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3122+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3123+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3124+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3125+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3126+
3127+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
3128+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1<<10);
3129+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3130+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3131+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3132+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3133+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3134+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3135+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3136+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3137+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3138+ }
3139+
3140+ seq_printf(s, "\nBSSGrp[%d]:\n", idx);
3141+ if (!is_mt7915(&dev->mt76))
3142+ max_sta_line = 8;
3143+
3144+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
3145+ seq_printf(s, "0x%08x ", drr_sta_status[sta_line]);
3146+
3147+ if ((sta_line % 4) == 3)
3148+ seq_printf(s, "\n");
3149+ }
3150+ }
3151+
3152+ return 0;
3153+}
3154+
developerf32dabf2022-06-01 10:59:24 +08003155+#define CR_NUM_OF_AC 17
developer3fa816c2022-04-19 10:21:20 +08003156+
3157+typedef enum _ENUM_UMAC_PORT_T {
3158+ ENUM_UMAC_HIF_PORT_0 = 0,
3159+ ENUM_UMAC_CPU_PORT_1 = 1,
3160+ ENUM_UMAC_LMAC_PORT_2 = 2,
3161+ ENUM_PLE_CTRL_PSE_PORT_3 = 3,
3162+ ENUM_UMAC_PSE_PLE_PORT_TOTAL_NUM = 4
3163+} ENUM_UMAC_PORT_T, *P_ENUM_UMAC_PORT_T;
3164+
3165+/* N9 MCU QUEUE LIST */
3166+typedef enum _ENUM_UMAC_CPU_P_QUEUE_T {
3167+ ENUM_UMAC_CTX_Q_0 = 0,
3168+ ENUM_UMAC_CTX_Q_1 = 1,
3169+ ENUM_UMAC_CTX_Q_2 = 2,
3170+ ENUM_UMAC_CTX_Q_3 = 3,
3171+ ENUM_UMAC_CRX = 0,
3172+ ENUM_UMAC_CIF_QUEUE_TOTAL_NUM = 4
3173+} ENUM_UMAC_CPU_P_QUEUE_T, *P_ENUM_UMAC_CPU_P_QUEUE_T;
3174+
3175+/* LMAC PLE TX QUEUE LIST */
3176+typedef enum _ENUM_UMAC_LMAC_PLE_TX_P_QUEUE_T {
3177+ ENUM_UMAC_LMAC_PLE_TX_Q_00 = 0x00,
3178+ ENUM_UMAC_LMAC_PLE_TX_Q_01 = 0x01,
3179+ ENUM_UMAC_LMAC_PLE_TX_Q_02 = 0x02,
3180+ ENUM_UMAC_LMAC_PLE_TX_Q_03 = 0x03,
3181+
3182+ ENUM_UMAC_LMAC_PLE_TX_Q_10 = 0x04,
3183+ ENUM_UMAC_LMAC_PLE_TX_Q_11 = 0x05,
3184+ ENUM_UMAC_LMAC_PLE_TX_Q_12 = 0x06,
3185+ ENUM_UMAC_LMAC_PLE_TX_Q_13 = 0x07,
3186+
3187+ ENUM_UMAC_LMAC_PLE_TX_Q_20 = 0x08,
3188+ ENUM_UMAC_LMAC_PLE_TX_Q_21 = 0x09,
3189+ ENUM_UMAC_LMAC_PLE_TX_Q_22 = 0x0a,
3190+ ENUM_UMAC_LMAC_PLE_TX_Q_23 = 0x0b,
3191+
3192+ ENUM_UMAC_LMAC_PLE_TX_Q_30 = 0x0c,
3193+ ENUM_UMAC_LMAC_PLE_TX_Q_31 = 0x0d,
3194+ ENUM_UMAC_LMAC_PLE_TX_Q_32 = 0x0e,
3195+ ENUM_UMAC_LMAC_PLE_TX_Q_33 = 0x0f,
3196+
3197+ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 = 0x10,
3198+ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0 = 0x11,
3199+ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0 = 0x12,
3200+ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0 = 0x13,
3201+
3202+ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 = 0x14,
3203+ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1 = 0x15,
3204+ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1 = 0x16,
3205+ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1 = 0x17,
3206+ ENUM_UMAC_LMAC_PLE_TX_Q_NAF = 0x18,
3207+ ENUM_UMAC_LMAC_PLE_TX_Q_NBCN = 0x19,
3208+ ENUM_UMAC_LMAC_PLE_TX_Q_RELEASE = 0x1f, /* DE suggests not to use 0x1f, it's only for hw free queue */
3209+ ENUM_UMAC_LMAC_QUEUE_TOTAL_NUM = 24,
3210+
3211+} ENUM_UMAC_LMAC_TX_P_QUEUE_T, *P_ENUM_UMAC_LMAC_TX_P_QUEUE_T;
3212+
3213+typedef struct _EMPTY_QUEUE_INFO_T {
3214+ char *QueueName;
3215+ u32 Portid;
3216+ u32 Queueid;
3217+} EMPTY_QUEUE_INFO_T, *P_EMPTY_QUEUE_INFO_T;
3218+
3219+static EMPTY_QUEUE_INFO_T ple_queue_empty_info[] = {
3220+ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
3221+ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
3222+ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
3223+ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
3224+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
3225+ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0}, /* Q16 */
3226+ {"BMC Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0},
3227+ {"BCN Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0},
3228+ {"PSMP Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0},
3229+ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1},
3230+ {"BMC Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1},
3231+ {"BCN Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1},
3232+ {"PSMP Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1},
3233+ {"NAF Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NAF},
3234+ {"NBCN Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NBCN},
3235+ {NULL, 0, 0}, {NULL, 0, 0}, /* 18, 19 not defined */
3236+ {"FIXFID Q", ENUM_UMAC_LMAC_PORT_2, 0x1a},
3237+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
3238+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 21~29 not defined */
3239+ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7e},
3240+ {"RLS2 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7f}
3241+};
3242+
3243+static EMPTY_QUEUE_INFO_T ple_txcmd_queue_empty_info[] = {
3244+ {"AC00Q", ENUM_UMAC_LMAC_PORT_2, 0x40},
3245+ {"AC01Q", ENUM_UMAC_LMAC_PORT_2, 0x41},
3246+ {"AC02Q", ENUM_UMAC_LMAC_PORT_2, 0x42},
3247+ {"AC03Q", ENUM_UMAC_LMAC_PORT_2, 0x43},
3248+ {"AC10Q", ENUM_UMAC_LMAC_PORT_2, 0x44},
3249+ {"AC11Q", ENUM_UMAC_LMAC_PORT_2, 0x45},
3250+ {"AC12Q", ENUM_UMAC_LMAC_PORT_2, 0x46},
3251+ {"AC13Q", ENUM_UMAC_LMAC_PORT_2, 0x47},
3252+ {"AC20Q", ENUM_UMAC_LMAC_PORT_2, 0x48},
3253+ {"AC21Q", ENUM_UMAC_LMAC_PORT_2, 0x49},
3254+ {"AC22Q", ENUM_UMAC_LMAC_PORT_2, 0x4a},
3255+ {"AC23Q", ENUM_UMAC_LMAC_PORT_2, 0x4b},
3256+ {"AC30Q", ENUM_UMAC_LMAC_PORT_2, 0x4c},
3257+ {"AC31Q", ENUM_UMAC_LMAC_PORT_2, 0x4d},
3258+ {"AC32Q", ENUM_UMAC_LMAC_PORT_2, 0x4e},
3259+ {"AC33Q", ENUM_UMAC_LMAC_PORT_2, 0x4f},
3260+ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, 0x50},
3261+ {"TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x51},
3262+ {"TWT TSF-TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x52},
3263+ {"TWT DL Q0", ENUM_UMAC_LMAC_PORT_2, 0x53},
3264+ {"TWT UL Q0", ENUM_UMAC_LMAC_PORT_2, 0x54},
3265+ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, 0x55},
3266+ {"TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x56},
3267+ {"TWT TSF-TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x57},
3268+ {"TWT DL Q1", ENUM_UMAC_LMAC_PORT_2, 0x58},
3269+ {"TWT UL Q1", ENUM_UMAC_LMAC_PORT_2, 0x59},
3270+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
3271+};
3272+
3273+
3274+
3275+static char* sta_ctrl_reg[] = {"ENABLE", "DISABLE", "PAUSE"};
3276+static u32 chip_show_sta_acq_info(struct seq_file *s, struct mt7915_dev *dev, u32 *ple_stat,
3277+ u32 *sta_pause, u32 *dis_sta_map,
3278+ u32 dumptxd)
3279+{
3280+ int i, j;
3281+ u32 total_nonempty_cnt = 0;
3282+ u32 ac_num = 9, all_ac_num;
3283+
3284+ /* TDO: ac_num = 16 for mt7986 */
developerf32dabf2022-06-01 10:59:24 +08003285+ if (!is_mt7915(&dev->mt76))
3286+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003287+
3288+ all_ac_num = ac_num * 4;
3289+
3290+ for (j = 0; j < all_ac_num; j++) { /* show AC Q info */
3291+ for (i = 0; i < 32; i++) {
3292+ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
developerf32dabf2022-06-01 10:59:24 +08003293+ u32 hfid, tfid, pktcnt, ac_n = j / ac_num, ctrl = 0;
developer3fa816c2022-04-19 10:21:20 +08003294+ u32 sta_num = i + (j % ac_num) * 32, fl_que_ctrl[3] = {0};
3295+ //struct wifi_dev *wdev = wdev_search_by_wcid(pAd, sta_num);
3296+ u32 wmmidx = 0;
3297+ struct mt7915_sta *msta;
3298+ struct mt76_wcid *wcid;
developer3fa816c2022-04-19 10:21:20 +08003299+
3300+ wcid = rcu_dereference(dev->mt76.wcid[sta_num]);
developerdfb50982023-09-11 13:34:36 +08003301+ if (!wcid) {
developer3fa816c2022-04-19 10:21:20 +08003302+ printk("ERROR!! no found STA wcid=%d\n", sta_num);
developerf32dabf2022-06-01 10:59:24 +08003303+ continue;
developer3fa816c2022-04-19 10:21:20 +08003304+ }
3305+ msta = container_of(wcid, struct mt7915_sta, wcid);
3306+ wmmidx = msta->vif->mt76.wmm_idx;
3307+
developerf32dabf2022-06-01 10:59:24 +08003308+ seq_printf(s, "\tSTA%d AC%d: ", sta_num, ac_n);
developer3fa816c2022-04-19 10:21:20 +08003309+
3310+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3311+ fl_que_ctrl[0] |= (ENUM_UMAC_LMAC_PORT_2 << MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
developerf32dabf2022-06-01 10:59:24 +08003312+ fl_que_ctrl[0] |= (ac_n << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
developer3fa816c2022-04-19 10:21:20 +08003313+ fl_que_ctrl[0] |= sta_num;
3314+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3315+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3316+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3317+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3318+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3319+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3320+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x",
3321+ tfid, hfid, pktcnt);
3322+
developerb0c86782023-10-27 15:40:47 +08003323+ if (((sta_pause[j % ac_num] & 0x1 << i) >> i) == 1)
developer3fa816c2022-04-19 10:21:20 +08003324+ ctrl = 2;
3325+
developerb0c86782023-10-27 15:40:47 +08003326+ if (((dis_sta_map[j % ac_num] & 0x1 << i) >> i) == 1)
developer3fa816c2022-04-19 10:21:20 +08003327+ ctrl = 1;
3328+
3329+ seq_printf(s, " ctrl = %s", sta_ctrl_reg[ctrl]);
3330+ seq_printf(s, " (wmmidx=%d)\n", wmmidx);
3331+
3332+ total_nonempty_cnt++;
3333+
3334+ // TODO
3335+ //if (pktcnt > 0 && dumptxd > 0)
3336+ // ShowTXDInfo(pAd, hfid);
3337+ }
3338+ }
3339+ }
3340+
3341+ return total_nonempty_cnt;
3342+}
3343+
3344+static void chip_show_txcmdq_info(struct seq_file *s, struct mt7915_dev *dev, u32 ple_txcmd_stat)
3345+{
3346+ int i;
3347+
3348+ seq_printf(s, "Nonempty TXCMD Q info:\n");
developerf32dabf2022-06-01 10:59:24 +08003349+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003350+ if (((ple_txcmd_stat & (0x1 << i)) >> i) == 0) {
3351+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3352+
3353+ if (ple_txcmd_queue_empty_info[i].QueueName != NULL) {
3354+ seq_printf(s, "\t%s: ", ple_txcmd_queue_empty_info[i].QueueName);
3355+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3356+ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Portid <<
3357+ MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
3358+ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Queueid <<
3359+ MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
3360+ } else
3361+ continue;
3362+
3363+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3364+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3365+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3366+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3367+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3368+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3369+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3370+ tfid, hfid, pktcnt);
3371+ }
3372+ }
3373+}
3374+
3375+static void chip_get_ple_acq_stat(struct mt7915_dev *dev, u32 *ple_stat)
3376+{
3377+ int i;
3378+ int cr_num = 9, all_cr_num;
3379+ u32 ac , index;
3380+
3381+ /* TDO: cr_num = 16 for mt7986 */
developer3fa816c2022-04-19 10:21:20 +08003382+ if(!is_mt7915(&dev->mt76))
developerf32dabf2022-06-01 10:59:24 +08003383+ cr_num = 17;
3384+
developer3fa816c2022-04-19 10:21:20 +08003385+ all_cr_num = cr_num * 4;
3386+
3387+ ple_stat[0] = mt76_rr(dev, MT_DBG_PLE_QUEUE_EMPTY);
3388+
3389+ for(i = 0; i < all_cr_num; i++) {
3390+ ac = i / cr_num;
3391+ index = i % cr_num;
3392+ ple_stat[i + 1] =
3393+ mt76_rr(dev, MT_DBG_PLE_AC_QEMPTY(ac, index));
3394+
3395+ }
3396+}
3397+
3398+static void chip_get_dis_sta_map(struct mt7915_dev *dev, u32 *dis_sta_map)
3399+{
3400+ int i;
developerf32dabf2022-06-01 10:59:24 +08003401+ u32 ac_num = 9;
3402+
3403+ /* TDO: ac_num = 16 for mt7986 */
3404+ if (!is_mt7915(&dev->mt76))
3405+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003406+
developerf32dabf2022-06-01 10:59:24 +08003407+ for(i = 0; i < ac_num; i++) {
developer3fa816c2022-04-19 10:21:20 +08003408+ dis_sta_map[i] = mt76_rr(dev, MT_DBG_PLE_DIS_STA_MAP(i));
3409+ }
3410+}
3411+
3412+static void chip_get_sta_pause(struct mt7915_dev *dev, u32 *sta_pause)
3413+{
3414+ int i;
developerf32dabf2022-06-01 10:59:24 +08003415+ u32 ac_num = 9;
developer3fa816c2022-04-19 10:21:20 +08003416+
developerf32dabf2022-06-01 10:59:24 +08003417+ /* TDO: ac_num = 16 for mt7986 */
3418+ if (!is_mt7915(&dev->mt76))
3419+ ac_num = 17;
3420+
3421+ for(i = 0; i < ac_num; i++) {
developer3fa816c2022-04-19 10:21:20 +08003422+ sta_pause[i] = mt76_rr(dev, MT_DBG_PLE_STATION_PAUSE(i));
3423+ }
3424+}
3425+
3426+static int mt7915_pleinfo_read(struct seq_file *s, void *data)
3427+{
3428+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3429+ u32 ple_buf_ctrl, pg_sz, pg_num;
developerf32dabf2022-06-01 10:59:24 +08003430+ u32 ple_stat[70] = {0}, pg_flow_ctrl[8] = {0};
developer3fa816c2022-04-19 10:21:20 +08003431+ u32 ple_native_txcmd_stat;
3432+ u32 ple_txcmd_stat;
3433+ u32 sta_pause[CR_NUM_OF_AC] = {0}, dis_sta_map[CR_NUM_OF_AC] = {0};
3434+ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail, hif_max_q, hif_min_q;
3435+ u32 rpg_hif, upg_hif, cpu_max_q, cpu_min_q, rpg_cpu, upg_cpu;
3436+ int i, j;
3437+ u32 ac_num = 9, all_ac_num;
3438+
3439+ /* TDO: ac_num = 16 for mt7986 */
developerf32dabf2022-06-01 10:59:24 +08003440+ if (!is_mt7915(&dev->mt76))
3441+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003442+
3443+ all_ac_num = ac_num * 4;
3444+
3445+ ple_buf_ctrl = mt76_rr(dev, MT_DBG_PLE_PBUF_CTRL_ADDR);
3446+ chip_get_ple_acq_stat(dev, ple_stat);
3447+ ple_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_TXCMD_Q_EMPTY);
3448+ ple_native_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY);
3449+ pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PLE_FREEPG_CNT);
3450+ pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FREEPG_HEAD_TAIL);
3451+ pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_GROUP);
3452+ pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PLE_HIF_PG_INFO);
3453+ pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PLE_PG_CPU_GROUP);
3454+ pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PLE_CPU_PG_INFO);
3455+ pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_TXCMD_GROUP);
3456+ pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PLE_HIF_TXCMD_PG_INFO);
3457+ chip_get_dis_sta_map(dev, dis_sta_map);
3458+ chip_get_sta_pause(dev, sta_pause);
3459+
3460+ seq_printf(s, "PLE Configuration Info:\n");
3461+ seq_printf(s, "\tPacket Buffer Control(0x%x): 0x%08x\n",
3462+ MT_DBG_PLE_PBUF_CTRL_ADDR, ple_buf_ctrl);
3463+
3464+ pg_sz = FIELD_GET(MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK, ple_buf_ctrl);
3465+ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n",
3466+ pg_sz, (pg_sz == 1 ? 128 : 64));
3467+ seq_printf(s, "\t\tPage Offset=%ld(in unit of 2KB)\n",
3468+ FIELD_GET(MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK, ple_buf_ctrl));
3469+
3470+ pg_num = FIELD_GET(MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK, ple_buf_ctrl);
3471+ seq_printf(s, "\t\tTotal Page=%d pages\n", pg_num);
3472+
3473+ /* Page Flow Control */
3474+ seq_printf(s, "PLE Page Flow Control:\n");
3475+ seq_printf(s, "\tFree page counter(0x%x): 0x%08x\n",
3476+ MT_DBG_PLE_FREEPG_CNT, pg_flow_ctrl[0]);
3477+ fpg_cnt = FIELD_GET(MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK, pg_flow_ctrl[0]);
3478+
3479+ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3480+ ffa_cnt = FIELD_GET(MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK, pg_flow_ctrl[0]);
3481+
3482+ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3483+ seq_printf(s, "\tFree page head and tail(0x%x): 0x%08x\n",
3484+ MT_DBG_PLE_FREEPG_HEAD_TAIL, pg_flow_ctrl[1]);
3485+
3486+ fpg_head = FIELD_GET(MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK, pg_flow_ctrl[1]);
3487+ fpg_tail = FIELD_GET(MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK, pg_flow_ctrl[1]);
3488+ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3489+ seq_printf(s, "\tReserved page counter of HIF group(0x%x): 0x%08x\n",
3490+ MT_DBG_PLE_PG_HIF_GROUP, pg_flow_ctrl[2]);
3491+ seq_printf(s, "\tHIF group page status(0x%x): 0x%08x\n",
3492+ MT_DBG_PLE_HIF_PG_INFO, pg_flow_ctrl[3]);
3493+
3494+ hif_min_q = FIELD_GET(MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK, pg_flow_ctrl[2]);
3495+ hif_max_q = FIELD_GET(MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK, pg_flow_ctrl[2]);
3496+ seq_printf(s, "\t\tThe max/min quota pages of HIF group=0x%03x/0x%03x\n", hif_max_q, hif_min_q);
3497+
3498+ rpg_hif = FIELD_GET(MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK, pg_flow_ctrl[3]);
3499+ upg_hif = FIELD_GET(MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK, pg_flow_ctrl[3]);
3500+ seq_printf(s, "\t\tThe used/reserved pages of HIF group=0x%03x/0x%03x\n", upg_hif, rpg_hif);
3501+
3502+ seq_printf(s, "\tReserved page counter of HIF_TXCMD group(0x%x): 0x%08x\n",
3503+ MT_DBG_PLE_PG_HIF_TXCMD_GROUP, pg_flow_ctrl[6]);
3504+ seq_printf(s, "\tHIF_TXCMD group page status(0x%x): 0x%08x\n",
3505+ MT_DBG_PLE_HIF_TXCMD_PG_INFO, pg_flow_ctrl[7]);
3506+ cpu_min_q = FIELD_GET(MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
developerf32dabf2022-06-01 10:59:24 +08003507+ cpu_max_q = FIELD_GET(MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK, pg_flow_ctrl[6]);
developer3fa816c2022-04-19 10:21:20 +08003508+ seq_printf(s, "\t\tThe max/min quota pages of HIF_TXCMD group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
3509+
3510+ rpg_cpu = FIELD_GET(MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK, pg_flow_ctrl[7]);
3511+ upg_cpu = FIELD_GET(MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK, pg_flow_ctrl[7]);
3512+ seq_printf(s, "\t\tThe used/reserved pages of HIF_TXCMD group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
3513+
developerf32dabf2022-06-01 10:59:24 +08003514+ seq_printf(s, "\tReserved page counter of CPU group(0x%x): 0x%08x\n",
3515+ MT_DBG_PLE_PG_CPU_GROUP, pg_flow_ctrl[4]);
3516+ seq_printf(s, "\tCPU group page status(0x%x): 0x%08x\n",
3517+ MT_DBG_PLE_CPU_PG_INFO, pg_flow_ctrl[5]);
developer3fa816c2022-04-19 10:21:20 +08003518+ cpu_min_q = FIELD_GET(MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK, pg_flow_ctrl[4]);
3519+ cpu_max_q = FIELD_GET(MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK, pg_flow_ctrl[4]);
3520+ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
3521+
3522+ rpg_cpu = FIELD_GET(MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK, pg_flow_ctrl[5]);
3523+ upg_cpu = FIELD_GET(MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK, pg_flow_ctrl[5]);
3524+ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
3525+
3526+ if ((ple_stat[0] & MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK) == 0) {
3527+ for (j = 0; j < all_ac_num; j++) {
3528+ if (j % ac_num == 0) {
3529+ seq_printf(s, "\n\tNonempty AC%d Q of STA#: ", j / ac_num);
3530+ }
3531+
developerf32dabf2022-06-01 10:59:24 +08003532+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003533+ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
3534+ seq_printf(s, "%d ", i + (j % ac_num) * 32);
3535+ }
3536+ }
3537+ }
3538+
3539+ seq_printf(s, "\n");
3540+ }
3541+
3542+ seq_printf(s, "non-native/native txcmd queue empty = %d/%d\n", ple_txcmd_stat, ple_native_txcmd_stat);
3543+
3544+ seq_printf(s, "Nonempty Q info:\n");
3545+
developerf32dabf2022-06-01 10:59:24 +08003546+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003547+ if (((ple_stat[0] & (0x1 << i)) >> i) == 0) {
3548+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3549+
3550+ if (ple_queue_empty_info[i].QueueName != NULL) {
3551+ seq_printf(s, "\t%s: ", ple_queue_empty_info[i].QueueName);
3552+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3553+ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Portid << MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
3554+ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Queueid << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
3555+ } else
3556+ continue;
3557+
3558+ if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 &&
3559+ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0)
3560+ /* band0 set TGID 0, bit31 = 0 */
3561+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x0);
3562+ else if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 &&
3563+ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1)
3564+ /* band1 set TGID 1, bit31 = 1 */
3565+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x80000000);
3566+
3567+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3568+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3569+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3570+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3571+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3572+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3573+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3574+ tfid, hfid, pktcnt);
3575+
3576+ /* TODO */
3577+ //if (pktcnt > 0 && dumptxd > 0)
3578+ // ShowTXDInfo(pAd, hfid);
3579+ }
3580+ }
3581+
3582+ chip_show_sta_acq_info(s, dev, ple_stat, sta_pause, dis_sta_map, 0/*dumptxd*/);
3583+ chip_show_txcmdq_info(s, dev, ple_native_txcmd_stat);
3584+
3585+ return 0;
3586+}
3587+
3588+typedef enum _ENUM_UMAC_PLE_CTRL_P3_QUEUE_T {
3589+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1E = 0x1e,
3590+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1F = 0x1f,
3591+ ENUM_UMAC_PLE_CTRL_P3_TOTAL_NUM = 2
3592+} ENUM_UMAC_PLE_CTRL_P3_QUEUE_T, *P_ENUM_UMAC_PLE_CTRL_P3_QUEUE_T;
3593+
3594+static EMPTY_QUEUE_INFO_T pse_queue_empty_info[] = {
3595+ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
3596+ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
3597+ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
3598+ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
3599+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
3600+ {"HIF Q0", ENUM_UMAC_HIF_PORT_0, 0}, /* Q8 */
3601+ {"HIF Q1", ENUM_UMAC_HIF_PORT_0, 1},
3602+ {"HIF Q2", ENUM_UMAC_HIF_PORT_0, 2},
3603+ {"HIF Q3", ENUM_UMAC_HIF_PORT_0, 3},
3604+ {"HIF Q4", ENUM_UMAC_HIF_PORT_0, 4},
3605+ {"HIF Q5", ENUM_UMAC_HIF_PORT_0, 5},
3606+ {NULL, 0, 0}, {NULL, 0, 0}, /* 14~15 not defined */
3607+ {"LMAC Q", ENUM_UMAC_LMAC_PORT_2, 0},
3608+ {"MDP TX Q", ENUM_UMAC_LMAC_PORT_2, 1},
3609+ {"MDP RX Q", ENUM_UMAC_LMAC_PORT_2, 2},
3610+ {"SEC TX Q", ENUM_UMAC_LMAC_PORT_2, 3},
3611+ {"SEC RX Q", ENUM_UMAC_LMAC_PORT_2, 4},
3612+ {"SFD_PARK Q", ENUM_UMAC_LMAC_PORT_2, 5},
3613+ {"MDP_TXIOC Q", ENUM_UMAC_LMAC_PORT_2, 6},
3614+ {"MDP_RXIOC Q", ENUM_UMAC_LMAC_PORT_2, 7},
3615+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 24~30 not defined */
3616+ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, ENUM_UMAC_PLE_CTRL_P3_Q_0X1F}
3617+};
3618+
3619+static int mt7915_pseinfo_read(struct seq_file *s, void *data)
3620+{
3621+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3622+ u32 pse_buf_ctrl, pg_sz, pg_num;
3623+ u32 pse_stat, pg_flow_ctrl[22] = {0};
3624+ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail;
3625+ u32 max_q, min_q, rsv_pg, used_pg;
3626+ int i;
3627+
3628+ pse_buf_ctrl = mt76_rr(dev, MT_DBG_PSE_PBUF_CTRL);
3629+ pse_stat = mt76_rr(dev, MT_DBG_PSE_QUEUE_EMPTY);
3630+ pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PSE_FREEPG_CNT);
3631+ pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PSE_FREEPG_HEAD_TAIL);
3632+ pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PSE_PG_HIF0_GROUP);
3633+ pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PSE_HIF0_PG_INFO);
3634+ pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PSE_PG_HIF1_GROUP);
3635+ pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PSE_HIF1_PG_INFO);
3636+ pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PSE_PG_CPU_GROUP);
3637+ pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PSE_CPU_PG_INFO);
3638+ pg_flow_ctrl[8] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC0_GROUP);
3639+ pg_flow_ctrl[9] = mt76_rr(dev, MT_DBG_PSE_LMAC0_PG_INFO);
3640+ pg_flow_ctrl[10] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC1_GROUP);
3641+ pg_flow_ctrl[11] = mt76_rr(dev, MT_DBG_PSE_LMAC1_PG_INFO);
3642+ pg_flow_ctrl[12] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC2_GROUP);
3643+ pg_flow_ctrl[13] = mt76_rr(dev, MT_DBG_PSE_LMAC2_PG_INFO);
3644+ pg_flow_ctrl[14] = mt76_rr(dev, MT_DBG_PSE_PG_PLE_GROUP);
3645+ pg_flow_ctrl[15] = mt76_rr(dev, MT_DBG_PSE_PLE_PG_INFO);
3646+ pg_flow_ctrl[16] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC3_GROUP);
3647+ pg_flow_ctrl[17] = mt76_rr(dev, MT_DBG_PSE_LMAC3_PG_INFO);
3648+ pg_flow_ctrl[18] = mt76_rr(dev, MT_DBG_PSE_PG_MDP_GROUP);
3649+ pg_flow_ctrl[19] = mt76_rr(dev, MT_DBG_PSE_MDP_PG_INFO);
3650+ pg_flow_ctrl[20] = mt76_rr(dev, MT_DBG_PSE_PG_PLE1_GROUP);
3651+ pg_flow_ctrl[21] = mt76_rr(dev,MT_DBG_PSE_PLE1_PG_INFO);
3652+
3653+ /* Configuration Info */
3654+ seq_printf(s, "PSE Configuration Info:\n");
3655+ seq_printf(s, "\tPacket Buffer Control(0x82068014): 0x%08x\n", pse_buf_ctrl);
3656+ pg_sz = FIELD_GET(MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK, pse_buf_ctrl);
3657+
3658+ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n", pg_sz, (pg_sz == 1 ? 256 : 128));
3659+ seq_printf(s, "\t\tPage Offset=%ld(in unit of 64KB)\n",
3660+ FIELD_GET(MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK, pse_buf_ctrl));
3661+ pg_num = FIELD_GET(MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK, pse_buf_ctrl);
3662+
3663+ seq_printf(s, "\t\tTotal page numbers=%d pages\n", pg_num);
3664+
3665+ /* Page Flow Control */
3666+ seq_printf(s, "PSE Page Flow Control:\n");
3667+ seq_printf(s, "\tFree page counter(0x82068100): 0x%08x\n", pg_flow_ctrl[0]);
3668+ fpg_cnt = FIELD_GET(MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK, pg_flow_ctrl[0]);
3669+ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3670+
3671+ ffa_cnt = FIELD_GET(MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK, pg_flow_ctrl[0]);
3672+ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3673+
3674+ seq_printf(s, "\tFree page head and tail(0x82068104): 0x%08x\n", pg_flow_ctrl[1]);
3675+ fpg_head = FIELD_GET(MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK, pg_flow_ctrl[1]);
3676+
3677+ fpg_tail = FIELD_GET(MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK, pg_flow_ctrl[1]);
3678+ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3679+ seq_printf(s, "\tReserved page counter of HIF0 group(0x82068110): 0x%08x\n", pg_flow_ctrl[2]);
3680+ seq_printf(s, "\tHIF0 group page status(0x82068114): 0x%08x\n", pg_flow_ctrl[3]);
3681+ min_q = FIELD_GET(MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK, pg_flow_ctrl[2]);
3682+ max_q = FIELD_GET(MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK, pg_flow_ctrl[2]);
3683+ seq_printf(s, "\t\tThe max/min quota pages of HIF0 group=0x%03x/0x%03x\n", max_q, min_q);
3684+ rsv_pg = FIELD_GET(MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK, pg_flow_ctrl[3]);;
3685+ used_pg = FIELD_GET(MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK, pg_flow_ctrl[3]);
3686+ seq_printf(s, "\t\tThe used/reserved pages of HIF0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3687+ seq_printf(s, "\tReserved page counter of HIF1 group(0x82068118): 0x%08x\n", pg_flow_ctrl[4]);
3688+ seq_printf(s, "\tHIF1 group page status(0x8206811c): 0x%08x\n", pg_flow_ctrl[5]);
3689+ min_q = FIELD_GET(MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK, pg_flow_ctrl[4]);
3690+ max_q = FIELD_GET(MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK, pg_flow_ctrl[4]);
3691+ seq_printf(s, "\t\tThe max/min quota pages of HIF1 group=0x%03x/0x%03x\n", max_q, min_q);
3692+ rsv_pg = FIELD_GET(MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK, pg_flow_ctrl[5]);
3693+ used_pg = FIELD_GET(MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK, pg_flow_ctrl[5]);
3694+
3695+ seq_printf(s, "\t\tThe used/reserved pages of HIF1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3696+ seq_printf(s, "\tReserved page counter of CPU group(0x82068150): 0x%08x\n", pg_flow_ctrl[6]);
3697+ seq_printf(s, "\tCPU group page status(0x82068154): 0x%08x\n", pg_flow_ctrl[7]);
3698+ min_q = FIELD_GET(MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
3699+ max_q = FIELD_GET(MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK, pg_flow_ctrl[6]);
3700+ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", max_q, min_q);
3701+ rsv_pg = FIELD_GET(MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK, pg_flow_ctrl[7]);
3702+ used_pg = FIELD_GET(MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK, pg_flow_ctrl[7]);
3703+ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3704+ seq_printf(s, "\tReserved page counter of LMAC0 group(0x82068170): 0x%08x\n", pg_flow_ctrl[8]);
3705+ seq_printf(s, "\tLMAC0 group page status(0x82068174): 0x%08x\n", pg_flow_ctrl[9]);
3706+ min_q = FIELD_GET(MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK, pg_flow_ctrl[8]);
3707+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK, pg_flow_ctrl[8]);
3708+ seq_printf(s, "\t\tThe max/min quota pages of LMAC0 group=0x%03x/0x%03x\n", max_q, min_q);
3709+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK, pg_flow_ctrl[9]);
3710+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK, pg_flow_ctrl[9]);
3711+ seq_printf(s, "\t\tThe used/reserved pages of LMAC0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3712+ seq_printf(s, "\tReserved page counter of LMAC1 group(0x82068178): 0x%08x\n", pg_flow_ctrl[10]);
3713+ seq_printf(s, "\tLMAC1 group page status(0x8206817c): 0x%08x\n", pg_flow_ctrl[11]);
3714+ min_q = FIELD_GET(MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK, pg_flow_ctrl[10]);
3715+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK, pg_flow_ctrl[10]);
3716+ seq_printf(s, "\t\tThe max/min quota pages of LMAC1 group=0x%03x/0x%03x\n", max_q, min_q);
3717+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK, pg_flow_ctrl[11]);
3718+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK, pg_flow_ctrl[11]);
3719+ seq_printf(s, "\t\tThe used/reserved pages of LMAC1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3720+ seq_printf(s, "\tReserved page counter of LMAC2 group(0x82068180): 0x%08x\n", pg_flow_ctrl[11]);
3721+ seq_printf(s, "\tLMAC2 group page status(0x82068184): 0x%08x\n", pg_flow_ctrl[12]);
3722+ min_q = FIELD_GET(MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK, pg_flow_ctrl[12]);
3723+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK, pg_flow_ctrl[12]);
3724+ seq_printf(s, "\t\tThe max/min quota pages of LMAC2 group=0x%03x/0x%03x\n", max_q, min_q);
3725+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK, pg_flow_ctrl[13]);
3726+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK, pg_flow_ctrl[13]);
3727+ seq_printf(s, "\t\tThe used/reserved pages of LMAC2 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3728+
3729+ seq_printf(s, "\tReserved page counter of LMAC3 group(0x82068188): 0x%08x\n", pg_flow_ctrl[16]);
3730+ seq_printf(s, "\tLMAC3 group page status(0x8206818c): 0x%08x\n", pg_flow_ctrl[17]);
3731+ min_q = FIELD_GET(MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK, pg_flow_ctrl[16]);
3732+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK, pg_flow_ctrl[16]);
3733+ seq_printf(s, "\t\tThe max/min quota pages of LMAC3 group=0x%03x/0x%03x\n", max_q, min_q);
3734+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK, pg_flow_ctrl[17]);
3735+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK, pg_flow_ctrl[17]);
3736+ seq_printf(s, "\t\tThe used/reserved pages of LMAC3 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3737+
3738+ seq_printf(s, "\tReserved page counter of PLE group(0x82068160): 0x%08x\n", pg_flow_ctrl[14]);
3739+ seq_printf(s, "\tPLE group page status(0x82068164): 0x%08x\n", pg_flow_ctrl[15]);
3740+ min_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK, pg_flow_ctrl[14]);
3741+ max_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK, pg_flow_ctrl[14]);
3742+ seq_printf(s, "\t\tThe max/min quota pages of PLE group=0x%03x/0x%03x\n", max_q, min_q);
3743+ rsv_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK, pg_flow_ctrl[15]);
3744+ used_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK, pg_flow_ctrl[15]);
3745+ seq_printf(s, "\t\tThe used/reserved pages of PLE group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3746+
3747+ seq_printf(s, "\tReserved page counter of PLE1 group(0x82068168): 0x%08x\n", pg_flow_ctrl[14]);
3748+ seq_printf(s, "\tPLE1 group page status(0x8206816c): 0x%08x\n", pg_flow_ctrl[15]);
3749+ min_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK, pg_flow_ctrl[20]);
3750+ max_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK, pg_flow_ctrl[20]);
3751+ seq_printf(s, "\t\tThe max/min quota pages of PLE1 group=0x%03x/0x%03x\n", max_q, min_q);
3752+ rsv_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK, pg_flow_ctrl[21]);
3753+ used_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK, pg_flow_ctrl[21]);
3754+ seq_printf(s, "\t\tThe used/reserved pages of PLE1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3755+
3756+ seq_printf(s, "\tReserved page counter of MDP group(0x82068198): 0x%08x\n", pg_flow_ctrl[18]);
3757+ seq_printf(s, "\tMDP group page status(0x8206819c): 0x%08x\n", pg_flow_ctrl[19]);
3758+ min_q = FIELD_GET(MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK, pg_flow_ctrl[18]);
3759+ max_q = FIELD_GET(MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK, pg_flow_ctrl[18]);
3760+ seq_printf(s, "\t\tThe max/min quota pages of MDP group=0x%03x/0x%03x\n", max_q, min_q);
3761+ rsv_pg = FIELD_GET(MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK, pg_flow_ctrl[19]);
3762+ used_pg = FIELD_GET(MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK, pg_flow_ctrl[19]);
3763+ seq_printf(s, "\t\tThe used/reserved pages of MDP group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3764+
3765+ /* Queue Empty Status */
3766+ seq_printf(s, "PSE Queue Empty Status:\n");
3767+ seq_printf(s, "\tQUEUE_EMPTY(0x820680b0): 0x%08x\n", pse_stat);
3768+ seq_printf(s, "\t\tCPU Q0/1/2/3 empty=%ld/%ld/%ld/%ld\n",
3769+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK, pse_stat),
3770+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK, pse_stat),
3771+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK, pse_stat),
3772+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK, pse_stat));
3773+
3774+ seq_printf(s, "\t\tHIF Q0/1/2/3/4/5 empty=%ld/%ld/%ld/%ld/%ld/%ld\n",
3775+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK, pse_stat),
3776+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK, pse_stat),
3777+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK, pse_stat),
3778+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK, pse_stat),
3779+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK, pse_stat),
3780+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK, pse_stat));
3781+
3782+ seq_printf(s, "\t\tLMAC TX Q empty=%ld\n",
3783+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK, pse_stat));
3784+ seq_printf(s, "\t\tMDP TX Q/RX Q empty=%ld/%ld\n",
3785+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK, pse_stat),
3786+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK, pse_stat));
3787+ seq_printf(s, "\t\tSEC TX Q/RX Q empty=%ld/%ld\n",
3788+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK, pse_stat),
3789+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT, pse_stat));
3790+ seq_printf(s, "\t\tSFD PARK Q empty=%ld\n",
3791+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK, pse_stat));
3792+ seq_printf(s, "\t\tMDP TXIOC Q/RXIOC Q empty=%ld/%ld\n",
3793+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK, pse_stat),
3794+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK, pse_stat));
3795+ seq_printf(s, "\t\tRLS Q empty=%ld\n",
3796+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK, pse_stat));
3797+ seq_printf(s, "Nonempty Q info:\n");
3798+
3799+ for (i = 0; i < 31; i++) {
3800+ if (((pse_stat & (0x1 << i)) >> i) == 0) {
3801+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3802+
3803+ if (pse_queue_empty_info[i].QueueName != NULL) {
3804+ seq_printf(s, "\t%s: ", pse_queue_empty_info[i].QueueName);
3805+ fl_que_ctrl[0] |= MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK;
3806+ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Portid << MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT);
3807+ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Queueid << MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT);
3808+ } else
3809+ continue;
3810+
3811+ fl_que_ctrl[0] |= (0x1 << 31);
3812+
3813+ mt76_wr(dev, MT_DBG_PSE_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]);
3814+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PSE_FL_QUE_CTRL_2_ADDR);
3815+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PSE_FL_QUE_CTRL_3_ADDR);
3816+
3817+ hfid = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK, fl_que_ctrl[1]);
3818+ tfid = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK, fl_que_ctrl[1]);
3819+ pktcnt = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK, fl_que_ctrl[2]);
3820+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3821+ tfid, hfid, pktcnt);
3822+ }
3823+ }
3824+
3825+ return 0;
3826+}
3827+
3828+static int mt7915_mibinfo_read_per_band(struct seq_file *s, int band_idx)
3829+{
3830+#define BSS_NUM 4
3831+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3832+ u32 mac_val0, mac_val, mac_val1, idx, band_offset = 0;
3833+ u32 msdr6, msdr7, msdr8, msdr9, msdr10, msdr16, msdr17, msdr18, msdr19, msdr20, msdr21;
3834+ u32 mbxsdr[BSS_NUM][7];
3835+ u32 mbtcr[16], mbtbcr[16], mbrcr[16], mbrbcr[16];
3836+ u32 btcr[BSS_NUM], btbcr[BSS_NUM], brcr[BSS_NUM], brbcr[BSS_NUM], btdcr[BSS_NUM], brdcr[BSS_NUM];
3837+ u32 mu_cnt[5];
3838+ u32 ampdu_cnt[3];
3839+ unsigned long per;
3840+
3841+ seq_printf(s, "Band %d MIB Status\n", band_idx);
3842+ seq_printf(s, "===============================\n");
3843+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SCR0(band_idx));
3844+ seq_printf(s, "MIB Status Control=0x%x\n", mac_val);
3845+ if (is_mt7915(&dev->mt76)) {
3846+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0PBSCR(band_idx));
3847+ seq_printf(s, "MIB Per-BSS Status Control=0x%x\n", mac_val);
3848+ }
3849+
3850+ msdr6 = mt76_rr(dev, MT_DBG_MIB_M0SDR6(band_idx));
3851+ msdr7 = mt76_rr(dev, MT_DBG_MIB_M0SDR7(band_idx));
3852+ msdr8 = mt76_rr(dev, MT_DBG_MIB_M0SDR8(band_idx));
3853+ msdr9 = mt76_rr(dev, MT_DBG_MIB_M0SDR9(band_idx));
3854+ msdr10 = mt76_rr(dev, MT_DBG_MIB_M0SDR10(band_idx));
3855+ msdr16 = mt76_rr(dev, MT_DBG_MIB_M0SDR16(band_idx));
3856+ msdr17 = mt76_rr(dev, MT_DBG_MIB_M0SDR17(band_idx));
3857+ msdr18 = mt76_rr(dev, MT_DBG_MIB_M0SDR18(band_idx));
3858+ msdr19 = mt76_rr(dev, MT_DBG_MIB_M0SDR19(band_idx));
3859+ msdr20 = mt76_rr(dev, MT_DBG_MIB_M0SDR20(band_idx));
3860+ msdr21 = mt76_rr(dev, MT_DBG_MIB_M0SDR21(band_idx));
3861+ ampdu_cnt[0] = mt76_rr(dev, MT_DBG_MIB_M0SDR12(band_idx));
3862+ ampdu_cnt[1] = mt76_rr(dev, MT_DBG_MIB_M0SDR14(band_idx));
3863+ ampdu_cnt[2] = mt76_rr(dev, MT_DBG_MIB_M0SDR15(band_idx));
3864+ ampdu_cnt[1] &= MT_DBG_MIB_M0SDR14_AMPDU_MASK;
3865+ ampdu_cnt[2] &= MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK;
3866+
3867+ seq_printf(s, "===Phy/Timing Related Counters===\n");
3868+ seq_printf(s, "\tChannelIdleCnt=0x%x\n", msdr6 & BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK);
3869+ seq_printf(s, "\tCCA_NAV_Tx_Time=0x%x\n", msdr9 & BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK);
3870+ seq_printf(s, "\tRx_MDRDY_CNT=0x%lx\n", msdr10 & MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK);
3871+ seq_printf(s, "\tCCK_MDRDY_TIME=0x%x, OFDM_MDRDY_TIME=0x%x, OFDM_GREEN_MDRDY_TIME=0x%x\n",
3872+ msdr19 & BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK,
3873+ msdr20 & BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK,
3874+ msdr21 & BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK);
3875+ seq_printf(s, "\tPrim CCA Time=0x%x\n", msdr16 & BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK);
3876+ seq_printf(s, "\tSec CCA Time=0x%x\n", msdr17 & BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK);
3877+ seq_printf(s, "\tPrim ED Time=0x%x\n", msdr18 & BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK);
3878+
3879+ seq_printf(s, "===Tx Related Counters(Generic)===\n");
3880+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR0(band_idx));
3881+ dev->dbg.bcn_total_cnt[band_idx] += (mac_val & BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK);
3882+ seq_printf(s, "\tBeaconTxCnt=0x%x\n",dev->dbg.bcn_total_cnt[band_idx]);
3883+ dev->dbg.bcn_total_cnt[band_idx] = 0;
3884+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR0(band_idx));
3885+ seq_printf(s, "\tTx 20MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK);
3886+ seq_printf(s, "\tTx 40MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT);
3887+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR1(band_idx));
3888+ seq_printf(s, "\tTx 80MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK);
3889+ seq_printf(s, "\tTx 160MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT);
3890+ seq_printf(s, "\tAMPDU Cnt=0x%x\n", ampdu_cnt[0]);
3891+ seq_printf(s, "\tAMPDU MPDU Cnt=0x%x\n", ampdu_cnt[1]);
3892+ seq_printf(s, "\tAMPDU MPDU Ack Cnt=0x%x\n", ampdu_cnt[2]);
3893+ per = (ampdu_cnt[2] == 0 ? 0 : 1000 * (ampdu_cnt[1] - ampdu_cnt[2]) / ampdu_cnt[1]);
3894+ seq_printf(s, "\tAMPDU MPDU PER=%ld.%1ld%%\n", per / 10, per % 10);
3895+
3896+ seq_printf(s, "===MU Related Counters===\n");
3897+ mu_cnt[0] = mt76_rr(dev, MT_DBG_MIB_MUBF(band_idx));
3898+ mu_cnt[1] = mt76_rr(dev, MT_DBG_MIB_M0DR8(band_idx));
3899+ mu_cnt[2] = mt76_rr(dev, MT_DBG_MIB_M0DR9(band_idx));
3900+ mu_cnt[3] = mt76_rr(dev, MT_DBG_MIB_M0DR10(band_idx));
3901+ mu_cnt[4] = mt76_rr(dev, MT_DBG_MIB_M0DR11(band_idx));
3902+ seq_printf(s, "\tMUBF_TX_COUNT=0x%x\n", mu_cnt[0] & BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK);
3903+ seq_printf(s, "\tMU_TX_MPDU_COUNT(Ok+Fail)=0x%x\n", mu_cnt[1]);
3904+ seq_printf(s, "\tMU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[2]);
3905+ seq_printf(s, "\tMU_TO_SU_PPDU_COUNT=0x%x\n", mu_cnt[3] & BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK);
3906+ seq_printf(s, "\tSU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[4]);
3907+
3908+ seq_printf(s, "===Rx Related Counters(Generic)===\n");
3909+ seq_printf(s, "\tVector Mismacth Cnt=0x%x\n", msdr7 & BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK);
3910+ seq_printf(s, "\tDelimiter Fail Cnt=0x%x\n", msdr8 & BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK);
3911+
3912+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR3(band_idx));
3913+ seq_printf(s, "\tRxFCSErrCnt=0x%lx\n", __DBG_FIELD_GET(DBG_MIB_RX_FCS_ERROR_COUNT, mac_val));
3914+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR4(band_idx));
3915+ seq_printf(s, "\tRxFifoFullCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK));
3916+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR11(band_idx));
3917+ seq_printf(s, "\tRxLenMismatch=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK));
3918+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR5(band_idx));
3919+ seq_printf(s, "\tRxMPDUCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK));
3920+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR22(band_idx));
3921+ seq_printf(s, "\tRx AMPDU Cnt=0x%x\n", mac_val);
3922+ /* TODO: shiang-MT7615, is MIB_M0SDR23 used for Rx total byte count for all or just AMPDU only??? */
3923+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR23(band_idx));
3924+ seq_printf(s, "\tRx Total ByteCnt=0x%x\n", mac_val);
3925+
3926+ if (is_mt7915(&dev->mt76)) {
3927+ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;//check
3928+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3929+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
3930+
3931+ for (idx = 0; idx < BSS_NUM; idx++) {
3932+ btcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTCRn_ADDR + band_offset + idx * 4);
3933+ btbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTBCRn_ADDR + band_offset + idx * 4);
3934+ brcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRCRn_ADDR + band_offset + idx * 4);
3935+ brbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRBCRn_ADDR + band_offset + idx * 4);
3936+ btdcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTDCRn_ADDR + band_offset + idx * 4);
3937+ brdcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRDCRn_ADDR + band_offset + idx * 4);
3938+ }
3939+
3940+ for (idx = 0; idx < BSS_NUM; idx++) {
3941+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3942+ idx, btcr[idx], btdcr[idx], btbcr[idx],
3943+ brcr[idx], brdcr[idx], brbcr[idx]);
3944+ }
3945+
3946+ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
3947+ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
3948+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3949+
3950+ for (idx = 0; idx < BSS_NUM; idx++) {
3951+ mbxsdr[idx][0] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR0_ADDR + band_offset + idx * 0x10);
3952+ mbxsdr[idx][1] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR1_ADDR + band_offset + idx * 0x10);
3953+ mbxsdr[idx][2] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR2_ADDR + band_offset + idx * 0x10);
3954+ mbxsdr[idx][3] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR3_ADDR + band_offset + idx * 0x10);
3955+ }
3956+
3957+ for (idx = 0; idx < BSS_NUM; idx++) {
3958+ seq_printf(s, "%d:\t0x%08x/0x%08x 0x%08x \t 0x%08x \t 0x%08x/0x%08x/0x%08x\n",
3959+ idx, (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK),
3960+ (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT,
3961+ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK),
3962+ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT,
3963+ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK),
3964+ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT,
3965+ (mbxsdr[idx][3] & BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK));
3966+ }
3967+
3968+ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;
3969+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3970+ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
3971+
3972+ for (idx = 0; idx < 16; idx++) {
3973+ mbtcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBTCRn_ADDR + band_offset + idx * 4);
3974+ mbtbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBTBCRn_ADDR + band_offset + idx * 4);
3975+ mbrcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBRCRn_ADDR + band_offset + idx * 4);
3976+ mbrbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBRBCRn_ADDR + band_offset + idx * 4);
3977+ }
3978+
3979+ for (idx = 0; idx < 16; idx++) {
3980+ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
3981+ idx, mbtcr[idx], mbtbcr[idx], mbrcr[idx], mbrbcr[idx]);
3982+ }
3983+ return 0;
3984+ } else {
3985+ u32 btocr[BSS_NUM], mbtocr[16],mbrocr[16], brocr[BSS_NUM];
3986+ u8 bss_nums = BSS_NUM;
3987+
3988+ band_offset = (BN1_WF_MIB_TOP_BTOCR_ADDR - BN0_WF_MIB_TOP_BTOCR_ADDR) * band_idx;
3989+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3990+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
3991+
3992+ for (idx = 0; idx < BSS_NUM; idx++) {
3993+ btocr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (idx >> 1) * 4));
3994+ btdcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTDCR_ADDR + band_offset + (idx >> 1) * 4));
3995+ btbcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (idx * 4)));
3996+ brocr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BROCR_ADDR + band_offset + (idx >> 1) * 4));
3997+ brdcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BRDCR_ADDR + band_offset + (idx >> 1) * 4));
3998+ brbcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BRBCR_ADDR + band_offset + (idx * 4)));
3999+
4000+ if ((idx % 2) == 0) {
4001+ btocr[idx] = ((btocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT);
4002+ btdcr[idx] = ((btdcr[idx] & BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT);
4003+ brocr[idx] = ((brocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT);
4004+ brdcr[idx] = ((brdcr[idx] & BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT);
4005+ } else {
4006+ btocr[idx] = ((btocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT);
4007+ btdcr[idx] = ((btdcr[idx] & BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT);
4008+ brocr[idx] = ((brocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT);
4009+ brdcr[idx] = ((brdcr[idx] & BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT);
4010+ }
4011+ }
4012+
4013+ for (idx = 0; idx < BSS_NUM; idx++) {
4014+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
4015+ idx, btocr[idx], btdcr[idx], btbcr[idx], brocr[idx], brdcr[idx], brbcr[idx]);
4016+ }
4017+
4018+ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
4019+ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
4020+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
4021+
4022+ for (idx = 0; idx < BSS_NUM; idx++) {
4023+ mbxsdr[idx][0] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR0_ADDR + band_offset + ((idx >> 1) * 4));
4024+ mbxsdr[idx][1] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR1_ADDR + band_offset + ((idx >> 1) * 4));
4025+ mbxsdr[idx][2] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR2_ADDR + band_offset + ((idx >> 1) * 4));
4026+ mbxsdr[idx][3] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR3_ADDR + band_offset + ((idx >> 1) * 4));
4027+ mbxsdr[idx][4] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR4_ADDR + band_offset + ((idx >> 1) * 4));
4028+ mbxsdr[idx][5] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR5_ADDR + band_offset + ((idx >> 1) * 4));
4029+ mbxsdr[idx][6] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR6_ADDR + band_offset + ((idx >> 1) * 4));
4030+
4031+ if ((idx % 2) == 0) {
4032+ mbxsdr[idx][0] = ((mbxsdr[idx][0] & BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT);
4033+ mbxsdr[idx][1] = ((mbxsdr[idx][1] & BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT);
4034+ mbxsdr[idx][2] = ((mbxsdr[idx][2] & BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT);
4035+ mbxsdr[idx][3] = ((mbxsdr[idx][3] & BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT);
4036+ mbxsdr[idx][4] = ((mbxsdr[idx][4] & BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT);
4037+ mbxsdr[idx][5] = ((mbxsdr[idx][5] & BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT);
4038+ mbxsdr[idx][6] = ((mbxsdr[idx][6] & BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT);
4039+ } else {
4040+ mbxsdr[idx][0] = ((mbxsdr[idx][0] & BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT);
4041+ mbxsdr[idx][1] = ((mbxsdr[idx][1] & BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT);
4042+ mbxsdr[idx][2] = ((mbxsdr[idx][2] & BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT);
4043+ mbxsdr[idx][3] = ((mbxsdr[idx][3] & BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT);
4044+ mbxsdr[idx][4] = ((mbxsdr[idx][4] & BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT);
4045+ mbxsdr[idx][5] = ((mbxsdr[idx][5] & BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT);
4046+ mbxsdr[idx][6] = ((mbxsdr[idx][6] & BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT);
4047+ }
4048+ }
4049+
4050+ for (idx = 0; idx < BSS_NUM; idx++) {
4051+ seq_printf(s, "%d:\t0x%x/0x%x 0x%x \t 0x%x \t 0x%x/0x%x/0x%x\n",
4052+ idx,
4053+ mbxsdr[idx][0], mbxsdr[idx][1], mbxsdr[idx][2], mbxsdr[idx][3],
4054+ mbxsdr[idx][4], mbxsdr[idx][5], mbxsdr[idx][6]);
4055+ }
4056+
4057+ band_offset = (BN1_WF_MIB_TOP_BTOCR_ADDR - BN0_WF_MIB_TOP_BTOCR_ADDR) * band_idx;
4058+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
4059+ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
4060+
4061+ for (idx = 0; idx < 16; idx++) {
4062+ mbtocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + ((idx >> 1) * 4)));
4063+ mbtbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + (idx * 4)));
4064+ mbrocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BROCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + ((idx >> 1) * 4)));
4065+ mbrbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BRBCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + (idx * 4)));
4066+
4067+ if ((idx % 2) == 0) {
4068+ mbtocr[idx] = ((mbtocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT);
4069+ mbrocr[idx] = ((mbrocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT);
4070+ } else {
4071+ mbtocr[idx] = ((mbtocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT);
4072+ mbrocr[idx] = ((mbrocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT);
4073+ }
4074+ }
4075+
4076+ for (idx = 0; idx < 16; idx++) {
4077+ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
4078+ idx, mbtocr[idx], mbtbcr[idx], mbrocr[idx], mbrbcr[idx]);
4079+ }
4080+ }
4081+
4082+ seq_printf(s, "===Dummy delimiter insertion result===\n");
4083+ mac_val0 = mt76_rr(dev, MT_DBG_MIB_M0DR11(band_idx));
4084+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR6(band_idx));
4085+ mac_val1 = mt76_rr(dev, MT_DBG_MIB_M0DR7(band_idx));
4086+ seq_printf(s, "Range0 = %d\t Range1 = %d\t Range2 = %d\t Range3 = %d\t Range4 = %d\n",
4087+ (mac_val0 & BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK),
4088+ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK),
4089+ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT,
4090+ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK),
4091+ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT);
4092+
4093+ return 0;
4094+}
4095+
4096+static int mt7915_mibinfo_band0(struct seq_file *s, void *data)
4097+{
4098+ mt7915_mibinfo_read_per_band(s, 0);
4099+ return 0;
4100+}
4101+
4102+static int mt7915_mibinfo_band1(struct seq_file *s, void *data)
4103+{
4104+ mt7915_mibinfo_read_per_band(s, 1);
4105+ return 0;
4106+}
4107+
4108+static int mt7915_token_read(struct seq_file *s, void *data)
4109+{
4110+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4111+ int id, count = 0;
4112+ struct mt76_txwi_cache *txwi;
4113+
4114+ seq_printf(s, "Cut through token:\n");
4115+ spin_lock_bh(&dev->mt76.token_lock);
4116+ idr_for_each_entry(&dev->mt76.token, txwi, id) {
4117+ seq_printf(s, "%4d ", id);
4118+ count++;
4119+ if (count % 8 == 0)
4120+ seq_printf(s, "\n");
4121+ }
4122+ spin_unlock_bh(&dev->mt76.token_lock);
4123+ seq_printf(s, "\n");
4124+
4125+ return 0;
4126+}
4127+
4128+struct txd_l {
4129+ u32 txd_0;
4130+ u32 txd_1;
4131+ u32 txd_2;
4132+ u32 txd_3;
4133+ u32 txd_4;
4134+ u32 txd_5;
4135+ u32 txd_6;
4136+ u32 txd_7;
4137+} __packed;
4138+
4139+char *pkt_ft_str[] = {"cut_through", "store_forward", "cmd", "PDA_FW_Download"};
4140+char *hdr_fmt_str[] = {
4141+ "Non-80211-Frame",
4142+ "Command-Frame",
4143+ "Normal-80211-Frame",
4144+ "enhanced-80211-Frame",
4145+};
4146+/* TMAC_TXD_1.hdr_format */
4147+#define TMI_HDR_FT_NON_80211 0x0
4148+#define TMI_HDR_FT_CMD 0x1
4149+#define TMI_HDR_FT_NOR_80211 0x2
4150+#define TMI_HDR_FT_ENH_80211 0x3
4151+
4152+void mt7915_dump_tmac_info(u8 *tmac_info)
4153+{
4154+ struct txd_l *txd = (struct txd_l *)tmac_info;
4155+
4156+ printk("txd raw data: size=%d\n", MT_TXD_SIZE);
4157+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, tmac_info, MT_TXD_SIZE, false);
4158+
4159+ printk("TMAC_TXD Fields:\n");
4160+ printk("\tTMAC_TXD_0:\n");
4161+
4162+ /* DW0 */
4163+ /* TX Byte Count [15:0] */
4164+ printk("\t\tTxByteCnt = %ld\n", FIELD_GET(MT_TXD0_TX_BYTES, txd->txd_0));
4165+
4166+ /* PKT_FT: Packet Format [24:23] */
4167+ printk("\t\tpkt_ft = %ld(%s)\n",
4168+ FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0),
4169+ pkt_ft_str[FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0)]);
4170+
4171+ /* Q_IDX [31:25] */
4172+ printk("\t\tQueID =0x%lx\n", FIELD_GET(MT_TXD0_Q_IDX, txd->txd_0));
4173+
4174+ printk("\tTMAC_TXD_1:\n");
4175+
4176+ /* DW1 */
4177+ /* WLAN Indec [9:0] */
4178+ printk("\t\tWlan Index = %ld\n", FIELD_GET(MT_TXD1_WLAN_IDX, txd->txd_1));
4179+
4180+ /* VTA [10] */
4181+ printk("\t\tVTA = %d\n", ((txd->txd_1 & MT_TXD1_VTA) ? 1 : 0));
4182+
4183+ /* HF: Header Format [17:16] */
4184+ printk("\t\tHdrFmt = %ld(%s)\n",
4185+ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1),
4186+ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1) < 4 ?
4187+ hdr_fmt_str[FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)] : "N/A");
4188+
4189+ switch (FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)) {
4190+ case TMI_HDR_FT_NON_80211:
4191+ /* MRD [11], EOSP [12], RMVL [13], VLAN [14], ETYPE [15] */
4192+ printk("\t\t\tMRD = %d, EOSP = %d,\
4193+ RMVL = %d, VLAN = %d, ETYP = %d\n",
4194+ (txd->txd_1 & MT_TXD1_MRD) ? 1 : 0,
4195+ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
4196+ (txd->txd_1 & MT_TXD1_RMVL) ? 1 : 0,
4197+ (txd->txd_1 & MT_TXD1_VLAN) ? 1 : 0,
4198+ (txd->txd_1 & MT_TXD1_ETYP) ? 1 : 0);
4199+ break;
4200+ case TMI_HDR_FT_NOR_80211:
4201+ /* HEADER_LENGTH [15:11] */
4202+ printk("\t\t\tHeader Len = %ld(WORD)\n", FIELD_GET(MT_TXD1_HDR_INFO, txd->txd_1));
4203+ break;
4204+
4205+ case TMI_HDR_FT_ENH_80211:
4206+ /* EOSP [12], AMS [13] */
4207+ printk("\t\t\tEOSP = %d, AMS = %d\n",
4208+ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
4209+ (txd->txd_1 & MT_TXD1_AMS) ? 1 : 0);
4210+ break;
4211+ }
4212+
4213+ /* Header Padding [19:18] */
4214+ printk("\t\tHdrPad = %ld\n", FIELD_GET(MT_TXD1_HDR_PAD, txd->txd_1));
4215+
4216+ /* TID [22:20] */
4217+ printk("\t\tTID = %ld\n", FIELD_GET(MT_TXD1_TID, txd->txd_1));
4218+
4219+
4220+ /* UtxB/AMSDU_C/AMSDU [23] */
4221+ printk("\t\tamsdu = %d\n", ((txd->txd_1 & MT_TXD1_AMSDU) ? 1 : 0));
4222+
4223+ /* OM [29:24] */
4224+ printk("\t\town_mac = %ld\n", FIELD_GET(MT_TXD1_OWN_MAC, txd->txd_1));
4225+
4226+
4227+ /* TGID [30] */
4228+ printk("\t\tTGID = %d\n", ((txd->txd_1 & MT_TXD1_TGID) ? 1 : 0));
4229+
4230+
4231+ /* FT [31] */
4232+ printk("\t\tTxDFormatType = %d\n", (txd->txd_1 & MT_TXD1_LONG_FORMAT) ? 1 : 0);
4233+
4234+ printk("\tTMAC_TXD_2:\n");
4235+ /* DW2 */
4236+ /* Subtype [3:0] */
4237+ printk("\t\tsub_type = %ld\n", FIELD_GET(MT_TXD2_SUB_TYPE, txd->txd_2));
4238+
4239+ /* Type[5:4] */
4240+ printk("\t\tfrm_type = %ld\n", FIELD_GET(MT_TXD2_FRAME_TYPE, txd->txd_2));
4241+
4242+ /* NDP [6] */
4243+ printk("\t\tNDP = %d\n", ((txd->txd_2 & MT_TXD2_NDP) ? 1 : 0));
4244+
4245+ /* NDPA [7] */
4246+ printk("\t\tNDPA = %d\n", ((txd->txd_2 & MT_TXD2_NDPA) ? 1 : 0));
4247+
4248+ /* SD [8] */
4249+ printk("\t\tSounding = %d\n", ((txd->txd_2 & MT_TXD2_SOUNDING) ? 1 : 0));
4250+
4251+ /* RTS [9] */
4252+ printk("\t\tRTS = %d\n", ((txd->txd_2 & MT_TXD2_RTS) ? 1 : 0));
4253+
4254+ /* BM [10] */
4255+ printk("\t\tbc_mc_pkt = %d\n", ((txd->txd_2 & MT_TXD2_MULTICAST) ? 1 : 0));
4256+
4257+ /* B [11] */
4258+ printk("\t\tBIP = %d\n", ((txd->txd_2 & MT_TXD2_BIP) ? 1 : 0));
4259+
4260+ /* DU [12] */
4261+ printk("\t\tDuration = %d\n", ((txd->txd_2 & MT_TXD2_DURATION) ? 1 : 0));
4262+
4263+ /* HE [13] */
4264+ printk("\t\tHE(HTC Exist) = %d\n", ((txd->txd_2 & MT_TXD2_HTC_VLD) ? 1 : 0));
4265+
4266+ /* FRAG [15:14] */
4267+ printk("\t\tFRAG = %ld\n", FIELD_GET(MT_TXD2_FRAG, txd->txd_2));
4268+
4269+
4270+ /* Remaining Life Time [23:16]*/
4271+ printk("\t\tReamingLife/MaxTx time = %ld (unit: 64TU)\n",
4272+ FIELD_GET(MT_TXD2_MAX_TX_TIME, txd->txd_2));
4273+
4274+ /* Power Offset [29:24] */
4275+ printk("\t\tpwr_offset = %ld\n", FIELD_GET(MT_TXD2_POWER_OFFSET, txd->txd_2));
4276+
4277+ /* FRM [30] */
4278+ printk("\t\tfix rate mode = %d\n", (txd->txd_2 & MT_TXD2_FIXED_RATE) ? 1 : 0);
4279+
4280+ /* FR[31] */
4281+ printk("\t\tfix rate = %d\n", (txd->txd_2 & MT_TXD2_FIX_RATE) ? 1 : 0);
4282+
4283+
4284+ printk("\tTMAC_TXD_3:\n");
4285+
4286+ /* DW3 */
4287+ /* NA [0] */
4288+ printk("\t\tNoAck = %d\n", (txd->txd_3 & MT_TXD3_NO_ACK) ? 1 : 0);
4289+
4290+ /* PF [1] */
4291+ printk("\t\tPF = %d\n", (txd->txd_3 & MT_TXD3_PROTECT_FRAME) ? 1 : 0);
4292+
4293+ /* EMRD [2] */
4294+ printk("\t\tEMRD = %d\n", (txd->txd_3 & MT_TXD3_EMRD) ? 1 : 0);
4295+
4296+ /* EEOSP [3] */
4297+ printk("\t\tEEOSP = %d\n", (txd->txd_3 & MT_TXD3_EEOSP) ? 1 : 0);
4298+
4299+ /* DAS [4] */
4300+ printk("\t\tda_select = %d\n", (txd->txd_3 & MT_TXD3_DAS) ? 1 : 0);
4301+
4302+ /* TM [5] */
4303+ printk("\t\ttm = %d\n", (txd->txd_3 & MT_TXD3_TIMING_MEASURE) ? 1 : 0);
4304+
4305+ /* TX Count [10:6] */
4306+ printk("\t\ttx_cnt = %ld\n", FIELD_GET(MT_TXD3_TX_COUNT, txd->txd_3));
4307+
4308+ /* Remaining TX Count [15:11] */
4309+ printk("\t\tremain_tx_cnt = %ld\n", FIELD_GET(MT_TXD3_REM_TX_COUNT, txd->txd_3));
4310+
4311+ /* SN [27:16] */
4312+ printk("\t\tsn = %ld\n", FIELD_GET(MT_TXD3_SEQ, txd->txd_3));
4313+
4314+ /* BA_DIS [28] */
4315+ printk("\t\tba dis = %d\n", (txd->txd_3 & MT_TXD3_BA_DISABLE) ? 1 : 0);
4316+
4317+ /* Power Management [29] */
4318+ printk("\t\tpwr_mgmt = 0x%x\n", (txd->txd_3 & MT_TXD3_SW_POWER_MGMT) ? 1 : 0);
4319+
4320+ /* PN_VLD [30] */
4321+ printk("\t\tpn_vld = %d\n", (txd->txd_3 & MT_TXD3_PN_VALID) ? 1 : 0);
4322+
4323+ /* SN_VLD [31] */
4324+ printk("\t\tsn_vld = %d\n", (txd->txd_3 & MT_TXD3_SN_VALID) ? 1 : 0);
4325+
4326+
4327+ /* DW4 */
4328+ printk("\tTMAC_TXD_4:\n");
4329+
4330+ /* PN_LOW [31:0] */
4331+ printk("\t\tpn_low = 0x%lx\n", FIELD_GET(MT_TXD4_PN_LOW, txd->txd_4));
4332+
4333+
4334+ /* DW5 */
4335+ printk("\tTMAC_TXD_5:\n");
4336+
4337+ /* PID [7:0] */
4338+ printk("\t\tpid = %ld\n", FIELD_GET(MT_TXD5_PID, txd->txd_5));
4339+
4340+ /* TXSFM [8] */
4341+ printk("\t\ttx_status_fmt = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_FMT) ? 1 : 0);
4342+
4343+ /* TXS2M [9] */
4344+ printk("\t\ttx_status_2_mcu = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_MCU) ? 1 : 0);
4345+
4346+ /* TXS2H [10] */
4347+ printk("\t\ttx_status_2_host = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_HOST) ? 1 : 0);
4348+
4349+ /* ADD_BA [14] */
4350+ printk("\t\tADD_BA = %d\n", (txd->txd_5 & MT_TXD5_ADD_BA) ? 1 : 0);
4351+
4352+ /* MD [15] */
4353+ printk("\t\tMD = %d\n", (txd->txd_5 & MT_TXD5_MD) ? 1 : 0);
4354+
4355+ /* PN_HIGH [31:16] */
4356+ printk("\t\tpn_high = 0x%lx\n", FIELD_GET(MT_TXD5_PN_HIGH, txd->txd_5));
4357+
4358+ /* DW6 */
4359+ printk("\tTMAC_TXD_6:\n");
4360+
4361+ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4362+ /* Fixed BandWidth mode [2:0] */
developer2aa1e642022-12-19 11:33:22 +08004363+ printk("\t\tbw = %ld\n",
4364+ FIELD_GET(MT_TXD6_BW, txd->txd_6) | (txd->txd_6 & MT_TXD6_FIXED_BW));
developer3fa816c2022-04-19 10:21:20 +08004365+
4366+ /* DYN_BW [3] */
4367+ printk("\t\tdyn_bw = %d\n", (txd->txd_6 & MT_TXD6_DYN_BW) ? 1 : 0);
4368+
4369+ /* ANT_ID [7:4] */
4370+ printk("\t\tant_id = %ld\n", FIELD_GET(MT_TXD6_ANT_ID, txd->txd_6));
4371+
4372+ /* SPE_IDX_SEL [10] */
4373+ printk("\t\tspe_idx_sel = %d\n", (txd->txd_6 & MT_TXD6_SPE_ID_IDX) ? 1 : 0);
4374+
4375+ /* LDPC [11] */
4376+ printk("\t\tldpc = %d\n", (txd->txd_6 & MT_TXD6_LDPC) ? 1 : 0);
4377+
4378+ /* HELTF Type[13:12] */
4379+ printk("\t\tHELTF Type = %ld\n", FIELD_GET(MT_TXD6_HELTF, txd->txd_6));
4380+
4381+ /* GI Type [15:14] */
4382+ printk("\t\tGI = %ld\n", FIELD_GET(MT_TXD6_SGI, txd->txd_6));
4383+
4384+ /* Rate to be Fixed [29:16] */
4385+ printk("\t\ttx_rate = 0x%lx\n", FIELD_GET(MT_TXD6_TX_RATE, txd->txd_6));
4386+ }
4387+
4388+ /* TXEBF [30] */
4389+ printk("\t\ttxebf = %d\n", (txd->txd_6 & MT_TXD6_TX_EBF) ? 1 : 0);
4390+
4391+ /* TXIBF [31] */
4392+ printk("\t\ttxibf = %d\n", (txd->txd_6 & MT_TXD6_TX_IBF) ? 1 : 0);
4393+
4394+ /* DW7 */
4395+ printk("\tTMAC_TXD_7:\n");
4396+
4397+ if ((txd->txd_1 & MT_TXD1_VTA) == 0) {
4398+ /* SW Tx Time [9:0] */
4399+ printk("\t\tsw_tx_time = %ld\n", FIELD_GET(MT_TXD7_TX_TIME, txd->txd_7));
4400+ } else {
4401+ /* TXD Arrival Time [9:0] */
4402+ printk("\t\tat = %ld\n", FIELD_GET(MT_TXD7_TAT, txd->txd_7));
4403+ }
4404+
4405+ /* HW_AMSDU_CAP [10] */
4406+ printk("\t\thw amsdu cap = %d\n",(txd->txd_7 & MT_TXD7_HW_AMSDU) ? 1 : 0);
4407+
4408+ /* SPE_IDX [15:11] */
4409+ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4410+ printk("\t\tspe_idx = 0x%lx\n", FIELD_GET(MT_TXD7_SPE_IDX, txd->txd_7));
4411+ }
4412+
4413+ /* PSE_FID [27:16] */
4414+ printk("\t\tpse_fid = 0x%lx\n", FIELD_GET(MT_TXD7_PSE_FID, txd->txd_7));
4415+
4416+ /* Subtype [19:16] */
4417+ printk("\t\tpp_sub_type=%ld\n", FIELD_GET(MT_TXD7_SUB_TYPE, txd->txd_7));
4418+
4419+ /* Type [21:20] */
4420+ printk("\t\tpp_type=%ld\n", FIELD_GET(MT_TXD7_TYPE, txd->txd_7));
4421+
4422+ /* CTXD_CNT [25:23] */
4423+ printk("\t\tctxd cnt=0x%lx\n", FIELD_GET(MT_TXD7_CTXD_CNT, txd->txd_7));
4424+
4425+ /* CTXD [26] */
4426+ printk("\t\tctxd = %d\n", (txd->txd_7 & MT_TXD7_CTXD) ? 1 : 0);
4427+
4428+ /* I [28] */
4429+ printk("\t\ti = %d\n", (txd->txd_7 & MT_TXD7_IP_SUM) ? 1 : 0);
4430+
4431+ /* UT [29] */
4432+ printk("\t\tUT = %d\n", (txd->txd_7 & MT_TXD7_UDP_TCP_SUM) ? 1 : 0);
4433+
4434+ /* TXDLEN [31:30] */
4435+ printk("\t\t txd len= %ld\n", FIELD_GET(MT_TXD7_TXD_LEN, txd->txd_7));
4436+}
4437+
4438+
4439+static int mt7915_token_txd_read(struct seq_file *s, void *data)
4440+{
4441+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4442+ struct mt76_txwi_cache *t;
4443+ u8* txwi;
4444+
4445+ seq_printf(s, "\n");
4446+ spin_lock_bh(&dev->mt76.token_lock);
4447+
4448+ t = idr_find(&dev->mt76.token, dev->dbg.token_idx);
4449+
developer3fa816c2022-04-19 10:21:20 +08004450+ if (t != NULL) {
4451+ struct mt76_dev *mdev = &dev->mt76;
4452+ txwi = ((u8*)(t)) - (mdev->drv->txwi_size);
4453+ mt7915_dump_tmac_info((u8*) txwi);
4454+ seq_printf(s, "\n");
4455+ printk("[SKB]\n");
4456+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)t->skb->data, t->skb->len, false);
4457+ seq_printf(s, "\n");
4458+ }
developerdfb50982023-09-11 13:34:36 +08004459+ spin_unlock_bh(&dev->mt76.token_lock);
developer3fa816c2022-04-19 10:21:20 +08004460+ return 0;
4461+}
4462+
4463+static int mt7915_amsduinfo_read(struct seq_file *s, void *data)
4464+{
4465+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4466+ u32 ple_stat[8] = {0}, total_amsdu = 0;
4467+ u8 i;
4468+
4469+ for (i = 0; i < 8; i++)
4470+ ple_stat[i] = mt76_rr(dev, MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(i));
4471+
4472+ seq_printf(s, "TXD counter status of MSDU:\n");
4473+
4474+ for (i = 0; i < 8; i++)
4475+ total_amsdu += ple_stat[i];
4476+
4477+ for (i = 0; i < 8; i++) {
4478+ seq_printf(s, "AMSDU pack count of %d MSDU in TXD: 0x%x ", i + 1, ple_stat[i]);
4479+ if (total_amsdu != 0)
4480+ seq_printf(s, "(%d%%)\n", ple_stat[i] * 100 / total_amsdu);
4481+ else
4482+ seq_printf(s, "\n");
4483+ }
4484+
4485+ return 0;
4486+
4487+}
4488+
4489+static int mt7915_agginfo_read_per_band(struct seq_file *s, int band_idx)
4490+{
4491+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4492+ u32 value, idx, agg_rang_sel[15], ampdu_cnt[11], total_ampdu = 0;
4493+
4494+ seq_printf(s, "Band %d AGG Status\n", band_idx);
4495+ seq_printf(s, "===============================\n");
4496+ value = mt76_rr(dev, MT_DBG_AGG_AALCR0(band_idx));
4497+ seq_printf(s, "AC00 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4498+ seq_printf(s, "AC01 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4499+ seq_printf(s, "AC02 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4500+ seq_printf(s, "AC03 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4501+
4502+ value = mt76_rr(dev, MT_DBG_AGG_AALCR1(band_idx));
4503+ seq_printf(s, "AC10 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4504+ seq_printf(s, "AC11 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4505+ seq_printf(s, "AC12 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4506+ seq_printf(s, "AC13 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4507+
4508+ value = mt76_rr(dev, MT_DBG_AGG_AALCR2(band_idx));
4509+ seq_printf(s, "AC20 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4510+ seq_printf(s, "AC21 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4511+ seq_printf(s, "AC22 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4512+ seq_printf(s, "AC23 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4513+
4514+ value = mt76_rr(dev, MT_DBG_AGG_AALCR3(band_idx));
4515+ seq_printf(s, "AC30 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4516+ seq_printf(s, "AC31 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4517+ seq_printf(s, "AC32 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4518+ seq_printf(s, "AC33 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4519+
4520+ value = mt76_rr(dev, MT_DBG_AGG_AALCR4(band_idx));
4521+ seq_printf(s, "ALTX Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK, value));
4522+
4523+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 0));
4524+ seq_printf(s, "Winsize0 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE0_MASK, value));
4525+ seq_printf(s, "Winsize1 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE1_MASK, value));
4526+ seq_printf(s, "Winsize2 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE2_MASK, value));
4527+ seq_printf(s, "Winsize3 limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE3_MASK, value));
4528+
4529+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 1));
4530+ seq_printf(s, "Winsize4 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE4_MASK, value));
4531+ seq_printf(s, "Winsize5 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE5_MASK, value));
4532+ seq_printf(s, "Winsize6 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE6_MASK, value));
4533+ seq_printf(s, "Winsize7 limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE7_MASK, value));
4534+
4535+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 2));
4536+ seq_printf(s, "Winsize8 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZE8_MASK, value));
4537+ seq_printf(s, "Winsize9 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZE9_MASK, value));
4538+ seq_printf(s, "WinsizeA limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZEA_MASK, value));
4539+ seq_printf(s, "WinsizeB limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZEB_MASK, value));
4540+
4541+
4542+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 3));
4543+ seq_printf(s, "WinsizeC limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZEC_MASK, value));
4544+ seq_printf(s, "WinsizeD limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZED_MASK, value));
4545+ seq_printf(s, "WinsizeE limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZEE_MASK, value));
4546+
4547+ seq_printf(s, "===AMPDU Related Counters===\n");
4548+
4549+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 0));
4550+ agg_rang_sel[0] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK, value);
4551+ agg_rang_sel[1] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK, value);
4552+ agg_rang_sel[2] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK, value);
4553+ agg_rang_sel[3] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK, value);
4554+
4555+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 1));
4556+ agg_rang_sel[4] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK, value);
4557+ agg_rang_sel[5] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK, value);
4558+ agg_rang_sel[6] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK, value);
4559+ agg_rang_sel[7] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK, value);
4560+
4561+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 2));
4562+ agg_rang_sel[8] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK, value);
4563+ agg_rang_sel[9] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK, value);
4564+ agg_rang_sel[10] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK, value);
4565+ agg_rang_sel[11] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK, value);
4566+
4567+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 3));
4568+ agg_rang_sel[12] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK, value);
4569+ agg_rang_sel[13] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK, value);
4570+ agg_rang_sel[14] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK, value);
4571+
4572+ /* Need to add 1 after read from AGG_RANG_SEL CR */
4573+ for (idx = 0; idx < 15; idx++)
4574+ agg_rang_sel[idx]++;
4575+
4576+ ampdu_cnt[3] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 0));
4577+ ampdu_cnt[4] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 1));
4578+ ampdu_cnt[5] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 2));
4579+ ampdu_cnt[6] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 3));
4580+ ampdu_cnt[7] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 0));
4581+ ampdu_cnt[8] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 1));
4582+ ampdu_cnt[9] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 2));
4583+ ampdu_cnt[10] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 3));
4584+
4585+ seq_printf(s, "\tTx Agg Range: \t%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d\n",
4586+ agg_rang_sel[0],
4587+ agg_rang_sel[0] + 1, agg_rang_sel[1],
4588+ agg_rang_sel[1] + 1, agg_rang_sel[2],
4589+ agg_rang_sel[2] + 1, agg_rang_sel[3],
4590+ agg_rang_sel[3] + 1, agg_rang_sel[4],
4591+ agg_rang_sel[4] + 1, agg_rang_sel[5],
4592+ agg_rang_sel[5] + 1, agg_rang_sel[6],
4593+ agg_rang_sel[6] + 1, agg_rang_sel[7]);
4594+
4595+#define BIT_0_to_15_MASK 0x0000FFFF
4596+#define BIT_15_to_31_MASK 0xFFFF0000
4597+#define SHFIT_16_BIT 16
4598+
4599+ for (idx = 3; idx < 11; idx++)
4600+ total_ampdu = total_ampdu + (ampdu_cnt[idx] & BIT_0_to_15_MASK) + ((ampdu_cnt[idx] & BIT_15_to_31_MASK) >> SHFIT_16_BIT);
4601+
4602+ seq_printf(s, "\t\t\t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx\n",
4603+ (ampdu_cnt[3]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK,
4604+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[3]),
4605+ (ampdu_cnt[4]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK,
4606+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[4]),
4607+ (ampdu_cnt[5]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK,
4608+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[5]),
4609+ (ampdu_cnt[6]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK,
4610+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[6]));
4611+
4612+ if (total_ampdu != 0) {
4613+ seq_printf(s, "\t\t\t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%)\n",
4614+ ((ampdu_cnt[3]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK) * 100 / total_ampdu,
4615+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[3]) * 100 / total_ampdu,
4616+ ((ampdu_cnt[4]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK) * 100 / total_ampdu,
4617+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[4]) * 100 / total_ampdu,
4618+ ((ampdu_cnt[5]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK) * 100 / total_ampdu,
4619+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[5]) * 100 / total_ampdu,
4620+ ((ampdu_cnt[6]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK) * 100 / total_ampdu,
4621+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[6]) * 100 / total_ampdu);
4622+ }
4623+
4624+ seq_printf(s, "\t\t\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~256\n",
4625+ agg_rang_sel[7] + 1, agg_rang_sel[8],
4626+ agg_rang_sel[8] + 1, agg_rang_sel[9],
4627+ agg_rang_sel[9] + 1, agg_rang_sel[10],
4628+ agg_rang_sel[10] + 1, agg_rang_sel[11],
4629+ agg_rang_sel[11] + 1, agg_rang_sel[12],
4630+ agg_rang_sel[12] + 1, agg_rang_sel[13],
4631+ agg_rang_sel[13] + 1, agg_rang_sel[14],
4632+ agg_rang_sel[14] + 1);
4633+
4634+ seq_printf(s, "\t\t\t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx\n",
4635+ (ampdu_cnt[7]) & MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK,
4636+ FIELD_GET(MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK, ampdu_cnt[7]),
4637+ (ampdu_cnt[8]) & MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK,
4638+ FIELD_GET(MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK, ampdu_cnt[8]),
4639+ (ampdu_cnt[9]) & MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK,
4640+ FIELD_GET(MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK, ampdu_cnt[9]),
4641+ (ampdu_cnt[10]) & MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK,
4642+ FIELD_GET(MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK, ampdu_cnt[10]));
4643+
4644+ if (total_ampdu != 0) {
4645+ seq_printf(s, "\t\t\t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%)\n",
4646+ ((ampdu_cnt[7]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK) * 100 / total_ampdu,
4647+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[7]) * 100 / total_ampdu,
4648+ ((ampdu_cnt[8]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK) * 100 / total_ampdu,
4649+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[8]) * 100 / total_ampdu,
4650+ ((ampdu_cnt[9]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK) * 100 / total_ampdu,
4651+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[9]) * 100 / total_ampdu,
4652+ ((ampdu_cnt[10]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK) * 100 / total_ampdu,
4653+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[10]) * 100 / total_ampdu);
4654+ }
4655+
4656+ return 0;
4657+}
4658+
4659+static int mt7915_agginfo_read_band0(struct seq_file *s, void *data)
4660+{
4661+ mt7915_agginfo_read_per_band(s, 0);
4662+ return 0;
4663+}
4664+
4665+static int mt7915_agginfo_read_band1(struct seq_file *s, void *data)
4666+{
4667+ mt7915_agginfo_read_per_band(s, 1);
4668+ return 0;
4669+}
4670+
4671+/*usage: <en> <num> <len>
4672+ en: BIT(16) 0: sw amsdu 1: hw amsdu
4673+ num: GENMASK(15, 8) range 1-8
4674+ len: GENMASK(7, 0) unit: 256 bytes */
4675+static int mt7915_sta_tx_amsdu_set(void *data, u64 tx_amsdu)
4676+{
4677+/* UWTBL DW 6 */
4678+#define WTBL_AMSDU_LEN_MASK GENMASK(5, 0)
4679+#define WTBL_AMSDU_NUM_MASK GENMASK(8, 6)
4680+#define WTBL_AMSDU_EN_MASK BIT(9)
4681+#define UWTBL_HW_AMSDU_DW 6
4682+
4683+ struct mt7915_dev *dev = data;
4684+ u32 len = FIELD_GET(GENMASK(7, 0), tx_amsdu);
4685+ u32 num = FIELD_GET(GENMASK(15, 8), tx_amsdu);
4686+ u32 uwtbl;
4687+
developer9e5bcc52022-09-27 10:30:15 +08004688+ mt7915_mcu_set_amsdu_algo(dev, dev->wlan_idx, 0);
4689+
developer3fa816c2022-04-19 10:21:20 +08004690+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC,
4691+ UWTBL_HW_AMSDU_DW, 1, &uwtbl);
4692+
4693+ if (len) {
4694+ uwtbl &= ~WTBL_AMSDU_LEN_MASK;
4695+ uwtbl |= FIELD_PREP(WTBL_AMSDU_LEN_MASK, len);
4696+ }
4697+
4698+ uwtbl &= ~WTBL_AMSDU_NUM_MASK;
4699+ uwtbl |= FIELD_PREP(WTBL_AMSDU_NUM_MASK, num);
4700+
4701+ if (tx_amsdu & BIT(16))
4702+ uwtbl |= WTBL_AMSDU_EN_MASK;
4703+
4704+ mt7915_wtbl_write_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC,
4705+ UWTBL_HW_AMSDU_DW, uwtbl);
4706+
4707+ return 0;
4708+}
4709+
4710+DEFINE_DEBUGFS_ATTRIBUTE(fops_tx_amsdu, NULL,
4711+ mt7915_sta_tx_amsdu_set, "%llx\n");
4712+
4713+static int mt7915_red_enable_set(void *data, u64 en)
4714+{
4715+ struct mt7915_dev *dev = data;
4716+
4717+ return mt7915_mcu_set_red(dev, en);
4718+}
4719+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_en, NULL,
4720+ mt7915_red_enable_set, "%llx\n");
4721+
4722+static int mt7915_red_show_sta_set(void *data, u64 wlan_idx)
4723+{
4724+ struct mt7915_dev *dev = data;
4725+
4726+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
4727+ MCU_WA_PARAM_RED_SHOW_STA,
4728+ wlan_idx, 0, true);
4729+
4730+ return 0;
4731+}
4732+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_show_sta, NULL,
4733+ mt7915_red_show_sta_set, "%llx\n");
4734+
4735+static int mt7915_red_target_dly_set(void *data, u64 delay)
4736+{
4737+ struct mt7915_dev *dev = data;
4738+
4739+ if (delay > 0 && delay <= 32767)
4740+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
4741+ MCU_WA_PARAM_RED_TARGET_DELAY,
4742+ delay, 0, true);
4743+
4744+ return 0;
4745+}
4746+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_target_dly, NULL,
4747+ mt7915_red_target_dly_set, "%llx\n");
4748+
4749+static int
4750+mt7915_txpower_level_set(void *data, u64 val)
4751+{
4752+ struct mt7915_dev *dev = data;
4753+ struct mt7915_phy *ext_phy = mt7915_ext_phy(dev);
4754+ mt7915_mcu_set_txpower_level(&dev->phy, val);
4755+ if (ext_phy)
4756+ mt7915_mcu_set_txpower_level(ext_phy, val);
4757+
4758+ return 0;
4759+}
4760+
4761+DEFINE_DEBUGFS_ATTRIBUTE(fops_txpower_level, NULL,
4762+ mt7915_txpower_level_set, "%lld\n");
4763+
4764+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_set */
4765+static int
4766+mt7915_wa_set(void *data, u64 val)
4767+{
4768+ struct mt7915_dev *dev = data;
4769+ u32 arg1, arg2, arg3;
4770+
4771+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
4772+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
4773+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
4774+
4775+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), arg1, arg2, arg3, false);
4776+
4777+ return 0;
4778+}
4779+
4780+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_set, NULL, mt7915_wa_set,
4781+ "0x%llx\n");
4782+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_query */
4783+static int
4784+mt7915_wa_query(void *data, u64 val)
4785+{
4786+ struct mt7915_dev *dev = data;
4787+ u32 arg1, arg2, arg3;
4788+
4789+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
4790+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
4791+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
4792+
4793+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY), arg1, arg2, arg3, false);
4794+
4795+ return 0;
4796+}
4797+
4798+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_query, NULL, mt7915_wa_query,
4799+ "0x%llx\n");
4800+/* set wa debug level
4801+ usage:
4802+ echo 0x[arg] > fw_wa_debug
4803+ bit0 : DEBUG_WIFI_TX
4804+ bit1 : DEBUG_CMD_EVENT
4805+ bit2 : DEBUG_RED
4806+ bit3 : DEBUG_WARN
4807+ bit4 : DEBUG_WIFI_RX
4808+ bit5 : DEBUG_TIME_STAMP
4809+ bit6 : DEBUG_TX_FREE_DONE_EVENT
4810+ bit12 : DEBUG_WIFI_TXD */
4811+static int
4812+mt7915_wa_debug(void *data, u64 val)
4813+{
4814+ struct mt7915_dev *dev = data;
4815+ u32 arg;
4816+
4817+ arg = FIELD_GET(GENMASK_ULL(15, 0), val);
4818+
4819+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(DEBUG), arg, 0, 0, false);
4820+
4821+ return 0;
4822+}
4823+
4824+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_debug, NULL, mt7915_wa_debug,
4825+ "0x%llx\n");
4826+
developer8e5fecd2023-05-30 11:58:00 +08004827+static int mt7915_dump_version(struct seq_file *s, void *data)
4828+{
4829+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4830+ struct mt76_dev *mdev = NULL;
developere35b8e42023-10-16 11:04:00 +08004831+ seq_printf(s, "Version: 2.2.14.0\n");
developer8e5fecd2023-05-30 11:58:00 +08004832+
4833+ if (!test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state))
4834+ return 0;
4835+
4836+ mdev = &dev->mt76;
4837+ seq_printf(s, "Rom Patch Build Time: %.16s\n", mdev->patch_hdr->build_date);
4838+ seq_printf(s, "WM Patch Build Time: %.16s\n", mdev->wm_hdr->build_date);
4839+ seq_printf(s, "WA Patch Build Time: %.16s\n", mdev->wa_hdr->build_date);
4840+ return 0;
4841+}
4842+
developera43cc482023-04-17 15:57:28 +08004843+static inline int mt7915_snprintf_error(size_t size, int res)
4844+{
4845+ return res < 0 || (unsigned int) res >= size;
4846+}
4847+
4848+static void mt7915_show_lp_history(struct seq_file *s, bool fgIsExp)
4849+{
4850+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4851+ u32 macVal = 0, gpr_log_idx = 0, oldest_idx = 0;
4852+ u32 idx = 0, i = 0;
4853+
4854+ if (!fgIsExp) {
4855+ /* disable LP recored */
4856+ macVal = mt76_rr(dev, 0x89050200);
4857+ macVal &= (~0x1);
4858+ mt76_wr(dev, 0x89050200, macVal);
4859+ udelay(100);
4860+ }
4861+
4862+ macVal = 0;
4863+ macVal = mt76_rr(dev, 0x89050200);
4864+ gpr_log_idx = ((macVal >> 16) & 0x1f);
4865+ oldest_idx = gpr_log_idx + 2;
4866+
4867+ seq_printf(s, " lp history (from old to new):\n");
4868+ for (i = 0; i < 16; i++) {
4869+ idx = ((oldest_idx + 2*i + 1)%32);
4870+ macVal = mt76_rr(dev, (0x89050204 + idx*4));
4871+ seq_printf(s, " %d: 0x%x\n", i, macVal);
4872+ }
4873+
4874+ if (!fgIsExp) {
4875+ /* enable LP recored */
4876+ macVal = mt76_rr(dev, 0x89050200);
4877+ macVal |= 0x1;
4878+ mt76_wr(dev, 0x89050200, macVal);
4879+ }
4880+}
4881+
4882+static void mt7915_show_irq_history(struct seq_file *s)
4883+{
4884+#define SYSIRQ_INTERRUPT_HISTORY_NUM 10
4885+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4886+ u32 macVal = 0;
4887+ u32 i = 0;
4888+ u32 start = 0;
4889+ u32 idx = 0;
4890+ u8 ucIrqDisIdx = 0;
4891+ u8 ucIrqResIdx = 0;
4892+ u32 irq_dis_time[10];
4893+ u32 irq_dis_lp[10];
4894+ u32 irq_res_time[10];
4895+ u32 irq_res_lp[10];
4896+
4897+ macVal = 0;
4898+ macVal = mt76_rr(dev, 0x022051C0);
4899+ ucIrqResIdx = (macVal & 0xff);
4900+ ucIrqDisIdx = ((macVal >> 8) & 0xff);
4901+
4902+ seq_printf(s, "\n\n\n Irq Idx (Dis=%d Res=%d):\n",
4903+ ucIrqDisIdx, ucIrqResIdx);
4904+
4905+ start = mt76_rr(dev, 0x022051C8);
4906+ for (i = 0; i < SYSIRQ_INTERRUPT_HISTORY_NUM; i++) {
4907+ macVal = mt76_rr(dev, (start + (i * 8)));
4908+ irq_dis_time[i] = macVal;
4909+ macVal = mt76_rr(dev, (start + (i * 8) + 4));
4910+ irq_dis_lp[i] = macVal;
4911+ }
4912+
4913+ start = mt76_rr(dev, 0x022051C4);
4914+
4915+ for (i = 0; i < SYSIRQ_INTERRUPT_HISTORY_NUM; i++) {
4916+ macVal = mt76_rr(dev, (start + (i * 8)));
4917+ irq_res_time[i] = macVal;
4918+ macVal = mt76_rr(dev, (start + (i * 8) + 4));
4919+ irq_res_lp[i] = macVal;
4920+ }
4921+
4922+ seq_printf(s, "\n Dis Irq history (from old to new):\n");
4923+ for (i = 0; i < SYSIRQ_INTERRUPT_HISTORY_NUM; i++) {
4924+ idx = (i + ucIrqDisIdx) % SYSIRQ_INTERRUPT_HISTORY_NUM;
4925+ seq_printf(s, " [%d].LP = 0x%x time=%u\n",
4926+ idx, irq_dis_lp[idx], irq_dis_time[idx]);
4927+ }
4928+
4929+ seq_printf(s, "\n Restore Irq history (from old to new):\n");
4930+ for (i = 0; i < SYSIRQ_INTERRUPT_HISTORY_NUM; i++) {
4931+ idx = (i + ucIrqResIdx) % SYSIRQ_INTERRUPT_HISTORY_NUM;
4932+ seq_printf(s, " [%d].LP = 0x%x time=%u\n",
4933+ idx, irq_res_lp[idx], irq_res_time[idx]);
4934+ }
4935+}
4936+
4937+static void MemSectionRead(struct mt7915_dev *dev, char *buf, u32 length, u32 addr)
4938+{
4939+ int idx = 0;
4940+ u32 *ptr =(u32 *)buf;
4941+
4942+ while (idx < length) {
4943+ *ptr = mt76_rr(dev, (addr + idx));
4944+ idx += 4;
4945+ ptr++;
4946+ }
4947+}
4948+
4949+static void mt7915_show_msg_trace(struct seq_file *s)
4950+{
4951+#define MSG_HISTORY_NUM 64
4952+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4953+ struct cos_msg_trace_t *msg_trace = NULL;
4954+ u32 ptr_addr = 0;
4955+ u32 length = 0;
developer004e50c2023-06-29 20:33:22 +08004956+ u32 idx = 0;
developera43cc482023-04-17 15:57:28 +08004957+ u32 cnt = 0;
4958+ u32 msg_history_num = 0;
4959+
4960+ msg_trace = kmalloc(MSG_HISTORY_NUM * sizeof(struct cos_msg_trace_t), GFP_KERNEL);
4961+ if (!msg_trace) {
4962+ seq_printf(s, "can not allocate cmd msg_trace\n");
4963+ return;
4964+ }
4965+
4966+ memset(msg_trace, 0, MSG_HISTORY_NUM * sizeof(struct cos_msg_trace_t));
4967+
4968+ ptr_addr = mt76_rr(dev, 0x02205188);
4969+ msg_history_num = mt76_rr(dev, 0x0220518C);
4970+
4971+ idx = (msg_history_num >> 8) & 0xff;
4972+ msg_history_num = msg_history_num & 0xff;
4973+
4974+ if (idx >= msg_history_num) {
4975+ kfree(msg_trace);
4976+ return;
4977+ }
4978+
4979+ length = msg_history_num * sizeof(struct cos_msg_trace_t);
4980+ MemSectionRead(dev, (char *)&(msg_trace[0]), length, ptr_addr);
4981+ seq_printf(s,"\n");
4982+ seq_printf(s, " msg trace:\n");
4983+ seq_printf(s, " format: t_id=task_id/task_prempt_cnt/msg_read_idx\n");
4984+
4985+ while (1) {
4986+ seq_printf(s, " (m_%d)t_id=%x/%d/%d, m_id=%d, ts_en=%u, ts_de = %u, ts_fin=%u, wait=%d, exe=%d\n",
4987+ idx,
4988+ msg_trace[idx].dest_id,
4989+ msg_trace[idx].pcount,
4990+ msg_trace[idx].qread,
4991+ msg_trace[idx].msg_id,
4992+ msg_trace[idx].ts_enq,
4993+ msg_trace[idx].ts_deq,
4994+ msg_trace[idx].ts_finshq,
4995+ (msg_trace[idx].ts_deq - msg_trace[idx].ts_enq),
4996+ (msg_trace[idx].ts_finshq - msg_trace[idx].ts_deq));
4997+
4998+ if (++idx >= msg_history_num)
4999+ idx = 0;
5000+
5001+ if (++cnt >= msg_history_num)
5002+ break;
5003+ }
5004+ if (msg_trace)
5005+ kfree(msg_trace);
5006+}
5007+
5008+static int mt7915_show_assert_line(struct seq_file *s)
5009+{
5010+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
5011+ char *msg;
5012+ u32 addr;
5013+ u32 macVal = 0;
5014+ char *ptr;
5015+ char idx;
5016+
5017+ msg = kmalloc(256, GFP_KERNEL);
5018+ if (!msg)
5019+ return 0;
5020+
5021+ memset(msg, 0, 256);
5022+ addr = 0x00400000;
5023+ ptr = msg;
5024+ for (idx = 0 ; idx < 32; idx++) {
5025+ macVal = 0;
5026+ macVal = mt76_rr(dev, addr);
5027+ memcpy(ptr, &macVal, 4);
5028+ addr += 4;
5029+ ptr += 4;
5030+ }
5031+
5032+ *ptr = 0;
5033+ seq_printf(s,"\n\n");
5034+ seq_printf(s," Assert line\n");
5035+ seq_printf(s," %s\n", msg);
5036+ if (msg)
5037+ kfree(msg);
5038+
5039+ return 0;
5040+}
5041+
5042+
5043+static void mt7915_show_sech_trace(struct seq_file *s)
5044+{
5045+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
5046+ struct cos_task_info_struct task_info_g[2];
5047+ u32 length = 0, i = 0;
5048+ u32 idx = 0;
5049+ u32 km_total_time = 0;
5050+ u32 addr = 0;
5051+ struct cos_task_type tcb;
5052+ struct cos_task_type *tcb_ptr;
5053+ char name[2][15] = {
5054+ "WIFI ", "WIFI2 "
5055+ };
5056+
5057+ length = 2 * sizeof(struct cos_task_info_struct);
5058+ MemSectionRead(dev, (char *)&(task_info_g[0]), length, 0x02202A18);
5059+
5060+ /*while(i < length) {
5061+ task_info_g[i] = mt76_rr(dev, 0x02202A18 + i * 0x4);
5062+ i++;
5063+ }*/
5064+ km_total_time = mt76_rr(dev, 0x022051B4);
5065+ if (km_total_time == 0) {
5066+ seq_printf(s, "km_total_time zero!\n");
5067+ return;
5068+ }
5069+
5070+ seq_printf(s,"\n\n\n TASK XTIME RATIO PREMPT CNT\n");
5071+ for (idx = 0 ; idx < 2 ; idx++) {
5072+ addr = task_info_g[idx].task_id;
5073+ i = 0;
5074+ MemSectionRead(dev, (char *)&(tcb), sizeof(struct cos_task_type), addr);
5075+
5076+ length = sizeof(struct cos_task_type);
5077+
5078+ tcb_ptr = &(tcb);
5079+
5080+ if (tcb_ptr) {
5081+ seq_printf(s, " %s %d %d %d\n",
5082+ name[idx],
5083+ tcb_ptr->tc_exe_time,
5084+ (tcb_ptr->tc_exe_time*100/km_total_time),
5085+ tcb_ptr->tc_pcount);
5086+ }
5087+ }
5088+
5089+}
5090+
5091+static void mt7915_show_prog_trace(struct seq_file *s)
5092+{
5093+#define PROGRAM_TRACE_HISTORY_NUM 32
5094+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
5095+ struct cos_program_trace_t *cos_program_trace_ptr = NULL;
5096+ u32 trace_ptr = 0;
developer004e50c2023-06-29 20:33:22 +08005097+ u32 idx = 0;
developera43cc482023-04-17 15:57:28 +08005098+ u32 old_idx = 0;
5099+ u32 old_idx_addr = 0;
5100+ u32 prev_idx = 0;
5101+ u32 prev_time = 0;
5102+ u32 curr_time = 0;
5103+ u32 diff = 0;
developer004e50c2023-06-29 20:33:22 +08005104+ //u32 length = 0, i = 0;
developera43cc482023-04-17 15:57:28 +08005105+
5106+ cos_program_trace_ptr = kmalloc(PROGRAM_TRACE_HISTORY_NUM * sizeof(struct cos_program_trace_t), GFP_KERNEL);
5107+ if (!cos_program_trace_ptr) {
5108+ seq_printf(s, "can not allocate cos_program_trace_ptr memory\n");
5109+ return;
5110+ }
5111+ memset(cos_program_trace_ptr, 0, PROGRAM_TRACE_HISTORY_NUM * sizeof(struct cos_program_trace_t));
5112+
5113+ trace_ptr = mt76_rr(dev, 0x0220514C);
5114+ old_idx_addr = mt76_rr(dev, 0x02205148);
5115+
5116+ old_idx = (old_idx_addr >> 8) & 0xff;
5117+
5118+ MemSectionRead(dev, (char *)&cos_program_trace_ptr[0], PROGRAM_TRACE_HISTORY_NUM * sizeof(struct cos_program_trace_t), trace_ptr);
5119+
5120+ /*length = PROGRAM_TRACE_HISTORY_NUM * sizeof(struct cos_program_trace_t);
5121+ while(i < length) {
5122+ cos_program_trace_ptr[i] = mt76_rr(dev, trace_ptr + i * 0x4);
5123+ i++;
5124+ }*/
5125+ seq_printf(s, "\n");
5126+ seq_printf(s, " program trace:\n");
5127+ for (idx = 0 ; idx < PROGRAM_TRACE_HISTORY_NUM ; idx++) {
5128+ prev_idx = ((old_idx + 32 - 1) % 32);
5129+
5130+ seq_printf(s, " (p_%d)t_id=%x/%d, m_id=%d, LP=0x%x, name=%s, ts2=%d, ",
5131+ old_idx,
5132+ cos_program_trace_ptr[old_idx].dest_id,
5133+ cos_program_trace_ptr[old_idx].msg_sn,
5134+ cos_program_trace_ptr[old_idx].msg_id,
5135+ cos_program_trace_ptr[old_idx].LP,
5136+ cos_program_trace_ptr[old_idx].name,
5137+ cos_program_trace_ptr[old_idx].ts_gpt2);
5138+
5139+ /* diff for gpt2 */
5140+ prev_time = cos_program_trace_ptr[prev_idx].ts_gpt2;
5141+ curr_time = cos_program_trace_ptr[old_idx].ts_gpt2;
5142+
5143+ if (prev_time) {
5144+ if ((cos_program_trace_ptr[prev_idx].dest_id == cos_program_trace_ptr[old_idx].dest_id) &&
5145+ (cos_program_trace_ptr[prev_idx].msg_sn == cos_program_trace_ptr[old_idx].msg_sn)) {
5146+ if (curr_time > prev_time)
5147+ diff = curr_time - prev_time;
5148+ else
5149+ diff = 0xFFFFFFFF - prev_time + curr_time + 1;
5150+ } else
5151+ diff = 0xFFFFFFFF;
5152+ } else
5153+ diff = 0xFFFFFFFF;
5154+
5155+ if (diff == 0xFFFFFFFF)
5156+ seq_printf(s, "diff2=NA, \n");
5157+ else
5158+ seq_printf(s, "diff2=%8d\n", diff);
5159+
5160+ old_idx++;
5161+ if (old_idx >= 32)
5162+ old_idx = 0;
5163+ }
5164+ if (cos_program_trace_ptr)
5165+ kfree(cos_program_trace_ptr);
5166+}
5167+
5168+static int mt7915_fw_wm_info_read(struct seq_file *s, void *data)
5169+{
5170+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
5171+ u32 macVal = 0, g_exp_type = 0, COS_Interrupt_Count = 0;
developer004e50c2023-06-29 20:33:22 +08005172+ u8 exp_assert_proc_entry_cnt = 0, exp_assert_state = 0, g_irq_history_num = 0;
developera43cc482023-04-17 15:57:28 +08005173+ u16 processing_irqx = 0;
5174+ u32 processing_lisr = 0, Current_Task_Id = 0, Current_Task_Indx = 0;
5175+ u8 km_irq_info_idx = 0, km_eint_info_idx = 0, km_sched_info_idx = 0, g_sched_history_num = 0;
5176+ u32 km_sched_trace_ptr = 0,km_irq_trace_ptr = 0, km_total_time = 0, TaskStart[3] = {0};
5177+ bool fgIsExp = false, fgIsAssert = false;
5178+ u32 TaskEnd[3] = {0}, exp_assert_state_addr = 0, g1_exp_counter_addr = 0;
5179+ u32 g_exp_type_addr = 0, cos_interrupt_count_addr = 0;
5180+ u32 processing_irqx_addr = 0, processing_lisr_addr = 0;
5181+ u32 Current_Task_Id_addr = 0, Current_Task_Indx_addr = 0, last_dequeued_msg_id_addr = 0;
5182+ u32 km_irq_info_idx_addr = 0, km_eint_info_idx_addr = 0, km_sched_info_idx_addr = 0;
5183+ u32 g_sched_history_num_addr = 0, km_sched_trace_ptr_addr = 0;
5184+ u32 km_irq_trace_ptr_addr = 0, km_total_time_addr = 0, last_dequeued_msg_id = 0;
5185+ u32 i = 0 ,t1 = 0, t2 = 0, t3 = 0;
developer004e50c2023-06-29 20:33:22 +08005186+ u8 idx = 0, str[32], exp_type[64];
developera43cc482023-04-17 15:57:28 +08005187+ int ret;
5188+
5189+ g_exp_type_addr = 0x022050DC;
5190+ exp_assert_state_addr = 0x02204B54;
5191+ g1_exp_counter_addr = 0x02204FFC;
5192+ cos_interrupt_count_addr = 0x022001AC;
5193+ processing_irqx_addr = 0x02204EC4;
5194+ processing_lisr_addr = 0x02205010;
5195+ Current_Task_Id_addr = 0x02204FAC;
5196+ Current_Task_Indx_addr = 0x02204F4C;
5197+ last_dequeued_msg_id_addr = 0x02204F28;
5198+ km_irq_info_idx_addr = 0x0220519C;
5199+ km_eint_info_idx_addr = 0x02205194;
5200+ km_sched_info_idx_addr = 0x022051A4;
5201+ g_sched_history_num_addr = 0x022051A4;
5202+ km_sched_trace_ptr_addr = 0x022051A0;
5203+ km_irq_trace_ptr_addr = 0x02205198;
5204+ km_total_time_addr = 0x022051B4;
5205+
5206+ macVal = 0;
5207+ macVal = mt76_rr(dev, exp_assert_state_addr);
5208+ exp_assert_state = (macVal & 0xff);
5209+
5210+ macVal = 0;
5211+ macVal = mt76_rr(dev, g1_exp_counter_addr);
5212+ exp_assert_proc_entry_cnt = (macVal & 0xff);
5213+
5214+ macVal = 0;
5215+ macVal = mt76_rr(dev, g_exp_type_addr);
5216+ g_exp_type = macVal;
5217+
5218+ macVal = 0;
5219+ macVal = mt76_rr(dev, cos_interrupt_count_addr);
5220+ COS_Interrupt_Count = macVal;
5221+
5222+ macVal = 0;
5223+ macVal = mt76_rr(dev, processing_irqx_addr);
5224+ processing_irqx = (macVal & 0xffff);
5225+
5226+ macVal = 0;
5227+ macVal = mt76_rr(dev, processing_lisr_addr);
5228+ processing_lisr = macVal;
5229+
5230+ macVal = 0;
5231+ macVal = mt76_rr(dev, Current_Task_Id_addr);
5232+ Current_Task_Id = macVal;
5233+
5234+ macVal = 0;
5235+ macVal = mt76_rr(dev, Current_Task_Indx_addr);
5236+ Current_Task_Indx = macVal;
5237+
5238+ macVal = 0;
5239+ macVal = mt76_rr(dev, last_dequeued_msg_id_addr);
5240+ last_dequeued_msg_id = macVal;
5241+
5242+ macVal = 0;
5243+ macVal = mt76_rr(dev, km_eint_info_idx_addr);
5244+ km_eint_info_idx = ((macVal >> 8) & 0xff);
5245+
5246+ macVal = 0;
5247+ macVal = mt76_rr(dev, g_sched_history_num_addr);
5248+ g_sched_history_num = (macVal & 0xff);
5249+ km_sched_info_idx = ((macVal >> 8) & 0xff);
5250+
5251+ macVal = 0;
5252+ macVal = mt76_rr(dev, km_sched_trace_ptr_addr);
5253+ km_sched_trace_ptr = macVal;
5254+
5255+ macVal = 0;
5256+ macVal = mt76_rr(dev, km_irq_info_idx_addr);
5257+ g_irq_history_num = (macVal & 0xff);
5258+ km_irq_info_idx = ((macVal >> 16) & 0xff);
5259+
5260+ macVal = 0;
5261+ macVal = mt76_rr(dev, km_irq_trace_ptr_addr);
5262+ km_irq_trace_ptr = macVal;
5263+
5264+ macVal = 0;
5265+ macVal = mt76_rr(dev, km_total_time_addr);
5266+ km_total_time = macVal;
5267+
5268+ TaskStart[0] = mt76_rr(dev, 0x02202814);
5269+ TaskEnd[0] = mt76_rr(dev, 0x02202810);
5270+ TaskStart[1] = mt76_rr(dev, 0x02202984);
5271+ TaskEnd[1] = mt76_rr(dev, 0x02202980);
5272+
5273+ seq_printf(s, "================FW DBG INFO===================\n");
5274+ seq_printf(s, " exp_assert_proc_entry_cnt = 0x%x\n",
5275+ exp_assert_proc_entry_cnt);
5276+ seq_printf(s, " exp_assert_state = 0x%x\n",
5277+ exp_assert_state);
5278+
5279+ if (exp_assert_proc_entry_cnt == 0) {
5280+ ret = snprintf(exp_type, sizeof(exp_type), "%s", "exp_type : Normal");
5281+ if (mt7915_snprintf_error(sizeof(exp_type), ret)) {
5282+ seq_printf(s, " exp_type Snprintf failed!\n");
5283+ return 0;
5284+ }
5285+ } else if (exp_assert_proc_entry_cnt == 1 &&
5286+ exp_assert_state > 1 && g_exp_type == 5) {
5287+ ret = snprintf(exp_type, sizeof(exp_type), "%s", "exp_type : Assert");
5288+ if (mt7915_snprintf_error(sizeof(exp_type), ret)) {
5289+ seq_printf(s, " exp_type Snprintf failed!\n");
5290+ return 0;
5291+ }
5292+ fgIsExp = true;
5293+ fgIsAssert = true;
5294+ } else if (exp_assert_proc_entry_cnt == 1 && exp_assert_state > 1) {
5295+ ret = snprintf(exp_type, sizeof(exp_type), "%s", "exp_type : Exception");
5296+ if (mt7915_snprintf_error(sizeof(exp_type), ret)) {
5297+ seq_printf(s, " exp_type Snprintf failed!\n");
5298+ return 0;
5299+ }
5300+ fgIsExp = true;
5301+ } else if (exp_assert_proc_entry_cnt > 1) {
5302+ ret = snprintf(exp_type, sizeof(exp_type), "%s", "exp_type : Exception re-entry");
5303+ if (mt7915_snprintf_error(sizeof(exp_type), ret)) {
5304+ seq_printf(s, " exp_type Snprintf failed!\n");
5305+ return 0;
5306+ }
5307+ fgIsExp = true;
5308+ } else {
5309+ ret = snprintf(exp_type, sizeof(exp_type), "%s", "exp_type : Unknown'?");
5310+ if (mt7915_snprintf_error(sizeof(exp_type), ret)) {
5311+ seq_printf(s, " exp_type Snprintf failed!\n");
5312+ return 0;
5313+ }
5314+ }
5315+
5316+ seq_printf(s, " COS_Interrupt_Count = 0x%x\n", COS_Interrupt_Count);
5317+ seq_printf(s, " processing_irqx = 0x%x\n", processing_irqx);
5318+ seq_printf(s, " processing_lisr = 0x%x\n", processing_lisr);
5319+ seq_printf(s, " Current_Task_Id = 0x%x\n", Current_Task_Id);
5320+ seq_printf(s, " Current_Task_Indx = 0x%x\n", Current_Task_Indx);
5321+ seq_printf(s, " last_dequeued_msg_id = %d\n", last_dequeued_msg_id);
5322+
5323+ seq_printf(s, " km_irq_info_idx = 0x%x\n", km_irq_info_idx);
5324+ seq_printf(s, " km_eint_info_idx = 0x%x\n", km_eint_info_idx);
5325+ seq_printf(s, " km_sched_info_idx = 0x%x\n", km_sched_info_idx);
5326+ seq_printf(s, " g_sched_history_num = %d\n", g_sched_history_num);
5327+ seq_printf(s, " km_sched_trace_ptr = 0x%x\n", km_sched_trace_ptr);
5328+
5329+ if (fgIsExp) {
5330+ seq_printf(s, "\n <1>print sched trace\n");
5331+ if (g_sched_history_num > 60)
5332+ g_sched_history_num = 60;
5333+
5334+ idx = km_sched_info_idx;
5335+ for (i = 0 ; i < g_sched_history_num ; i++) {
5336+ t1 = mt76_rr(dev, (km_sched_trace_ptr+(idx*12)));
5337+ t2 = mt76_rr(dev, (km_sched_trace_ptr+(idx*12)+4));
5338+ t3 = mt76_rr(dev, (km_sched_trace_ptr+(idx*12)+8));
5339+ seq_printf(s, " (sched_info_%d)sched_t=0x%x, sched_start=%d, PC=0x%x\n",
5340+ idx, t1, t2, t3);
5341+ idx++;
5342+ if (idx >= g_sched_history_num)
5343+ idx = 0;
5344+ }
5345+
5346+ seq_printf(s, "\n <2>print irq trace\n");
5347+ if (g_irq_history_num > 60)
5348+ g_irq_history_num = 60;
5349+
5350+ idx = km_irq_info_idx;
5351+ for (i = 0 ; i < g_irq_history_num ; i++) {
5352+ t1 = mt76_rr(dev, (km_irq_trace_ptr+(idx*16)));
5353+ t2 = mt76_rr(dev, (km_irq_trace_ptr+(idx*16) + 4));
5354+ seq_printf(s, " (irq_info_%d)irq_t=%x, sched_start=%d\n",
5355+ idx, t1, t2);
5356+ idx++;
5357+ if (idx >= g_irq_history_num)
5358+ idx = 0;
5359+ }
5360+ }
5361+
5362+ seq_printf(s, "\n <3>task q_id.read q_id.write\n");
5363+ seq_printf(s, " (WIFI )1 0x%x 0x%x\n", TaskStart[0], TaskEnd[0]);
5364+ seq_printf(s, " (WIFI2 )2 0x%x 0x%x\n", TaskStart[1], TaskEnd[1]);
5365+ seq_printf(s, "\n <4>TASK STACK INFO (size in byte)\n");
5366+ seq_printf(s, " TASK START END SIZE PEAK INTEGRITY\n");
5367+
5368+ for (i = 0 ; i < 2 ; i++) {
5369+ t1 = mt76_rr(dev, 0x022027B8+(i*368));
5370+ t2 = mt76_rr(dev, 0x022027BC+(i*368));
5371+ t3 = mt76_rr(dev, 0x022027C4+(i*368));
5372+
5373+ if (i == 0) {
5374+ ret = snprintf(str, sizeof(str), "%s", "WIFI");
5375+ if (mt7915_snprintf_error(sizeof(str), ret)) {
5376+ seq_printf(s, " str Snprintf failed!\n");
5377+ return 0;
5378+ }
5379+ } else if (i == 1) {
5380+ ret = snprintf(str, sizeof(str), "%s", "WIFI2");
5381+ if (mt7915_snprintf_error(sizeof(str), ret)) {
5382+ seq_printf(s, " str Snprintf failed!\n");
5383+ return 0;
5384+ }
5385+ }
5386+
5387+ seq_printf(s, " %s 0x%x 0x%x %d\n",
5388+ str, t1, t2, t3);
5389+ }
5390+
5391+ seq_printf(s, "\n <5>fw state\n");
5392+ seq_printf(s, " %s\n", exp_type);
5393+ if (COS_Interrupt_Count > 0)
5394+ seq_printf(s, " FW in Interrupt CIRQ index (0x%x) CIRQ handler(0x%x)\n"
5395+ , processing_irqx, processing_lisr);
5396+ else {
5397+ if (Current_Task_Id == 0 && Current_Task_Indx == 3)
5398+ seq_printf(s, " FW in IDLE\n");
5399+
5400+ if (Current_Task_Id != 0 && Current_Task_Indx != 3)
5401+ seq_printf(s, " FW in Task , Task id(0x%x) Task index(0x%x)\n",
5402+ Current_Task_Id, Current_Task_Indx);
5403+ }
5404+
5405+ macVal = 0;
5406+ macVal= mt76_rr(dev, g1_exp_counter_addr);
5407+ seq_printf(s, " EXCP_CNT = 0x%x\n", macVal);
5408+
5409+ seq_printf(s, " EXCP_TYPE = 0x%x\n", g_exp_type);
5410+
5411+ macVal = 0;
5412+ macVal = mt76_rr(dev, 0x022050E0);
5413+ seq_printf(s, " CPU_ITYPE = 0x%x\n", macVal);
5414+
5415+ macVal = 0;
5416+ macVal = mt76_rr(dev, 0x022050E8);
5417+ seq_printf(s, " CPU_EVA = 0x%x\n", macVal);
5418+
5419+ macVal = 0;
5420+ macVal = mt76_rr(dev, 0x022050E4);
5421+ seq_printf(s, " CPU_IPC = 0x%x\n", macVal);
5422+
5423+ macVal = 0;
5424+ macVal = mt76_rr(dev, 0x7C060204);
5425+ seq_printf(s, " PC = 0x%x\n\n\n", macVal);
5426+
5427+ mt7915_show_lp_history(s, fgIsExp);
5428+ mt7915_show_irq_history(s);
5429+
5430+ seq_printf(s, "\n\n cpu ultility\n");
5431+ seq_printf(s, " Busy:%d%% Peak:%d%%\n\n",
5432+ mt76_rr(dev, 0x7C053B20), mt76_rr(dev, 0x7C053B24));
5433+
5434+ mt7915_show_msg_trace(s);
5435+ mt7915_show_sech_trace(s);
5436+ mt7915_show_prog_trace(s);
5437+ if (fgIsAssert)
5438+ mt7915_show_assert_line(s);
5439+
5440+ seq_printf(s, "============================================\n");
5441+ return 0;
5442+}
5443+
developer3fa816c2022-04-19 10:21:20 +08005444+int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir)
5445+{
5446+ struct mt7915_dev *dev = phy->dev;
5447+ u32 device_id = (dev->mt76.rev) >> 16;
5448+ int i = 0;
5449+
5450+ for (i = 0; i < ARRAY_SIZE(dbg_reg_s); i++) {
5451+ if (device_id == dbg_reg_s[i].id) {
5452+ dev->dbg_reg = &dbg_reg_s[i];
5453+ break;
5454+ }
5455+ }
5456+
5457+ mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 0);
5458+
5459+ debugfs_create_file("fw_debug_module", 0600, dir, dev,
5460+ &fops_fw_debug_module);
5461+ debugfs_create_file("fw_debug_level", 0600, dir, dev,
5462+ &fops_fw_debug_level);
5463+
developerf32dabf2022-06-01 10:59:24 +08005464+ debugfs_create_devm_seqfile(dev->mt76.dev, "sta_info", dir,
5465+ mt7915_sta_info);
developer3fa816c2022-04-19 10:21:20 +08005466+ debugfs_create_devm_seqfile(dev->mt76.dev, "wtbl_info", dir,
5467+ mt7915_wtbl_read);
5468+ debugfs_create_devm_seqfile(dev->mt76.dev, "uwtbl_info", dir,
5469+ mt7915_uwtbl_read);
5470+
5471+ debugfs_create_devm_seqfile(dev->mt76.dev, "tr_info", dir,
5472+ mt7915_trinfo_read);
5473+
5474+ debugfs_create_devm_seqfile(dev->mt76.dev, "drr_info", dir,
5475+ mt7915_drr_info);
5476+
5477+ debugfs_create_devm_seqfile(dev->mt76.dev, "ple_info", dir,
5478+ mt7915_pleinfo_read);
5479+
5480+ debugfs_create_devm_seqfile(dev->mt76.dev, "pse_info", dir,
5481+ mt7915_pseinfo_read);
5482+
5483+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info0", dir,
5484+ mt7915_mibinfo_band0);
5485+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info1", dir,
5486+ mt7915_mibinfo_band1);
5487+
5488+ debugfs_create_u32("token_idx", 0600, dir, &dev->dbg.token_idx);
5489+ debugfs_create_devm_seqfile(dev->mt76.dev, "token", dir,
5490+ mt7915_token_read);
5491+ debugfs_create_devm_seqfile(dev->mt76.dev, "token_txd", dir,
5492+ mt7915_token_txd_read);
5493+
5494+ debugfs_create_devm_seqfile(dev->mt76.dev, "amsdu_info", dir,
5495+ mt7915_amsduinfo_read);
5496+
5497+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info0", dir,
5498+ mt7915_agginfo_read_band0);
5499+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info1", dir,
5500+ mt7915_agginfo_read_band1);
5501+
5502+ debugfs_create_file("tx_amsdu", 0600, dir, dev, &fops_tx_amsdu);
5503+
5504+ debugfs_create_file("fw_wa_query", 0600, dir, dev, &fops_wa_query);
5505+ debugfs_create_file("fw_wa_set", 0600, dir, dev, &fops_wa_set);
developer8e5fecd2023-05-30 11:58:00 +08005506+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_version", dir,
5507+ mt7915_dump_version);
developer3fa816c2022-04-19 10:21:20 +08005508+ debugfs_create_file("fw_wa_debug", 0600, dir, dev, &fops_wa_debug);
developera43cc482023-04-17 15:57:28 +08005509+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_wm_info", dir,
5510+ mt7915_fw_wm_info_read);
developer3fa816c2022-04-19 10:21:20 +08005511+
5512+ debugfs_create_file("red_en", 0600, dir, dev,
5513+ &fops_red_en);
5514+ debugfs_create_file("red_show_sta", 0600, dir, dev,
5515+ &fops_red_show_sta);
5516+ debugfs_create_file("red_target_dly", 0600, dir, dev,
5517+ &fops_red_target_dly);
5518+
5519+ debugfs_create_file("txpower_level", 0400, dir, dev,
5520+ &fops_txpower_level);
5521+
developeraace7f52022-06-24 13:40:42 +08005522+ debugfs_create_u8("sku_disable", 0600, dir, &dev->dbg.sku_disable);
5523+
developer3fa816c2022-04-19 10:21:20 +08005524+ return 0;
5525+}
5526+#endif
5527diff --git a/mt7915/mtk_mcu.c b/mt7915/mtk_mcu.c
5528new file mode 100644
developer36fe7092023-09-27 12:24:47 +08005529index 00000000..143dae26
developer3fa816c2022-04-19 10:21:20 +08005530--- /dev/null
5531+++ b/mt7915/mtk_mcu.c
5532@@ -0,0 +1,51 @@
5533+#include <linux/firmware.h>
5534+#include <linux/fs.h>
5535+#include<linux/inet.h>
5536+#include "mt7915.h"
5537+#include "mcu.h"
5538+#include "mac.h"
5539+
5540+int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level)
5541+{
5542+ struct mt7915_dev *dev = phy->dev;
5543+ struct mt7915_sku_val {
5544+ u8 format_id;
5545+ u8 val;
5546+ u8 band;
5547+ u8 _rsv;
5548+ } __packed req = {
5549+ .format_id = 1,
developer2458e702022-12-13 15:52:04 +08005550+ .band = phy->mt76->band_idx,
developer3fa816c2022-04-19 10:21:20 +08005551+ .val = !!drop_level,
5552+ };
5553+ int ret;
5554+
5555+ ret = mt76_mcu_send_msg(&dev->mt76,
5556+ MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
5557+ sizeof(req), true);
5558+ if (ret)
5559+ return ret;
5560+
5561+ req.format_id = 2;
5562+ if ((drop_level > 90 && drop_level < 100) || !drop_level)
5563+ req.val = 0;
5564+ else if (drop_level > 60 && drop_level <= 90)
5565+ /* reduce Pwr for 1 dB. */
5566+ req.val = 2;
5567+ else if (drop_level > 30 && drop_level <= 60)
5568+ /* reduce Pwr for 3 dB. */
5569+ req.val = 6;
5570+ else if (drop_level > 15 && drop_level <= 30)
5571+ /* reduce Pwr for 6 dB. */
5572+ req.val = 12;
5573+ else if (drop_level > 9 && drop_level <= 15)
5574+ /* reduce Pwr for 9 dB. */
5575+ req.val = 18;
5576+ else if (drop_level > 0 && drop_level <= 9)
5577+ /* reduce Pwr for 12 dB. */
5578+ req.val = 24;
5579+
5580+ return mt76_mcu_send_msg(&dev->mt76,
5581+ MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
5582+ sizeof(req), true);
5583+}
5584diff --git a/tools/fwlog.c b/tools/fwlog.c
developer36fe7092023-09-27 12:24:47 +08005585index e5d4a105..3d51d9ec 100644
developer3fa816c2022-04-19 10:21:20 +08005586--- a/tools/fwlog.c
5587+++ b/tools/fwlog.c
5588@@ -26,7 +26,7 @@ static const char *debugfs_path(const char *phyname, const char *file)
5589 return path;
5590 }
5591
5592-static int mt76_set_fwlog_en(const char *phyname, bool en)
5593+static int mt76_set_fwlog_en(const char *phyname, bool en, char *val)
5594 {
5595 FILE *f = fopen(debugfs_path(phyname, "fw_debug_bin"), "w");
5596
5597@@ -35,7 +35,13 @@ static int mt76_set_fwlog_en(const char *phyname, bool en)
5598 return 1;
5599 }
5600
5601- fprintf(f, "7");
5602+ if (en && val)
5603+ fprintf(f, "%s", val);
5604+ else if (en)
5605+ fprintf(f, "7");
5606+ else
5607+ fprintf(f, "0");
5608+
5609 fclose(f);
5610
5611 return 0;
5612@@ -76,6 +82,7 @@ static void handle_signal(int sig)
5613
5614 int mt76_fwlog(const char *phyname, int argc, char **argv)
5615 {
5616+#define BUF_SIZE 1504
5617 struct sockaddr_in local = {
5618 .sin_family = AF_INET,
5619 .sin_addr.s_addr = INADDR_ANY,
developerf32dabf2022-06-01 10:59:24 +08005620@@ -84,9 +91,10 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
developer3fa816c2022-04-19 10:21:20 +08005621 .sin_family = AF_INET,
5622 .sin_port = htons(55688),
5623 };
5624- char buf[1504];
5625+ char *buf = calloc(BUF_SIZE, sizeof(char));
developerf32dabf2022-06-01 10:59:24 +08005626+ FILE *logfile = NULL;
developer3fa816c2022-04-19 10:21:20 +08005627 int ret = 0;
5628- int yes = 1;
5629+ /* int yes = 1; */
5630 int s, fd;
5631
5632 if (argc < 1) {
developerf32dabf2022-06-01 10:59:24 +08005633@@ -99,19 +107,28 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
5634 return 1;
5635 }
5636
5637+ if (argc == 3) {
5638+ fprintf(stdout, "start logging to file %s\n", argv[2]);
5639+ logfile = fopen(argv[2], "wb");
5640+ if (!logfile) {
5641+ perror("fopen");
5642+ return 1;
5643+ }
5644+ }
5645+
5646 s = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP);
5647 if (s < 0) {
5648 perror("socket");
developer3fa816c2022-04-19 10:21:20 +08005649 return 1;
5650 }
5651
5652- setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes));
5653+ /* setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes)); */
5654 if (bind(s, (struct sockaddr *)&local, sizeof(local)) < 0) {
5655 perror("bind");
5656 return 1;
5657 }
5658
5659- if (mt76_set_fwlog_en(phyname, true))
5660+ if (mt76_set_fwlog_en(phyname, true, argv[1]))
5661 return 1;
5662
5663 fd = open(debugfs_path(phyname, "fwlog_data"), O_RDONLY);
developerf32dabf2022-06-01 10:59:24 +08005664@@ -145,8 +162,8 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
developer3fa816c2022-04-19 10:21:20 +08005665 if (!r)
5666 continue;
5667
5668- if (len > sizeof(buf)) {
5669- fprintf(stderr, "Length error: %d > %d\n", len, (int)sizeof(buf));
5670+ if (len > BUF_SIZE) {
5671+ fprintf(stderr, "Length error: %d > %d\n", len, BUF_SIZE);
5672 ret = 1;
5673 break;
5674 }
developerf32dabf2022-06-01 10:59:24 +08005675@@ -164,14 +181,19 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
5676 break;
5677 }
5678
5679- /* send buf */
5680- sendto(s, buf, len, 0, (struct sockaddr *)&remote, sizeof(remote));
5681+ if (logfile)
5682+ fwrite(buf, 1, len, logfile);
5683+ else
5684+ /* send buf */
5685+ sendto(s, buf, len, 0, (struct sockaddr *)&remote, sizeof(remote));
5686 }
5687
developer3fa816c2022-04-19 10:21:20 +08005688 close(fd);
5689
5690 out:
5691- mt76_set_fwlog_en(phyname, false);
5692+ mt76_set_fwlog_en(phyname, false, NULL);
5693+ free(buf);
developerf32dabf2022-06-01 10:59:24 +08005694+ fclose(logfile);
developer3fa816c2022-04-19 10:21:20 +08005695
5696 return ret;
5697 }
5698--
developerdfb50982023-09-11 13:34:36 +080056992.18.0
developer3fa816c2022-04-19 10:21:20 +08005700