blob: 0e55e52b765cf7558235d6ab6378616313474d17 [file] [log] [blame]
developer36fe7092023-09-27 12:24:47 +08001From 11e837febd8092b39d13b74c76d9134496c6e9d4 Mon Sep 17 00:00:00 2001
developeraace7f52022-06-24 13:40:42 +08002From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Wed, 22 Jun 2022 10:39:47 +0800
developer36fe7092023-09-27 12:24:47 +08004Subject: [PATCH] wifi: mt76: mt7915: add mtk internal debug tools for mt76
developer3fa816c2022-04-19 10:21:20 +08005
6---
developerf3f5d9b2023-02-07 15:24:34 +08007 mt76_connac_mcu.h | 6 +
developer27b55252022-09-05 19:09:45 +08008 mt7915/Makefile | 2 +-
developerd5789dc2023-03-27 11:22:06 +08009 mt7915/debugfs.c | 89 +-
developer27b55252022-09-05 19:09:45 +080010 mt7915/mac.c | 14 +
developer36fe7092023-09-27 12:24:47 +080011 mt7915/main.c | 5 +
developerf3f5d9b2023-02-07 15:24:34 +080012 mt7915/mcu.c | 48 +-
developer27b55252022-09-05 19:09:45 +080013 mt7915/mcu.h | 4 +
developer5eddc512023-02-13 16:01:56 +080014 mt7915/mt7915.h | 43 +
developera43cc482023-04-17 15:57:28 +080015 mt7915/mt7915_debug.h | 1418 ++++++++++++++++
developerdfb50982023-09-11 13:34:36 +080016 mt7915/mtk_debugfs.c | 3622 +++++++++++++++++++++++++++++++++++++++++
developer27b55252022-09-05 19:09:45 +080017 mt7915/mtk_mcu.c | 51 +
18 tools/fwlog.c | 44 +-
developer36fe7092023-09-27 12:24:47 +080019 12 files changed, 5327 insertions(+), 19 deletions(-)
developer27b55252022-09-05 19:09:45 +080020 create mode 100644 mt7915/mt7915_debug.h
21 create mode 100644 mt7915/mtk_debugfs.c
22 create mode 100644 mt7915/mtk_mcu.c
developer3fa816c2022-04-19 10:21:20 +080023
24diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
developer36fe7092023-09-27 12:24:47 +080025index bd0bf4bb..ab3b58e1 100644
developer3fa816c2022-04-19 10:21:20 +080026--- a/mt76_connac_mcu.h
27+++ b/mt76_connac_mcu.h
developer36fe7092023-09-27 12:24:47 +080028@@ -1151,6 +1151,7 @@ enum {
developer9e5bcc52022-09-27 10:30:15 +080029 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
30 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
31 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
32+ MCU_EXT_CMD_MEC_CTRL = 0x1f,
33 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
34 MCU_EXT_CMD_THERMAL_PROT = 0x23,
35 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
developer36fe7092023-09-27 12:24:47 +080036@@ -1174,6 +1175,11 @@ enum {
developer3fa816c2022-04-19 10:21:20 +080037 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
38 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
39 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
40+#ifdef MTK_DEBUG
developer3fa816c2022-04-19 10:21:20 +080041+ MCU_EXT_CMD_RED_SHOW_STA = 0x69,
42+ MCU_EXT_CMD_RED_TARGET_DELAY = 0x6A,
43+ MCU_EXT_CMD_RED_TX_RPT = 0x6B,
44+#endif
45 MCU_EXT_CMD_TXDPD_CAL = 0x60,
46 MCU_EXT_CMD_CAL_CACHE = 0x67,
developerf3f5d9b2023-02-07 15:24:34 +080047 MCU_EXT_CMD_RED_ENABLE = 0x68,
developer3fa816c2022-04-19 10:21:20 +080048diff --git a/mt7915/Makefile b/mt7915/Makefile
developer36fe7092023-09-27 12:24:47 +080049index c4dca9c1..fd711416 100644
developer3fa816c2022-04-19 10:21:20 +080050--- a/mt7915/Makefile
51+++ b/mt7915/Makefile
developerf3f5d9b2023-02-07 15:24:34 +080052@@ -4,7 +4,7 @@ EXTRA_CFLAGS += -DCONFIG_MT76_LEDS
developer3fa816c2022-04-19 10:21:20 +080053 obj-$(CONFIG_MT7915E) += mt7915e.o
54
55 mt7915e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
56- debugfs.o mmio.o
57+ debugfs.o mmio.o mtk_debugfs.o mtk_mcu.o
58
59 mt7915e-$(CONFIG_NL80211_TESTMODE) += testmode.o
developerad9333b2023-05-22 15:16:16 +080060 mt7915e-$(CONFIG_MT798X_WMAC) += soc.o
developer3fa816c2022-04-19 10:21:20 +080061diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c
developer36fe7092023-09-27 12:24:47 +080062index 93e549c3..f1813776 100644
developer3fa816c2022-04-19 10:21:20 +080063--- a/mt7915/debugfs.c
64+++ b/mt7915/debugfs.c
65@@ -8,6 +8,9 @@
66 #include "mac.h"
67
68 #define FW_BIN_LOG_MAGIC 0x44e98caf
69+#ifdef MTK_DEBUG
70+#define FW_BIN_LOG_MAGIC_V2 0x44d9c99a
71+#endif
72
73 /** global debugfs **/
74
developer004e50c2023-06-29 20:33:22 +080075@@ -496,6 +499,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080076 int ret;
77
developer42b63282022-06-16 13:33:13 +080078 dev->fw.debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
developer3fa816c2022-04-19 10:21:20 +080079+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +080080+ dev->fw.debug_wm = val;
developer3fa816c2022-04-19 10:21:20 +080081+#endif
82
developer42b63282022-06-16 13:33:13 +080083 if (dev->fw.debug_bin)
developer3fa816c2022-04-19 10:21:20 +080084 val = 16;
developer004e50c2023-06-29 20:33:22 +080085@@ -520,6 +526,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080086 if (ret)
developer42b63282022-06-16 13:33:13 +080087 goto out;
developer3fa816c2022-04-19 10:21:20 +080088 }
89+#ifdef MTK_DEBUG
90+ mt7915_mcu_fw_dbg_ctrl(dev, 68, !!val);
91+#endif
92
93 /* WM CPU info record control */
94 mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0));
developer004e50c2023-06-29 20:33:22 +080095@@ -527,6 +536,12 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080096 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5));
97 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5));
98
99+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +0800100+ if (dev->fw.debug_bin & BIT(3))
developer3fa816c2022-04-19 10:21:20 +0800101+ /* use bit 7 to indicate v2 magic number */
developer42b63282022-06-16 13:33:13 +0800102+ dev->fw.debug_wm |= BIT(7);
developer3fa816c2022-04-19 10:21:20 +0800103+#endif
104+
developer42b63282022-06-16 13:33:13 +0800105 out:
106 if (ret)
107 dev->fw.debug_wm = 0;
developer004e50c2023-06-29 20:33:22 +0800108@@ -539,7 +554,11 @@ mt7915_fw_debug_wm_get(void *data, u64 *val)
developer3fa816c2022-04-19 10:21:20 +0800109 {
110 struct mt7915_dev *dev = data;
111
developer42b63282022-06-16 13:33:13 +0800112- *val = dev->fw.debug_wm;
developer3fa816c2022-04-19 10:21:20 +0800113+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +0800114+ *val = dev->fw.debug_wm & ~BIT(7);
developer3fa816c2022-04-19 10:21:20 +0800115+#else
developer42b63282022-06-16 13:33:13 +0800116+ val = dev->fw.debug_wm;
developer3fa816c2022-04-19 10:21:20 +0800117+#endif
118
119 return 0;
120 }
developer004e50c2023-06-29 20:33:22 +0800121@@ -614,16 +633,30 @@ mt7915_fw_debug_bin_set(void *data, u64 val)
developerd5789dc2023-03-27 11:22:06 +0800122 };
123 struct mt7915_dev *dev = data;
124
125- if (!dev->relay_fwlog)
126+ if (!dev->relay_fwlog && val) {
127 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir,
128 1500, 512, &relay_cb, NULL);
129- if (!dev->relay_fwlog)
130- return -ENOMEM;
131+ if (!dev->relay_fwlog)
132+ return -ENOMEM;
133+ }
134
135 dev->fw.debug_bin = val;
developer3fa816c2022-04-19 10:21:20 +0800136
137 relay_reset(dev->relay_fwlog);
138
139+#ifdef MTK_DEBUG
140+ dev->dbg.dump_mcu_pkt = val & BIT(4) ? true : false;
141+ dev->dbg.dump_txd = val & BIT(5) ? true : false;
142+ dev->dbg.dump_tx_pkt = val & BIT(6) ? true : false;
143+ dev->dbg.dump_rx_pkt = val & BIT(7) ? true : false;
144+ dev->dbg.dump_rx_raw = val & BIT(8) ? true : false;
developer3fa816c2022-04-19 10:21:20 +0800145+#endif
146+
developerd5789dc2023-03-27 11:22:06 +0800147+ if (dev->relay_fwlog && !val) {
148+ relay_close(dev->relay_fwlog);
149+ dev->relay_fwlog = NULL;
150+ }
developer42b63282022-06-16 13:33:13 +0800151+
152 return mt7915_fw_debug_wm_set(dev, dev->fw.debug_wm);
developer3fa816c2022-04-19 10:21:20 +0800153 }
154
developer2b96a9e2023-08-09 10:28:15 +0800155@@ -1253,6 +1286,11 @@ int mt7915_init_debugfs(struct mt7915_phy *phy)
developer3fa816c2022-04-19 10:21:20 +0800156 if (!ext_phy)
157 dev->debugfs_dir = dir;
158
159+#ifdef MTK_DEBUG
160+ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
161+ mt7915_mtk_init_debugfs(phy, dir);
162+#endif
163+
164 return 0;
165 }
166
developer2b96a9e2023-08-09 10:28:15 +0800167@@ -1265,6 +1303,12 @@ mt7915_debugfs_write_fwlog(struct mt7915_dev *dev, const void *hdr, int hdrlen,
developerd5789dc2023-03-27 11:22:06 +0800168 void *dest;
169
170 spin_lock_irqsave(&lock, flags);
171+
172+ if (!dev->relay_fwlog) {
173+ spin_unlock_irqrestore(&lock, flags);
174+ return;
175+ }
176+
177 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4);
178 if (dest) {
179 *(u32 *)dest = hdrlen + len;
developer2b96a9e2023-08-09 10:28:15 +0800180@@ -1293,17 +1337,50 @@ void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int
developer3fa816c2022-04-19 10:21:20 +0800181 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),
182 };
183
developerd5789dc2023-03-27 11:22:06 +0800184- if (!dev->relay_fwlog)
185- return;
developer3fa816c2022-04-19 10:21:20 +0800186+#ifdef MTK_DEBUG
187+ struct {
188+ __le32 magic;
189+ u8 version;
190+ u8 _rsv;
191+ __le16 serial_id;
192+ __le32 timestamp;
193+ __le16 msg_type;
194+ __le16 len;
195+ } hdr2 = {
196+ .version = 0x1,
197+ .magic = cpu_to_le32(FW_BIN_LOG_MAGIC_V2),
198+ .msg_type = PKT_TYPE_RX_FW_MONITOR,
199+ };
200+#endif
developer3fa816c2022-04-19 10:21:20 +0800201
202+#ifdef MTK_DEBUG
203+ /* old magic num */
developer42b63282022-06-16 13:33:13 +0800204+ if (!(dev->fw.debug_wm & BIT(7))) {
developer3fa816c2022-04-19 10:21:20 +0800205+ hdr.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
206+ hdr.len = *(__le16 *)data;
207+ mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
208+ } else {
209+ hdr2.serial_id = dev->dbg.fwlog_seq++;
210+ hdr2.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
211+ hdr2.len = *(__le16 *)data;
212+ mt7915_debugfs_write_fwlog(dev, &hdr2, sizeof(hdr2), data, len);
213+ }
214+#else
215 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
216 hdr.len = *(__le16 *)data;
217 mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
218+#endif
219 }
220
221 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len)
222 {
223+#ifdef MTK_DEBUG
224+ if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC &&
225+ get_unaligned_le32(data) != FW_BIN_LOG_MAGIC_V2 &&
226+ get_unaligned_le32(data) != PKT_BIN_DEBUG_MAGIC)
227+#else
228 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC)
229+#endif
230 return false;
231
232 if (dev->relay_fwlog)
233diff --git a/mt7915/mac.c b/mt7915/mac.c
developer36fe7092023-09-27 12:24:47 +0800234index d9d5aad4..d22a4079 100644
developer3fa816c2022-04-19 10:21:20 +0800235--- a/mt7915/mac.c
236+++ b/mt7915/mac.c
developerad9333b2023-05-22 15:16:16 +0800237@@ -275,6 +275,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb,
developer3fa816c2022-04-19 10:21:20 +0800238 __le16 fc = 0;
239 int idx;
240
241+#ifdef MTK_DEBUG
242+ if (dev->dbg.dump_rx_raw)
243+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX_RAW, 0);
244+#endif
245 memset(status, 0, sizeof(*status));
246
developer2458e702022-12-13 15:52:04 +0800247 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->mt76->band_idx) {
developer004e50c2023-06-29 20:33:22 +0800248@@ -459,6 +463,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb,
developer3fa816c2022-04-19 10:21:20 +0800249 }
250
251 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
252+#ifdef MTK_DEBUG
253+ if (dev->dbg.dump_rx_pkt)
254+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX, hdr_gap);
255+#endif
256 if (hdr_trans && ieee80211_has_morefrags(fc)) {
developeraace7f52022-06-24 13:40:42 +0800257 struct ieee80211_vif *vif;
258 int err;
developer004e50c2023-06-29 20:33:22 +0800259@@ -796,6 +804,12 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developer3fa816c2022-04-19 10:21:20 +0800260 tx_info->buf[1].skip_unmap = true;
261 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
262
263+#ifdef MTK_DEBUG
264+ if (dev->dbg.dump_txd)
265+ mt7915_packet_log_to_host(dev, txwi, MT_TXD_SIZE, PKT_BIN_DEBUG_TXD, 0);
266+ if (dev->dbg.dump_tx_pkt)
267+ mt7915_packet_log_to_host(dev, t->skb->data, t->skb->len, PKT_BIN_DEBUG_TX, 0);
268+#endif
269 return 0;
270 }
271
developeraace7f52022-06-24 13:40:42 +0800272diff --git a/mt7915/main.c b/mt7915/main.c
developer36fe7092023-09-27 12:24:47 +0800273index 4e5c138f..b6dc9513 100644
developeraace7f52022-06-24 13:40:42 +0800274--- a/mt7915/main.c
275+++ b/mt7915/main.c
developer2aa1e642022-12-19 11:33:22 +0800276@@ -73,7 +73,11 @@ int mt7915_run(struct ieee80211_hw *hw)
developeraace7f52022-06-24 13:40:42 +0800277 if (ret)
278 goto out;
279
280+#ifdef MTK_DEBUG
281+ ret = mt7915_mcu_set_sku_en(phy, !dev->dbg.sku_disable);
282+#else
283 ret = mt7915_mcu_set_sku_en(phy, true);
284+#endif
285 if (ret)
286 goto out;
287
developer36fe7092023-09-27 12:24:47 +0800288@@ -253,6 +257,7 @@ static int mt7915_add_interface(struct ieee80211_hw *hw,
289 mvif->sta.wcid.phy_idx = ext_phy;
290 mvif->sta.wcid.hw_key_idx = -1;
291 mvif->sta.wcid.tx_info |= MT_WCID_TX_INFO_SET;
292+ mvif->sta.vif = mvif;
293 mt76_packet_id_init(&mvif->sta.wcid);
294
295 mt7915_mac_wtbl_update(dev, idx,
developer3fa816c2022-04-19 10:21:20 +0800296diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developer36fe7092023-09-27 12:24:47 +0800297index 03f84343..6b19af74 100644
developer3fa816c2022-04-19 10:21:20 +0800298--- a/mt7915/mcu.c
299+++ b/mt7915/mcu.c
developer004e50c2023-06-29 20:33:22 +0800300@@ -205,6 +205,11 @@ mt7915_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
developeraace7f52022-06-24 13:40:42 +0800301 else
302 qid = MT_MCUQ_WM;
developer3fa816c2022-04-19 10:21:20 +0800303
developer3fa816c2022-04-19 10:21:20 +0800304+#ifdef MTK_DEBUG
305+ if (dev->dbg.dump_mcu_pkt)
306+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_MCU, 0);
307+#endif
developeraace7f52022-06-24 13:40:42 +0800308+
309 return mt76_tx_queue_skb_raw(dev, mdev->q_mcu[qid], skb, 0);
310 }
311
developer36fe7092023-09-27 12:24:47 +0800312@@ -2288,7 +2293,10 @@ static int mt7915_red_set_watermark(struct mt7915_dev *dev)
developerf3f5d9b2023-02-07 15:24:34 +0800313 sizeof(req), false);
314 }
315
316-static int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled)
317+#ifndef MTK_DEBUG
318+static
319+#endif
320+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled)
321 {
322 #define RED_DISABLE 0
323 #define RED_BY_WA_ENABLE 2
developer36fe7092023-09-27 12:24:47 +0800324@@ -3352,6 +3360,8 @@ int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable)
developeraace7f52022-06-24 13:40:42 +0800325 .sku_enable = enable,
326 };
developer3fa816c2022-04-19 10:21:20 +0800327
developeraace7f52022-06-24 13:40:42 +0800328+ pr_info("%s: enable = %d\n", __func__, enable);
329+
330 return mt76_mcu_send_msg(&dev->mt76,
331 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
332 sizeof(req), true);
developer36fe7092023-09-27 12:24:47 +0800333@@ -4006,6 +4016,23 @@ out:
developer004e50c2023-06-29 20:33:22 +0800334 return ret;
developer3fa816c2022-04-19 10:21:20 +0800335 }
developer1eeb8e82022-05-03 14:10:10 +0800336
developer3fa816c2022-04-19 10:21:20 +0800337+#ifdef MTK_DEBUG
338+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp)
339+{
340+ struct {
341+ __le32 args[3];
342+ } req = {
343+ .args = {
344+ cpu_to_le32(a1),
345+ cpu_to_le32(a2),
346+ cpu_to_le32(a3),
347+ },
348+ };
349+
350+ return mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), wait_resp);
351+}
developer3fa816c2022-04-19 10:21:20 +0800352+#endif
developer1eeb8e82022-05-03 14:10:10 +0800353+
354 int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set)
355 {
356 struct {
developer36fe7092023-09-27 12:24:47 +0800357@@ -4034,3 +4061,22 @@ int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set)
developer9e5bcc52022-09-27 10:30:15 +0800358
359 return 0;
360 }
361+
362+#ifdef MTK_DEBUG
363+int mt7915_mcu_set_amsdu_algo(struct mt7915_dev *dev, u16 wcid, u8 enable)
364+{
365+ struct {
366+ u16 action;
367+ u8 _rsv1[2];
368+ u16 wcid;
369+ u8 enable;
370+ u8 _rsv2[5];
371+ } __packed req = {
372+ .action = cpu_to_le16(1),
373+ .wcid = cpu_to_le16(wcid),
374+ .enable = enable,
375+ };
376+
377+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MEC_CTRL), &req, sizeof(req), true);
378+}
379+#endif
developer3fa816c2022-04-19 10:21:20 +0800380diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developer36fe7092023-09-27 12:24:47 +0800381index 8f365461..dd3b5062 100644
developer3fa816c2022-04-19 10:21:20 +0800382--- a/mt7915/mcu.h
383+++ b/mt7915/mcu.h
developerad9333b2023-05-22 15:16:16 +0800384@@ -333,6 +333,10 @@ enum {
developer3fa816c2022-04-19 10:21:20 +0800385 MCU_WA_PARAM_PDMA_RX = 0x04,
386 MCU_WA_PARAM_CPU_UTIL = 0x0b,
387 MCU_WA_PARAM_RED = 0x0e,
388+#ifdef MTK_DEBUG
389+ MCU_WA_PARAM_RED_SHOW_STA = 0xf,
390+ MCU_WA_PARAM_RED_TARGET_DELAY = 0x10,
391+#endif
developerf3f5d9b2023-02-07 15:24:34 +0800392 MCU_WA_PARAM_RED_SETTING = 0x40,
developer3fa816c2022-04-19 10:21:20 +0800393 };
394
developer3fa816c2022-04-19 10:21:20 +0800395diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developer36fe7092023-09-27 12:24:47 +0800396index 24d8da28..f9e6917c 100644
developer3fa816c2022-04-19 10:21:20 +0800397--- a/mt7915/mt7915.h
398+++ b/mt7915/mt7915.h
399@@ -9,6 +9,7 @@
400 #include "../mt76_connac.h"
401 #include "regs.h"
402
403+#define MTK_DEBUG 1
404 #define MT7915_MAX_INTERFACES 19
developer3fa816c2022-04-19 10:21:20 +0800405 #define MT7915_WTBL_SIZE 288
developeraace7f52022-06-24 13:40:42 +0800406 #define MT7916_WTBL_SIZE 544
developer36fe7092023-09-27 12:24:47 +0800407@@ -320,6 +321,28 @@ struct mt7915_dev {
developer3fa816c2022-04-19 10:21:20 +0800408 struct reset_control *rstc;
409 void __iomem *dcm;
410 void __iomem *sku;
411+
412+#ifdef MTK_DEBUG
413+ u16 wlan_idx;
414+ struct {
415+ u32 fixed_rate;
416+ u32 l1debugfs_reg;
417+ u32 l2debugfs_reg;
418+ u32 mac_reg;
419+ u32 fw_dbg_module;
420+ u8 fw_dbg_lv;
421+ u32 bcn_total_cnt[2];
422+ u16 fwlog_seq;
423+ bool dump_mcu_pkt;
424+ bool dump_txd;
425+ bool dump_tx_pkt;
426+ bool dump_rx_pkt;
427+ bool dump_rx_raw;
428+ u32 token_idx;
developeraace7f52022-06-24 13:40:42 +0800429+ u8 sku_disable;
developer3fa816c2022-04-19 10:21:20 +0800430+ } dbg;
431+ const struct mt7915_dbg_reg_desc *dbg_reg;
432+#endif
433 };
434
435 enum {
developer36fe7092023-09-27 12:24:47 +0800436@@ -599,4 +622,24 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developerf1313102022-10-11 11:02:55 +0800437 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
438 bool pci, int *irq);
developer3fa816c2022-04-19 10:21:20 +0800439
440+#ifdef MTK_DEBUG
441+int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir);
442+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp);
443+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled);
444+void mt7915_dump_tmac_info(u8 *tmac_info);
445+int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level);
446+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len);
developer9e5bcc52022-09-27 10:30:15 +0800447+int mt7915_mcu_set_amsdu_algo(struct mt7915_dev *dev, u16 wcid, u8 enable);
developer3fa816c2022-04-19 10:21:20 +0800448+
449+#define PKT_BIN_DEBUG_MAGIC 0xc8763123
450+enum {
451+ PKT_BIN_DEBUG_MCU,
452+ PKT_BIN_DEBUG_TXD,
453+ PKT_BIN_DEBUG_TX,
454+ PKT_BIN_DEBUG_RX,
455+ PKT_BIN_DEBUG_RX_RAW,
456+};
457+
458+#endif
459+
460 #endif
461diff --git a/mt7915/mt7915_debug.h b/mt7915/mt7915_debug.h
462new file mode 100644
developer36fe7092023-09-27 12:24:47 +0800463index 00000000..fa8794fd
developer3fa816c2022-04-19 10:21:20 +0800464--- /dev/null
465+++ b/mt7915/mt7915_debug.h
developera43cc482023-04-17 15:57:28 +0800466@@ -0,0 +1,1418 @@
developer3fa816c2022-04-19 10:21:20 +0800467+#ifndef __MT7915_DEBUG_H
468+#define __MT7915_DEBUG_H
469+
470+#ifdef MTK_DEBUG
471+
472+#define DBG_INVALID_BASE 0xffffffff
473+#define DBG_INVALID_OFFSET 0x0
474+
475+struct __dbg_map {
476+ u32 phys;
477+ u32 maps;
478+ u32 size;
479+};
480+
481+struct __dbg_reg {
482+ u32 base;
483+ u32 offs;
484+};
485+
486+struct __dbg_mask {
487+ u32 end;
488+ u32 start;
489+};
490+
491+enum dbg_base_rev {
492+ MT_DBG_WFDMA0_BASE,
493+ MT_DBG_WFDMA1_BASE,
494+ MT_DBG_WFDMA0_PCIE1_BASE,
495+ MT_DBG_WFDMA1_PCIE1_BASE,
496+ MT_DBG_WFDMA_EXT_CSR_BASE,
497+ MT_DBG_SWDEF_BASE,
498+ __MT_DBG_BASE_REV_MAX,
499+};
500+
501+enum dbg_reg_rev {
502+ DBG_INT_SOURCE_CSR,
503+ DBG_INT_MASK_CSR,
504+ DBG_INT1_SOURCE_CSR,
505+ DBG_INT1_MASK_CSR,
506+ DBG_TX_RING_BASE,
507+ DBG_RX_EVENT_RING_BASE,
508+ DBG_RX_STS_RING_BASE,
509+ DBG_RX_DATA_RING_BASE,
510+ DBG_DMA_ICSC_FR0,
511+ DBG_DMA_ICSC_FR1,
512+ DBG_TMAC_ICSCR0,
513+ DBG_RMAC_RXICSRPT,
514+ DBG_MIB_M0SDR0,
515+ DBG_MIB_M0SDR3,
516+ DBG_MIB_M0SDR4,
517+ DBG_MIB_M0SDR5,
518+ DBG_MIB_M0SDR7,
519+ DBG_MIB_M0SDR8,
520+ DBG_MIB_M0SDR9,
521+ DBG_MIB_M0SDR10,
522+ DBG_MIB_M0SDR11,
523+ DBG_MIB_M0SDR12,
524+ DBG_MIB_M0SDR14,
525+ DBG_MIB_M0SDR15,
526+ DBG_MIB_M0SDR16,
527+ DBG_MIB_M0SDR17,
528+ DBG_MIB_M0SDR18,
529+ DBG_MIB_M0SDR19,
530+ DBG_MIB_M0SDR20,
531+ DBG_MIB_M0SDR21,
532+ DBG_MIB_M0SDR22,
533+ DBG_MIB_M0SDR23,
534+ DBG_MIB_M0DR0,
535+ DBG_MIB_M0DR1,
536+ DBG_MIB_MUBF,
537+ DBG_MIB_M0DR6,
538+ DBG_MIB_M0DR7,
539+ DBG_MIB_M0DR8,
540+ DBG_MIB_M0DR9,
541+ DBG_MIB_M0DR10,
542+ DBG_MIB_M0DR11,
543+ DBG_MIB_M0DR12,
544+ DBG_WTBLON_WDUCR,
545+ DBG_UWTBL_WDUCR,
546+ DBG_PLE_DRR_TABLE_CTRL,
547+ DBG_PLE_DRR_TABLE_RDATA,
548+ DBG_PLE_PBUF_CTRL,
549+ DBG_PLE_QUEUE_EMPTY,
550+ DBG_PLE_FREEPG_CNT,
551+ DBG_PLE_FREEPG_HEAD_TAIL,
552+ DBG_PLE_PG_HIF_GROUP,
553+ DBG_PLE_HIF_PG_INFO,
554+ DBG_PLE_PG_HIF_TXCMD_GROUP,
555+ DBG_PLE_HIF_TXCMD_PG_INFO,
556+ DBG_PLE_PG_CPU_GROUP,
557+ DBG_PLE_CPU_PG_INFO,
558+ DBG_PLE_FL_QUE_CTRL,
559+ DBG_PLE_NATIVE_TXCMD_Q_EMPTY,
560+ DBG_PLE_TXCMD_Q_EMPTY,
561+ DBG_PLE_AC_QEMPTY,
562+ DBG_PLE_AC_OFFSET,
563+ DBG_PLE_STATION_PAUSE,
564+ DBG_PLE_DIS_STA_MAP,
565+ DBG_PSE_PBUF_CTRL,
566+ DBG_PSE_FREEPG_CNT,
567+ DBG_PSE_FREEPG_HEAD_TAIL,
568+ DBG_PSE_HIF0_PG_INFO,
569+ DBG_PSE_PG_HIF1_GROUP,
570+ DBG_PSE_HIF1_PG_INFO,
571+ DBG_PSE_PG_CPU_GROUP,
572+ DBG_PSE_CPU_PG_INFO,
573+ DBG_PSE_PG_PLE_GROUP,
574+ DBG_PSE_PLE_PG_INFO,
575+ DBG_PSE_PG_LMAC0_GROUP,
576+ DBG_PSE_LMAC0_PG_INFO,
577+ DBG_PSE_PG_LMAC1_GROUP,
578+ DBG_PSE_LMAC1_PG_INFO,
579+ DBG_PSE_PG_LMAC2_GROUP,
580+ DBG_PSE_LMAC2_PG_INFO,
581+ DBG_PSE_PG_LMAC3_GROUP,
582+ DBG_PSE_LMAC3_PG_INFO,
583+ DBG_PSE_PG_MDP_GROUP,
584+ DBG_PSE_MDP_PG_INFO,
585+ DBG_PSE_PG_PLE1_GROUP,
586+ DBG_PSE_PLE1_PG_INFO,
587+ DBG_AGG_AALCR0,
588+ DBG_AGG_AALCR1,
589+ DBG_AGG_AALCR2,
590+ DBG_AGG_AALCR3,
591+ DBG_AGG_AALCR4,
592+ DBG_AGG_B0BRR0,
593+ DBG_AGG_B1BRR0,
594+ DBG_AGG_B2BRR0,
595+ DBG_AGG_B3BRR0,
596+ DBG_AGG_AWSCR0,
597+ DBG_AGG_PCR0,
598+ DBG_AGG_TTCR0,
599+ DBG_MIB_M0ARNG0,
600+ DBG_MIB_M0DR2,
601+ DBG_MIB_M0DR13,
developer79a21a22023-01-09 13:57:39 +0800602+ DBG_WFDMA_WED_TX_CTRL,
603+ DBG_WFDMA_WED_RX_CTRL,
developer3fa816c2022-04-19 10:21:20 +0800604+ __MT_DBG_REG_REV_MAX,
605+};
606+
607+enum dbg_mask_rev {
608+ DBG_MIB_M0SDR10_RX_MDRDY_COUNT,
609+ DBG_MIB_M0SDR14_AMPDU,
610+ DBG_MIB_M0SDR15_AMPDU_ACKED,
611+ DBG_MIB_RX_FCS_ERROR_COUNT,
612+ __MT_DBG_MASK_REV_MAX,
613+};
614+
615+enum dbg_bit_rev {
616+ __MT_DBG_BIT_REV_MAX,
617+};
618+
619+static const u32 mt7915_dbg_base[] = {
620+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
621+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
622+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
623+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
624+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
625+ [MT_DBG_SWDEF_BASE] = 0x41f200,
626+};
627+
628+static const u32 mt7916_dbg_base[] = {
629+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
630+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
631+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
632+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
633+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
634+ [MT_DBG_SWDEF_BASE] = 0x411400,
635+};
636+
637+static const u32 mt7986_dbg_base[] = {
638+ [MT_DBG_WFDMA0_BASE] = 0x24000,
639+ [MT_DBG_WFDMA1_BASE] = 0x25000,
640+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0x28000,
641+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0x29000,
642+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0x27000,
643+ [MT_DBG_SWDEF_BASE] = 0x411400,
644+};
645+
646+/* mt7915 regs with different base and offset */
647+static const struct __dbg_reg mt7915_dbg_reg[] = {
developer79a21a22023-01-09 13:57:39 +0800648+ [DBG_WFDMA_WED_TX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x300 },
649+ [DBG_WFDMA_WED_RX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x400 },
developer3fa816c2022-04-19 10:21:20 +0800650+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x10 },
651+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x14 },
652+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x88 },
653+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x8c },
654+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x400 },
655+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x500 },
656+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x510 },
657+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
658+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x0f0 },
659+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x0f4 },
660+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x200 },
661+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0x618},
662+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x010},
663+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x014},
664+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x018},
665+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x01c},
666+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x024},
667+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x028},
668+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x02C},
669+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x030},
670+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x034},
671+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x038},
672+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x040},
673+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x044},
674+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x048},
675+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x04c},
676+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x050},
677+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x054},
678+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x058},
679+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x05c},
680+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x060},
681+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x064},
682+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x0a0},
683+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x0a4},
684+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x090},
685+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x0b8},
686+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x0bc},
687+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x0c0},
688+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x0c4},
689+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x0c8},
690+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x0cc},
691+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x160},
692+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x0},
693+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x0},
694+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x388},
695+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x350},
696+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
697+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x0b0},
698+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
699+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
700+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x110},
701+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x114},
702+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x120},
703+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x124},
704+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
705+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
706+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x1b0},
707+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x22c},
708+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x230},
709+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x500},
710+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x040},
711+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x400},
712+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x440},
developerf32dabf2022-06-01 10:59:24 +0800713+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
developer3fa816c2022-04-19 10:21:20 +0800714+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
715+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
716+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x114},
717+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x118},
718+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x11c},
719+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
720+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
721+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x160},
722+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x164},
723+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x170},
724+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x174},
725+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x178},
726+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
727+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x180},
728+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x184},
729+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x188},
730+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x18c},
731+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x198},
732+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x19c},
733+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x168},
734+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
735+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x048},
736+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x04c},
737+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x050},
738+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x054},
739+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x058},
740+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x100},
741+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x104},
742+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x108},
743+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x10c},
744+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x030},
745+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x040},
746+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x04c},
747+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x4b8},
748+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x0a8},
749+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x164},
750+};
751+
752+/* mt7986/mt7916 regs with different base and offset */
753+static const struct __dbg_reg mt7916_dbg_reg[] = {
developer79a21a22023-01-09 13:57:39 +0800754+ [DBG_WFDMA_WED_TX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x300 },
755+ [DBG_WFDMA_WED_RX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x400 },
developer3fa816c2022-04-19 10:21:20 +0800756+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA0_BASE, 0x200 },
757+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA0_BASE, 0x204 },
758+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x200 },
759+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x204 },
760+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x400 },
761+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
762+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x520 },
763+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x540 },
764+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x05c },
765+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x060 },
766+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x120 },
767+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0xd0 },
768+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x7d8},
769+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x698},
770+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x788},
771+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x780},
772+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x5a8},
773+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x78c},
774+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x024},
775+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x76c},
776+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x790},
777+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x558},
778+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x564},
779+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x564},
780+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x7fc},
781+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x800},
782+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x030},
783+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x5ac},
784+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x5b0},
785+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x5b4},
786+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x770},
787+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x774},
788+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x594},
789+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x598},
790+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x7ac},
791+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x658},
792+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x65c},
793+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x56c},
794+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x570},
795+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x578},
796+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x574},
797+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x654},
798+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x200},
799+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x094},
800+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x490},
801+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x470},
802+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
803+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x360},
804+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
805+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
806+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x00c},
807+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x388},
808+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x014},
809+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x390},
810+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x018},
811+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x394},
812+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x3e0},
813+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x370},
developerf32dabf2022-06-01 10:59:24 +0800814+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x36c},
developer3fa816c2022-04-19 10:21:20 +0800815+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x600},
816+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x080},
817+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x100},
818+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x180},
819+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
820+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
821+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
822+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x150},
823+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x154},
824+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
825+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x118},
826+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x158},
827+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x11c},
828+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x15c},
829+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x124},
830+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x164},
831+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x128},
832+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x168},
833+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x12c},
834+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
835+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x130},
836+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
837+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x134},
838+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x174},
839+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x120},
840+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
841+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x028},
842+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x144},
843+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x14c},
844+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x154},
845+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x02c},
846+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x08c},
847+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x148},
848+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x150},
849+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x158},
850+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x05c},
851+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x06c},
852+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x07c},
853+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x0b0},
854+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x7dc},
855+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x7ec},
856+};
857+
858+static const struct __dbg_mask mt7915_dbg_mask[] = {
859+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {25, 0},
860+ [DBG_MIB_M0SDR14_AMPDU] = {23, 0},
861+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {23, 0},
862+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {15, 0},
863+};
864+
865+static const struct __dbg_mask mt7916_dbg_mask[] = {
866+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {31, 0},
867+ [DBG_MIB_M0SDR14_AMPDU] = {31, 0},
868+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {31, 0},
869+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {31, 16},
870+};
871+
872+/* used to differentiate between generations */
873+struct mt7915_dbg_reg_desc {
874+ const u32 id;
875+ const u32 *base_rev;
876+ const struct __dbg_reg *reg_rev;
877+ const struct __dbg_mask *mask_rev;
878+};
879+
880+static const struct mt7915_dbg_reg_desc dbg_reg_s[] = {
881+ { 0x7915,
882+ mt7915_dbg_base,
883+ mt7915_dbg_reg,
884+ mt7915_dbg_mask
885+ },
886+ { 0x7906,
887+ mt7916_dbg_base,
888+ mt7916_dbg_reg,
889+ mt7916_dbg_mask
890+ },
891+ { 0x7986,
892+ mt7986_dbg_base,
893+ mt7916_dbg_reg,
894+ mt7916_dbg_mask
895+ },
896+};
897+
898+struct bin_debug_hdr {
899+ __le32 magic_num;
900+ __le16 serial_id;
901+ __le16 msg_type;
902+ __le16 len;
903+ __le16 des_len; /* descriptor len for rxd */
904+} __packed;
905+
developera43cc482023-04-17 15:57:28 +0800906+/* fw wm info related strcture */
907+struct cos_msg_trace_t {
908+ u32 dest_id;
909+ u8 msg_id;
910+ u32 pcount;
911+ u32 qread;
912+ u32 ts_enq;
913+ u32 ts_deq;
914+ u32 ts_finshq;
915+};
916+
917+struct cos_task_info_struct {
918+ u32 task_name_ptr;
919+ u32 task_qname_ptr;
920+ u32 task_priority;
921+ u16 task_stack_size;
922+ u8 task_ext_qsize;
923+ u32 task_id;
924+ u32 task_ext_qid;
925+ u32 task_main_func;
926+ u32 task_init_func;
927+};
928+
929+struct cos_program_trace_t{
930+ u32 dest_id;
931+ u32 msg_id;
932+ u32 msg_sn;
933+ u32 ts_gpt2;
934+ u32 LP;
935+ char name[12];
936+} ;
937+
938+struct cos_msg_type {
939+ u32 finish_cnt;
940+ u32 exe_time;
941+ u32 exe_peak;
942+};
943+
944+struct cos_task_type{
945+ u32 tc_stack_start;
946+ u32 tc_stack_end;
947+ u32 tc_stack_pointer;
948+ u32 tc_stack_size;
949+ u32 tc_schedule_count;
950+ u8 tc_status;
951+ u8 tc_priority;
952+ u8 tc_weight;
953+ u8 RSVD[28];
954+ u32 tc_entry_func;
955+ u32 tc_exe_start;
956+ u32 tc_exe_time;
957+ u32 tc_exe_peak;
958+ u32 tc_pcount;
959+};
960+
developer3fa816c2022-04-19 10:21:20 +0800961+#define __DBG_REG_MAP(_dev, id, ofs) ((_dev)->dbg_reg->base_rev[(id)] + (ofs))
962+#define __DBG_REG_BASE(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].base)
963+#define __DBG_REG_OFFS(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].offs)
964+
965+#define __DBG_MASK(_dev, id) GENMASK((_dev)->dbg_reg->mask_rev[(id)].end, \
966+ (_dev)->dbg_reg->mask_rev[(id)].start)
967+#define __DBG_REG(_dev, id) __DBG_REG_MAP((_dev), __DBG_REG_BASE((_dev), (id)), \
968+ __DBG_REG_OFFS((_dev), (id)))
969+
970+#define __DBG_FIELD_GET(id, _reg) (((_reg) & __DBG_MASK(dev, (id))) >> \
971+ dev->dbg_reg->mask_rev[(id)].start)
972+#define __DBG_FIELD_PREP(id, _reg) (((_reg) << dev->dbg_reg->mask_rev[(id)].start) & \
973+ __DBG_MASK(dev, (id)))
974+
975+
976+#define MT_DBG_TX_RING_BASE __DBG_REG(dev, DBG_TX_RING_BASE)
977+#define MT_DBG_RX_EVENT_RING_BASE __DBG_REG(dev, DBG_RX_EVENT_RING_BASE)
978+#define MT_DBG_RX_STS_RING_BASE __DBG_REG(dev, DBG_RX_STS_RING_BASE)
979+#define MT_DBG_RX_DATA_RING_BASE __DBG_REG(dev, DBG_RX_DATA_RING_BASE)
developer79a21a22023-01-09 13:57:39 +0800980+#define MT_DBG_WFDMA_WED_TX_CTRL_BASE __DBG_REG(dev, DBG_WFDMA_WED_TX_CTRL)
981+#define MT_DBG_WFDMA_WED_RX_CTRL_BASE __DBG_REG(dev, DBG_WFDMA_WED_RX_CTRL)
developer3fa816c2022-04-19 10:21:20 +0800982+
983+#define MT_DBG_TX_RING_CTRL(n) (MT_DBG_TX_RING_BASE + (0x10 * (n)))
984+#define MT_DBG_RX_DATA_RING_CTRL(n) (MT_DBG_RX_DATA_RING_BASE + (0x10 * (n)))
985+#define MT_DBG_RX_EVENT_RING_CTRL(n) (MT_DBG_RX_EVENT_RING_BASE + (0x10 * (n)))
986+
developer79a21a22023-01-09 13:57:39 +0800987+#define MT_DBG_WFDMA_WED_TX_CTRL(n) (MT_DBG_WFDMA_WED_TX_CTRL_BASE + (0x10 * (n)))
988+#define MT_DBG_WFDMA_WED_RX_CTRL(n) (MT_DBG_WFDMA_WED_RX_CTRL_BASE + (0x10 * (n)))
developer3fa816c2022-04-19 10:21:20 +0800989+/* WFDMA COMMON */
990+#define MT_DBG_INT_SOURCE_CSR __DBG_REG(dev, DBG_INT_SOURCE_CSR)
991+#define MT_DBG_INT_MASK_CSR __DBG_REG(dev, DBG_INT_MASK_CSR)
992+#define MT_DBG_INT1_SOURCE_CSR __DBG_REG(dev, DBG_INT1_SOURCE_CSR)
993+#define MT_DBG_INT1_MASK_CSR __DBG_REG(dev, DBG_INT1_MASK_CSR)
994+
995+/* WFDMA0 */
996+#define MT_DBG_WFDMA0(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_BASE, (_ofs))
997+
998+#define MT_DBG_WFDMA0_INT_SOURCE_CSR MT_DBG_WFDMA0(0x200)
999+#define MT_DBG_WFDMA0_INT_MASK_CSR MT_DBG_WFDMA0(0x204)
1000+
1001+#define MT_DBG_WFDMA0_GLO_CFG MT_DBG_WFDMA0(0x208)
1002+#define MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
1003+#define MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
1004+#define MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK BIT(1)
1005+#define MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK BIT(3)
1006+
1007+
1008+/* WFDMA1 */
1009+#define MT_DBG_WFDMA1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_BASE, (_ofs))
1010+#define MT_DBG_WFDMA1_INT_SOURCE_CSR MT_DBG_WFDMA1(0x200)
1011+#define MT_DBG_WFDMA1_INT_MASK_CSR MT_DBG_WFDMA1(0x204)
1012+
1013+#define MT_DBG_WFDMA1_GLO_CFG MT_DBG_WFDMA1(0x208)
1014+
1015+#define MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
1016+#define MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
1017+#define MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK BIT(1)
1018+#define MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK BIT(3)
1019+
1020+/* WFDMA0 PCIE1 */
1021+#define MT_DBG_WFDMA0_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_PCIE1_BASE, (_ofs))
1022+
1023+#define MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA0_PCIE1(0x200)
1024+#define MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR MT_DBG_WFDMA0_PCIE1(0x204)
1025+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG MT_DBG_WFDMA0_PCIE1(0x208)
1026+#define MT_DBG_WFDMA0_PCIE1_RX1_CTRL0 MT_DBG_WFDMA1_PCIE1(0x510)
1027+
1028+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
1029+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
1030+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
1031+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
1032+
1033+/* WFDMA1 PCIE1 */
1034+#define MT_DBG_WFDMA1_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_PCIE1_BASE, (_ofs))
1035+#define MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA1_PCIE1(0x200)
1036+#define MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR MT_DBG_WFDMA1_PCIE1(0x204)
1037+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG MT_DBG_WFDMA1_PCIE1(0x208)
1038+#define MT_DBG_WFDMA1_PCIE1_TX19_CTRL0 MT_DBG_WFDMA1_PCIE1(0x330)
1039+#define MT_DBG_WFDMA1_PCIE1_RX2_CTRL0 MT_DBG_WFDMA1_PCIE1(0x520)
1040+
1041+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
1042+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
1043+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
1044+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
1045+
1046+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK BIT(2)
1047+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK BIT(0)
1048+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK BIT(3)
1049+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK BIT(1)
1050+
1051+
1052+/* WF DMA TOP: band 0(0x820E7000),band 1(0x820F7000) */
1053+#define MT_DBG_WF_DMA_BASE(_band) ((_band) ? 0x820F7000 : 0x820E7000)
1054+#define MT_DBG_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
1055+
1056+#define MT_DBG_DMA_DCR0(_band) MT_DBG_WF_DMA((_band), 0x000)
1057+#define MT_DBG_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
1058+#define MT_DBG_DMA_DCR0_RXD_G5_EN BIT(23)
1059+
1060+#define MT_DBG_DMA_ICSC_FR0(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR0))
1061+#define MT_DBG_DMA_ICSC_FR0_RXBF_EN BIT(25)
1062+#define MT_DBG_DMA_ICSC_FR0_EN BIT(24)
1063+#define MT_DBG_DMA_ICSC_FR0_TOUT_MASK GENMASK(23, 16)
1064+#define MT_DBG_DMA_ICSC_FR0_PID_MASK GENMASK(9, 8)
1065+#define MT_DBG_DMA_ICSC_FR0_QID_MASK GENMASK(6, 0)
1066+
1067+#define MT_DBG_DMA_ICSC_FR1(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR1))
1068+#define MT_DBG_DMA_ICSC_FR1_AGG_SIZE_MASK GENMASK(26, 16)
1069+#define MT_DBG_DMA_ICSC_FR1_MAX_FRAME_SIZE_MASK GENMASK(10, 0)
1070+
1071+/* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
1072+#define MT_DBG_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
1073+#define MT_DBG_WF_TMAC(_band, ofs) (MT_DBG_WF_TMAC_BASE(_band) + (ofs))
1074+
1075+#define MT_DBG_TMAC_ICSCR0(_band) MT_DBG_WF_TMAC((_band), __DBG_REG_OFFS(dev, DBG_TMAC_ICSCR0))
1076+#define MT_DBG_TMAC_ICSCR0_ICSRPT_EN BIT(0)
1077+
1078+/* RMAC: band 0(0x820E5000), band 1(0x820f5000) */
1079+#define MT_DBG_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820E5000)
1080+#define MT_DBG_WF_RMAC(_band, ofs) (MT_DBG_WF_RMAC_BASE(_band) + (ofs))
1081+
1082+#define MT_DBG_RMAC_RXICSRPT(_band) MT_DBG_WF_RMAC((_band), __DBG_REG_OFFS(dev, DBG_RMAC_RXICSRPT))
1083+#define MT_DBG_RMAC_RXICSRPT_ICSRPT_EN BIT(0)
1084+
1085+/* MIB: band 0(0x820ed000), band 1(0x820fd000) */
1086+#define MT_DBG_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
1087+#define MT_DBG_MIB(_band, ofs) (MT_DBG_MIB_BASE(_band) + (ofs))
1088+
1089+
1090+#define MT_DBG_MIB_M0SCR0(_band) MT_DBG_MIB((_band), 0x00)
1091+#define MT_DBG_MIB_M0PBSCR(_band) MT_DBG_MIB((_band), 0x04)
1092+
1093+#define MT_DBG_MIB_M0SDR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR0))
1094+#define MT_DBG_MIB_M0SDR3(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR3))
1095+#define MT_DBG_MIB_RX_FCS_ERROR_COUNT_MASK __DBG_MASK(dev, DBG_MIB_RX_FCS_ERROR_COUNT)
1096+#define MT_DBG_MIB_M0SDR4(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR4))
1097+#define MT_DBG_MIB_M0SDR5(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR5))
1098+#define MT_DBG_MIB_M0SDR6(_band) MT_DBG_MIB((_band), 0x20)
1099+#define MT_DBG_MIB_M0SDR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR7))
1100+#define MT_DBG_MIB_M0SDR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR8))
1101+#define MT_DBG_MIB_M0SDR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR9))
1102+#define MT_DBG_MIB_M0SDR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR10))
1103+#define MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK __DBG_MASK(dev, DBG_MIB_M0SDR10_RX_MDRDY_COUNT)
1104+#define MT_DBG_MIB_M0SDR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR11))
1105+
1106+#define MT_DBG_MIB_M0SDR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR12))
1107+
1108+#define MT_DBG_MIB_M0SDR14(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR14))
1109+#define MT_DBG_MIB_M0SDR14_AMPDU_MASK __DBG_MASK(dev, DBG_MIB_M0SDR14_AMPDU)
1110+#define MT_DBG_MIB_M0SDR15(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR15))
1111+#define MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK __DBG_MASK(dev, DBG_MIB_M0SDR15_AMPDU_ACKED)
1112+#define MT_DBG_MIB_M0SDR16(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR16))
1113+#define MT_DBG_MIB_M0SDR17(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR17))
1114+#define MT_DBG_MIB_M0SDR18(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR18))
1115+#define MT_DBG_MIB_M0SDR19(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR19))
1116+#define MT_DBG_MIB_M0SDR20(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR20))
1117+#define MT_DBG_MIB_M0SDR21(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR21))
1118+#define MT_DBG_MIB_M0SDR22(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR22))
1119+#define MT_DBG_MIB_M0SDR23(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR23))
1120+#define MT_DBG_MIB_M0DR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR0))
1121+#define MT_DBG_MIB_M0DR1(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR1))
1122+
1123+#define MT_DBG_MIB_MUBF(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_MUBF))
1124+#define MT_DBG_MIB_M0DR6(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR6))
1125+#define MT_DBG_MIB_M0DR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR7))
1126+#define MT_DBG_MIB_M0DR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR8))
1127+#define MT_DBG_MIB_M0DR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR9))
1128+#define MT_DBG_MIB_M0DR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR10))
1129+#define MT_DBG_MIB_M0DR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR11))
1130+ #define MT_DBG_MIB_M0DR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR12))
1131+
1132+/* WTBLON TOP: 0x820D4000/pcie(0x34000) rbus(0x434000) */
1133+#define MT_DBG_WTBLON_TOP_BASE 0x820D4000
1134+#define MT_DBG_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
1135+#define MT_DBG_WTBLON_TOP_WDUCR MT_DBG_WTBLON_TOP(__DBG_REG_OFFS(dev, DBG_WTBLON_WDUCR))
1136+#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
1137+
1138+#define WF_WTBLON_TOP_B0BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1000) // 5000
1139+#define WF_WTBLON_TOP_B0BTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1010) // 5010
1140+#define WF_WTBLON_TOP_B0BRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1020) // 5020
1141+#define WF_WTBLON_TOP_B0BRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1030) // 5030
1142+#define WF_WTBLON_TOP_B0BTDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1040) // 5040
1143+#define WF_WTBLON_TOP_B0BRDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1050) // 5050
1144+#define WF_WTBLON_TOP_B0MBTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1100) // 5100
1145+#define WF_WTBLON_TOP_B0MBTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1140) // 5140
1146+#define WF_WTBLON_TOP_B0MBRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1180) // 5180
1147+#define WF_WTBLON_TOP_B0MBRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x11C0) // 51C0
1148+
1149+#define WF_WTBLON_TOP_B1BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1800) // 5800
1150+
1151+/* WTBLON TOP: 0x820C4000/pcie(0xa8000) rbus(0x4a8000) */
1152+#define MT_DBG_UWTBL_TOP_BASE 0x820C4000
1153+#define MT_DBG_UWTBL_TOP(ofs) (MT_DBG_UWTBL_TOP_BASE + (ofs))
1154+
developerf1313102022-10-11 11:02:55 +08001155+#define MT_DBG_UWTBL_TOP_WDUCR MT_DBG_UWTBL_TOP(__DBG_REG_OFFS(dev, DBG_UWTBL_WDUCR))
developer3fa816c2022-04-19 10:21:20 +08001156+
1157+#define MT_UWTBL_TOP_WDUCR_TARGET BIT(31)
1158+#define MT_UWTBL_TOP_WDUCR_GROUP GENMASK(3, 0)
1159+
1160+
1161+/* WTBL : 0x820D8000/pcie(0x38000) rbus(0x438000) */
1162+#define MT_DBG_WTBL_BASE 0x820D8000
1163+
1164+/* PLE related CRs. */
1165+#define MT_DBG_PLE_BASE 0x820C0000
1166+#define MT_DBG_PLE(ofs) (MT_DBG_PLE_BASE + (ofs))
1167+
1168+#define MT_DBG_PLE_DRR_TAB_CTRL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_CTRL))
1169+#define MT_DBG_PLE_DRR_TAB_RD_OFS __DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_RDATA)
1170+
1171+#define MT_DBG_PLE_DRR_TABLE_RDATA0 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x0)
1172+#define MT_DBG_PLE_DRR_TABLE_RDATA1 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x4)
1173+#define MT_DBG_PLE_DRR_TABLE_RDATA2 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x8)
1174+#define MT_DBG_PLE_DRR_TABLE_RDATA3 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0xc)
1175+#define MT_DBG_PLE_DRR_TABLE_RDATA4 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x10)
1176+#define MT_DBG_PLE_DRR_TABLE_RDATA5 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x14)
1177+#define MT_DBG_PLE_DRR_TABLE_RDATA6 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x18)
1178+#define MT_DBG_PLE_DRR_TABLE_RDATA7 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS+ 0x1c)
1179+
1180+#define MT_DBG_PLE_PBUF_CTRL_ADDR MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PBUF_CTRL))
1181+#define MT_DBG_PLE_QUEUE_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_QUEUE_EMPTY))
1182+#define MT_DBG_PLE_FREEPG_CNT MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_CNT))
1183+#define MT_DBG_PLE_FREEPG_HEAD_TAIL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_HEAD_TAIL))
1184+#define MT_DBG_PLE_PG_HIF_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_GROUP))
1185+#define MT_DBG_PLE_HIF_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_PG_INFO))
1186+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_TXCMD_GROUP))
1187+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_TXCMD_PG_INFO))
1188+#define MT_DBG_PLE_PG_CPU_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_CPU_GROUP))
1189+#define MT_DBG_PLE_CPU_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_CPU_PG_INFO))
1190+#define PLE_FL_QUE_CTRL_OFFSET __DBG_REG_OFFS(dev, DBG_PLE_FL_QUE_CTRL)
1191+#define MT_DBG_PLE_FL_QUE_CTRL0 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x0)
1192+#define MT_DBG_PLE_FL_QUE_CTRL1 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x4)
1193+#define MT_DBG_PLE_FL_QUE_CTRL2 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x8)
1194+#define MT_DBG_PLE_FL_QUE_CTRL3 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0xc)
1195+#define MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_NATIVE_TXCMD_Q_EMPTY))
1196+#define MT_DBG_PLE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_TXCMD_Q_EMPTY))
1197+
1198+#define MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK BIT(31)
1199+#define MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK GENMASK(25, 17)
1200+#define MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1201+
1202+#define MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1203+#define MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1204+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1205+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1206+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK GENMASK(27, 16)
1207+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK GENMASK(11, 0)
1208+
1209+#define MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK GENMASK(27, 16)
1210+#define MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK GENMASK(11, 0)
1211+
1212+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK GENMASK(27, 16)
1213+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK GENMASK(11, 0)
1214+
1215+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
1216+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
1217+
1218+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
1219+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
1220+
1221+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1222+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1223+
1224+#define MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1225+#define MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1226+
1227+#define MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK BIT(24)
1228+#define MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK BIT(31)
1229+#define MT_DBG_PLE_FL_QUE_CTRL0_Q_BUF_QID_MASK GENMASK(30, 24)
1230+
1231+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT 24
1232+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT 10
1233+
1234+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK GENMASK(27, 16)
1235+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK GENMASK(11, 0)
1236+#define MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK GENMASK(11, 0)
1237+
1238+#define MT_DBG_PLE_STATION_PAUSE(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_STATION_PAUSE) + ((n) << 2))
1239+#define MT_DBG_PLE_DIS_STA_MAP(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DIS_STA_MAP) + ((n) << 2))
1240+#define MT_DBG_PLE_AC_QEMPTY(ac, n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_AC_QEMPTY) + \
1241+ __DBG_REG_OFFS(dev, DBG_PLE_AC_OFFSET) * (ac) + ((n) << 2))
1242+
1243+#define MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(n) MT_DBG_PLE(0x10e0 + ((n) << 2))
1244+
1245+/* pseinfo related CRs. */
1246+#define MT_DBG_PSE_BASE 0x820C8000
1247+#define MT_DBG_PSE(ofs) (MT_DBG_PSE_BASE + (ofs))
1248+
developerf32dabf2022-06-01 10:59:24 +08001249+#define MT_DBG_PSE_PBUF_CTRL MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PBUF_CTRL))
1250+#define MT_DBG_PSE_QUEUE_EMPTY MT_DBG_PSE(0x0b0)
1251+#define MT_DBG_PSE_FREEPG_CNT MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_CNT))
1252+#define MT_DBG_PSE_FREEPG_HEAD_TAIL MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_HEAD_TAIL))
1253+#define MT_DBG_PSE_PG_HIF0_GROUP MT_DBG_PSE(0x110)
1254+#define MT_DBG_PSE_HIF0_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_HIF0_PG_INFO))
1255+#define MT_DBG_PSE_PG_HIF1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_HIF1_GROUP))
1256+#define MT_DBG_PSE_HIF1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_HIF1_PG_INFO))
1257+#define MT_DBG_PSE_PG_CPU_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_CPU_GROUP))
1258+#define MT_DBG_PSE_CPU_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_CPU_PG_INFO))
1259+#define MT_DBG_PSE_PG_LMAC0_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC0_GROUP))
1260+#define MT_DBG_PSE_LMAC0_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC0_PG_INFO))
1261+#define MT_DBG_PSE_PG_LMAC1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC1_GROUP))
1262+#define MT_DBG_PSE_LMAC1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC1_PG_INFO))
1263+#define MT_DBG_PSE_PG_LMAC2_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC2_GROUP))
1264+#define MT_DBG_PSE_LMAC2_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC2_PG_INFO))
1265+#define MT_DBG_PSE_PG_PLE_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE_GROUP))
1266+#define MT_DBG_PSE_PLE_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PLE_PG_INFO))
1267+#define MT_DBG_PSE_PG_LMAC3_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC3_GROUP))
1268+#define MT_DBG_PSE_LMAC3_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC3_PG_INFO))
1269+#define MT_DBG_PSE_PG_MDP_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_MDP_GROUP))
1270+#define MT_DBG_PSE_MDP_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_MDP_PG_INFO))
1271+#define MT_DBG_PSE_PG_PLE1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE1_GROUP))
1272+#define MT_DBG_PSE_PLE1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PLE1_PG_INFO))
developer3fa816c2022-04-19 10:21:20 +08001273+
1274+#define MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK BIT(31)
1275+#define MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK GENMASK(25, 17)
1276+#define MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1277+#define MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK BIT(31)
1278+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK BIT(23)
1279+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK BIT(22)
1280+#define MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK BIT(21)
1281+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT BIT(20)
1282+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK BIT(19)
1283+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK BIT(18)
1284+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK BIT(17)
1285+#define MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK BIT(16)
1286+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK BIT(13)
1287+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK BIT(12)
1288+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK BIT(11)
1289+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK BIT(10)
1290+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK BIT(9)
1291+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK BIT(8)
1292+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK BIT(3)
1293+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK BIT(2)
1294+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK BIT(1)
1295+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK BIT(0)
1296+#define MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1297+#define MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1298+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1299+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1300+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1301+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1302+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1303+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1304+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK GENMASK(27, 16)
1305+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK GENMASK(11, 0)
1306+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK GENMASK(27, 16)
1307+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK GENMASK(11, 0)
1308+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK GENMASK(27, 16)
1309+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK GENMASK(11, 0)
1310+#define MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1311+#define MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1312+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK GENMASK(27, 16)
1313+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK GENMASK(11, 0)
1314+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1315+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1316+#define MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK GENMASK(27, 16)
1317+#define MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK GENMASK(11, 0)
1318+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK GENMASK(27, 16)
1319+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK GENMASK(11, 0)
1320+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK GENMASK(27, 16)
1321+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK GENMASK(11, 0)
1322+#define MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK GENMASK(27, 16)
1323+#define MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK GENMASK(11, 0)
1324+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK GENMASK(27, 16)
1325+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK GENMASK(11, 0)
1326+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK GENMASK(27, 16)
1327+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK GENMASK(11, 0)
1328+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK GENMASK(27, 16)
1329+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK GENMASK(11, 0)
1330+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1331+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1332+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK GENMASK(27, 16)
1333+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK GENMASK(11, 0)
1334+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1335+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1336+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK GENMASK(27, 16)
1337+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK GENMASK(11, 0)
1338+#define MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK GENMASK(27, 16)
1339+#define MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK GENMASK(11, 0)
1340+
1341+#define MT_DBG_PSE_FL_QUE_CTRL_0_ADDR MT_DBG_PLE(0x1b0)
1342+#define MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK BIT(31)
1343+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24
1344+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT 10
1345+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK GENMASK(9, 0)
1346+
1347+#define MT_DBG_PSE_FL_QUE_CTRL_2_ADDR MT_DBG_PLE(0x1b8)
1348+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK GENMASK(27, 16)
1349+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK GENMASK(11, 0)
1350+
1351+#define MT_DBG_PSE_FL_QUE_CTRL_3_ADDR MT_DBG_PLE(0x1bc)
1352+#define MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK GENMASK(11, 0)
1353+
1354+
1355+/* AGG */
1356+#define MT_DBG_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
1357+#define MT_DBG_AGG(_band, ofs) (MT_DBG_AGG_BASE(_band) + (ofs))
1358+
1359+#define MT_DBG_AGG_AALCR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR0))
1360+#define MT_DBG_AGG_AALCR1(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR1))
1361+#define MT_DBG_AGG_AALCR2(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR2))
1362+#define MT_DBG_AGG_AALCR3(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR3))
1363+#define MT_DBG_AGG_AALCR4(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR4))
1364+#define MT_DBG_AGG_B0BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B0BRR0))
1365+#define MT_DBG_AGG_B1BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B1BRR0))
1366+#define MT_DBG_AGG_B2BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B2BRR0))
1367+#define MT_DBG_AGG_B3BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B3BRR0))
1368+#define MT_DBG_AGG_AWSCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AWSCR0) + ((n) << 2))
1369+#define MT_DBG_AGG_PCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_PCR0) + ((n) << 2))
1370+#define MT_DBG_AGG_TTCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_TTCR0) + ((n) << 2))
1371+#define MT_DBG_MIB_M0ARNG(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0ARNG0) + ((n) << 2))
1372+#define MT_DBG_MIB_M0DR2(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR2) + ((n) << 2))
1373+#define MT_DBG_MIB_M0DR13(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR13) + ((n) << 2))
1374+
1375+#define MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK GENMASK(31, 24)
1376+#define MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK GENMASK(23, 16)
1377+#define MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK GENMASK(15, 8)
1378+#define MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK GENMASK(7, 0)
1379+#define MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK GENMASK(7, 0)
1380+
1381+#define MT_DBG_AGG_AWSCR0_WINSIZE3_MASK GENMASK(31, 24)
1382+#define MT_DBG_AGG_AWSCR0_WINSIZE2_MASK GENMASK(23, 16)
1383+#define MT_DBG_AGG_AWSCR0_WINSIZE1_MASK GENMASK(15, 8)
1384+#define MT_DBG_AGG_AWSCR0_WINSIZE0_MASK GENMASK(7, 0)
1385+
1386+#define MT_DBG_AGG_AWSCR1_WINSIZE7_MASK GENMASK(31, 24)
1387+#define MT_DBG_AGG_AWSCR1_WINSIZE6_MASK GENMASK(23, 16)
1388+#define MT_DBG_AGG_AWSCR1_WINSIZE5_MASK GENMASK(15, 8)
1389+#define MT_DBG_AGG_AWSCR1_WINSIZE4_MASK GENMASK(7, 0)
1390+
1391+#define MT_DBG_AGG_AWSCR2_WINSIZEB_MASK GENMASK(31, 24)
1392+#define MT_DBG_AGG_AWSCR2_WINSIZEA_MASK GENMASK(23, 16)
1393+#define MT_DBG_AGG_AWSCR2_WINSIZE9_MASK GENMASK(15, 8)
1394+#define MT_DBG_AGG_AWSCR2_WINSIZE8_MASK GENMASK(7, 0)
1395+
1396+#define MT_DBG_AGG_AWSCR3_WINSIZEE_MASK GENMASK(23, 16)
1397+#define MT_DBG_AGG_AWSCR3_WINSIZED_MASK GENMASK(15, 8)
1398+#define MT_DBG_AGG_AWSCR3_WINSIZEC_MASK GENMASK(7, 0)
1399+
1400+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK GENMASK(31, 24)
1401+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK GENMASK(23, 16)
1402+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK GENMASK(15, 8)
1403+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK GENMASK(7, 0)
1404+
1405+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK GENMASK(31, 24)
1406+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK GENMASK(23, 16)
1407+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK GENMASK(15, 8)
1408+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK GENMASK(7, 0)
1409+
1410+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK GENMASK(31, 24)
1411+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK GENMASK(23, 16)
1412+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK GENMASK(15, 8)
1413+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK GENMASK(7, 0)
1414+
1415+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK GENMASK(23, 16)
1416+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK GENMASK(15, 8)
1417+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK GENMASK(7, 0)
1418+
1419+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK GENMASK(31, 16)
1420+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK GENMASK(15, 0)
1421+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK GENMASK(31, 16)
1422+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK GENMASK(15, 0)
1423+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK GENMASK(31, 16)
1424+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK GENMASK(15, 0)
1425+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK GENMASK(31, 16)
1426+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK GENMASK(15, 0)
1427+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK GENMASK(31, 16)
1428+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK GENMASK(15, 0)
1429+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK GENMASK(31, 16)
1430+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK GENMASK(15, 0)
1431+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK GENMASK(31, 16)
1432+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK GENMASK(15, 0)
1433+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK GENMASK(31, 16)
1434+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK GENMASK(15, 0)
1435+
1436+/* mt7915 host DMA*/
1437+#define MT_DBG_INT_DMA1_R0_DONE BIT(0)
1438+#define MT_DBG_INT_DMA1_R1_DONE BIT(1)
1439+#define MT_DBG_INT_DMA1_R2_DONE BIT(2)
1440+
1441+#define MT_DBG_INT_DMA1_T16_DONE BIT(26)
1442+#define MT_DBG_INT_DMA1_T17_DONE BIT(27)
1443+#define MT_DBG_INT_DMA1_T18_DONE BIT(30)
1444+#define MT_DBG_INT_DMA1_T19_DONE BIT(31)
1445+#define MT_DBG_INT_DMA1_T20_DONE BIT(15)
1446+
1447+#define MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE BIT(16)
1448+#define MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE BIT(17)
1449+
1450+/* mt7986 host DMA */
1451+#define MT_DBG_INT_DMA0_R0_DONE BIT(0)
1452+#define MT_DBG_INT_DMA0_R1_DONE BIT(1)
1453+#define MT_DBG_INT_DMA0_R2_DONE BIT(2)
1454+#define MT_DBG_INT_DMA0_R3_DONE BIT(3)
1455+#define MT_DBG_INT_DMA0_R4_DONE BIT(22)
1456+#define MT_DBG_INT_DMA0_R5_DONE BIT(23)
1457+
1458+#define MT_DBG_INT_DMA0_T16_DONE BIT(26)
1459+#define MT_DBG_INT_DMA0_T17_DONE BIT(27)
1460+#define MT_DBG_INT_DMA0_T18_DONE BIT(30)
1461+#define MT_DBG_INT_DMA0_T19_DONE BIT(31)
1462+#define MT_DBG_INT_DMA0_T20_DONE BIT(25)
1463+
1464+/* MCU DMA */
1465+#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
1466+#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
1467+#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
1468+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
1469+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1470+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1471+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1472+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1473+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1474+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1475+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1476+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1477+
1478+#define WF_WFDMA_MCU_DMA1_BASE 0x55000000
1479+#define WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x200) // 0200
1480+#define WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0X204) // 0204
1481+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x208) // 0208
1482+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1483+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1484+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1485+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1486+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1487+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1488+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1489+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1490+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x300) // 0300
1491+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x310) // 0310
1492+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x320) // 0320
1493+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x500) // 0500
1494+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x510) // 0510
1495+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x520) // 0520
1496+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x530) // 0530
1497+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x540) // 0540
1498+
1499+#define WF_WFDMA_MCU_DMA1_PCIE1_BASE 0x59000000
1500+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x200) // 0200
1501+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0X204) // 0204
1502+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x208) // 0208
1503+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1504+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1505+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1506+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1507+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1508+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1509+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1510+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1511+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x320) // 0320
1512+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x530) // 0530
1513+
1514+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
1515+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
1516+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
1517+/* mt7986 add */
1518+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330
1519+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340
1520+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350
1521+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360
1522+
1523+
1524+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
1525+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
1526+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
1527+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
1528+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
1529+
1530+/* mt7986 add */
1531+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550
1532+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560
1533+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570
1534+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580
1535+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590
1536+
1537+/* MEM DMA */
1538+#define WF_WFDMA_MEM_DMA_BASE 0x58000000
1539+#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
1540+#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
1541+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
1542+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1543+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1544+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1545+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1546+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1547+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1548+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1549+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1550+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
1551+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
1552+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
1553+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
1554+
1555+enum resource_attr {
1556+ HIF_TX_DATA,
1557+ HIF_TX_CMD,
1558+ HIF_TX_CMD_WM, /* direct path to WMCPU, only exist for WFDMA arch with 2 CPU */
1559+ HIF_TX_FWDL,
1560+ HIF_RX_DATA,
1561+ HIF_RX_EVENT,
1562+ RING_ATTR_NUM
1563+};
1564+
1565+struct hif_pci_tx_ring_desc {
1566+ u32 hw_int_mask;
1567+ u16 ring_size;
1568+ enum resource_attr ring_attr;
1569+ u8 band_idx;
1570+ char *const ring_info;
1571+};
1572+
1573+struct hif_pci_rx_ring_desc {
1574+ u32 hw_desc_base;
1575+ u32 hw_int_mask;
1576+ u16 ring_size;
1577+ enum resource_attr ring_attr;
1578+ u16 max_rx_process_cnt;
1579+ u16 max_sw_read_idx_inc;
1580+ char *const ring_info;
developer79a21a22023-01-09 13:57:39 +08001581+ bool flags;
developer3fa816c2022-04-19 10:21:20 +08001582+};
1583+
1584+const struct hif_pci_tx_ring_desc mt7915_tx_ring_layout[] = {
1585+ {
1586+ .hw_int_mask = MT_DBG_INT_DMA1_T16_DONE,
1587+ .ring_size = 128,
1588+ .ring_attr = HIF_TX_FWDL,
1589+ .ring_info = "FWDL"
1590+ },
1591+ {
1592+ .hw_int_mask = MT_DBG_INT_DMA1_T17_DONE,
1593+ .ring_size = 256,
1594+ .ring_attr = HIF_TX_CMD_WM,
1595+ .ring_info = "cmd to WM"
1596+ },
1597+ {
1598+ .hw_int_mask = MT_DBG_INT_DMA1_T18_DONE,
1599+ .ring_size = 2048,
1600+ .ring_attr = HIF_TX_DATA,
1601+ .ring_info = "band0 TXD"
1602+ },
1603+ {
1604+ .hw_int_mask = MT_DBG_INT_DMA1_T19_DONE,
1605+ .ring_size = 2048,
1606+ .ring_attr = HIF_TX_DATA,
1607+ .ring_info = "band1 TXD"
1608+ },
1609+ {
1610+ .hw_int_mask = MT_DBG_INT_DMA1_T20_DONE,
1611+ .ring_size = 256,
1612+ .ring_attr = HIF_TX_CMD,
1613+ .ring_info = "cmd to WA"
1614+ }
1615+};
1616+
1617+const struct hif_pci_rx_ring_desc mt7915_rx_ring_layout[] = {
1618+ {
1619+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE,
1620+ .ring_size = 1536,
1621+ .ring_attr = HIF_RX_DATA,
1622+ .ring_info = "band0 RX data"
1623+ },
1624+ {
1625+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE,
1626+ .ring_size = 1536,
1627+ .ring_attr = HIF_RX_DATA,
1628+ .ring_info = "band1 RX data"
1629+ },
1630+ {
1631+ .hw_int_mask = MT_DBG_INT_DMA1_R0_DONE,
1632+ .ring_size = 512,
1633+ .ring_attr = HIF_RX_EVENT,
1634+ .ring_info = "event from WM"
1635+ },
1636+ {
1637+ .hw_int_mask = MT_DBG_INT_DMA1_R1_DONE,
1638+ .ring_size = 1024,
1639+ .ring_attr = HIF_RX_EVENT,
developer79a21a22023-01-09 13:57:39 +08001640+ .ring_info = "event from WA band0",
1641+ .flags = true
developer3fa816c2022-04-19 10:21:20 +08001642+ },
1643+ {
1644+ .hw_int_mask = MT_DBG_INT_DMA1_R2_DONE,
1645+ .ring_size = 512,
1646+ .ring_attr = HIF_RX_EVENT,
1647+ .ring_info = "event from WA band1"
1648+ }
1649+};
1650+
1651+const struct hif_pci_tx_ring_desc mt7986_tx_ring_layout[] = {
1652+ {
1653+ .hw_int_mask = MT_DBG_INT_DMA0_T16_DONE,
1654+ .ring_size = 128,
1655+ .ring_attr = HIF_TX_FWDL,
1656+ .ring_info = "FWDL"
1657+ },
1658+ {
1659+ .hw_int_mask = MT_DBG_INT_DMA0_T17_DONE,
1660+ .ring_size = 256,
1661+ .ring_attr = HIF_TX_CMD_WM,
1662+ .ring_info = "cmd to WM"
1663+ },
1664+ {
1665+ .hw_int_mask = MT_DBG_INT_DMA0_T18_DONE,
1666+ .ring_size = 2048,
1667+ .ring_attr = HIF_TX_DATA,
1668+ .ring_info = "band0 TXD"
1669+ },
1670+ {
1671+ .hw_int_mask = MT_DBG_INT_DMA0_T19_DONE,
1672+ .ring_size = 2048,
1673+ .ring_attr = HIF_TX_DATA,
1674+ .ring_info = "band1 TXD"
1675+ },
1676+ {
1677+ .hw_int_mask = MT_DBG_INT_DMA0_T20_DONE,
1678+ .ring_size = 256,
1679+ .ring_attr = HIF_TX_CMD,
1680+ .ring_info = "cmd to WA"
1681+ }
1682+};
1683+
1684+const struct hif_pci_rx_ring_desc mt7986_rx_ring_layout[] = {
1685+ {
1686+ .hw_int_mask = MT_DBG_INT_DMA0_R4_DONE,
1687+ .ring_size = 1536,
1688+ .ring_attr = HIF_RX_DATA,
1689+ .ring_info = "band0 RX data"
1690+ },
1691+ {
1692+ .hw_int_mask = MT_DBG_INT_DMA0_R5_DONE,
1693+ .ring_size = 1536,
1694+ .ring_attr = HIF_RX_DATA,
1695+ .ring_info = "band1 RX data"
1696+ },
1697+ {
1698+ .hw_int_mask = MT_DBG_INT_DMA0_R0_DONE,
1699+ .ring_size = 512,
1700+ .ring_attr = HIF_RX_EVENT,
1701+ .ring_info = "event from WM"
1702+ },
1703+ {
1704+ .hw_int_mask = MT_DBG_INT_DMA0_R1_DONE,
1705+ .ring_size = 512,
1706+ .ring_attr = HIF_RX_EVENT,
1707+ .ring_info = "event from WA"
1708+ },
1709+ {
1710+ .hw_int_mask = MT_DBG_INT_DMA0_R2_DONE,
1711+ .ring_size = 1024,
1712+ .ring_attr = HIF_RX_EVENT,
developer79a21a22023-01-09 13:57:39 +08001713+ .ring_info = "STS WA band0",
1714+ .flags = true
developer3fa816c2022-04-19 10:21:20 +08001715+ },
1716+ {
1717+ .hw_int_mask = MT_DBG_INT_DMA0_R3_DONE,
1718+ .ring_size = 512,
1719+ .ring_attr = HIF_RX_EVENT,
1720+ .ring_info = "STS WA band1"
1721+ },
1722+};
1723+
1724+/* mibinfo related CRs. */
1725+#define BN0_WF_MIB_TOP_BASE 0x820ed000
1726+#define BN1_WF_MIB_TOP_BASE 0x820fd000
1727+
1728+#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400
1729+#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x428) // D428
1730+#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x4F0) // D4F0
1731+
1732+#define BN0_WF_MIB_TOP_BSDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x688) // D688
1733+#define BN0_WF_MIB_TOP_BSDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x690) // D690
1734+
1735+#define BN0_WF_MIB_TOP_BSDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x518) // D518
1736+#define BN0_WF_MIB_TOP_BSDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x520) // D520
1737+#define BN0_WF_MIB_TOP_BSDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x528) // D528
1738+#define BN0_WF_MIB_TOP_BSDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x530) // D530
1739+#define BN0_WF_MIB_TOP_BSDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x538) // D538
1740+
1741+#define BN0_WF_MIB_TOP_BROCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5B8) // D5B8
1742+#define BN0_WF_MIB_TOP_BRBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0
1743+#define BN0_WF_MIB_TOP_BRDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x630) // D630
1744+
1745+#define BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK 0x0000FFFF // BEACONTXCOUNT[15..0]
1746+
1747+#define BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK 0x0000FFFF // RX_FIFO_FULL_COUNT[15..0]
1748+
1749+#define BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
1750+
1751+#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
1752+
1753+#define BN1_WF_MIB_TOP_BTOCR_ADDR (BN1_WF_MIB_TOP_BASE + 0x400) // D400
1754+
1755+#define BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK 0x0000FFFF // VEC_MISS_COUNT[15..0]
1756+#define BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK 0x0000FFFF // DELIMITER_FAIL_COUNT[15..0]
1757+#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
1758+
1759+#define BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK 0x0000FFFF // RX_LEN_MISMATCH[15..0]
1760+
1761+#define BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK 0x00FFFFFF // P_CCA_TIME[23..0]
1762+#define BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK 0x00FFFFFF // S_CCA_TIME[23..0]
1763+#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
1764+#define BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK 0x00FFFFFF // CCK_MDRDY_TIME[23..0]
1765+#define BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[23..0]
1766+#define BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_GREEN_MDRDY_TIME[23..0]
1767+
1768+#define BN0_WF_MIB_TOP_M0SDR22_ADDR (BN0_WF_MIB_TOP_BASE + 0x60) // D060
1769+#define BN0_WF_MIB_TOP_M0SDR23_ADDR (BN0_WF_MIB_TOP_BASE + 0x64) // D064
1770+
1771+#define BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK 0x0000FFFF // MUBF_TX_COUNT[15..0]
1772+
1773+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK 0xFFFF0000 // TX_40MHZ_CNT[31..16]
1774+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT 16
1775+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK 0x0000FFFF // TX_20MHZ_CNT[15..0]
1776+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_SHFT 0
1777+
1778+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK 0xFFFF0000 // TX_160MHZ_CNT[31..16]
1779+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT 16
1780+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK 0x0000FFFF // TX_80MHZ_CNT[15..0]
1781+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_SHFT 0
1782+
1783+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG2_CNT[31..16]
1784+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT 16
1785+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG1_CNT[15..0]
1786+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_SHFT 0
1787+
1788+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG4_CNT[31..16]
1789+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT 16
1790+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG3_CNT[15..0]
1791+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_SHFT 0
1792+
1793+#define BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK 0x0000FFFF // MU_FAIL_PPDU_CNT[15..0]
1794+
1795+#define BN0_WF_MIB_TOP_M0B0SDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x100) // D100
1796+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK 0xFFFF0000 // RTSRETRYCOUNT[31..16]
1797+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT 16
1798+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK 0x0000FFFF // RTSTXCOUNT[15..0]
1799+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_SHFT 0
1800+#define BN0_WF_MIB_TOP_M0B0SDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x104) // D104
1801+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK 0xFFFF0000 // ACKFAILCOUNT[31..16]
1802+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT 16
1803+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK 0x0000FFFF // BAMISSCOUNT[15..0]
1804+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_SHFT 0
1805+#define BN0_WF_MIB_TOP_M0B0SDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x108) // D108
1806+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK 0xFFFF0000 // FRAMERETRY2COUNT[31..16]
1807+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT 16
1808+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK 0x0000FFFF // FRAMERETRYCOUNT[15..0]
1809+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_SHFT 0
1810+#define BN0_WF_MIB_TOP_M0B0SDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x10C) // D10C
1811+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK 0x0000FFFF // FRAMERETRY3COUNT[15..0]
1812+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_SHFT 0
1813+#define BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG0_CNT[15..0]
1814+
1815+
1816+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK 0xFFFF0000 // TX_OK_COUNT2np1[31..16]
1817+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT 16
1818+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK 0x0000FFFF // TX_OK_COUNT2n[15..0]
1819+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT 0
1820+
1821+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK 0xFFFF0000 // TX_DATA_COUNT2np1[31..16]
1822+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT 16
1823+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK 0x0000FFFF // TX_DATA_COUNT2n[15..0]
1824+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT 0
1825+
1826+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK 0xFFFF0000 // RX_OK_COUNT2np1[31..16]
1827+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT 16
1828+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK 0x0000FFFF // RX_OK_COUNT2n[15..0]
1829+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT 0
1830+
1831+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK 0xFFFF0000 // RX_DATA_COUNT2np1[31..16]
1832+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT 16
1833+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK 0x0000FFFF // RX_DATA_COUNT2n[15..0]
1834+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT 0
1835+
1836+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK 0xFFFF0000 // RTSTXCOUNT2np1[31..16]
1837+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT 16
1838+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK 0x0000FFFF // RTSTXCOUNT2n[15..0]
1839+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT 0
1840+
1841+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK 0xFFFF0000 // RTSRETRYCOUNT2np1[31..16]
1842+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT 16
1843+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK 0x0000FFFF // RTSRETRYCOUNT2n[15..0]
1844+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT 0
1845+
1846+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK 0xFFFF0000 // BAMISSCOUNT2np1[31..16]
1847+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT 16
1848+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK 0x0000FFFF // BAMISSCOUNT2n[15..0]
1849+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT 0
1850+
1851+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK 0xFFFF0000 // ACKFAILCOUNT2np1[31..16]
1852+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT 16
1853+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK 0x0000FFFF // ACKFAILCOUNT2n[15..0]
1854+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT 0
1855+
1856+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK 0xFFFF0000 // FRAMERETRYCOUNT2np1[31..16]
1857+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT 16
1858+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK 0x0000FFFF // FRAMERETRYCOUNT2n[15..0]
1859+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT 0
1860+
1861+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY2COUNT2np1[31..16]
1862+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT 16
1863+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK 0x0000FFFF // FRAMERETRY2COUNT2n[15..0]
1864+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT 0
1865+
1866+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY3COUNT2np1[31..16]
1867+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT 16
1868+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK 0x0000FFFF // FRAMERETRY3COUNT2n[15..0]
1869+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT 0
1870+/* TXD */
1871+
1872+#define MT_TXD1_ETYP BIT(15)
1873+#define MT_TXD1_VLAN BIT(14)
1874+#define MT_TXD1_RMVL BIT(13)
1875+#define MT_TXD1_AMS BIT(13)
1876+#define MT_TXD1_EOSP BIT(12)
1877+#define MT_TXD1_MRD BIT(11)
1878+
1879+#define MT_TXD7_CTXD BIT(26)
1880+#define MT_TXD7_CTXD_CNT GENMASK(25, 23)
1881+#define MT_TXD7_TAT GENMASK(9, 0)
1882+
1883+#endif
1884+#endif
1885diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c
1886new file mode 100644
developer36fe7092023-09-27 12:24:47 +08001887index 00000000..275acc61
developer3fa816c2022-04-19 10:21:20 +08001888--- /dev/null
1889+++ b/mt7915/mtk_debugfs.c
developerdfb50982023-09-11 13:34:36 +08001890@@ -0,0 +1,3622 @@
developer3fa816c2022-04-19 10:21:20 +08001891+#include<linux/inet.h>
1892+#include "mt7915.h"
1893+#include "mt7915_debug.h"
1894+#include "mac.h"
1895+#include "mcu.h"
1896+
1897+#ifdef MTK_DEBUG
1898+#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
1899+#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
1900+#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \
1901+ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
1902+ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
1903+
1904+#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
1905+#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
1906+#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1907+ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
1908+ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
1909+
1910+#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
1911+#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
1912+#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1913+ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
1914+ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
1915+
1916+enum mt7915_wtbl_type {
1917+ WTBL_TYPE_LMAC, /* WTBL in LMAC */
1918+ WTBL_TYPE_UMAC, /* WTBL in UMAC */
1919+ WTBL_TYPE_KEY, /* Key Table */
1920+ MAX_NUM_WTBL_TYPE
1921+};
1922+
1923+static int mt7915_wtbl_read_raw(struct mt7915_dev *dev, u16 idx,
1924+ enum mt7915_wtbl_type type, u16 start_dw,
1925+ u16 len, void *buf)
1926+{
1927+ u32 *dest_cpy = (u32 *)buf;
1928+ u32 size_dw = len;
1929+ u32 src = 0;
1930+
1931+ if (!buf)
1932+ return 0xFF;
1933+
1934+ if (type == WTBL_TYPE_LMAC) {
1935+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1936+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1937+ src = LWTBL_IDX2BASE(idx, start_dw);
1938+ } else if (type == WTBL_TYPE_UMAC) {
1939+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1940+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1941+ src = UWTBL_IDX2BASE(idx, start_dw);
1942+ } else if (type == WTBL_TYPE_KEY) {
1943+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1944+ MT_UWTBL_TOP_WDUCR_TARGET |
1945+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1946+ src = KEYTBL_IDX2BASE(idx, start_dw);
1947+ }
1948+
1949+ while (size_dw--) {
1950+ *dest_cpy++ = mt76_rr(dev, src);
1951+ src += 4;
1952+ };
1953+
1954+ return 0;
1955+}
1956+
1957+static int mt7915_wtbl_write_raw(struct mt7915_dev *dev, u16 idx,
1958+ enum mt7915_wtbl_type type, u16 start_dw,
1959+ u32 val)
1960+{
1961+ u32 addr = 0;
1962+
1963+ if (type == WTBL_TYPE_LMAC) {
1964+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1965+ FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1966+ addr = LWTBL_IDX2BASE(idx, start_dw);
1967+ } else if (type == WTBL_TYPE_UMAC) {
1968+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1969+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1970+ addr = UWTBL_IDX2BASE(idx, start_dw);
1971+ } else if (type == WTBL_TYPE_KEY) {
1972+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1973+ MT_UWTBL_TOP_WDUCR_TARGET |
1974+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1975+ addr = KEYTBL_IDX2BASE(idx, start_dw);
1976+ }
1977+
1978+ mt76_wr(dev, addr, val);
1979+
1980+ return 0;
1981+}
1982+
1983+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len)
1984+{
1985+ struct bin_debug_hdr *hdr;
1986+ char *buf;
1987+
1988+ if (len > 1500 - sizeof(*hdr))
1989+ len = 1500 - sizeof(*hdr);
1990+
1991+ buf = kzalloc(sizeof(*hdr) + len, GFP_KERNEL);
1992+ if (!buf)
1993+ return;
1994+
1995+ hdr = (struct bin_debug_hdr *)buf;
1996+ hdr->magic_num = cpu_to_le32(PKT_BIN_DEBUG_MAGIC);
1997+ hdr->serial_id = cpu_to_le16(dev->dbg.fwlog_seq++);
1998+ hdr->msg_type = cpu_to_le16(type);
1999+ hdr->len = cpu_to_le16(len);
2000+ hdr->des_len = cpu_to_le16(des_len);
2001+
2002+ memcpy(buf + sizeof(*hdr), data, len);
2003+
2004+ mt7915_debugfs_rx_log(dev, buf, sizeof(*hdr) + len);
2005+}
2006+
2007+static int
2008+mt7915_fw_debug_module_set(void *data, u64 module)
2009+{
2010+ struct mt7915_dev *dev = data;
2011+
2012+ dev->dbg.fw_dbg_module = module;
2013+ return 0;
2014+}
2015+
2016+static int
2017+mt7915_fw_debug_module_get(void *data, u64 *module)
2018+{
2019+ struct mt7915_dev *dev = data;
2020+
2021+ *module = dev->dbg.fw_dbg_module;
2022+ return 0;
2023+}
2024+
2025+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, mt7915_fw_debug_module_get,
2026+ mt7915_fw_debug_module_set, "%lld\n");
2027+
2028+static int
2029+mt7915_fw_debug_level_set(void *data, u64 level)
2030+{
2031+ struct mt7915_dev *dev = data;
2032+
2033+ dev->dbg.fw_dbg_lv = level;
2034+ mt7915_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv);
2035+ return 0;
2036+}
2037+
2038+static int
2039+mt7915_fw_debug_level_get(void *data, u64 *level)
2040+{
2041+ struct mt7915_dev *dev = data;
2042+
2043+ *level = dev->dbg.fw_dbg_lv;
2044+ return 0;
2045+}
2046+
2047+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, mt7915_fw_debug_level_get,
2048+ mt7915_fw_debug_level_set, "%lld\n");
2049+
2050+#define MAX_TX_MODE 12
2051+static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT",
2052+ "N/A", "N/A", "N/A", "HE_SU", "HE_EXT_SU",
2053+ "HE_TRIG", "HE_MU", "N/A"};
2054+static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong",
2055+ "N/A", "2Mshort", "5.5Mshort", "11Mshort",
2056+ "N/A"};
2057+static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M",
2058+ "48M", "54M", "N/A"};
2059+static char *fcap_str[] = {"20MHz", "20/40MHz", "20/40/80MHz",
2060+ "20/40/80/160/80+80MHz"};
2061+
2062+static char *hw_rate_ofdm_str(u16 ofdm_idx)
2063+{
2064+ switch (ofdm_idx) {
2065+ case 11: /* 6M */
2066+ return HW_TX_RATE_OFDM_STR[0];
2067+
2068+ case 15: /* 9M */
2069+ return HW_TX_RATE_OFDM_STR[1];
2070+
2071+ case 10: /* 12M */
2072+ return HW_TX_RATE_OFDM_STR[2];
2073+
2074+ case 14: /* 18M */
2075+ return HW_TX_RATE_OFDM_STR[3];
2076+
2077+ case 9: /* 24M */
2078+ return HW_TX_RATE_OFDM_STR[4];
2079+
2080+ case 13: /* 36M */
2081+ return HW_TX_RATE_OFDM_STR[5];
2082+
2083+ case 8: /* 48M */
2084+ return HW_TX_RATE_OFDM_STR[6];
2085+
2086+ case 12: /* 54M */
2087+ return HW_TX_RATE_OFDM_STR[7];
2088+
2089+ default:
2090+ return HW_TX_RATE_OFDM_STR[8];
2091+ }
2092+}
2093+
2094+static char *hw_rate_str(u8 mode, u16 rate_idx)
2095+{
2096+ if (mode == 0)
2097+ return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8];
2098+ else if (mode == 1)
2099+ return hw_rate_ofdm_str(rate_idx);
2100+ else
2101+ return "MCS";
2102+}
2103+
2104+static void parse_rate(struct seq_file *s, u16 rate_idx, u16 txrate)
2105+{
2106+ u16 txmode, mcs, nss, stbc;
2107+
2108+ txmode = FIELD_GET(GENMASK(9, 6), txrate);
2109+ mcs = FIELD_GET(GENMASK(5, 0), txrate);
2110+ nss = FIELD_GET(GENMASK(12, 10), txrate);
2111+ stbc = FIELD_GET(BIT(13), txrate);
2112+
2113+ seq_printf(s, "\tRate%d(0x%x):TxMode=%d(%s), TxRate=%d(%s), Nsts=%d, STBC=%d\n",
2114+ rate_idx + 1, txrate,
2115+ txmode, (txmode < MAX_TX_MODE ? HW_TX_MODE_STR[txmode] : HW_TX_MODE_STR[MAX_TX_MODE]),
2116+ mcs, hw_rate_str(txmode, mcs), nss, stbc);
2117+}
2118+
2119+#define LWTBL_LEN_IN_DW 32
2120+#define UWTBL_LEN_IN_DW 8
2121+#define ONE_KEY_ENTRY_LEN_IN_DW 8
developerf32dabf2022-06-01 10:59:24 +08002122+static int mt7915_sta_info(struct seq_file *s, void *data)
2123+{
2124+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2125+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
2126+ u16 i = 0;
2127+
2128+ for (i=0; i < mt7915_wtbl_size(dev); i++) {
2129+ mt7915_wtbl_read_raw(dev, i, WTBL_TYPE_LMAC, 0,
2130+ LWTBL_LEN_IN_DW, lwtbl);
2131+ if (lwtbl[4] || lwtbl[5] || lwtbl[6] || lwtbl[7] || lwtbl[0] || lwtbl[1])
2132+ seq_printf(s, "wcid:%d\tAddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
2133+ i, lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
2134+ }
2135+
2136+ return 0;
2137+}
2138+
developer3fa816c2022-04-19 10:21:20 +08002139+static int mt7915_wtbl_read(struct seq_file *s, void *data)
2140+{
2141+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2142+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
2143+ int x;
2144+ u32 *addr = 0;
2145+ u32 dw_value = 0;
2146+
2147+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_LMAC, 0,
2148+ LWTBL_LEN_IN_DW, lwtbl);
2149+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
2150+ seq_printf(s, "LMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2151+ MT_DBG_WTBLON_TOP_WDUCR,
2152+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2153+ LWTBL_IDX2BASE(dev->wlan_idx, 0));
2154+ for (x = 0; x < LWTBL_LEN_IN_DW; x++) {
2155+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2156+ x,
2157+ lwtbl[x * 4 + 3],
2158+ lwtbl[x * 4 + 2],
2159+ lwtbl[x * 4 + 1],
2160+ lwtbl[x * 4]);
2161+ }
2162+
2163+ seq_printf(s, "\n\tAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
2164+ lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
2165+
2166+ // DW0, DW1
2167+ seq_printf(s, "LWTBL DW 0/1\n\t");
2168+ addr = (u32 *)&(lwtbl[0]);
2169+ dw_value = *addr;
2170+ seq_printf(s, "MUAR_IDX:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
2171+ seq_printf(s, "RCA1:%ld/ ", FIELD_GET(BIT(22), dw_value));
2172+ seq_printf(s, "KID:%lu/ ", FIELD_GET(GENMASK(24, 23), dw_value));
2173+ seq_printf(s, "RCID:%ld/ ", FIELD_GET(BIT(25), dw_value));
2174+ seq_printf(s, "FROM_DS:%ld\n\t", FIELD_GET(BIT(26), dw_value));
2175+ seq_printf(s, "TO_DS:%ld/ ", FIELD_GET(BIT(27), dw_value));
2176+ seq_printf(s, "RV:%ld/ ", FIELD_GET(BIT(28), dw_value));
2177+ seq_printf(s, "RCA2:%ld/ ", FIELD_GET(BIT(29), dw_value));
2178+ seq_printf(s, "WPI_FLAG:%ld\n", FIELD_GET(BIT(30), dw_value));
2179+
2180+ // DW2
2181+ seq_printf(s, "LWTBL DW 2\n\t");
2182+ addr = (u32 *)&(lwtbl[2*4]);
2183+ dw_value = *addr;
2184+ seq_printf(s, "AID12:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
2185+ seq_printf(s, "SU:%ld/ ", FIELD_GET(BIT(12), dw_value));
2186+ seq_printf(s, "SPP_EN:%ld/ ", FIELD_GET(BIT(13), dw_value));
2187+ seq_printf(s, "WPI_EVEN:%ld\n\t",FIELD_GET(BIT(14), dw_value));
2188+ seq_printf(s, "CIPHER:%lu/ ", FIELD_GET(GENMASK(20, 16), dw_value));
2189+ seq_printf(s, "CIPHER_IGTK:%lu/ ",FIELD_GET(GENMASK(22, 21), dw_value));
2190+ seq_printf(s, "AAD_OM:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2191+ seq_printf(s, "SW:%ld/ ", FIELD_GET(BIT(24), dw_value));
2192+ seq_printf(s, "UL:%ld/ ", FIELD_GET(BIT(25), dw_value));
2193+ seq_printf(s, "TX_POWER_SAVE:%ld\n\t", FIELD_GET(BIT(26), dw_value));
2194+ seq_printf(s, "QOS:%ld/ ", FIELD_GET(BIT(27), dw_value));
2195+ seq_printf(s, "HT:%ld/ ", FIELD_GET(BIT(28), dw_value));
2196+ seq_printf(s, "VHT:%ld/ ", FIELD_GET(BIT(29), dw_value));
2197+ seq_printf(s, "HE:%ld/ ", FIELD_GET(BIT(30), dw_value));
2198+ seq_printf(s, "MESH:%ld\n", FIELD_GET(BIT(31), dw_value));
2199+
2200+ // DW3
2201+ seq_printf(s, "LWTBL DW 3\n\t");
2202+ addr = (u32 *)&(lwtbl[3*4]);
2203+ dw_value = *addr;
2204+ seq_printf(s, "WMM_Q:%lu/ ", FIELD_GET(GENMASK(1, 0), dw_value));
2205+ seq_printf(s, "RXD_DUP_MODE:%lu\n\t", FIELD_GET(GENMASK(3, 2), dw_value));
2206+ seq_printf(s, "VLAN2ETH:%ld/ ", FIELD_GET(BIT(4), dw_value));
2207+ seq_printf(s, "BEAM_CHG:%ld/ ", FIELD_GET(BIT(5), dw_value));
2208+ seq_printf(s, "DIS_BA256:%ld\n\t", FIELD_GET(BIT(6), dw_value));
2209+ seq_printf(s, "PFMU_IDX:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2210+ seq_printf(s, "ULPF_IDX:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
2211+ seq_printf(s, "RIBF:%ld/ ", FIELD_GET(BIT(24), dw_value));
2212+ seq_printf(s, "ULPF:%ld\n\t", FIELD_GET(BIT(25), dw_value));
2213+ seq_printf(s, "IGN_FBK:%ld/ ", FIELD_GET(BIT(26), dw_value));
2214+ seq_printf(s, "TBF:%ld/ ", FIELD_GET(BIT(29), dw_value));
2215+ seq_printf(s, "TBF_VHT:%ld/ ", FIELD_GET(BIT(30), dw_value));
2216+ seq_printf(s, "TBF_HE:%ld\n", FIELD_GET(BIT(31), dw_value));
2217+
2218+ // DW4
2219+ seq_printf(s, "LWTBL DW 4\n\t");
2220+ addr = (u32 *)&(lwtbl[4*4]);
2221+ dw_value = *addr;
2222+ seq_printf(s, "ANT_ID_STS0:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2223+ seq_printf(s, "STS1:%lu/ ", FIELD_GET(GENMASK(5, 3), dw_value));
2224+ seq_printf(s, "STS2:%lu/ ", FIELD_GET(GENMASK(8, 6), dw_value));
2225+ seq_printf(s, "STS3:%lu\n\t", FIELD_GET(GENMASK(11, 9), dw_value));
2226+ seq_printf(s, "ANT_ID_STS4:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
2227+ seq_printf(s, "STS5:%lu/ ", FIELD_GET(GENMASK(17, 15), dw_value));
2228+ seq_printf(s, "STS6:%ld/ ", FIELD_GET(GENMASK(20, 18), dw_value));
2229+ seq_printf(s, "STS7:%lu\n\t", FIELD_GET(GENMASK(23, 21), dw_value));
2230+ seq_printf(s, "CASCAD:%ld/ ", FIELD_GET(BIT(24), dw_value));
2231+ seq_printf(s, "LDPC_HT:%ld/ ", FIELD_GET(BIT(25), dw_value));
2232+ seq_printf(s, "LDPC_VHT:%ld/ ", FIELD_GET(BIT(26), dw_value));
2233+ seq_printf(s, "LDPC_HE:%ld\n\t", FIELD_GET(BIT(27), dw_value));
2234+ seq_printf(s, "DIS_RHTR:%ld/ ", FIELD_GET(BIT(28), dw_value));
2235+ seq_printf(s, "ALL_ACK:%ld/ ", FIELD_GET(BIT(29), dw_value));
2236+ seq_printf(s, "DROP:%ld/ ", FIELD_GET(BIT(30), dw_value));
2237+ seq_printf(s, "ACK_EN:%ld\n", FIELD_GET(BIT(31), dw_value));
2238+
2239+ // DW5
2240+ seq_printf(s, "LWTBL DW 5\n\t");
2241+ addr = (u32 *)&(lwtbl[5*4]);
2242+ dw_value = *addr;
2243+ seq_printf(s, "AF:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2244+ seq_printf(s, "AF_HE:%lu/ ", FIELD_GET(GENMASK(4, 3), dw_value));
2245+ seq_printf(s, "RTS:%ld/ ", FIELD_GET(BIT(5), dw_value));
2246+ seq_printf(s, "SMPS:%ld/ ", FIELD_GET(BIT(6), dw_value));
2247+ seq_printf(s, "DYN_BW:%ld\n\t", FIELD_GET(BIT(7), dw_value));
2248+ seq_printf(s, "MMSS:%lu/ ", FIELD_GET(GENMASK(10, 8), dw_value));
2249+ seq_printf(s, "USR:%ld/ ", FIELD_GET(BIT(11), dw_value));
2250+ seq_printf(s, "SR_RATE:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
2251+ seq_printf(s, "SR_ABORT:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2252+ seq_printf(s, "TX_POWER_OFFSET:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
2253+ seq_printf(s, "WTBL_MPDU_SIZE:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
2254+ seq_printf(s, "PE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
2255+ seq_printf(s, "DOPPL:%ld/ ", FIELD_GET(BIT(26), dw_value));
2256+ seq_printf(s, "TXOP_PS_CAP:%ld/ ", FIELD_GET(BIT(27), dw_value));
2257+ seq_printf(s, "DONOT_UPDATE_I_PSM:%ld\n\t", FIELD_GET(BIT(28), dw_value));
2258+ seq_printf(s, "I_PSM:%ld/ ", FIELD_GET(BIT(29), dw_value));
2259+ seq_printf(s, "PSM:%ld/ ", FIELD_GET(BIT(30), dw_value));
2260+ seq_printf(s, "SKIP_TX:%ld\n", FIELD_GET(BIT(31), dw_value));
2261+
2262+ // DW6
2263+ seq_printf(s, "LWTBL DW 6\n\t");
2264+ seq_printf(s, "TID 0/1/2/3/4/5/6/7 BA_WIN_SIZE:");
2265+ addr = (u32 *)&(lwtbl[6*4]);
2266+ dw_value = *addr;
2267+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(3, 0), dw_value));
2268+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(7, 4), dw_value));
2269+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(11, 8), dw_value));
2270+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(15, 12), dw_value));
2271+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(19, 16), dw_value));
2272+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(23, 20), dw_value));
2273+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(27, 24), dw_value));
2274+ seq_printf(s, "%lu\n", FIELD_GET(GENMASK(31, 28), dw_value));
2275+
2276+ // DW7
2277+ seq_printf(s, "LWTBL DW 7\n\t");
2278+ addr = (u32 *)&(lwtbl[7*4]);
2279+ dw_value = *addr;
2280+ seq_printf(s, "CBRN:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2281+ seq_printf(s, "DBNSS_EN:%ld/ ", FIELD_GET(BIT(3), dw_value));
2282+ seq_printf(s, "BAF_EN:%ld/ ", FIELD_GET(BIT(4), dw_value));
2283+ seq_printf(s, "RDGBA:%ld\n\t", FIELD_GET(BIT(5), dw_value));
2284+ seq_printf(s, "RDG:%ld/ ", FIELD_GET(BIT(6), dw_value));
2285+ seq_printf(s, "SPE_IDX:%lu/ ", FIELD_GET(GENMASK(11, 7), dw_value));
2286+ seq_printf(s, "G2:%ld/ ", FIELD_GET(BIT(12), dw_value));
2287+ seq_printf(s, "G4:%ld/ ", FIELD_GET(BIT(13), dw_value));
2288+ seq_printf(s, "G8:%ld/ ", FIELD_GET(BIT(14), dw_value));
2289+ seq_printf(s, "G16:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2290+ seq_printf(s, "G2_LTF:%lu/ ", FIELD_GET(GENMASK(17, 16), dw_value));
2291+ seq_printf(s, "G4_LTF:%lu/ ", FIELD_GET(GENMASK(19, 18), dw_value));
2292+ seq_printf(s, "G8_LTF:%lu/ ", FIELD_GET(GENMASK(21, 20), dw_value));
2293+ seq_printf(s, "G16_LTF:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
2294+ seq_printf(s, "G2_HE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
2295+ seq_printf(s, "G4_HE:%lu/ ", FIELD_GET(GENMASK(27, 27), dw_value));
2296+ seq_printf(s, "G8_HE:%lu/ ", FIELD_GET(GENMASK(29, 28), dw_value));
2297+ seq_printf(s, "G16_HE:%lu\n", FIELD_GET(GENMASK(31, 30), dw_value));
2298+
2299+ // DW8
2300+ seq_printf(s, "LWTBL DW 8\n\t");
2301+ addr = (u32 *)&(lwtbl[8*4]);
2302+ dw_value = *addr;
2303+ seq_printf(s, "FAIL_CNT_AC0:%lu/ ", FIELD_GET(GENMASK(4, 0), dw_value));
2304+ seq_printf(s, "AC1:%lu/ ", FIELD_GET(GENMASK(9, 5), dw_value));
2305+ seq_printf(s, "AC2:%lu/ ", FIELD_GET(GENMASK(14, 10), dw_value));
2306+ seq_printf(s, "AC3:%lu\n\t", FIELD_GET(GENMASK(19, 15), dw_value));
2307+ seq_printf(s, "PARTIAL_AID:%lu/ ", FIELD_GET(GENMASK(28, 20), dw_value));
2308+ seq_printf(s, "CHK_PER:%lu\n", FIELD_GET(BIT(31), dw_value));
2309+
2310+ // DW9
2311+ seq_printf(s, "LWTBL DW 9\n\t");
2312+ addr = (u32 *)&(lwtbl[9*4]);
2313+ dw_value = *addr;
2314+ seq_printf(s, "RX_AVG_MPDU:%lu/ ", FIELD_GET(GENMASK(13, 0), dw_value));
2315+ seq_printf(s, "PRITX_SW_MODE:%ld/ ", FIELD_GET(BIT(16), dw_value));
2316+ seq_printf(s, "PRITX_PLR:%ld\n\t", FIELD_GET(BIT(17), dw_value));
2317+ seq_printf(s, "PRITX_DCM:%ld/ ", FIELD_GET(BIT(18), dw_value));
2318+ seq_printf(s, "PRITX_ER160:%ld/ ", FIELD_GET(BIT(19), dw_value));
2319+ seq_printf(s, "PRITX_ERSU:%lu\n\t", FIELD_GET(BIT(20), dw_value));
2320+ seq_printf(s, "MPDU_FAIL_CNT:%lu/ ", FIELD_GET(GENMASK(25, 23), dw_value));
2321+ seq_printf(s, "MPDU_OK_CNT:%lu/ ", FIELD_GET(GENMASK(28, 26), dw_value));
2322+ seq_printf(s, "RATE_IDX:%lu\n\t", FIELD_GET(GENMASK(31, 29), dw_value));
2323+ seq_printf(s, "FCAP:%s\n", fcap_str[FIELD_GET(GENMASK(22, 21), dw_value)]);
2324+
2325+ // DW10
2326+ seq_printf(s, "LWTBL DW 10\n");
2327+ addr = (u32 *)&(lwtbl[10*4]);
2328+ dw_value = *addr;
2329+ parse_rate(s, 0, FIELD_GET(GENMASK(13, 0), dw_value));
2330+ parse_rate(s, 1, FIELD_GET(GENMASK(29, 16), dw_value));
2331+ // DW11
2332+ seq_printf(s, "LWTBL DW 11\n");
2333+ addr = (u32 *)&(lwtbl[11*4]);
2334+ dw_value = *addr;
2335+ parse_rate(s, 2, FIELD_GET(GENMASK(13, 0), dw_value));
2336+ parse_rate(s, 3, FIELD_GET(GENMASK(29, 16), dw_value));
2337+ // DW12
2338+ seq_printf(s, "LWTBL DW 12\n");
2339+ addr = (u32 *)&(lwtbl[12*4]);
2340+ dw_value = *addr;
2341+ parse_rate(s, 4, FIELD_GET(GENMASK(13, 0), dw_value));
2342+ parse_rate(s, 5, FIELD_GET(GENMASK(29, 16), dw_value));
2343+ // DW13
2344+ seq_printf(s, "LWTBL DW 13\n");
2345+ addr = (u32 *)&(lwtbl[13*4]);
2346+ dw_value = *addr;
2347+ parse_rate(s, 6, FIELD_GET(GENMASK(13, 0), dw_value));
2348+ parse_rate(s, 7, FIELD_GET(GENMASK(29, 16), dw_value));
2349+
2350+ //DW28
2351+ seq_printf(s, "LWTBL DW 28\n\t");
2352+ addr = (u32 *)&(lwtbl[28*4]);
2353+ dw_value = *addr;
2354+ seq_printf(s, "OM_INFO:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
2355+ seq_printf(s, "OM_RXD_DUP_MODE:%u\n\t", !!(dw_value & BIT(12)) );
2356+
2357+ //DW29
2358+ seq_printf(s, "LWTBL DW 29\n");
2359+ addr = (u32 *)&(lwtbl[29*4]);
2360+ dw_value = *addr;
2361+ seq_printf(s, "USER_RSSI:%lu/ ", FIELD_GET(GENMASK(8, 0), dw_value));
2362+ seq_printf(s, "USER_SNR:%lu/ ", FIELD_GET(GENMASK(14, 9), dw_value));
2363+ seq_printf(s, "RAPID_REACTION_RATE:%lu/ ", FIELD_GET(GENMASK(26, 16), dw_value));
2364+ seq_printf(s, "HT_AMSDU(Read Only):%u/ ", !!(dw_value & BIT(30)) );
2365+ seq_printf(s, "AMSDU_CROSS_LG(Read Only):%u\n\t ", !!(dw_value & BIT(31)));
2366+
2367+ //DW30
2368+ seq_printf(s, "LWTBL DW 30\n\t");
2369+ addr = (u32 *)&(lwtbl[30*4]);
2370+ dw_value = *addr;
2371+ seq_printf(s, "RCPI 0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2372+ seq_printf(s, "RCPI 1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2373+ seq_printf(s, "RCPI 2:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
2374+ seq_printf(s, "RCPI 3:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
2375+
2376+ //DW31
2377+ seq_printf(s, "LWTBL DW 31\n\t");
2378+ addr = (u32 *)&(lwtbl[31*4]);
2379+ dw_value = *addr;
2380+ seq_printf(s, "RCPI 4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2381+ seq_printf(s, "RCPI 5:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2382+ seq_printf(s, "RCPI 6:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
2383+ seq_printf(s, "RCPI 7:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
2384+
2385+ return 0;
2386+}
2387+
2388+static int mt7915_uwtbl_read(struct seq_file *s, void *data)
2389+{
2390+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2391+ u8 uwtbl[UWTBL_LEN_IN_DW * 4] = {0};
2392+ u8 keytbl[ONE_KEY_ENTRY_LEN_IN_DW*4] = {0};
2393+ int x;
2394+ u32 *addr = 0;
2395+ u32 dw_value = 0;
2396+ u32 amsdu_len = 0;
2397+ u32 u2SN = 0;
2398+ u16 keyloc0, keyloc1;
2399+
2400+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC, 0,
2401+ UWTBL_LEN_IN_DW, uwtbl);
2402+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
2403+ seq_printf(s, "UMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
developerb8853042023-02-17 11:50:45 +08002404+ MT_DBG_UWTBL_TOP_WDUCR,
2405+ mt76_rr(dev, MT_DBG_UWTBL_TOP_BASE),
developer3fa816c2022-04-19 10:21:20 +08002406+ UWTBL_IDX2BASE(dev->wlan_idx, 0));
2407+ for (x = 0; x < UWTBL_LEN_IN_DW; x++) {
2408+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2409+ x,
2410+ uwtbl[x * 4 + 3],
2411+ uwtbl[x * 4 + 2],
2412+ uwtbl[x * 4 + 1],
2413+ uwtbl[x * 4]);
2414+ }
2415+
2416+ /* UMAC WTBL DW 0 */
2417+ seq_printf(s, "\nUWTBL PN\n\t");
2418+ addr = (u32 *)&(uwtbl[0]);
2419+ dw_value = *addr;
2420+ seq_printf(s, "PN0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2421+ seq_printf(s, "PN1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2422+ seq_printf(s, "PN2:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
2423+ seq_printf(s, "PN3:%lu/ ", FIELD_GET(GENMASK(31, 24), dw_value));
2424+
2425+ addr = (u32 *)&(uwtbl[1 * 4]);
2426+ dw_value = *addr;
2427+ seq_printf(s, "PN4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2428+ seq_printf(s, "PN5:%lu\n", FIELD_GET(GENMASK(15, 8), dw_value));
2429+
2430+ /* UMAC WTBL DW SN part */
2431+ seq_printf(s, "\nUWTBL SN\n");
2432+ addr = (u32 *)&(uwtbl[2 * 4]);
2433+ dw_value = *addr;
2434+ seq_printf(s, "TID0_AC0_SN:%lu\n", FIELD_GET(GENMASK(11, 0), dw_value));
2435+ seq_printf(s, "TID1_AC1_SN:%lu\n", FIELD_GET(GENMASK(23, 12), dw_value));
2436+
2437+ u2SN = FIELD_GET(GENMASK(31, 24), dw_value);
2438+ addr = (u32 *)&(uwtbl[3 * 4]);
2439+ dw_value = *addr;
2440+ u2SN |= FIELD_GET(GENMASK(3, 0), dw_value);
2441+ seq_printf(s, "TID2_AC2_SN:%u\n", u2SN);
2442+ seq_printf(s, "TID3_AC3_SN:%lu\n", FIELD_GET(GENMASK(15, 4), dw_value));
2443+ seq_printf(s, "TID4_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
2444+
2445+ u2SN = FIELD_GET(GENMASK(31, 28), dw_value);
2446+ addr = (u32 *)&(uwtbl[4 * 4]);
2447+ dw_value = *addr;
2448+ u2SN |= FIELD_GET(GENMASK(7, 0), dw_value);
2449+ seq_printf(s, "TID5_SN:%u\n", u2SN);
2450+ seq_printf(s, "TID6_SN:%lu\n", FIELD_GET(GENMASK(19, 8), dw_value));
2451+ seq_printf(s, "TID7_SN:%lu\n", FIELD_GET(GENMASK(31, 20), dw_value));
2452+
2453+ addr = (u32 *)&(uwtbl[1 * 4]);
2454+ dw_value = *addr;
2455+ seq_printf(s, "COM_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
2456+
2457+ /* UMAC WTBL DW 0 */
2458+ seq_printf(s, "\nUWTBL others\n");
2459+
2460+ addr = (u32 *)&(uwtbl[5 * 4]);
2461+ dw_value = *addr;
2462+ keyloc0 = FIELD_GET(GENMASK(10, 0), dw_value);
2463+ keyloc1 = FIELD_GET(GENMASK(26, 16), dw_value);
2464+ seq_printf(s, "\tKey Loc 1/2:%lu/%lu\n",
2465+ FIELD_GET(GENMASK(10, 0), dw_value),
2466+ FIELD_GET(GENMASK(26, 16), dw_value));
2467+ seq_printf(s, "\tUWTBL_QOS:%lu\n", FIELD_GET(BIT(27), dw_value));
2468+ seq_printf(s, "\tUWTBL_HT_VHT_HE:%lu\n", FIELD_GET(BIT(28), dw_value));
2469+
2470+ addr = (u32 *)&(uwtbl[6*4]);
2471+ dw_value = *addr;
2472+ seq_printf(s, "\tHW AMSDU Enable:%lu\n", FIELD_GET(BIT(9), dw_value));
2473+
2474+ amsdu_len = FIELD_GET(GENMASK(5, 0), dw_value);
2475+ if (amsdu_len == 0)
2476+ seq_printf(s, "\tHW AMSDU Len:invalid (WTBL value=0x%x)\n", amsdu_len);
2477+ else if (amsdu_len == 1)
2478+ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
2479+ 1,
2480+ 255,
2481+ amsdu_len);
2482+ else
2483+ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
2484+ 256 * (amsdu_len - 1),
2485+ 256 * (amsdu_len - 1) + 255,
2486+ amsdu_len
2487+ );
2488+ seq_printf(s, "\tHW AMSDU Num:%lu (WTBL value=0x%lx)\n",
2489+ FIELD_GET(GENMASK(8, 6), dw_value) + 1,
2490+ FIELD_GET(GENMASK(8, 6), dw_value));
2491+
2492+ /* Parse KEY link */
2493+ seq_printf(s, "\n\tkeyloc0:%d\n", keyloc0);
2494+ if(keyloc0 != GENMASK(10, 0)) {
2495+ mt7915_wtbl_read_raw(dev, keyloc0, WTBL_TYPE_KEY,
2496+ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
2497+ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
developerb8853042023-02-17 11:50:45 +08002498+ MT_DBG_UWTBL_TOP_WDUCR,
2499+ mt76_rr(dev, MT_DBG_UWTBL_TOP_BASE),
developer3fa816c2022-04-19 10:21:20 +08002500+ KEYTBL_IDX2BASE(keyloc0, 0));
2501+
2502+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
2503+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2504+ x,
2505+ keytbl[x * 4 + 3],
2506+ keytbl[x * 4 + 2],
2507+ keytbl[x * 4 + 1],
2508+ keytbl[x * 4]);
2509+ }
2510+ }
2511+
2512+ seq_printf(s, "\n\tkeyloc1:%d\n", keyloc1);
2513+ if(keyloc1 != GENMASK(26, 16)) {
2514+ mt7915_wtbl_read_raw(dev, keyloc1, WTBL_TYPE_KEY,
2515+ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
2516+ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
developerb8853042023-02-17 11:50:45 +08002517+ MT_DBG_UWTBL_TOP_WDUCR,
2518+ mt76_rr(dev, MT_DBG_UWTBL_TOP_BASE),
developer3fa816c2022-04-19 10:21:20 +08002519+ KEYTBL_IDX2BASE(keyloc1, 0));
2520+
2521+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
2522+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2523+ x,
2524+ keytbl[x * 4 + 3],
2525+ keytbl[x * 4 + 2],
2526+ keytbl[x * 4 + 1],
2527+ keytbl[x * 4]);
2528+ }
2529+ }
2530+ return 0;
2531+}
2532+
2533+static void
2534+dump_dma_tx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
2535+{
2536+ u32 base, cnt, cidx, didx, queue_cnt;
2537+
2538+ base= mt76_rr(dev, ring_base);
2539+ cnt = mt76_rr(dev, ring_base + 4);
2540+ cidx = mt76_rr(dev, ring_base + 8);
2541+ didx = mt76_rr(dev, ring_base + 12);
2542+ queue_cnt = (cidx >= didx) ? (cidx - didx) : (cidx - didx + cnt);
2543+
2544+ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
2545+}
2546+
2547+static void
2548+dump_dma_rx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
2549+{
2550+ u32 base, cnt, cidx, didx, queue_cnt;
2551+
2552+ base= mt76_rr(dev, ring_base);
2553+ cnt = mt76_rr(dev, ring_base + 4);
2554+ cidx = mt76_rr(dev, ring_base + 8);
2555+ didx = mt76_rr(dev, ring_base + 12);
2556+ queue_cnt = (didx > cidx) ? (didx - cidx - 1) : (didx - cidx + cnt - 1);
2557+
2558+ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
2559+}
2560+
2561+static void
2562+mt7915_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2563+{
2564+ u32 sys_ctrl[10] = {};
2565+
2566+ /* HOST DMA */
2567+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
2568+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
2569+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
2570+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
2571+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_INT_SOURCE_CSR);
2572+ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_INT_MASK_CSR);
2573+ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
2574+ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_GLO_CFG);
2575+ seq_printf(s, "HOST_DMA Configuration\n");
2576+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2577+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2578+ seq_printf(s, "%10s %10x %10x\n",
2579+ "Merge", sys_ctrl[0], sys_ctrl[1]);
2580+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2581+ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
2582+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
2583+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
2584+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
2585+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
2586+
2587+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2588+ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
2589+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
2590+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
2591+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[7]),
2592+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[7]));
2593+
2594+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT1_SOURCE_CSR);
2595+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT1_MASK_CSR);
2596+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR);
2597+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR);
2598+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR);
2599+ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR);
2600+ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_GLO_CFG);
2601+ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_GLO_CFG);
2602+ seq_printf(s, "%10s %10x %10x\n",
2603+ "MergeP1", sys_ctrl[0], sys_ctrl[1]);
2604+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2605+ "DMA0P1", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
2606+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
2607+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
2608+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
2609+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
2610+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2611+ "DMA1P1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
2612+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
2613+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
2614+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[7]),
2615+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[7]));
2616+
2617+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2618+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2619+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2620+ dump_dma_rx_ring_info(s, dev, "R0:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2621+ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
2622+
2623+ seq_printf(s, "HOST_DMA0 PCIe 1 Ring Configuration\n");
2624+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2625+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2626+ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", MT_DBG_WFDMA0_PCIE1_RX1_CTRL0);
2627+
2628+ seq_printf(s, "HOST_DMA1 Ring Configuration\n");
2629+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2630+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2631+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
2632+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
developer79a21a22023-01-09 13:57:39 +08002633+ if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
2634+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(0));
2635+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(1));
2636+ } else {
2637+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
2638+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
2639+ }
developer3fa816c2022-04-19 10:21:20 +08002640+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
2641+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_EVENT_RING_CTRL(0));
developer79a21a22023-01-09 13:57:39 +08002642+ if (mtk_wed_device_active(&dev->mt76.mmio.wed))
2643+ dump_dma_rx_ring_info(s, dev, "R1:TxDone(WA2H)", MT_DBG_WFDMA_WED_RX_CTRL(1));
2644+ else
2645+ dump_dma_rx_ring_info(s, dev, "R1:Event0(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
developer3fa816c2022-04-19 10:21:20 +08002646+ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
2647+
2648+ seq_printf(s, "HOST_DMA1 PCIe 1 Ring Configuration\n");
2649+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2650+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2651+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA1_PCIE1_TX19_CTRL0);
2652+ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", MT_DBG_WFDMA1_PCIE1_RX2_CTRL0);
2653+}
2654+
2655+static void
2656+mt7915_show_mcu_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2657+{
2658+ u32 sys_ctrl[9] = {};
2659+
2660+ /* MCU DMA information */
2661+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2662+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2663+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2664+
2665+ sys_ctrl[3] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR);
2666+ sys_ctrl[4] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR);
2667+ sys_ctrl[5] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR);
2668+ sys_ctrl[6] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR);
2669+ sys_ctrl[7] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR);
2670+ sys_ctrl[8] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR);
2671+
2672+ seq_printf(s, "MCU_DMA Configuration\n");
2673+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2674+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2675+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2676+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2677+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2678+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2679+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2680+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2681+
2682+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2683+ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[3],
2684+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2685+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2686+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2687+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2688+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2689+ "DMA1P1", sys_ctrl[7], sys_ctrl[8], sys_ctrl[6],
2690+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2691+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2692+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2693+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2694+
2695+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2696+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2697+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2698+ dump_dma_tx_ring_info(s, dev, "T0:TXD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2699+ dump_dma_tx_ring_info(s, dev, "T1:TXCMD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2700+ dump_dma_tx_ring_info(s, dev, "T2:TXD(WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2701+ dump_dma_rx_ring_info(s, dev, "R0:Data(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2702+ dump_dma_rx_ring_info(s, dev, "R1:TxDone(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2703+ dump_dma_rx_ring_info(s, dev, "R2:SPL(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2704+ dump_dma_rx_ring_info(s, dev, "R3:TxDone(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2705+ dump_dma_rx_ring_info(s, dev, "R4:TXS(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2706+
2707+ seq_printf(s, "MCU_DMA1 Ring Configuration\n");
2708+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2709+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2710+ dump_dma_tx_ring_info(s, dev, "T0:Event(WM2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR);
2711+ dump_dma_tx_ring_info(s, dev, "T1:Event0(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR);
2712+ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR);
2713+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR);
2714+ dump_dma_rx_ring_info(s, dev, "R1:Cmd(H2WM)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR);
2715+ dump_dma_rx_ring_info(s, dev, "R2:TXD0(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR);
2716+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR);
2717+ dump_dma_rx_ring_info(s, dev, "R4:Cmd(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR);
2718+
2719+ seq_printf(s, "MCU_DMA1 PCIe 1 Ring Configuration\n");
2720+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2721+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2722+ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR);
2723+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR);
2724+}
2725+
2726+static void
2727+mt7986_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2728+{
2729+ u32 sys_ctrl[5] = {};
2730+
2731+ /* HOST DMA */
2732+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
2733+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
2734+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
2735+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
2736+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
2737+
2738+ seq_printf(s, "HOST_DMA Configuration\n");
2739+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2740+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2741+ seq_printf(s, "%10s %10x %10x\n",
2742+ "Merge", sys_ctrl[0], sys_ctrl[1]);
2743+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2744+ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[4],
2745+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK, sys_ctrl[4]),
2746+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK, sys_ctrl[4]),
2747+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK, sys_ctrl[4]),
2748+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK, sys_ctrl[4]));
2749+
2750+
2751+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2752+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2753+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2754+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
2755+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
developer79a21a22023-01-09 13:57:39 +08002756+
2757+ if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed)) {
2758+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(0));
2759+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(1));
2760+ } else {
2761+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
2762+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
2763+ }
2764+
developer3fa816c2022-04-19 10:21:20 +08002765+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
2766+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2767+ dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
developer79a21a22023-01-09 13:57:39 +08002768+ if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed))
2769+ dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_WFDMA_WED_RX_CTRL(1));
2770+ else
2771+ dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
developer3fa816c2022-04-19 10:21:20 +08002772+ dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(3));
2773+ dump_dma_rx_ring_info(s, dev, "R4:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2774+ dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
2775+}
2776+
2777+static void
2778+mt7986_show_mcu_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2779+{
2780+ u32 sys_ctrl[3] = {};
2781+
2782+ /* MCU DMA information */
2783+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2784+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2785+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2786+
2787+ seq_printf(s, "MCU_DMA Configuration\n");
2788+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2789+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2790+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2791+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2792+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2793+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2794+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2795+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2796+
2797+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2798+ seq_printf(s, "%22s %10s %10s %10s %10s %10s\n",
2799+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2800+ dump_dma_tx_ring_info(s, dev, "T0:Event (WM2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2801+ dump_dma_tx_ring_info(s, dev, "T1:Event (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2802+ dump_dma_tx_ring_info(s, dev, "T2:TxDone (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2803+ dump_dma_tx_ring_info(s, dev, "T3:TxDone1 (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR);
2804+ dump_dma_tx_ring_info(s, dev, "T4:TXD (WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR);
2805+ dump_dma_tx_ring_info(s, dev, "T5:TXCMD (WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR);
2806+ dump_dma_tx_ring_info(s, dev, "T6:TXD (WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR);
2807+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2808+ dump_dma_rx_ring_info(s, dev, "R1:Cmd (H2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2809+ dump_dma_rx_ring_info(s, dev, "R2:TXD (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2810+ dump_dma_rx_ring_info(s, dev, "R3:TXD1 (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2811+ dump_dma_rx_ring_info(s, dev, "R4:Cmd (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2812+ dump_dma_rx_ring_info(s, dev, "R5:Data (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR);
2813+ dump_dma_rx_ring_info(s, dev, "R6:TxDone/STS (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR);
2814+ dump_dma_rx_ring_info(s, dev, "R7:RPT (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR);
2815+ dump_dma_rx_ring_info(s, dev, "R8:TxDone/STS (MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR);
2816+ dump_dma_rx_ring_info(s, dev, "R9:Data1 (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR);
2817+
2818+}
2819+
2820+static void
2821+mt7915_show_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2822+{
2823+ u32 sys_ctrl[10] = {};
2824+
2825+ if(is_mt7915(&dev->mt76)) {
2826+ mt7915_show_host_dma_info(s, dev);
2827+ mt7915_show_mcu_dma_info(s, dev);
2828+ } else {
2829+ mt7986_show_host_dma_info(s, dev);
2830+ mt7986_show_mcu_dma_info(s, dev);
2831+ }
2832+
2833+ /* MEM DMA information */
2834+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR);
2835+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR);
2836+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR);
2837+
2838+ seq_printf(s, "MEM_DMA Configuration\n");
2839+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2840+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2841+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2842+ "MEM", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2843+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2844+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2845+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2846+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2847+
2848+ seq_printf(s, "MEM_DMA Ring Configuration\n");
2849+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2850+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2851+ dump_dma_tx_ring_info(s, dev, "T0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR);
2852+ dump_dma_tx_ring_info(s, dev, "T1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR);
2853+ dump_dma_rx_ring_info(s, dev, "R0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR);
2854+ dump_dma_rx_ring_info(s, dev, "R1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR);
2855+}
2856+
2857+static int mt7915_trinfo_read(struct seq_file *s, void *data)
2858+{
2859+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2860+ const struct hif_pci_tx_ring_desc *tx_ring_layout;
2861+ const struct hif_pci_rx_ring_desc *rx_ring_layout;
developer79a21a22023-01-09 13:57:39 +08002862+ struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
developer3fa816c2022-04-19 10:21:20 +08002863+ u32 tx_ring_num, rx_ring_num;
2864+ u32 tbase[5], tcnt[5];
2865+ u32 tcidx[5], tdidx[5];
2866+ u32 rbase[6], rcnt[6];
2867+ u32 rcidx[6], rdidx[6];
2868+ int idx;
developer79a21a22023-01-09 13:57:39 +08002869+ bool flags = false;
developer3fa816c2022-04-19 10:21:20 +08002870+
2871+ if(is_mt7915(&dev->mt76)) {
2872+ tx_ring_layout = &mt7915_tx_ring_layout[0];
2873+ rx_ring_layout = &mt7915_rx_ring_layout[0];
2874+ tx_ring_num = ARRAY_SIZE(mt7915_tx_ring_layout);
2875+ rx_ring_num = ARRAY_SIZE(mt7915_rx_ring_layout);
2876+ } else {
2877+ tx_ring_layout = &mt7986_tx_ring_layout[0];
2878+ rx_ring_layout = &mt7986_rx_ring_layout[0];
2879+ tx_ring_num = ARRAY_SIZE(mt7986_tx_ring_layout);
2880+ rx_ring_num = ARRAY_SIZE(mt7986_rx_ring_layout);
2881+ }
2882+
2883+ for (idx = 0; idx < tx_ring_num; idx++) {
developer79a21a22023-01-09 13:57:39 +08002884+ if (mtk_wed_device_active(wed) &&
2885+ (tx_ring_layout[idx].ring_attr == HIF_TX_DATA)) {
2886+ struct mt76_phy *phy = dev->mt76.phys[MT_BAND0];
2887+ struct mt76_phy *ext_phy = dev->mt76.phys[MT_BAND1];
2888+ struct mt76_queue *q;
2889+
2890+ tbase[idx] = tcnt[idx] = tcidx[idx] = tdidx[idx] = 0;
2891+
2892+ if (!phy)
2893+ continue;
2894+
2895+ if (flags && !ext_phy)
2896+ continue;
2897+
2898+ if (flags && ext_phy)
2899+ phy = ext_phy;
2900+
2901+ q = phy->q_tx[0];
2902+
2903+ if (q->wed_regs) {
2904+ tbase[idx] = mtk_wed_device_reg_read(wed, q->wed_regs);
2905+ tcnt[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x04);
2906+ tcidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x08);
2907+ tdidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x0c);
2908+ }
2909+
2910+ flags = true;
2911+ } else {
2912+ tbase[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx));
2913+ tcnt[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x04);
2914+ tcidx[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x08);
2915+ tdidx[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x0c);}
developer3fa816c2022-04-19 10:21:20 +08002916+ }
2917+
2918+ for (idx = 0; idx < rx_ring_num; idx++) {
developer79a21a22023-01-09 13:57:39 +08002919+ if (rx_ring_layout[idx].ring_attr == HIF_RX_DATA) {
2920+ if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) {
2921+ struct mt76_queue *q = &dev->mt76.q_rx[MT_RXQ_MAIN];
2922+
2923+ rbase[idx] = rcnt[idx] = rcidx[idx] = rdidx[idx] = 0;
2924+
2925+ if (idx == 1)
2926+ q = &dev->mt76.q_rx[MT_RXQ_BAND1];
2927+
2928+ if (q->wed_regs) {
2929+ rbase[idx] = mtk_wed_device_reg_read(wed, q->wed_regs);
2930+ rcnt[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x04);
2931+ rcidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x08);
2932+ rdidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x0c);
2933+ }
2934+ } else {
2935+ rbase[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx));
2936+ rcnt[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x04);
2937+ rcidx[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x08);
2938+ rdidx[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x0c);
2939+ }
developer3fa816c2022-04-19 10:21:20 +08002940+ } else {
developer79a21a22023-01-09 13:57:39 +08002941+ if (mtk_wed_device_active(wed) && rx_ring_layout[idx].flags) {
2942+ struct mt76_queue *q = &dev->mt76.q_rx[MT_RXQ_MAIN_WA];
2943+
2944+ if (is_mt7915(&dev->mt76))
2945+ q = &dev->mt76.q_rx[MT_RXQ_MCU_WA];
2946+
2947+ rbase[idx] = mtk_wed_device_reg_read(wed, q->wed_regs);
2948+ rcnt[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x04);
2949+ rcidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x08);
2950+ rdidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x0c);
2951+
2952+ } else {
2953+ rbase[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2));
2954+ rcnt[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x04);
2955+ rcidx[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x08);
2956+ rdidx[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x0c);
2957+ }
developer3fa816c2022-04-19 10:21:20 +08002958+ }
2959+ }
2960+
2961+ seq_printf(s, "=================================================\n");
2962+ seq_printf(s, "TxRing Configuration\n");
2963+ seq_printf(s, "%4s %10s %8s %1s %6s %6s %6s %6s\n",
2964+ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
2965+ "QCnt");
2966+ for (idx = 0; idx < tx_ring_num; idx++) {
2967+ u32 queue_cnt;
2968+
2969+ queue_cnt = (tcidx[idx] >= tdidx[idx]) ?
2970+ (tcidx[idx] - tdidx[idx]) :
2971+ (tcidx[idx] - tdidx[idx] + tcnt[idx]);
2972+ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
2973+ idx, tx_ring_layout[idx].ring_info,
2974+ MT_DBG_TX_RING_CTRL(idx), tbase[idx],
2975+ tcnt[idx], tcidx[idx], tdidx[idx], queue_cnt);
2976+ }
2977+
2978+ seq_printf(s, "RxRing Configuration\n");
2979+ seq_printf(s, "%4s %10s %8s %10s %6s %6s %6s %6s\n",
2980+ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
2981+ "QCnt");
2982+
2983+ for (idx = 0; idx < rx_ring_num; idx++) {
2984+ u32 queue_cnt;
2985+
2986+ queue_cnt = (rdidx[idx] > rcidx[idx]) ?
2987+ (rdidx[idx] - rcidx[idx] - 1) :
2988+ (rdidx[idx] - rcidx[idx] + rcnt[idx] - 1);
2989+ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
2990+ idx, rx_ring_layout[idx].ring_info,
2991+ (idx < 2) ? MT_DBG_RX_DATA_RING_CTRL(idx): MT_DBG_RX_EVENT_RING_CTRL(idx - 2),
2992+ rbase[idx], rcnt[idx], rcidx[idx], rdidx[idx], queue_cnt);
2993+ }
2994+
2995+ mt7915_show_dma_info(s, dev);
2996+ return 0;
2997+}
2998+
2999+static int mt7915_drr_info(struct seq_file *s, void *data)
3000+{
3001+#define DL_AC_START 0x00
3002+#define DL_AC_END 0x0F
3003+#define UL_AC_START 0x10
3004+#define UL_AC_END 0x1F
3005+
3006+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3007+ u32 drr_sta_status[16];
3008+ u32 drr_ctrl_def_val = 0x80220000, drr_ctrl_val = 0;
3009+ bool is_show = false;
3010+ int idx, sta_line = 0, sta_no = 0, max_sta_line = (mt7915_wtbl_size(dev) + 31) / 32;
3011+ seq_printf(s, "DRR Table STA Info:\n");
3012+
3013+ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
3014+ is_show = true;
3015+ drr_ctrl_val = (drr_ctrl_def_val | idx);
3016+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3017+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3018+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3019+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3020+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3021+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3022+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3023+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3024+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3025+
3026+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
3027+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1 << 10);
3028+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3029+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3030+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3031+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3032+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3033+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3034+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3035+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3036+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3037+ }
3038+ if (!is_mt7915(&dev->mt76))
3039+ max_sta_line = 8;
3040+
3041+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
3042+ if (drr_sta_status[sta_line] > 0) {
3043+ for (sta_no = 0; sta_no < 32; sta_no++) {
3044+ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
3045+ if (is_show) {
3046+ seq_printf(s, "\n DL AC%02d Queue Non-Empty STA:\n", idx);
3047+ is_show = false;
3048+ }
3049+ seq_printf(s, "%d ", sta_no + (sta_line * 32));
3050+ }
3051+ }
3052+ }
3053+ }
3054+ }
3055+
3056+ for (idx = UL_AC_START; idx <= UL_AC_END; idx++) {
3057+ is_show = true;
3058+ drr_ctrl_val = (drr_ctrl_def_val | idx);
3059+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3060+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3061+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3062+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3063+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3064+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3065+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3066+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3067+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3068+
3069+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
3070+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1 << 10);
3071+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3072+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3073+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3074+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3075+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3076+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3077+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3078+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3079+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3080+ }
3081+
3082+ if (!is_mt7915(&dev->mt76))
3083+ max_sta_line = 8;
3084+
3085+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
3086+ if (drr_sta_status[sta_line] > 0) {
3087+ for (sta_no = 0; sta_no < 32; sta_no++) {
3088+ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
3089+ if (is_show) {
3090+ seq_printf(s, "\n UL AC%02d Queue Non-Empty STA:\n", idx);
3091+ is_show = false;
3092+ }
3093+ seq_printf(s, "%d ", sta_no + (sta_line * 32));
3094+ }
3095+ }
3096+ }
3097+ }
3098+ }
3099+
3100+ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
3101+ drr_ctrl_def_val = 0x80420000;
3102+ drr_ctrl_val = (drr_ctrl_def_val | idx);
3103+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3104+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3105+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3106+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3107+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3108+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3109+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3110+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3111+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3112+
3113+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
3114+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1<<10);
3115+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3116+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3117+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3118+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3119+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3120+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3121+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3122+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3123+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3124+ }
3125+
3126+ seq_printf(s, "\nBSSGrp[%d]:\n", idx);
3127+ if (!is_mt7915(&dev->mt76))
3128+ max_sta_line = 8;
3129+
3130+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
3131+ seq_printf(s, "0x%08x ", drr_sta_status[sta_line]);
3132+
3133+ if ((sta_line % 4) == 3)
3134+ seq_printf(s, "\n");
3135+ }
3136+ }
3137+
3138+ return 0;
3139+}
3140+
developerf32dabf2022-06-01 10:59:24 +08003141+#define CR_NUM_OF_AC 17
developer3fa816c2022-04-19 10:21:20 +08003142+
3143+typedef enum _ENUM_UMAC_PORT_T {
3144+ ENUM_UMAC_HIF_PORT_0 = 0,
3145+ ENUM_UMAC_CPU_PORT_1 = 1,
3146+ ENUM_UMAC_LMAC_PORT_2 = 2,
3147+ ENUM_PLE_CTRL_PSE_PORT_3 = 3,
3148+ ENUM_UMAC_PSE_PLE_PORT_TOTAL_NUM = 4
3149+} ENUM_UMAC_PORT_T, *P_ENUM_UMAC_PORT_T;
3150+
3151+/* N9 MCU QUEUE LIST */
3152+typedef enum _ENUM_UMAC_CPU_P_QUEUE_T {
3153+ ENUM_UMAC_CTX_Q_0 = 0,
3154+ ENUM_UMAC_CTX_Q_1 = 1,
3155+ ENUM_UMAC_CTX_Q_2 = 2,
3156+ ENUM_UMAC_CTX_Q_3 = 3,
3157+ ENUM_UMAC_CRX = 0,
3158+ ENUM_UMAC_CIF_QUEUE_TOTAL_NUM = 4
3159+} ENUM_UMAC_CPU_P_QUEUE_T, *P_ENUM_UMAC_CPU_P_QUEUE_T;
3160+
3161+/* LMAC PLE TX QUEUE LIST */
3162+typedef enum _ENUM_UMAC_LMAC_PLE_TX_P_QUEUE_T {
3163+ ENUM_UMAC_LMAC_PLE_TX_Q_00 = 0x00,
3164+ ENUM_UMAC_LMAC_PLE_TX_Q_01 = 0x01,
3165+ ENUM_UMAC_LMAC_PLE_TX_Q_02 = 0x02,
3166+ ENUM_UMAC_LMAC_PLE_TX_Q_03 = 0x03,
3167+
3168+ ENUM_UMAC_LMAC_PLE_TX_Q_10 = 0x04,
3169+ ENUM_UMAC_LMAC_PLE_TX_Q_11 = 0x05,
3170+ ENUM_UMAC_LMAC_PLE_TX_Q_12 = 0x06,
3171+ ENUM_UMAC_LMAC_PLE_TX_Q_13 = 0x07,
3172+
3173+ ENUM_UMAC_LMAC_PLE_TX_Q_20 = 0x08,
3174+ ENUM_UMAC_LMAC_PLE_TX_Q_21 = 0x09,
3175+ ENUM_UMAC_LMAC_PLE_TX_Q_22 = 0x0a,
3176+ ENUM_UMAC_LMAC_PLE_TX_Q_23 = 0x0b,
3177+
3178+ ENUM_UMAC_LMAC_PLE_TX_Q_30 = 0x0c,
3179+ ENUM_UMAC_LMAC_PLE_TX_Q_31 = 0x0d,
3180+ ENUM_UMAC_LMAC_PLE_TX_Q_32 = 0x0e,
3181+ ENUM_UMAC_LMAC_PLE_TX_Q_33 = 0x0f,
3182+
3183+ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 = 0x10,
3184+ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0 = 0x11,
3185+ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0 = 0x12,
3186+ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0 = 0x13,
3187+
3188+ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 = 0x14,
3189+ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1 = 0x15,
3190+ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1 = 0x16,
3191+ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1 = 0x17,
3192+ ENUM_UMAC_LMAC_PLE_TX_Q_NAF = 0x18,
3193+ ENUM_UMAC_LMAC_PLE_TX_Q_NBCN = 0x19,
3194+ ENUM_UMAC_LMAC_PLE_TX_Q_RELEASE = 0x1f, /* DE suggests not to use 0x1f, it's only for hw free queue */
3195+ ENUM_UMAC_LMAC_QUEUE_TOTAL_NUM = 24,
3196+
3197+} ENUM_UMAC_LMAC_TX_P_QUEUE_T, *P_ENUM_UMAC_LMAC_TX_P_QUEUE_T;
3198+
3199+typedef struct _EMPTY_QUEUE_INFO_T {
3200+ char *QueueName;
3201+ u32 Portid;
3202+ u32 Queueid;
3203+} EMPTY_QUEUE_INFO_T, *P_EMPTY_QUEUE_INFO_T;
3204+
3205+static EMPTY_QUEUE_INFO_T ple_queue_empty_info[] = {
3206+ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
3207+ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
3208+ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
3209+ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
3210+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
3211+ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0}, /* Q16 */
3212+ {"BMC Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0},
3213+ {"BCN Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0},
3214+ {"PSMP Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0},
3215+ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1},
3216+ {"BMC Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1},
3217+ {"BCN Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1},
3218+ {"PSMP Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1},
3219+ {"NAF Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NAF},
3220+ {"NBCN Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NBCN},
3221+ {NULL, 0, 0}, {NULL, 0, 0}, /* 18, 19 not defined */
3222+ {"FIXFID Q", ENUM_UMAC_LMAC_PORT_2, 0x1a},
3223+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
3224+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 21~29 not defined */
3225+ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7e},
3226+ {"RLS2 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7f}
3227+};
3228+
3229+static EMPTY_QUEUE_INFO_T ple_txcmd_queue_empty_info[] = {
3230+ {"AC00Q", ENUM_UMAC_LMAC_PORT_2, 0x40},
3231+ {"AC01Q", ENUM_UMAC_LMAC_PORT_2, 0x41},
3232+ {"AC02Q", ENUM_UMAC_LMAC_PORT_2, 0x42},
3233+ {"AC03Q", ENUM_UMAC_LMAC_PORT_2, 0x43},
3234+ {"AC10Q", ENUM_UMAC_LMAC_PORT_2, 0x44},
3235+ {"AC11Q", ENUM_UMAC_LMAC_PORT_2, 0x45},
3236+ {"AC12Q", ENUM_UMAC_LMAC_PORT_2, 0x46},
3237+ {"AC13Q", ENUM_UMAC_LMAC_PORT_2, 0x47},
3238+ {"AC20Q", ENUM_UMAC_LMAC_PORT_2, 0x48},
3239+ {"AC21Q", ENUM_UMAC_LMAC_PORT_2, 0x49},
3240+ {"AC22Q", ENUM_UMAC_LMAC_PORT_2, 0x4a},
3241+ {"AC23Q", ENUM_UMAC_LMAC_PORT_2, 0x4b},
3242+ {"AC30Q", ENUM_UMAC_LMAC_PORT_2, 0x4c},
3243+ {"AC31Q", ENUM_UMAC_LMAC_PORT_2, 0x4d},
3244+ {"AC32Q", ENUM_UMAC_LMAC_PORT_2, 0x4e},
3245+ {"AC33Q", ENUM_UMAC_LMAC_PORT_2, 0x4f},
3246+ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, 0x50},
3247+ {"TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x51},
3248+ {"TWT TSF-TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x52},
3249+ {"TWT DL Q0", ENUM_UMAC_LMAC_PORT_2, 0x53},
3250+ {"TWT UL Q0", ENUM_UMAC_LMAC_PORT_2, 0x54},
3251+ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, 0x55},
3252+ {"TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x56},
3253+ {"TWT TSF-TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x57},
3254+ {"TWT DL Q1", ENUM_UMAC_LMAC_PORT_2, 0x58},
3255+ {"TWT UL Q1", ENUM_UMAC_LMAC_PORT_2, 0x59},
3256+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
3257+};
3258+
3259+
3260+
3261+static char* sta_ctrl_reg[] = {"ENABLE", "DISABLE", "PAUSE"};
3262+static u32 chip_show_sta_acq_info(struct seq_file *s, struct mt7915_dev *dev, u32 *ple_stat,
3263+ u32 *sta_pause, u32 *dis_sta_map,
3264+ u32 dumptxd)
3265+{
3266+ int i, j;
3267+ u32 total_nonempty_cnt = 0;
3268+ u32 ac_num = 9, all_ac_num;
3269+
3270+ /* TDO: ac_num = 16 for mt7986 */
developerf32dabf2022-06-01 10:59:24 +08003271+ if (!is_mt7915(&dev->mt76))
3272+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003273+
3274+ all_ac_num = ac_num * 4;
3275+
3276+ for (j = 0; j < all_ac_num; j++) { /* show AC Q info */
3277+ for (i = 0; i < 32; i++) {
3278+ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
developerf32dabf2022-06-01 10:59:24 +08003279+ u32 hfid, tfid, pktcnt, ac_n = j / ac_num, ctrl = 0;
developer3fa816c2022-04-19 10:21:20 +08003280+ u32 sta_num = i + (j % ac_num) * 32, fl_que_ctrl[3] = {0};
3281+ //struct wifi_dev *wdev = wdev_search_by_wcid(pAd, sta_num);
3282+ u32 wmmidx = 0;
3283+ struct mt7915_sta *msta;
3284+ struct mt76_wcid *wcid;
developer3fa816c2022-04-19 10:21:20 +08003285+
3286+ wcid = rcu_dereference(dev->mt76.wcid[sta_num]);
developerdfb50982023-09-11 13:34:36 +08003287+ if (!wcid) {
developer3fa816c2022-04-19 10:21:20 +08003288+ printk("ERROR!! no found STA wcid=%d\n", sta_num);
developerf32dabf2022-06-01 10:59:24 +08003289+ continue;
developer3fa816c2022-04-19 10:21:20 +08003290+ }
3291+ msta = container_of(wcid, struct mt7915_sta, wcid);
3292+ wmmidx = msta->vif->mt76.wmm_idx;
3293+
developerf32dabf2022-06-01 10:59:24 +08003294+ seq_printf(s, "\tSTA%d AC%d: ", sta_num, ac_n);
developer3fa816c2022-04-19 10:21:20 +08003295+
3296+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3297+ fl_que_ctrl[0] |= (ENUM_UMAC_LMAC_PORT_2 << MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
developerf32dabf2022-06-01 10:59:24 +08003298+ fl_que_ctrl[0] |= (ac_n << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
developer3fa816c2022-04-19 10:21:20 +08003299+ fl_que_ctrl[0] |= sta_num;
3300+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3301+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3302+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3303+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3304+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3305+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3306+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x",
3307+ tfid, hfid, pktcnt);
3308+
3309+ if (((sta_pause[j % 6] & 0x1 << i) >> i) == 1)
3310+ ctrl = 2;
3311+
3312+ if (((dis_sta_map[j % 6] & 0x1 << i) >> i) == 1)
3313+ ctrl = 1;
3314+
3315+ seq_printf(s, " ctrl = %s", sta_ctrl_reg[ctrl]);
3316+ seq_printf(s, " (wmmidx=%d)\n", wmmidx);
3317+
3318+ total_nonempty_cnt++;
3319+
3320+ // TODO
3321+ //if (pktcnt > 0 && dumptxd > 0)
3322+ // ShowTXDInfo(pAd, hfid);
3323+ }
3324+ }
3325+ }
3326+
3327+ return total_nonempty_cnt;
3328+}
3329+
3330+static void chip_show_txcmdq_info(struct seq_file *s, struct mt7915_dev *dev, u32 ple_txcmd_stat)
3331+{
3332+ int i;
3333+
3334+ seq_printf(s, "Nonempty TXCMD Q info:\n");
developerf32dabf2022-06-01 10:59:24 +08003335+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003336+ if (((ple_txcmd_stat & (0x1 << i)) >> i) == 0) {
3337+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3338+
3339+ if (ple_txcmd_queue_empty_info[i].QueueName != NULL) {
3340+ seq_printf(s, "\t%s: ", ple_txcmd_queue_empty_info[i].QueueName);
3341+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3342+ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Portid <<
3343+ MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
3344+ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Queueid <<
3345+ MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
3346+ } else
3347+ continue;
3348+
3349+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3350+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3351+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3352+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3353+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3354+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3355+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3356+ tfid, hfid, pktcnt);
3357+ }
3358+ }
3359+}
3360+
3361+static void chip_get_ple_acq_stat(struct mt7915_dev *dev, u32 *ple_stat)
3362+{
3363+ int i;
3364+ int cr_num = 9, all_cr_num;
3365+ u32 ac , index;
3366+
3367+ /* TDO: cr_num = 16 for mt7986 */
developer3fa816c2022-04-19 10:21:20 +08003368+ if(!is_mt7915(&dev->mt76))
developerf32dabf2022-06-01 10:59:24 +08003369+ cr_num = 17;
3370+
developer3fa816c2022-04-19 10:21:20 +08003371+ all_cr_num = cr_num * 4;
3372+
3373+ ple_stat[0] = mt76_rr(dev, MT_DBG_PLE_QUEUE_EMPTY);
3374+
3375+ for(i = 0; i < all_cr_num; i++) {
3376+ ac = i / cr_num;
3377+ index = i % cr_num;
3378+ ple_stat[i + 1] =
3379+ mt76_rr(dev, MT_DBG_PLE_AC_QEMPTY(ac, index));
3380+
3381+ }
3382+}
3383+
3384+static void chip_get_dis_sta_map(struct mt7915_dev *dev, u32 *dis_sta_map)
3385+{
3386+ int i;
developerf32dabf2022-06-01 10:59:24 +08003387+ u32 ac_num = 9;
3388+
3389+ /* TDO: ac_num = 16 for mt7986 */
3390+ if (!is_mt7915(&dev->mt76))
3391+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003392+
developerf32dabf2022-06-01 10:59:24 +08003393+ for(i = 0; i < ac_num; i++) {
developer3fa816c2022-04-19 10:21:20 +08003394+ dis_sta_map[i] = mt76_rr(dev, MT_DBG_PLE_DIS_STA_MAP(i));
3395+ }
3396+}
3397+
3398+static void chip_get_sta_pause(struct mt7915_dev *dev, u32 *sta_pause)
3399+{
3400+ int i;
developerf32dabf2022-06-01 10:59:24 +08003401+ u32 ac_num = 9;
developer3fa816c2022-04-19 10:21:20 +08003402+
developerf32dabf2022-06-01 10:59:24 +08003403+ /* TDO: ac_num = 16 for mt7986 */
3404+ if (!is_mt7915(&dev->mt76))
3405+ ac_num = 17;
3406+
3407+ for(i = 0; i < ac_num; i++) {
developer3fa816c2022-04-19 10:21:20 +08003408+ sta_pause[i] = mt76_rr(dev, MT_DBG_PLE_STATION_PAUSE(i));
3409+ }
3410+}
3411+
3412+static int mt7915_pleinfo_read(struct seq_file *s, void *data)
3413+{
3414+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3415+ u32 ple_buf_ctrl, pg_sz, pg_num;
developerf32dabf2022-06-01 10:59:24 +08003416+ u32 ple_stat[70] = {0}, pg_flow_ctrl[8] = {0};
developer3fa816c2022-04-19 10:21:20 +08003417+ u32 ple_native_txcmd_stat;
3418+ u32 ple_txcmd_stat;
3419+ u32 sta_pause[CR_NUM_OF_AC] = {0}, dis_sta_map[CR_NUM_OF_AC] = {0};
3420+ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail, hif_max_q, hif_min_q;
3421+ u32 rpg_hif, upg_hif, cpu_max_q, cpu_min_q, rpg_cpu, upg_cpu;
3422+ int i, j;
3423+ u32 ac_num = 9, all_ac_num;
3424+
3425+ /* TDO: ac_num = 16 for mt7986 */
developerf32dabf2022-06-01 10:59:24 +08003426+ if (!is_mt7915(&dev->mt76))
3427+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003428+
3429+ all_ac_num = ac_num * 4;
3430+
3431+ ple_buf_ctrl = mt76_rr(dev, MT_DBG_PLE_PBUF_CTRL_ADDR);
3432+ chip_get_ple_acq_stat(dev, ple_stat);
3433+ ple_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_TXCMD_Q_EMPTY);
3434+ ple_native_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY);
3435+ pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PLE_FREEPG_CNT);
3436+ pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FREEPG_HEAD_TAIL);
3437+ pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_GROUP);
3438+ pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PLE_HIF_PG_INFO);
3439+ pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PLE_PG_CPU_GROUP);
3440+ pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PLE_CPU_PG_INFO);
3441+ pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_TXCMD_GROUP);
3442+ pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PLE_HIF_TXCMD_PG_INFO);
3443+ chip_get_dis_sta_map(dev, dis_sta_map);
3444+ chip_get_sta_pause(dev, sta_pause);
3445+
3446+ seq_printf(s, "PLE Configuration Info:\n");
3447+ seq_printf(s, "\tPacket Buffer Control(0x%x): 0x%08x\n",
3448+ MT_DBG_PLE_PBUF_CTRL_ADDR, ple_buf_ctrl);
3449+
3450+ pg_sz = FIELD_GET(MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK, ple_buf_ctrl);
3451+ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n",
3452+ pg_sz, (pg_sz == 1 ? 128 : 64));
3453+ seq_printf(s, "\t\tPage Offset=%ld(in unit of 2KB)\n",
3454+ FIELD_GET(MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK, ple_buf_ctrl));
3455+
3456+ pg_num = FIELD_GET(MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK, ple_buf_ctrl);
3457+ seq_printf(s, "\t\tTotal Page=%d pages\n", pg_num);
3458+
3459+ /* Page Flow Control */
3460+ seq_printf(s, "PLE Page Flow Control:\n");
3461+ seq_printf(s, "\tFree page counter(0x%x): 0x%08x\n",
3462+ MT_DBG_PLE_FREEPG_CNT, pg_flow_ctrl[0]);
3463+ fpg_cnt = FIELD_GET(MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK, pg_flow_ctrl[0]);
3464+
3465+ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3466+ ffa_cnt = FIELD_GET(MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK, pg_flow_ctrl[0]);
3467+
3468+ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3469+ seq_printf(s, "\tFree page head and tail(0x%x): 0x%08x\n",
3470+ MT_DBG_PLE_FREEPG_HEAD_TAIL, pg_flow_ctrl[1]);
3471+
3472+ fpg_head = FIELD_GET(MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK, pg_flow_ctrl[1]);
3473+ fpg_tail = FIELD_GET(MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK, pg_flow_ctrl[1]);
3474+ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3475+ seq_printf(s, "\tReserved page counter of HIF group(0x%x): 0x%08x\n",
3476+ MT_DBG_PLE_PG_HIF_GROUP, pg_flow_ctrl[2]);
3477+ seq_printf(s, "\tHIF group page status(0x%x): 0x%08x\n",
3478+ MT_DBG_PLE_HIF_PG_INFO, pg_flow_ctrl[3]);
3479+
3480+ hif_min_q = FIELD_GET(MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK, pg_flow_ctrl[2]);
3481+ hif_max_q = FIELD_GET(MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK, pg_flow_ctrl[2]);
3482+ seq_printf(s, "\t\tThe max/min quota pages of HIF group=0x%03x/0x%03x\n", hif_max_q, hif_min_q);
3483+
3484+ rpg_hif = FIELD_GET(MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK, pg_flow_ctrl[3]);
3485+ upg_hif = FIELD_GET(MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK, pg_flow_ctrl[3]);
3486+ seq_printf(s, "\t\tThe used/reserved pages of HIF group=0x%03x/0x%03x\n", upg_hif, rpg_hif);
3487+
3488+ seq_printf(s, "\tReserved page counter of HIF_TXCMD group(0x%x): 0x%08x\n",
3489+ MT_DBG_PLE_PG_HIF_TXCMD_GROUP, pg_flow_ctrl[6]);
3490+ seq_printf(s, "\tHIF_TXCMD group page status(0x%x): 0x%08x\n",
3491+ MT_DBG_PLE_HIF_TXCMD_PG_INFO, pg_flow_ctrl[7]);
3492+ cpu_min_q = FIELD_GET(MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
developerf32dabf2022-06-01 10:59:24 +08003493+ cpu_max_q = FIELD_GET(MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK, pg_flow_ctrl[6]);
developer3fa816c2022-04-19 10:21:20 +08003494+ seq_printf(s, "\t\tThe max/min quota pages of HIF_TXCMD group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
3495+
3496+ rpg_cpu = FIELD_GET(MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK, pg_flow_ctrl[7]);
3497+ upg_cpu = FIELD_GET(MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK, pg_flow_ctrl[7]);
3498+ seq_printf(s, "\t\tThe used/reserved pages of HIF_TXCMD group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
3499+
developerf32dabf2022-06-01 10:59:24 +08003500+ seq_printf(s, "\tReserved page counter of CPU group(0x%x): 0x%08x\n",
3501+ MT_DBG_PLE_PG_CPU_GROUP, pg_flow_ctrl[4]);
3502+ seq_printf(s, "\tCPU group page status(0x%x): 0x%08x\n",
3503+ MT_DBG_PLE_CPU_PG_INFO, pg_flow_ctrl[5]);
developer3fa816c2022-04-19 10:21:20 +08003504+ cpu_min_q = FIELD_GET(MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK, pg_flow_ctrl[4]);
3505+ cpu_max_q = FIELD_GET(MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK, pg_flow_ctrl[4]);
3506+ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
3507+
3508+ rpg_cpu = FIELD_GET(MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK, pg_flow_ctrl[5]);
3509+ upg_cpu = FIELD_GET(MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK, pg_flow_ctrl[5]);
3510+ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
3511+
3512+ if ((ple_stat[0] & MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK) == 0) {
3513+ for (j = 0; j < all_ac_num; j++) {
3514+ if (j % ac_num == 0) {
3515+ seq_printf(s, "\n\tNonempty AC%d Q of STA#: ", j / ac_num);
3516+ }
3517+
developerf32dabf2022-06-01 10:59:24 +08003518+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003519+ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
3520+ seq_printf(s, "%d ", i + (j % ac_num) * 32);
3521+ }
3522+ }
3523+ }
3524+
3525+ seq_printf(s, "\n");
3526+ }
3527+
3528+ seq_printf(s, "non-native/native txcmd queue empty = %d/%d\n", ple_txcmd_stat, ple_native_txcmd_stat);
3529+
3530+ seq_printf(s, "Nonempty Q info:\n");
3531+
developerf32dabf2022-06-01 10:59:24 +08003532+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003533+ if (((ple_stat[0] & (0x1 << i)) >> i) == 0) {
3534+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3535+
3536+ if (ple_queue_empty_info[i].QueueName != NULL) {
3537+ seq_printf(s, "\t%s: ", ple_queue_empty_info[i].QueueName);
3538+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3539+ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Portid << MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
3540+ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Queueid << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
3541+ } else
3542+ continue;
3543+
3544+ if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 &&
3545+ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0)
3546+ /* band0 set TGID 0, bit31 = 0 */
3547+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x0);
3548+ else if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 &&
3549+ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1)
3550+ /* band1 set TGID 1, bit31 = 1 */
3551+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x80000000);
3552+
3553+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3554+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3555+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3556+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3557+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3558+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3559+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3560+ tfid, hfid, pktcnt);
3561+
3562+ /* TODO */
3563+ //if (pktcnt > 0 && dumptxd > 0)
3564+ // ShowTXDInfo(pAd, hfid);
3565+ }
3566+ }
3567+
3568+ chip_show_sta_acq_info(s, dev, ple_stat, sta_pause, dis_sta_map, 0/*dumptxd*/);
3569+ chip_show_txcmdq_info(s, dev, ple_native_txcmd_stat);
3570+
3571+ return 0;
3572+}
3573+
3574+typedef enum _ENUM_UMAC_PLE_CTRL_P3_QUEUE_T {
3575+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1E = 0x1e,
3576+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1F = 0x1f,
3577+ ENUM_UMAC_PLE_CTRL_P3_TOTAL_NUM = 2
3578+} ENUM_UMAC_PLE_CTRL_P3_QUEUE_T, *P_ENUM_UMAC_PLE_CTRL_P3_QUEUE_T;
3579+
3580+static EMPTY_QUEUE_INFO_T pse_queue_empty_info[] = {
3581+ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
3582+ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
3583+ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
3584+ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
3585+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
3586+ {"HIF Q0", ENUM_UMAC_HIF_PORT_0, 0}, /* Q8 */
3587+ {"HIF Q1", ENUM_UMAC_HIF_PORT_0, 1},
3588+ {"HIF Q2", ENUM_UMAC_HIF_PORT_0, 2},
3589+ {"HIF Q3", ENUM_UMAC_HIF_PORT_0, 3},
3590+ {"HIF Q4", ENUM_UMAC_HIF_PORT_0, 4},
3591+ {"HIF Q5", ENUM_UMAC_HIF_PORT_0, 5},
3592+ {NULL, 0, 0}, {NULL, 0, 0}, /* 14~15 not defined */
3593+ {"LMAC Q", ENUM_UMAC_LMAC_PORT_2, 0},
3594+ {"MDP TX Q", ENUM_UMAC_LMAC_PORT_2, 1},
3595+ {"MDP RX Q", ENUM_UMAC_LMAC_PORT_2, 2},
3596+ {"SEC TX Q", ENUM_UMAC_LMAC_PORT_2, 3},
3597+ {"SEC RX Q", ENUM_UMAC_LMAC_PORT_2, 4},
3598+ {"SFD_PARK Q", ENUM_UMAC_LMAC_PORT_2, 5},
3599+ {"MDP_TXIOC Q", ENUM_UMAC_LMAC_PORT_2, 6},
3600+ {"MDP_RXIOC Q", ENUM_UMAC_LMAC_PORT_2, 7},
3601+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 24~30 not defined */
3602+ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, ENUM_UMAC_PLE_CTRL_P3_Q_0X1F}
3603+};
3604+
3605+static int mt7915_pseinfo_read(struct seq_file *s, void *data)
3606+{
3607+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3608+ u32 pse_buf_ctrl, pg_sz, pg_num;
3609+ u32 pse_stat, pg_flow_ctrl[22] = {0};
3610+ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail;
3611+ u32 max_q, min_q, rsv_pg, used_pg;
3612+ int i;
3613+
3614+ pse_buf_ctrl = mt76_rr(dev, MT_DBG_PSE_PBUF_CTRL);
3615+ pse_stat = mt76_rr(dev, MT_DBG_PSE_QUEUE_EMPTY);
3616+ pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PSE_FREEPG_CNT);
3617+ pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PSE_FREEPG_HEAD_TAIL);
3618+ pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PSE_PG_HIF0_GROUP);
3619+ pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PSE_HIF0_PG_INFO);
3620+ pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PSE_PG_HIF1_GROUP);
3621+ pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PSE_HIF1_PG_INFO);
3622+ pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PSE_PG_CPU_GROUP);
3623+ pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PSE_CPU_PG_INFO);
3624+ pg_flow_ctrl[8] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC0_GROUP);
3625+ pg_flow_ctrl[9] = mt76_rr(dev, MT_DBG_PSE_LMAC0_PG_INFO);
3626+ pg_flow_ctrl[10] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC1_GROUP);
3627+ pg_flow_ctrl[11] = mt76_rr(dev, MT_DBG_PSE_LMAC1_PG_INFO);
3628+ pg_flow_ctrl[12] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC2_GROUP);
3629+ pg_flow_ctrl[13] = mt76_rr(dev, MT_DBG_PSE_LMAC2_PG_INFO);
3630+ pg_flow_ctrl[14] = mt76_rr(dev, MT_DBG_PSE_PG_PLE_GROUP);
3631+ pg_flow_ctrl[15] = mt76_rr(dev, MT_DBG_PSE_PLE_PG_INFO);
3632+ pg_flow_ctrl[16] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC3_GROUP);
3633+ pg_flow_ctrl[17] = mt76_rr(dev, MT_DBG_PSE_LMAC3_PG_INFO);
3634+ pg_flow_ctrl[18] = mt76_rr(dev, MT_DBG_PSE_PG_MDP_GROUP);
3635+ pg_flow_ctrl[19] = mt76_rr(dev, MT_DBG_PSE_MDP_PG_INFO);
3636+ pg_flow_ctrl[20] = mt76_rr(dev, MT_DBG_PSE_PG_PLE1_GROUP);
3637+ pg_flow_ctrl[21] = mt76_rr(dev,MT_DBG_PSE_PLE1_PG_INFO);
3638+
3639+ /* Configuration Info */
3640+ seq_printf(s, "PSE Configuration Info:\n");
3641+ seq_printf(s, "\tPacket Buffer Control(0x82068014): 0x%08x\n", pse_buf_ctrl);
3642+ pg_sz = FIELD_GET(MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK, pse_buf_ctrl);
3643+
3644+ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n", pg_sz, (pg_sz == 1 ? 256 : 128));
3645+ seq_printf(s, "\t\tPage Offset=%ld(in unit of 64KB)\n",
3646+ FIELD_GET(MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK, pse_buf_ctrl));
3647+ pg_num = FIELD_GET(MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK, pse_buf_ctrl);
3648+
3649+ seq_printf(s, "\t\tTotal page numbers=%d pages\n", pg_num);
3650+
3651+ /* Page Flow Control */
3652+ seq_printf(s, "PSE Page Flow Control:\n");
3653+ seq_printf(s, "\tFree page counter(0x82068100): 0x%08x\n", pg_flow_ctrl[0]);
3654+ fpg_cnt = FIELD_GET(MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK, pg_flow_ctrl[0]);
3655+ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3656+
3657+ ffa_cnt = FIELD_GET(MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK, pg_flow_ctrl[0]);
3658+ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3659+
3660+ seq_printf(s, "\tFree page head and tail(0x82068104): 0x%08x\n", pg_flow_ctrl[1]);
3661+ fpg_head = FIELD_GET(MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK, pg_flow_ctrl[1]);
3662+
3663+ fpg_tail = FIELD_GET(MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK, pg_flow_ctrl[1]);
3664+ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3665+ seq_printf(s, "\tReserved page counter of HIF0 group(0x82068110): 0x%08x\n", pg_flow_ctrl[2]);
3666+ seq_printf(s, "\tHIF0 group page status(0x82068114): 0x%08x\n", pg_flow_ctrl[3]);
3667+ min_q = FIELD_GET(MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK, pg_flow_ctrl[2]);
3668+ max_q = FIELD_GET(MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK, pg_flow_ctrl[2]);
3669+ seq_printf(s, "\t\tThe max/min quota pages of HIF0 group=0x%03x/0x%03x\n", max_q, min_q);
3670+ rsv_pg = FIELD_GET(MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK, pg_flow_ctrl[3]);;
3671+ used_pg = FIELD_GET(MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK, pg_flow_ctrl[3]);
3672+ seq_printf(s, "\t\tThe used/reserved pages of HIF0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3673+ seq_printf(s, "\tReserved page counter of HIF1 group(0x82068118): 0x%08x\n", pg_flow_ctrl[4]);
3674+ seq_printf(s, "\tHIF1 group page status(0x8206811c): 0x%08x\n", pg_flow_ctrl[5]);
3675+ min_q = FIELD_GET(MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK, pg_flow_ctrl[4]);
3676+ max_q = FIELD_GET(MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK, pg_flow_ctrl[4]);
3677+ seq_printf(s, "\t\tThe max/min quota pages of HIF1 group=0x%03x/0x%03x\n", max_q, min_q);
3678+ rsv_pg = FIELD_GET(MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK, pg_flow_ctrl[5]);
3679+ used_pg = FIELD_GET(MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK, pg_flow_ctrl[5]);
3680+
3681+ seq_printf(s, "\t\tThe used/reserved pages of HIF1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3682+ seq_printf(s, "\tReserved page counter of CPU group(0x82068150): 0x%08x\n", pg_flow_ctrl[6]);
3683+ seq_printf(s, "\tCPU group page status(0x82068154): 0x%08x\n", pg_flow_ctrl[7]);
3684+ min_q = FIELD_GET(MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
3685+ max_q = FIELD_GET(MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK, pg_flow_ctrl[6]);
3686+ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", max_q, min_q);
3687+ rsv_pg = FIELD_GET(MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK, pg_flow_ctrl[7]);
3688+ used_pg = FIELD_GET(MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK, pg_flow_ctrl[7]);
3689+ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3690+ seq_printf(s, "\tReserved page counter of LMAC0 group(0x82068170): 0x%08x\n", pg_flow_ctrl[8]);
3691+ seq_printf(s, "\tLMAC0 group page status(0x82068174): 0x%08x\n", pg_flow_ctrl[9]);
3692+ min_q = FIELD_GET(MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK, pg_flow_ctrl[8]);
3693+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK, pg_flow_ctrl[8]);
3694+ seq_printf(s, "\t\tThe max/min quota pages of LMAC0 group=0x%03x/0x%03x\n", max_q, min_q);
3695+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK, pg_flow_ctrl[9]);
3696+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK, pg_flow_ctrl[9]);
3697+ seq_printf(s, "\t\tThe used/reserved pages of LMAC0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3698+ seq_printf(s, "\tReserved page counter of LMAC1 group(0x82068178): 0x%08x\n", pg_flow_ctrl[10]);
3699+ seq_printf(s, "\tLMAC1 group page status(0x8206817c): 0x%08x\n", pg_flow_ctrl[11]);
3700+ min_q = FIELD_GET(MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK, pg_flow_ctrl[10]);
3701+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK, pg_flow_ctrl[10]);
3702+ seq_printf(s, "\t\tThe max/min quota pages of LMAC1 group=0x%03x/0x%03x\n", max_q, min_q);
3703+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK, pg_flow_ctrl[11]);
3704+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK, pg_flow_ctrl[11]);
3705+ seq_printf(s, "\t\tThe used/reserved pages of LMAC1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3706+ seq_printf(s, "\tReserved page counter of LMAC2 group(0x82068180): 0x%08x\n", pg_flow_ctrl[11]);
3707+ seq_printf(s, "\tLMAC2 group page status(0x82068184): 0x%08x\n", pg_flow_ctrl[12]);
3708+ min_q = FIELD_GET(MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK, pg_flow_ctrl[12]);
3709+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK, pg_flow_ctrl[12]);
3710+ seq_printf(s, "\t\tThe max/min quota pages of LMAC2 group=0x%03x/0x%03x\n", max_q, min_q);
3711+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK, pg_flow_ctrl[13]);
3712+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK, pg_flow_ctrl[13]);
3713+ seq_printf(s, "\t\tThe used/reserved pages of LMAC2 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3714+
3715+ seq_printf(s, "\tReserved page counter of LMAC3 group(0x82068188): 0x%08x\n", pg_flow_ctrl[16]);
3716+ seq_printf(s, "\tLMAC3 group page status(0x8206818c): 0x%08x\n", pg_flow_ctrl[17]);
3717+ min_q = FIELD_GET(MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK, pg_flow_ctrl[16]);
3718+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK, pg_flow_ctrl[16]);
3719+ seq_printf(s, "\t\tThe max/min quota pages of LMAC3 group=0x%03x/0x%03x\n", max_q, min_q);
3720+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK, pg_flow_ctrl[17]);
3721+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK, pg_flow_ctrl[17]);
3722+ seq_printf(s, "\t\tThe used/reserved pages of LMAC3 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3723+
3724+ seq_printf(s, "\tReserved page counter of PLE group(0x82068160): 0x%08x\n", pg_flow_ctrl[14]);
3725+ seq_printf(s, "\tPLE group page status(0x82068164): 0x%08x\n", pg_flow_ctrl[15]);
3726+ min_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK, pg_flow_ctrl[14]);
3727+ max_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK, pg_flow_ctrl[14]);
3728+ seq_printf(s, "\t\tThe max/min quota pages of PLE group=0x%03x/0x%03x\n", max_q, min_q);
3729+ rsv_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK, pg_flow_ctrl[15]);
3730+ used_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK, pg_flow_ctrl[15]);
3731+ seq_printf(s, "\t\tThe used/reserved pages of PLE group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3732+
3733+ seq_printf(s, "\tReserved page counter of PLE1 group(0x82068168): 0x%08x\n", pg_flow_ctrl[14]);
3734+ seq_printf(s, "\tPLE1 group page status(0x8206816c): 0x%08x\n", pg_flow_ctrl[15]);
3735+ min_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK, pg_flow_ctrl[20]);
3736+ max_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK, pg_flow_ctrl[20]);
3737+ seq_printf(s, "\t\tThe max/min quota pages of PLE1 group=0x%03x/0x%03x\n", max_q, min_q);
3738+ rsv_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK, pg_flow_ctrl[21]);
3739+ used_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK, pg_flow_ctrl[21]);
3740+ seq_printf(s, "\t\tThe used/reserved pages of PLE1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3741+
3742+ seq_printf(s, "\tReserved page counter of MDP group(0x82068198): 0x%08x\n", pg_flow_ctrl[18]);
3743+ seq_printf(s, "\tMDP group page status(0x8206819c): 0x%08x\n", pg_flow_ctrl[19]);
3744+ min_q = FIELD_GET(MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK, pg_flow_ctrl[18]);
3745+ max_q = FIELD_GET(MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK, pg_flow_ctrl[18]);
3746+ seq_printf(s, "\t\tThe max/min quota pages of MDP group=0x%03x/0x%03x\n", max_q, min_q);
3747+ rsv_pg = FIELD_GET(MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK, pg_flow_ctrl[19]);
3748+ used_pg = FIELD_GET(MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK, pg_flow_ctrl[19]);
3749+ seq_printf(s, "\t\tThe used/reserved pages of MDP group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3750+
3751+ /* Queue Empty Status */
3752+ seq_printf(s, "PSE Queue Empty Status:\n");
3753+ seq_printf(s, "\tQUEUE_EMPTY(0x820680b0): 0x%08x\n", pse_stat);
3754+ seq_printf(s, "\t\tCPU Q0/1/2/3 empty=%ld/%ld/%ld/%ld\n",
3755+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK, pse_stat),
3756+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK, pse_stat),
3757+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK, pse_stat),
3758+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK, pse_stat));
3759+
3760+ seq_printf(s, "\t\tHIF Q0/1/2/3/4/5 empty=%ld/%ld/%ld/%ld/%ld/%ld\n",
3761+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK, pse_stat),
3762+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK, pse_stat),
3763+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK, pse_stat),
3764+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK, pse_stat),
3765+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK, pse_stat),
3766+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK, pse_stat));
3767+
3768+ seq_printf(s, "\t\tLMAC TX Q empty=%ld\n",
3769+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK, pse_stat));
3770+ seq_printf(s, "\t\tMDP TX Q/RX Q empty=%ld/%ld\n",
3771+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK, pse_stat),
3772+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK, pse_stat));
3773+ seq_printf(s, "\t\tSEC TX Q/RX Q empty=%ld/%ld\n",
3774+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK, pse_stat),
3775+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT, pse_stat));
3776+ seq_printf(s, "\t\tSFD PARK Q empty=%ld\n",
3777+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK, pse_stat));
3778+ seq_printf(s, "\t\tMDP TXIOC Q/RXIOC Q empty=%ld/%ld\n",
3779+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK, pse_stat),
3780+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK, pse_stat));
3781+ seq_printf(s, "\t\tRLS Q empty=%ld\n",
3782+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK, pse_stat));
3783+ seq_printf(s, "Nonempty Q info:\n");
3784+
3785+ for (i = 0; i < 31; i++) {
3786+ if (((pse_stat & (0x1 << i)) >> i) == 0) {
3787+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3788+
3789+ if (pse_queue_empty_info[i].QueueName != NULL) {
3790+ seq_printf(s, "\t%s: ", pse_queue_empty_info[i].QueueName);
3791+ fl_que_ctrl[0] |= MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK;
3792+ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Portid << MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT);
3793+ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Queueid << MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT);
3794+ } else
3795+ continue;
3796+
3797+ fl_que_ctrl[0] |= (0x1 << 31);
3798+
3799+ mt76_wr(dev, MT_DBG_PSE_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]);
3800+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PSE_FL_QUE_CTRL_2_ADDR);
3801+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PSE_FL_QUE_CTRL_3_ADDR);
3802+
3803+ hfid = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK, fl_que_ctrl[1]);
3804+ tfid = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK, fl_que_ctrl[1]);
3805+ pktcnt = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK, fl_que_ctrl[2]);
3806+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3807+ tfid, hfid, pktcnt);
3808+ }
3809+ }
3810+
3811+ return 0;
3812+}
3813+
3814+static int mt7915_mibinfo_read_per_band(struct seq_file *s, int band_idx)
3815+{
3816+#define BSS_NUM 4
3817+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3818+ u32 mac_val0, mac_val, mac_val1, idx, band_offset = 0;
3819+ u32 msdr6, msdr7, msdr8, msdr9, msdr10, msdr16, msdr17, msdr18, msdr19, msdr20, msdr21;
3820+ u32 mbxsdr[BSS_NUM][7];
3821+ u32 mbtcr[16], mbtbcr[16], mbrcr[16], mbrbcr[16];
3822+ u32 btcr[BSS_NUM], btbcr[BSS_NUM], brcr[BSS_NUM], brbcr[BSS_NUM], btdcr[BSS_NUM], brdcr[BSS_NUM];
3823+ u32 mu_cnt[5];
3824+ u32 ampdu_cnt[3];
3825+ unsigned long per;
3826+
3827+ seq_printf(s, "Band %d MIB Status\n", band_idx);
3828+ seq_printf(s, "===============================\n");
3829+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SCR0(band_idx));
3830+ seq_printf(s, "MIB Status Control=0x%x\n", mac_val);
3831+ if (is_mt7915(&dev->mt76)) {
3832+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0PBSCR(band_idx));
3833+ seq_printf(s, "MIB Per-BSS Status Control=0x%x\n", mac_val);
3834+ }
3835+
3836+ msdr6 = mt76_rr(dev, MT_DBG_MIB_M0SDR6(band_idx));
3837+ msdr7 = mt76_rr(dev, MT_DBG_MIB_M0SDR7(band_idx));
3838+ msdr8 = mt76_rr(dev, MT_DBG_MIB_M0SDR8(band_idx));
3839+ msdr9 = mt76_rr(dev, MT_DBG_MIB_M0SDR9(band_idx));
3840+ msdr10 = mt76_rr(dev, MT_DBG_MIB_M0SDR10(band_idx));
3841+ msdr16 = mt76_rr(dev, MT_DBG_MIB_M0SDR16(band_idx));
3842+ msdr17 = mt76_rr(dev, MT_DBG_MIB_M0SDR17(band_idx));
3843+ msdr18 = mt76_rr(dev, MT_DBG_MIB_M0SDR18(band_idx));
3844+ msdr19 = mt76_rr(dev, MT_DBG_MIB_M0SDR19(band_idx));
3845+ msdr20 = mt76_rr(dev, MT_DBG_MIB_M0SDR20(band_idx));
3846+ msdr21 = mt76_rr(dev, MT_DBG_MIB_M0SDR21(band_idx));
3847+ ampdu_cnt[0] = mt76_rr(dev, MT_DBG_MIB_M0SDR12(band_idx));
3848+ ampdu_cnt[1] = mt76_rr(dev, MT_DBG_MIB_M0SDR14(band_idx));
3849+ ampdu_cnt[2] = mt76_rr(dev, MT_DBG_MIB_M0SDR15(band_idx));
3850+ ampdu_cnt[1] &= MT_DBG_MIB_M0SDR14_AMPDU_MASK;
3851+ ampdu_cnt[2] &= MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK;
3852+
3853+ seq_printf(s, "===Phy/Timing Related Counters===\n");
3854+ seq_printf(s, "\tChannelIdleCnt=0x%x\n", msdr6 & BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK);
3855+ seq_printf(s, "\tCCA_NAV_Tx_Time=0x%x\n", msdr9 & BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK);
3856+ seq_printf(s, "\tRx_MDRDY_CNT=0x%lx\n", msdr10 & MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK);
3857+ seq_printf(s, "\tCCK_MDRDY_TIME=0x%x, OFDM_MDRDY_TIME=0x%x, OFDM_GREEN_MDRDY_TIME=0x%x\n",
3858+ msdr19 & BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK,
3859+ msdr20 & BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK,
3860+ msdr21 & BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK);
3861+ seq_printf(s, "\tPrim CCA Time=0x%x\n", msdr16 & BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK);
3862+ seq_printf(s, "\tSec CCA Time=0x%x\n", msdr17 & BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK);
3863+ seq_printf(s, "\tPrim ED Time=0x%x\n", msdr18 & BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK);
3864+
3865+ seq_printf(s, "===Tx Related Counters(Generic)===\n");
3866+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR0(band_idx));
3867+ dev->dbg.bcn_total_cnt[band_idx] += (mac_val & BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK);
3868+ seq_printf(s, "\tBeaconTxCnt=0x%x\n",dev->dbg.bcn_total_cnt[band_idx]);
3869+ dev->dbg.bcn_total_cnt[band_idx] = 0;
3870+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR0(band_idx));
3871+ seq_printf(s, "\tTx 20MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK);
3872+ seq_printf(s, "\tTx 40MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT);
3873+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR1(band_idx));
3874+ seq_printf(s, "\tTx 80MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK);
3875+ seq_printf(s, "\tTx 160MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT);
3876+ seq_printf(s, "\tAMPDU Cnt=0x%x\n", ampdu_cnt[0]);
3877+ seq_printf(s, "\tAMPDU MPDU Cnt=0x%x\n", ampdu_cnt[1]);
3878+ seq_printf(s, "\tAMPDU MPDU Ack Cnt=0x%x\n", ampdu_cnt[2]);
3879+ per = (ampdu_cnt[2] == 0 ? 0 : 1000 * (ampdu_cnt[1] - ampdu_cnt[2]) / ampdu_cnt[1]);
3880+ seq_printf(s, "\tAMPDU MPDU PER=%ld.%1ld%%\n", per / 10, per % 10);
3881+
3882+ seq_printf(s, "===MU Related Counters===\n");
3883+ mu_cnt[0] = mt76_rr(dev, MT_DBG_MIB_MUBF(band_idx));
3884+ mu_cnt[1] = mt76_rr(dev, MT_DBG_MIB_M0DR8(band_idx));
3885+ mu_cnt[2] = mt76_rr(dev, MT_DBG_MIB_M0DR9(band_idx));
3886+ mu_cnt[3] = mt76_rr(dev, MT_DBG_MIB_M0DR10(band_idx));
3887+ mu_cnt[4] = mt76_rr(dev, MT_DBG_MIB_M0DR11(band_idx));
3888+ seq_printf(s, "\tMUBF_TX_COUNT=0x%x\n", mu_cnt[0] & BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK);
3889+ seq_printf(s, "\tMU_TX_MPDU_COUNT(Ok+Fail)=0x%x\n", mu_cnt[1]);
3890+ seq_printf(s, "\tMU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[2]);
3891+ seq_printf(s, "\tMU_TO_SU_PPDU_COUNT=0x%x\n", mu_cnt[3] & BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK);
3892+ seq_printf(s, "\tSU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[4]);
3893+
3894+ seq_printf(s, "===Rx Related Counters(Generic)===\n");
3895+ seq_printf(s, "\tVector Mismacth Cnt=0x%x\n", msdr7 & BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK);
3896+ seq_printf(s, "\tDelimiter Fail Cnt=0x%x\n", msdr8 & BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK);
3897+
3898+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR3(band_idx));
3899+ seq_printf(s, "\tRxFCSErrCnt=0x%lx\n", __DBG_FIELD_GET(DBG_MIB_RX_FCS_ERROR_COUNT, mac_val));
3900+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR4(band_idx));
3901+ seq_printf(s, "\tRxFifoFullCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK));
3902+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR11(band_idx));
3903+ seq_printf(s, "\tRxLenMismatch=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK));
3904+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR5(band_idx));
3905+ seq_printf(s, "\tRxMPDUCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK));
3906+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR22(band_idx));
3907+ seq_printf(s, "\tRx AMPDU Cnt=0x%x\n", mac_val);
3908+ /* TODO: shiang-MT7615, is MIB_M0SDR23 used for Rx total byte count for all or just AMPDU only??? */
3909+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR23(band_idx));
3910+ seq_printf(s, "\tRx Total ByteCnt=0x%x\n", mac_val);
3911+
3912+ if (is_mt7915(&dev->mt76)) {
3913+ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;//check
3914+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3915+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
3916+
3917+ for (idx = 0; idx < BSS_NUM; idx++) {
3918+ btcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTCRn_ADDR + band_offset + idx * 4);
3919+ btbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTBCRn_ADDR + band_offset + idx * 4);
3920+ brcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRCRn_ADDR + band_offset + idx * 4);
3921+ brbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRBCRn_ADDR + band_offset + idx * 4);
3922+ btdcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTDCRn_ADDR + band_offset + idx * 4);
3923+ brdcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRDCRn_ADDR + band_offset + idx * 4);
3924+ }
3925+
3926+ for (idx = 0; idx < BSS_NUM; idx++) {
3927+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3928+ idx, btcr[idx], btdcr[idx], btbcr[idx],
3929+ brcr[idx], brdcr[idx], brbcr[idx]);
3930+ }
3931+
3932+ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
3933+ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
3934+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3935+
3936+ for (idx = 0; idx < BSS_NUM; idx++) {
3937+ mbxsdr[idx][0] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR0_ADDR + band_offset + idx * 0x10);
3938+ mbxsdr[idx][1] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR1_ADDR + band_offset + idx * 0x10);
3939+ mbxsdr[idx][2] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR2_ADDR + band_offset + idx * 0x10);
3940+ mbxsdr[idx][3] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR3_ADDR + band_offset + idx * 0x10);
3941+ }
3942+
3943+ for (idx = 0; idx < BSS_NUM; idx++) {
3944+ seq_printf(s, "%d:\t0x%08x/0x%08x 0x%08x \t 0x%08x \t 0x%08x/0x%08x/0x%08x\n",
3945+ idx, (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK),
3946+ (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT,
3947+ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK),
3948+ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT,
3949+ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK),
3950+ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT,
3951+ (mbxsdr[idx][3] & BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK));
3952+ }
3953+
3954+ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;
3955+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3956+ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
3957+
3958+ for (idx = 0; idx < 16; idx++) {
3959+ mbtcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBTCRn_ADDR + band_offset + idx * 4);
3960+ mbtbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBTBCRn_ADDR + band_offset + idx * 4);
3961+ mbrcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBRCRn_ADDR + band_offset + idx * 4);
3962+ mbrbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBRBCRn_ADDR + band_offset + idx * 4);
3963+ }
3964+
3965+ for (idx = 0; idx < 16; idx++) {
3966+ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
3967+ idx, mbtcr[idx], mbtbcr[idx], mbrcr[idx], mbrbcr[idx]);
3968+ }
3969+ return 0;
3970+ } else {
3971+ u32 btocr[BSS_NUM], mbtocr[16],mbrocr[16], brocr[BSS_NUM];
3972+ u8 bss_nums = BSS_NUM;
3973+
3974+ band_offset = (BN1_WF_MIB_TOP_BTOCR_ADDR - BN0_WF_MIB_TOP_BTOCR_ADDR) * band_idx;
3975+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3976+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
3977+
3978+ for (idx = 0; idx < BSS_NUM; idx++) {
3979+ btocr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (idx >> 1) * 4));
3980+ btdcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTDCR_ADDR + band_offset + (idx >> 1) * 4));
3981+ btbcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (idx * 4)));
3982+ brocr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BROCR_ADDR + band_offset + (idx >> 1) * 4));
3983+ brdcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BRDCR_ADDR + band_offset + (idx >> 1) * 4));
3984+ brbcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BRBCR_ADDR + band_offset + (idx * 4)));
3985+
3986+ if ((idx % 2) == 0) {
3987+ btocr[idx] = ((btocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT);
3988+ btdcr[idx] = ((btdcr[idx] & BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT);
3989+ brocr[idx] = ((brocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT);
3990+ brdcr[idx] = ((brdcr[idx] & BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT);
3991+ } else {
3992+ btocr[idx] = ((btocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT);
3993+ btdcr[idx] = ((btdcr[idx] & BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT);
3994+ brocr[idx] = ((brocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT);
3995+ brdcr[idx] = ((brdcr[idx] & BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT);
3996+ }
3997+ }
3998+
3999+ for (idx = 0; idx < BSS_NUM; idx++) {
4000+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
4001+ idx, btocr[idx], btdcr[idx], btbcr[idx], brocr[idx], brdcr[idx], brbcr[idx]);
4002+ }
4003+
4004+ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
4005+ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
4006+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
4007+
4008+ for (idx = 0; idx < BSS_NUM; idx++) {
4009+ mbxsdr[idx][0] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR0_ADDR + band_offset + ((idx >> 1) * 4));
4010+ mbxsdr[idx][1] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR1_ADDR + band_offset + ((idx >> 1) * 4));
4011+ mbxsdr[idx][2] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR2_ADDR + band_offset + ((idx >> 1) * 4));
4012+ mbxsdr[idx][3] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR3_ADDR + band_offset + ((idx >> 1) * 4));
4013+ mbxsdr[idx][4] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR4_ADDR + band_offset + ((idx >> 1) * 4));
4014+ mbxsdr[idx][5] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR5_ADDR + band_offset + ((idx >> 1) * 4));
4015+ mbxsdr[idx][6] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR6_ADDR + band_offset + ((idx >> 1) * 4));
4016+
4017+ if ((idx % 2) == 0) {
4018+ mbxsdr[idx][0] = ((mbxsdr[idx][0] & BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT);
4019+ mbxsdr[idx][1] = ((mbxsdr[idx][1] & BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT);
4020+ mbxsdr[idx][2] = ((mbxsdr[idx][2] & BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT);
4021+ mbxsdr[idx][3] = ((mbxsdr[idx][3] & BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT);
4022+ mbxsdr[idx][4] = ((mbxsdr[idx][4] & BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT);
4023+ mbxsdr[idx][5] = ((mbxsdr[idx][5] & BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT);
4024+ mbxsdr[idx][6] = ((mbxsdr[idx][6] & BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT);
4025+ } else {
4026+ mbxsdr[idx][0] = ((mbxsdr[idx][0] & BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT);
4027+ mbxsdr[idx][1] = ((mbxsdr[idx][1] & BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT);
4028+ mbxsdr[idx][2] = ((mbxsdr[idx][2] & BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT);
4029+ mbxsdr[idx][3] = ((mbxsdr[idx][3] & BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT);
4030+ mbxsdr[idx][4] = ((mbxsdr[idx][4] & BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT);
4031+ mbxsdr[idx][5] = ((mbxsdr[idx][5] & BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT);
4032+ mbxsdr[idx][6] = ((mbxsdr[idx][6] & BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT);
4033+ }
4034+ }
4035+
4036+ for (idx = 0; idx < BSS_NUM; idx++) {
4037+ seq_printf(s, "%d:\t0x%x/0x%x 0x%x \t 0x%x \t 0x%x/0x%x/0x%x\n",
4038+ idx,
4039+ mbxsdr[idx][0], mbxsdr[idx][1], mbxsdr[idx][2], mbxsdr[idx][3],
4040+ mbxsdr[idx][4], mbxsdr[idx][5], mbxsdr[idx][6]);
4041+ }
4042+
4043+ band_offset = (BN1_WF_MIB_TOP_BTOCR_ADDR - BN0_WF_MIB_TOP_BTOCR_ADDR) * band_idx;
4044+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
4045+ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
4046+
4047+ for (idx = 0; idx < 16; idx++) {
4048+ mbtocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + ((idx >> 1) * 4)));
4049+ mbtbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + (idx * 4)));
4050+ mbrocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BROCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + ((idx >> 1) * 4)));
4051+ mbrbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BRBCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + (idx * 4)));
4052+
4053+ if ((idx % 2) == 0) {
4054+ mbtocr[idx] = ((mbtocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT);
4055+ mbrocr[idx] = ((mbrocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT);
4056+ } else {
4057+ mbtocr[idx] = ((mbtocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT);
4058+ mbrocr[idx] = ((mbrocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT);
4059+ }
4060+ }
4061+
4062+ for (idx = 0; idx < 16; idx++) {
4063+ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
4064+ idx, mbtocr[idx], mbtbcr[idx], mbrocr[idx], mbrbcr[idx]);
4065+ }
4066+ }
4067+
4068+ seq_printf(s, "===Dummy delimiter insertion result===\n");
4069+ mac_val0 = mt76_rr(dev, MT_DBG_MIB_M0DR11(band_idx));
4070+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR6(band_idx));
4071+ mac_val1 = mt76_rr(dev, MT_DBG_MIB_M0DR7(band_idx));
4072+ seq_printf(s, "Range0 = %d\t Range1 = %d\t Range2 = %d\t Range3 = %d\t Range4 = %d\n",
4073+ (mac_val0 & BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK),
4074+ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK),
4075+ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT,
4076+ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK),
4077+ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT);
4078+
4079+ return 0;
4080+}
4081+
4082+static int mt7915_mibinfo_band0(struct seq_file *s, void *data)
4083+{
4084+ mt7915_mibinfo_read_per_band(s, 0);
4085+ return 0;
4086+}
4087+
4088+static int mt7915_mibinfo_band1(struct seq_file *s, void *data)
4089+{
4090+ mt7915_mibinfo_read_per_band(s, 1);
4091+ return 0;
4092+}
4093+
4094+static int mt7915_token_read(struct seq_file *s, void *data)
4095+{
4096+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4097+ int id, count = 0;
4098+ struct mt76_txwi_cache *txwi;
4099+
4100+ seq_printf(s, "Cut through token:\n");
4101+ spin_lock_bh(&dev->mt76.token_lock);
4102+ idr_for_each_entry(&dev->mt76.token, txwi, id) {
4103+ seq_printf(s, "%4d ", id);
4104+ count++;
4105+ if (count % 8 == 0)
4106+ seq_printf(s, "\n");
4107+ }
4108+ spin_unlock_bh(&dev->mt76.token_lock);
4109+ seq_printf(s, "\n");
4110+
4111+ return 0;
4112+}
4113+
4114+struct txd_l {
4115+ u32 txd_0;
4116+ u32 txd_1;
4117+ u32 txd_2;
4118+ u32 txd_3;
4119+ u32 txd_4;
4120+ u32 txd_5;
4121+ u32 txd_6;
4122+ u32 txd_7;
4123+} __packed;
4124+
4125+char *pkt_ft_str[] = {"cut_through", "store_forward", "cmd", "PDA_FW_Download"};
4126+char *hdr_fmt_str[] = {
4127+ "Non-80211-Frame",
4128+ "Command-Frame",
4129+ "Normal-80211-Frame",
4130+ "enhanced-80211-Frame",
4131+};
4132+/* TMAC_TXD_1.hdr_format */
4133+#define TMI_HDR_FT_NON_80211 0x0
4134+#define TMI_HDR_FT_CMD 0x1
4135+#define TMI_HDR_FT_NOR_80211 0x2
4136+#define TMI_HDR_FT_ENH_80211 0x3
4137+
4138+void mt7915_dump_tmac_info(u8 *tmac_info)
4139+{
4140+ struct txd_l *txd = (struct txd_l *)tmac_info;
4141+
4142+ printk("txd raw data: size=%d\n", MT_TXD_SIZE);
4143+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, tmac_info, MT_TXD_SIZE, false);
4144+
4145+ printk("TMAC_TXD Fields:\n");
4146+ printk("\tTMAC_TXD_0:\n");
4147+
4148+ /* DW0 */
4149+ /* TX Byte Count [15:0] */
4150+ printk("\t\tTxByteCnt = %ld\n", FIELD_GET(MT_TXD0_TX_BYTES, txd->txd_0));
4151+
4152+ /* PKT_FT: Packet Format [24:23] */
4153+ printk("\t\tpkt_ft = %ld(%s)\n",
4154+ FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0),
4155+ pkt_ft_str[FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0)]);
4156+
4157+ /* Q_IDX [31:25] */
4158+ printk("\t\tQueID =0x%lx\n", FIELD_GET(MT_TXD0_Q_IDX, txd->txd_0));
4159+
4160+ printk("\tTMAC_TXD_1:\n");
4161+
4162+ /* DW1 */
4163+ /* WLAN Indec [9:0] */
4164+ printk("\t\tWlan Index = %ld\n", FIELD_GET(MT_TXD1_WLAN_IDX, txd->txd_1));
4165+
4166+ /* VTA [10] */
4167+ printk("\t\tVTA = %d\n", ((txd->txd_1 & MT_TXD1_VTA) ? 1 : 0));
4168+
4169+ /* HF: Header Format [17:16] */
4170+ printk("\t\tHdrFmt = %ld(%s)\n",
4171+ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1),
4172+ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1) < 4 ?
4173+ hdr_fmt_str[FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)] : "N/A");
4174+
4175+ switch (FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)) {
4176+ case TMI_HDR_FT_NON_80211:
4177+ /* MRD [11], EOSP [12], RMVL [13], VLAN [14], ETYPE [15] */
4178+ printk("\t\t\tMRD = %d, EOSP = %d,\
4179+ RMVL = %d, VLAN = %d, ETYP = %d\n",
4180+ (txd->txd_1 & MT_TXD1_MRD) ? 1 : 0,
4181+ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
4182+ (txd->txd_1 & MT_TXD1_RMVL) ? 1 : 0,
4183+ (txd->txd_1 & MT_TXD1_VLAN) ? 1 : 0,
4184+ (txd->txd_1 & MT_TXD1_ETYP) ? 1 : 0);
4185+ break;
4186+ case TMI_HDR_FT_NOR_80211:
4187+ /* HEADER_LENGTH [15:11] */
4188+ printk("\t\t\tHeader Len = %ld(WORD)\n", FIELD_GET(MT_TXD1_HDR_INFO, txd->txd_1));
4189+ break;
4190+
4191+ case TMI_HDR_FT_ENH_80211:
4192+ /* EOSP [12], AMS [13] */
4193+ printk("\t\t\tEOSP = %d, AMS = %d\n",
4194+ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
4195+ (txd->txd_1 & MT_TXD1_AMS) ? 1 : 0);
4196+ break;
4197+ }
4198+
4199+ /* Header Padding [19:18] */
4200+ printk("\t\tHdrPad = %ld\n", FIELD_GET(MT_TXD1_HDR_PAD, txd->txd_1));
4201+
4202+ /* TID [22:20] */
4203+ printk("\t\tTID = %ld\n", FIELD_GET(MT_TXD1_TID, txd->txd_1));
4204+
4205+
4206+ /* UtxB/AMSDU_C/AMSDU [23] */
4207+ printk("\t\tamsdu = %d\n", ((txd->txd_1 & MT_TXD1_AMSDU) ? 1 : 0));
4208+
4209+ /* OM [29:24] */
4210+ printk("\t\town_mac = %ld\n", FIELD_GET(MT_TXD1_OWN_MAC, txd->txd_1));
4211+
4212+
4213+ /* TGID [30] */
4214+ printk("\t\tTGID = %d\n", ((txd->txd_1 & MT_TXD1_TGID) ? 1 : 0));
4215+
4216+
4217+ /* FT [31] */
4218+ printk("\t\tTxDFormatType = %d\n", (txd->txd_1 & MT_TXD1_LONG_FORMAT) ? 1 : 0);
4219+
4220+ printk("\tTMAC_TXD_2:\n");
4221+ /* DW2 */
4222+ /* Subtype [3:0] */
4223+ printk("\t\tsub_type = %ld\n", FIELD_GET(MT_TXD2_SUB_TYPE, txd->txd_2));
4224+
4225+ /* Type[5:4] */
4226+ printk("\t\tfrm_type = %ld\n", FIELD_GET(MT_TXD2_FRAME_TYPE, txd->txd_2));
4227+
4228+ /* NDP [6] */
4229+ printk("\t\tNDP = %d\n", ((txd->txd_2 & MT_TXD2_NDP) ? 1 : 0));
4230+
4231+ /* NDPA [7] */
4232+ printk("\t\tNDPA = %d\n", ((txd->txd_2 & MT_TXD2_NDPA) ? 1 : 0));
4233+
4234+ /* SD [8] */
4235+ printk("\t\tSounding = %d\n", ((txd->txd_2 & MT_TXD2_SOUNDING) ? 1 : 0));
4236+
4237+ /* RTS [9] */
4238+ printk("\t\tRTS = %d\n", ((txd->txd_2 & MT_TXD2_RTS) ? 1 : 0));
4239+
4240+ /* BM [10] */
4241+ printk("\t\tbc_mc_pkt = %d\n", ((txd->txd_2 & MT_TXD2_MULTICAST) ? 1 : 0));
4242+
4243+ /* B [11] */
4244+ printk("\t\tBIP = %d\n", ((txd->txd_2 & MT_TXD2_BIP) ? 1 : 0));
4245+
4246+ /* DU [12] */
4247+ printk("\t\tDuration = %d\n", ((txd->txd_2 & MT_TXD2_DURATION) ? 1 : 0));
4248+
4249+ /* HE [13] */
4250+ printk("\t\tHE(HTC Exist) = %d\n", ((txd->txd_2 & MT_TXD2_HTC_VLD) ? 1 : 0));
4251+
4252+ /* FRAG [15:14] */
4253+ printk("\t\tFRAG = %ld\n", FIELD_GET(MT_TXD2_FRAG, txd->txd_2));
4254+
4255+
4256+ /* Remaining Life Time [23:16]*/
4257+ printk("\t\tReamingLife/MaxTx time = %ld (unit: 64TU)\n",
4258+ FIELD_GET(MT_TXD2_MAX_TX_TIME, txd->txd_2));
4259+
4260+ /* Power Offset [29:24] */
4261+ printk("\t\tpwr_offset = %ld\n", FIELD_GET(MT_TXD2_POWER_OFFSET, txd->txd_2));
4262+
4263+ /* FRM [30] */
4264+ printk("\t\tfix rate mode = %d\n", (txd->txd_2 & MT_TXD2_FIXED_RATE) ? 1 : 0);
4265+
4266+ /* FR[31] */
4267+ printk("\t\tfix rate = %d\n", (txd->txd_2 & MT_TXD2_FIX_RATE) ? 1 : 0);
4268+
4269+
4270+ printk("\tTMAC_TXD_3:\n");
4271+
4272+ /* DW3 */
4273+ /* NA [0] */
4274+ printk("\t\tNoAck = %d\n", (txd->txd_3 & MT_TXD3_NO_ACK) ? 1 : 0);
4275+
4276+ /* PF [1] */
4277+ printk("\t\tPF = %d\n", (txd->txd_3 & MT_TXD3_PROTECT_FRAME) ? 1 : 0);
4278+
4279+ /* EMRD [2] */
4280+ printk("\t\tEMRD = %d\n", (txd->txd_3 & MT_TXD3_EMRD) ? 1 : 0);
4281+
4282+ /* EEOSP [3] */
4283+ printk("\t\tEEOSP = %d\n", (txd->txd_3 & MT_TXD3_EEOSP) ? 1 : 0);
4284+
4285+ /* DAS [4] */
4286+ printk("\t\tda_select = %d\n", (txd->txd_3 & MT_TXD3_DAS) ? 1 : 0);
4287+
4288+ /* TM [5] */
4289+ printk("\t\ttm = %d\n", (txd->txd_3 & MT_TXD3_TIMING_MEASURE) ? 1 : 0);
4290+
4291+ /* TX Count [10:6] */
4292+ printk("\t\ttx_cnt = %ld\n", FIELD_GET(MT_TXD3_TX_COUNT, txd->txd_3));
4293+
4294+ /* Remaining TX Count [15:11] */
4295+ printk("\t\tremain_tx_cnt = %ld\n", FIELD_GET(MT_TXD3_REM_TX_COUNT, txd->txd_3));
4296+
4297+ /* SN [27:16] */
4298+ printk("\t\tsn = %ld\n", FIELD_GET(MT_TXD3_SEQ, txd->txd_3));
4299+
4300+ /* BA_DIS [28] */
4301+ printk("\t\tba dis = %d\n", (txd->txd_3 & MT_TXD3_BA_DISABLE) ? 1 : 0);
4302+
4303+ /* Power Management [29] */
4304+ printk("\t\tpwr_mgmt = 0x%x\n", (txd->txd_3 & MT_TXD3_SW_POWER_MGMT) ? 1 : 0);
4305+
4306+ /* PN_VLD [30] */
4307+ printk("\t\tpn_vld = %d\n", (txd->txd_3 & MT_TXD3_PN_VALID) ? 1 : 0);
4308+
4309+ /* SN_VLD [31] */
4310+ printk("\t\tsn_vld = %d\n", (txd->txd_3 & MT_TXD3_SN_VALID) ? 1 : 0);
4311+
4312+
4313+ /* DW4 */
4314+ printk("\tTMAC_TXD_4:\n");
4315+
4316+ /* PN_LOW [31:0] */
4317+ printk("\t\tpn_low = 0x%lx\n", FIELD_GET(MT_TXD4_PN_LOW, txd->txd_4));
4318+
4319+
4320+ /* DW5 */
4321+ printk("\tTMAC_TXD_5:\n");
4322+
4323+ /* PID [7:0] */
4324+ printk("\t\tpid = %ld\n", FIELD_GET(MT_TXD5_PID, txd->txd_5));
4325+
4326+ /* TXSFM [8] */
4327+ printk("\t\ttx_status_fmt = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_FMT) ? 1 : 0);
4328+
4329+ /* TXS2M [9] */
4330+ printk("\t\ttx_status_2_mcu = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_MCU) ? 1 : 0);
4331+
4332+ /* TXS2H [10] */
4333+ printk("\t\ttx_status_2_host = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_HOST) ? 1 : 0);
4334+
4335+ /* ADD_BA [14] */
4336+ printk("\t\tADD_BA = %d\n", (txd->txd_5 & MT_TXD5_ADD_BA) ? 1 : 0);
4337+
4338+ /* MD [15] */
4339+ printk("\t\tMD = %d\n", (txd->txd_5 & MT_TXD5_MD) ? 1 : 0);
4340+
4341+ /* PN_HIGH [31:16] */
4342+ printk("\t\tpn_high = 0x%lx\n", FIELD_GET(MT_TXD5_PN_HIGH, txd->txd_5));
4343+
4344+ /* DW6 */
4345+ printk("\tTMAC_TXD_6:\n");
4346+
4347+ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4348+ /* Fixed BandWidth mode [2:0] */
developer2aa1e642022-12-19 11:33:22 +08004349+ printk("\t\tbw = %ld\n",
4350+ FIELD_GET(MT_TXD6_BW, txd->txd_6) | (txd->txd_6 & MT_TXD6_FIXED_BW));
developer3fa816c2022-04-19 10:21:20 +08004351+
4352+ /* DYN_BW [3] */
4353+ printk("\t\tdyn_bw = %d\n", (txd->txd_6 & MT_TXD6_DYN_BW) ? 1 : 0);
4354+
4355+ /* ANT_ID [7:4] */
4356+ printk("\t\tant_id = %ld\n", FIELD_GET(MT_TXD6_ANT_ID, txd->txd_6));
4357+
4358+ /* SPE_IDX_SEL [10] */
4359+ printk("\t\tspe_idx_sel = %d\n", (txd->txd_6 & MT_TXD6_SPE_ID_IDX) ? 1 : 0);
4360+
4361+ /* LDPC [11] */
4362+ printk("\t\tldpc = %d\n", (txd->txd_6 & MT_TXD6_LDPC) ? 1 : 0);
4363+
4364+ /* HELTF Type[13:12] */
4365+ printk("\t\tHELTF Type = %ld\n", FIELD_GET(MT_TXD6_HELTF, txd->txd_6));
4366+
4367+ /* GI Type [15:14] */
4368+ printk("\t\tGI = %ld\n", FIELD_GET(MT_TXD6_SGI, txd->txd_6));
4369+
4370+ /* Rate to be Fixed [29:16] */
4371+ printk("\t\ttx_rate = 0x%lx\n", FIELD_GET(MT_TXD6_TX_RATE, txd->txd_6));
4372+ }
4373+
4374+ /* TXEBF [30] */
4375+ printk("\t\ttxebf = %d\n", (txd->txd_6 & MT_TXD6_TX_EBF) ? 1 : 0);
4376+
4377+ /* TXIBF [31] */
4378+ printk("\t\ttxibf = %d\n", (txd->txd_6 & MT_TXD6_TX_IBF) ? 1 : 0);
4379+
4380+ /* DW7 */
4381+ printk("\tTMAC_TXD_7:\n");
4382+
4383+ if ((txd->txd_1 & MT_TXD1_VTA) == 0) {
4384+ /* SW Tx Time [9:0] */
4385+ printk("\t\tsw_tx_time = %ld\n", FIELD_GET(MT_TXD7_TX_TIME, txd->txd_7));
4386+ } else {
4387+ /* TXD Arrival Time [9:0] */
4388+ printk("\t\tat = %ld\n", FIELD_GET(MT_TXD7_TAT, txd->txd_7));
4389+ }
4390+
4391+ /* HW_AMSDU_CAP [10] */
4392+ printk("\t\thw amsdu cap = %d\n",(txd->txd_7 & MT_TXD7_HW_AMSDU) ? 1 : 0);
4393+
4394+ /* SPE_IDX [15:11] */
4395+ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4396+ printk("\t\tspe_idx = 0x%lx\n", FIELD_GET(MT_TXD7_SPE_IDX, txd->txd_7));
4397+ }
4398+
4399+ /* PSE_FID [27:16] */
4400+ printk("\t\tpse_fid = 0x%lx\n", FIELD_GET(MT_TXD7_PSE_FID, txd->txd_7));
4401+
4402+ /* Subtype [19:16] */
4403+ printk("\t\tpp_sub_type=%ld\n", FIELD_GET(MT_TXD7_SUB_TYPE, txd->txd_7));
4404+
4405+ /* Type [21:20] */
4406+ printk("\t\tpp_type=%ld\n", FIELD_GET(MT_TXD7_TYPE, txd->txd_7));
4407+
4408+ /* CTXD_CNT [25:23] */
4409+ printk("\t\tctxd cnt=0x%lx\n", FIELD_GET(MT_TXD7_CTXD_CNT, txd->txd_7));
4410+
4411+ /* CTXD [26] */
4412+ printk("\t\tctxd = %d\n", (txd->txd_7 & MT_TXD7_CTXD) ? 1 : 0);
4413+
4414+ /* I [28] */
4415+ printk("\t\ti = %d\n", (txd->txd_7 & MT_TXD7_IP_SUM) ? 1 : 0);
4416+
4417+ /* UT [29] */
4418+ printk("\t\tUT = %d\n", (txd->txd_7 & MT_TXD7_UDP_TCP_SUM) ? 1 : 0);
4419+
4420+ /* TXDLEN [31:30] */
4421+ printk("\t\t txd len= %ld\n", FIELD_GET(MT_TXD7_TXD_LEN, txd->txd_7));
4422+}
4423+
4424+
4425+static int mt7915_token_txd_read(struct seq_file *s, void *data)
4426+{
4427+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4428+ struct mt76_txwi_cache *t;
4429+ u8* txwi;
4430+
4431+ seq_printf(s, "\n");
4432+ spin_lock_bh(&dev->mt76.token_lock);
4433+
4434+ t = idr_find(&dev->mt76.token, dev->dbg.token_idx);
4435+
developer3fa816c2022-04-19 10:21:20 +08004436+ if (t != NULL) {
4437+ struct mt76_dev *mdev = &dev->mt76;
4438+ txwi = ((u8*)(t)) - (mdev->drv->txwi_size);
4439+ mt7915_dump_tmac_info((u8*) txwi);
4440+ seq_printf(s, "\n");
4441+ printk("[SKB]\n");
4442+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)t->skb->data, t->skb->len, false);
4443+ seq_printf(s, "\n");
4444+ }
developerdfb50982023-09-11 13:34:36 +08004445+ spin_unlock_bh(&dev->mt76.token_lock);
developer3fa816c2022-04-19 10:21:20 +08004446+ return 0;
4447+}
4448+
4449+static int mt7915_amsduinfo_read(struct seq_file *s, void *data)
4450+{
4451+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4452+ u32 ple_stat[8] = {0}, total_amsdu = 0;
4453+ u8 i;
4454+
4455+ for (i = 0; i < 8; i++)
4456+ ple_stat[i] = mt76_rr(dev, MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(i));
4457+
4458+ seq_printf(s, "TXD counter status of MSDU:\n");
4459+
4460+ for (i = 0; i < 8; i++)
4461+ total_amsdu += ple_stat[i];
4462+
4463+ for (i = 0; i < 8; i++) {
4464+ seq_printf(s, "AMSDU pack count of %d MSDU in TXD: 0x%x ", i + 1, ple_stat[i]);
4465+ if (total_amsdu != 0)
4466+ seq_printf(s, "(%d%%)\n", ple_stat[i] * 100 / total_amsdu);
4467+ else
4468+ seq_printf(s, "\n");
4469+ }
4470+
4471+ return 0;
4472+
4473+}
4474+
4475+static int mt7915_agginfo_read_per_band(struct seq_file *s, int band_idx)
4476+{
4477+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4478+ u32 value, idx, agg_rang_sel[15], ampdu_cnt[11], total_ampdu = 0;
4479+
4480+ seq_printf(s, "Band %d AGG Status\n", band_idx);
4481+ seq_printf(s, "===============================\n");
4482+ value = mt76_rr(dev, MT_DBG_AGG_AALCR0(band_idx));
4483+ seq_printf(s, "AC00 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4484+ seq_printf(s, "AC01 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4485+ seq_printf(s, "AC02 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4486+ seq_printf(s, "AC03 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4487+
4488+ value = mt76_rr(dev, MT_DBG_AGG_AALCR1(band_idx));
4489+ seq_printf(s, "AC10 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4490+ seq_printf(s, "AC11 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4491+ seq_printf(s, "AC12 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4492+ seq_printf(s, "AC13 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4493+
4494+ value = mt76_rr(dev, MT_DBG_AGG_AALCR2(band_idx));
4495+ seq_printf(s, "AC20 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4496+ seq_printf(s, "AC21 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4497+ seq_printf(s, "AC22 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4498+ seq_printf(s, "AC23 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4499+
4500+ value = mt76_rr(dev, MT_DBG_AGG_AALCR3(band_idx));
4501+ seq_printf(s, "AC30 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4502+ seq_printf(s, "AC31 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4503+ seq_printf(s, "AC32 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4504+ seq_printf(s, "AC33 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4505+
4506+ value = mt76_rr(dev, MT_DBG_AGG_AALCR4(band_idx));
4507+ seq_printf(s, "ALTX Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK, value));
4508+
4509+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 0));
4510+ seq_printf(s, "Winsize0 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE0_MASK, value));
4511+ seq_printf(s, "Winsize1 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE1_MASK, value));
4512+ seq_printf(s, "Winsize2 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE2_MASK, value));
4513+ seq_printf(s, "Winsize3 limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE3_MASK, value));
4514+
4515+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 1));
4516+ seq_printf(s, "Winsize4 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE4_MASK, value));
4517+ seq_printf(s, "Winsize5 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE5_MASK, value));
4518+ seq_printf(s, "Winsize6 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE6_MASK, value));
4519+ seq_printf(s, "Winsize7 limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE7_MASK, value));
4520+
4521+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 2));
4522+ seq_printf(s, "Winsize8 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZE8_MASK, value));
4523+ seq_printf(s, "Winsize9 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZE9_MASK, value));
4524+ seq_printf(s, "WinsizeA limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZEA_MASK, value));
4525+ seq_printf(s, "WinsizeB limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZEB_MASK, value));
4526+
4527+
4528+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 3));
4529+ seq_printf(s, "WinsizeC limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZEC_MASK, value));
4530+ seq_printf(s, "WinsizeD limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZED_MASK, value));
4531+ seq_printf(s, "WinsizeE limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZEE_MASK, value));
4532+
4533+ seq_printf(s, "===AMPDU Related Counters===\n");
4534+
4535+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 0));
4536+ agg_rang_sel[0] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK, value);
4537+ agg_rang_sel[1] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK, value);
4538+ agg_rang_sel[2] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK, value);
4539+ agg_rang_sel[3] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK, value);
4540+
4541+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 1));
4542+ agg_rang_sel[4] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK, value);
4543+ agg_rang_sel[5] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK, value);
4544+ agg_rang_sel[6] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK, value);
4545+ agg_rang_sel[7] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK, value);
4546+
4547+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 2));
4548+ agg_rang_sel[8] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK, value);
4549+ agg_rang_sel[9] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK, value);
4550+ agg_rang_sel[10] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK, value);
4551+ agg_rang_sel[11] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK, value);
4552+
4553+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 3));
4554+ agg_rang_sel[12] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK, value);
4555+ agg_rang_sel[13] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK, value);
4556+ agg_rang_sel[14] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK, value);
4557+
4558+ /* Need to add 1 after read from AGG_RANG_SEL CR */
4559+ for (idx = 0; idx < 15; idx++)
4560+ agg_rang_sel[idx]++;
4561+
4562+ ampdu_cnt[3] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 0));
4563+ ampdu_cnt[4] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 1));
4564+ ampdu_cnt[5] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 2));
4565+ ampdu_cnt[6] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 3));
4566+ ampdu_cnt[7] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 0));
4567+ ampdu_cnt[8] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 1));
4568+ ampdu_cnt[9] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 2));
4569+ ampdu_cnt[10] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 3));
4570+
4571+ seq_printf(s, "\tTx Agg Range: \t%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d\n",
4572+ agg_rang_sel[0],
4573+ agg_rang_sel[0] + 1, agg_rang_sel[1],
4574+ agg_rang_sel[1] + 1, agg_rang_sel[2],
4575+ agg_rang_sel[2] + 1, agg_rang_sel[3],
4576+ agg_rang_sel[3] + 1, agg_rang_sel[4],
4577+ agg_rang_sel[4] + 1, agg_rang_sel[5],
4578+ agg_rang_sel[5] + 1, agg_rang_sel[6],
4579+ agg_rang_sel[6] + 1, agg_rang_sel[7]);
4580+
4581+#define BIT_0_to_15_MASK 0x0000FFFF
4582+#define BIT_15_to_31_MASK 0xFFFF0000
4583+#define SHFIT_16_BIT 16
4584+
4585+ for (idx = 3; idx < 11; idx++)
4586+ total_ampdu = total_ampdu + (ampdu_cnt[idx] & BIT_0_to_15_MASK) + ((ampdu_cnt[idx] & BIT_15_to_31_MASK) >> SHFIT_16_BIT);
4587+
4588+ seq_printf(s, "\t\t\t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx\n",
4589+ (ampdu_cnt[3]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK,
4590+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[3]),
4591+ (ampdu_cnt[4]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK,
4592+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[4]),
4593+ (ampdu_cnt[5]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK,
4594+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[5]),
4595+ (ampdu_cnt[6]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK,
4596+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[6]));
4597+
4598+ if (total_ampdu != 0) {
4599+ seq_printf(s, "\t\t\t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%)\n",
4600+ ((ampdu_cnt[3]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK) * 100 / total_ampdu,
4601+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[3]) * 100 / total_ampdu,
4602+ ((ampdu_cnt[4]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK) * 100 / total_ampdu,
4603+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[4]) * 100 / total_ampdu,
4604+ ((ampdu_cnt[5]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK) * 100 / total_ampdu,
4605+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[5]) * 100 / total_ampdu,
4606+ ((ampdu_cnt[6]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK) * 100 / total_ampdu,
4607+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[6]) * 100 / total_ampdu);
4608+ }
4609+
4610+ seq_printf(s, "\t\t\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~256\n",
4611+ agg_rang_sel[7] + 1, agg_rang_sel[8],
4612+ agg_rang_sel[8] + 1, agg_rang_sel[9],
4613+ agg_rang_sel[9] + 1, agg_rang_sel[10],
4614+ agg_rang_sel[10] + 1, agg_rang_sel[11],
4615+ agg_rang_sel[11] + 1, agg_rang_sel[12],
4616+ agg_rang_sel[12] + 1, agg_rang_sel[13],
4617+ agg_rang_sel[13] + 1, agg_rang_sel[14],
4618+ agg_rang_sel[14] + 1);
4619+
4620+ seq_printf(s, "\t\t\t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx\n",
4621+ (ampdu_cnt[7]) & MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK,
4622+ FIELD_GET(MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK, ampdu_cnt[7]),
4623+ (ampdu_cnt[8]) & MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK,
4624+ FIELD_GET(MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK, ampdu_cnt[8]),
4625+ (ampdu_cnt[9]) & MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK,
4626+ FIELD_GET(MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK, ampdu_cnt[9]),
4627+ (ampdu_cnt[10]) & MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK,
4628+ FIELD_GET(MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK, ampdu_cnt[10]));
4629+
4630+ if (total_ampdu != 0) {
4631+ seq_printf(s, "\t\t\t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%)\n",
4632+ ((ampdu_cnt[7]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK) * 100 / total_ampdu,
4633+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[7]) * 100 / total_ampdu,
4634+ ((ampdu_cnt[8]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK) * 100 / total_ampdu,
4635+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[8]) * 100 / total_ampdu,
4636+ ((ampdu_cnt[9]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK) * 100 / total_ampdu,
4637+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[9]) * 100 / total_ampdu,
4638+ ((ampdu_cnt[10]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK) * 100 / total_ampdu,
4639+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[10]) * 100 / total_ampdu);
4640+ }
4641+
4642+ return 0;
4643+}
4644+
4645+static int mt7915_agginfo_read_band0(struct seq_file *s, void *data)
4646+{
4647+ mt7915_agginfo_read_per_band(s, 0);
4648+ return 0;
4649+}
4650+
4651+static int mt7915_agginfo_read_band1(struct seq_file *s, void *data)
4652+{
4653+ mt7915_agginfo_read_per_band(s, 1);
4654+ return 0;
4655+}
4656+
4657+/*usage: <en> <num> <len>
4658+ en: BIT(16) 0: sw amsdu 1: hw amsdu
4659+ num: GENMASK(15, 8) range 1-8
4660+ len: GENMASK(7, 0) unit: 256 bytes */
4661+static int mt7915_sta_tx_amsdu_set(void *data, u64 tx_amsdu)
4662+{
4663+/* UWTBL DW 6 */
4664+#define WTBL_AMSDU_LEN_MASK GENMASK(5, 0)
4665+#define WTBL_AMSDU_NUM_MASK GENMASK(8, 6)
4666+#define WTBL_AMSDU_EN_MASK BIT(9)
4667+#define UWTBL_HW_AMSDU_DW 6
4668+
4669+ struct mt7915_dev *dev = data;
4670+ u32 len = FIELD_GET(GENMASK(7, 0), tx_amsdu);
4671+ u32 num = FIELD_GET(GENMASK(15, 8), tx_amsdu);
4672+ u32 uwtbl;
4673+
developer9e5bcc52022-09-27 10:30:15 +08004674+ mt7915_mcu_set_amsdu_algo(dev, dev->wlan_idx, 0);
4675+
developer3fa816c2022-04-19 10:21:20 +08004676+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC,
4677+ UWTBL_HW_AMSDU_DW, 1, &uwtbl);
4678+
4679+ if (len) {
4680+ uwtbl &= ~WTBL_AMSDU_LEN_MASK;
4681+ uwtbl |= FIELD_PREP(WTBL_AMSDU_LEN_MASK, len);
4682+ }
4683+
4684+ uwtbl &= ~WTBL_AMSDU_NUM_MASK;
4685+ uwtbl |= FIELD_PREP(WTBL_AMSDU_NUM_MASK, num);
4686+
4687+ if (tx_amsdu & BIT(16))
4688+ uwtbl |= WTBL_AMSDU_EN_MASK;
4689+
4690+ mt7915_wtbl_write_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC,
4691+ UWTBL_HW_AMSDU_DW, uwtbl);
4692+
4693+ return 0;
4694+}
4695+
4696+DEFINE_DEBUGFS_ATTRIBUTE(fops_tx_amsdu, NULL,
4697+ mt7915_sta_tx_amsdu_set, "%llx\n");
4698+
4699+static int mt7915_red_enable_set(void *data, u64 en)
4700+{
4701+ struct mt7915_dev *dev = data;
4702+
4703+ return mt7915_mcu_set_red(dev, en);
4704+}
4705+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_en, NULL,
4706+ mt7915_red_enable_set, "%llx\n");
4707+
4708+static int mt7915_red_show_sta_set(void *data, u64 wlan_idx)
4709+{
4710+ struct mt7915_dev *dev = data;
4711+
4712+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
4713+ MCU_WA_PARAM_RED_SHOW_STA,
4714+ wlan_idx, 0, true);
4715+
4716+ return 0;
4717+}
4718+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_show_sta, NULL,
4719+ mt7915_red_show_sta_set, "%llx\n");
4720+
4721+static int mt7915_red_target_dly_set(void *data, u64 delay)
4722+{
4723+ struct mt7915_dev *dev = data;
4724+
4725+ if (delay > 0 && delay <= 32767)
4726+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
4727+ MCU_WA_PARAM_RED_TARGET_DELAY,
4728+ delay, 0, true);
4729+
4730+ return 0;
4731+}
4732+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_target_dly, NULL,
4733+ mt7915_red_target_dly_set, "%llx\n");
4734+
4735+static int
4736+mt7915_txpower_level_set(void *data, u64 val)
4737+{
4738+ struct mt7915_dev *dev = data;
4739+ struct mt7915_phy *ext_phy = mt7915_ext_phy(dev);
4740+ mt7915_mcu_set_txpower_level(&dev->phy, val);
4741+ if (ext_phy)
4742+ mt7915_mcu_set_txpower_level(ext_phy, val);
4743+
4744+ return 0;
4745+}
4746+
4747+DEFINE_DEBUGFS_ATTRIBUTE(fops_txpower_level, NULL,
4748+ mt7915_txpower_level_set, "%lld\n");
4749+
4750+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_set */
4751+static int
4752+mt7915_wa_set(void *data, u64 val)
4753+{
4754+ struct mt7915_dev *dev = data;
4755+ u32 arg1, arg2, arg3;
4756+
4757+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
4758+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
4759+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
4760+
4761+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), arg1, arg2, arg3, false);
4762+
4763+ return 0;
4764+}
4765+
4766+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_set, NULL, mt7915_wa_set,
4767+ "0x%llx\n");
4768+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_query */
4769+static int
4770+mt7915_wa_query(void *data, u64 val)
4771+{
4772+ struct mt7915_dev *dev = data;
4773+ u32 arg1, arg2, arg3;
4774+
4775+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
4776+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
4777+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
4778+
4779+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY), arg1, arg2, arg3, false);
4780+
4781+ return 0;
4782+}
4783+
4784+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_query, NULL, mt7915_wa_query,
4785+ "0x%llx\n");
4786+/* set wa debug level
4787+ usage:
4788+ echo 0x[arg] > fw_wa_debug
4789+ bit0 : DEBUG_WIFI_TX
4790+ bit1 : DEBUG_CMD_EVENT
4791+ bit2 : DEBUG_RED
4792+ bit3 : DEBUG_WARN
4793+ bit4 : DEBUG_WIFI_RX
4794+ bit5 : DEBUG_TIME_STAMP
4795+ bit6 : DEBUG_TX_FREE_DONE_EVENT
4796+ bit12 : DEBUG_WIFI_TXD */
4797+static int
4798+mt7915_wa_debug(void *data, u64 val)
4799+{
4800+ struct mt7915_dev *dev = data;
4801+ u32 arg;
4802+
4803+ arg = FIELD_GET(GENMASK_ULL(15, 0), val);
4804+
4805+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(DEBUG), arg, 0, 0, false);
4806+
4807+ return 0;
4808+}
4809+
4810+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_debug, NULL, mt7915_wa_debug,
4811+ "0x%llx\n");
4812+
developer8e5fecd2023-05-30 11:58:00 +08004813+static int mt7915_dump_version(struct seq_file *s, void *data)
4814+{
4815+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4816+ struct mt76_dev *mdev = NULL;
developer2b96a9e2023-08-09 10:28:15 +08004817+ seq_printf(s, "Version: 2.2.13.0\n");
developer8e5fecd2023-05-30 11:58:00 +08004818+
4819+ if (!test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state))
4820+ return 0;
4821+
4822+ mdev = &dev->mt76;
4823+ seq_printf(s, "Rom Patch Build Time: %.16s\n", mdev->patch_hdr->build_date);
4824+ seq_printf(s, "WM Patch Build Time: %.16s\n", mdev->wm_hdr->build_date);
4825+ seq_printf(s, "WA Patch Build Time: %.16s\n", mdev->wa_hdr->build_date);
4826+ return 0;
4827+}
4828+
developera43cc482023-04-17 15:57:28 +08004829+static inline int mt7915_snprintf_error(size_t size, int res)
4830+{
4831+ return res < 0 || (unsigned int) res >= size;
4832+}
4833+
4834+static void mt7915_show_lp_history(struct seq_file *s, bool fgIsExp)
4835+{
4836+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4837+ u32 macVal = 0, gpr_log_idx = 0, oldest_idx = 0;
4838+ u32 idx = 0, i = 0;
4839+
4840+ if (!fgIsExp) {
4841+ /* disable LP recored */
4842+ macVal = mt76_rr(dev, 0x89050200);
4843+ macVal &= (~0x1);
4844+ mt76_wr(dev, 0x89050200, macVal);
4845+ udelay(100);
4846+ }
4847+
4848+ macVal = 0;
4849+ macVal = mt76_rr(dev, 0x89050200);
4850+ gpr_log_idx = ((macVal >> 16) & 0x1f);
4851+ oldest_idx = gpr_log_idx + 2;
4852+
4853+ seq_printf(s, " lp history (from old to new):\n");
4854+ for (i = 0; i < 16; i++) {
4855+ idx = ((oldest_idx + 2*i + 1)%32);
4856+ macVal = mt76_rr(dev, (0x89050204 + idx*4));
4857+ seq_printf(s, " %d: 0x%x\n", i, macVal);
4858+ }
4859+
4860+ if (!fgIsExp) {
4861+ /* enable LP recored */
4862+ macVal = mt76_rr(dev, 0x89050200);
4863+ macVal |= 0x1;
4864+ mt76_wr(dev, 0x89050200, macVal);
4865+ }
4866+}
4867+
4868+static void mt7915_show_irq_history(struct seq_file *s)
4869+{
4870+#define SYSIRQ_INTERRUPT_HISTORY_NUM 10
4871+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4872+ u32 macVal = 0;
4873+ u32 i = 0;
4874+ u32 start = 0;
4875+ u32 idx = 0;
4876+ u8 ucIrqDisIdx = 0;
4877+ u8 ucIrqResIdx = 0;
4878+ u32 irq_dis_time[10];
4879+ u32 irq_dis_lp[10];
4880+ u32 irq_res_time[10];
4881+ u32 irq_res_lp[10];
4882+
4883+ macVal = 0;
4884+ macVal = mt76_rr(dev, 0x022051C0);
4885+ ucIrqResIdx = (macVal & 0xff);
4886+ ucIrqDisIdx = ((macVal >> 8) & 0xff);
4887+
4888+ seq_printf(s, "\n\n\n Irq Idx (Dis=%d Res=%d):\n",
4889+ ucIrqDisIdx, ucIrqResIdx);
4890+
4891+ start = mt76_rr(dev, 0x022051C8);
4892+ for (i = 0; i < SYSIRQ_INTERRUPT_HISTORY_NUM; i++) {
4893+ macVal = mt76_rr(dev, (start + (i * 8)));
4894+ irq_dis_time[i] = macVal;
4895+ macVal = mt76_rr(dev, (start + (i * 8) + 4));
4896+ irq_dis_lp[i] = macVal;
4897+ }
4898+
4899+ start = mt76_rr(dev, 0x022051C4);
4900+
4901+ for (i = 0; i < SYSIRQ_INTERRUPT_HISTORY_NUM; i++) {
4902+ macVal = mt76_rr(dev, (start + (i * 8)));
4903+ irq_res_time[i] = macVal;
4904+ macVal = mt76_rr(dev, (start + (i * 8) + 4));
4905+ irq_res_lp[i] = macVal;
4906+ }
4907+
4908+ seq_printf(s, "\n Dis Irq history (from old to new):\n");
4909+ for (i = 0; i < SYSIRQ_INTERRUPT_HISTORY_NUM; i++) {
4910+ idx = (i + ucIrqDisIdx) % SYSIRQ_INTERRUPT_HISTORY_NUM;
4911+ seq_printf(s, " [%d].LP = 0x%x time=%u\n",
4912+ idx, irq_dis_lp[idx], irq_dis_time[idx]);
4913+ }
4914+
4915+ seq_printf(s, "\n Restore Irq history (from old to new):\n");
4916+ for (i = 0; i < SYSIRQ_INTERRUPT_HISTORY_NUM; i++) {
4917+ idx = (i + ucIrqResIdx) % SYSIRQ_INTERRUPT_HISTORY_NUM;
4918+ seq_printf(s, " [%d].LP = 0x%x time=%u\n",
4919+ idx, irq_res_lp[idx], irq_res_time[idx]);
4920+ }
4921+}
4922+
4923+static void MemSectionRead(struct mt7915_dev *dev, char *buf, u32 length, u32 addr)
4924+{
4925+ int idx = 0;
4926+ u32 *ptr =(u32 *)buf;
4927+
4928+ while (idx < length) {
4929+ *ptr = mt76_rr(dev, (addr + idx));
4930+ idx += 4;
4931+ ptr++;
4932+ }
4933+}
4934+
4935+static void mt7915_show_msg_trace(struct seq_file *s)
4936+{
4937+#define MSG_HISTORY_NUM 64
4938+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4939+ struct cos_msg_trace_t *msg_trace = NULL;
4940+ u32 ptr_addr = 0;
4941+ u32 length = 0;
developer004e50c2023-06-29 20:33:22 +08004942+ u32 idx = 0;
developera43cc482023-04-17 15:57:28 +08004943+ u32 cnt = 0;
4944+ u32 msg_history_num = 0;
4945+
4946+ msg_trace = kmalloc(MSG_HISTORY_NUM * sizeof(struct cos_msg_trace_t), GFP_KERNEL);
4947+ if (!msg_trace) {
4948+ seq_printf(s, "can not allocate cmd msg_trace\n");
4949+ return;
4950+ }
4951+
4952+ memset(msg_trace, 0, MSG_HISTORY_NUM * sizeof(struct cos_msg_trace_t));
4953+
4954+ ptr_addr = mt76_rr(dev, 0x02205188);
4955+ msg_history_num = mt76_rr(dev, 0x0220518C);
4956+
4957+ idx = (msg_history_num >> 8) & 0xff;
4958+ msg_history_num = msg_history_num & 0xff;
4959+
4960+ if (idx >= msg_history_num) {
4961+ kfree(msg_trace);
4962+ return;
4963+ }
4964+
4965+ length = msg_history_num * sizeof(struct cos_msg_trace_t);
4966+ MemSectionRead(dev, (char *)&(msg_trace[0]), length, ptr_addr);
4967+ seq_printf(s,"\n");
4968+ seq_printf(s, " msg trace:\n");
4969+ seq_printf(s, " format: t_id=task_id/task_prempt_cnt/msg_read_idx\n");
4970+
4971+ while (1) {
4972+ seq_printf(s, " (m_%d)t_id=%x/%d/%d, m_id=%d, ts_en=%u, ts_de = %u, ts_fin=%u, wait=%d, exe=%d\n",
4973+ idx,
4974+ msg_trace[idx].dest_id,
4975+ msg_trace[idx].pcount,
4976+ msg_trace[idx].qread,
4977+ msg_trace[idx].msg_id,
4978+ msg_trace[idx].ts_enq,
4979+ msg_trace[idx].ts_deq,
4980+ msg_trace[idx].ts_finshq,
4981+ (msg_trace[idx].ts_deq - msg_trace[idx].ts_enq),
4982+ (msg_trace[idx].ts_finshq - msg_trace[idx].ts_deq));
4983+
4984+ if (++idx >= msg_history_num)
4985+ idx = 0;
4986+
4987+ if (++cnt >= msg_history_num)
4988+ break;
4989+ }
4990+ if (msg_trace)
4991+ kfree(msg_trace);
4992+}
4993+
4994+static int mt7915_show_assert_line(struct seq_file *s)
4995+{
4996+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4997+ char *msg;
4998+ u32 addr;
4999+ u32 macVal = 0;
5000+ char *ptr;
5001+ char idx;
5002+
5003+ msg = kmalloc(256, GFP_KERNEL);
5004+ if (!msg)
5005+ return 0;
5006+
5007+ memset(msg, 0, 256);
5008+ addr = 0x00400000;
5009+ ptr = msg;
5010+ for (idx = 0 ; idx < 32; idx++) {
5011+ macVal = 0;
5012+ macVal = mt76_rr(dev, addr);
5013+ memcpy(ptr, &macVal, 4);
5014+ addr += 4;
5015+ ptr += 4;
5016+ }
5017+
5018+ *ptr = 0;
5019+ seq_printf(s,"\n\n");
5020+ seq_printf(s," Assert line\n");
5021+ seq_printf(s," %s\n", msg);
5022+ if (msg)
5023+ kfree(msg);
5024+
5025+ return 0;
5026+}
5027+
5028+
5029+static void mt7915_show_sech_trace(struct seq_file *s)
5030+{
5031+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
5032+ struct cos_task_info_struct task_info_g[2];
5033+ u32 length = 0, i = 0;
5034+ u32 idx = 0;
5035+ u32 km_total_time = 0;
5036+ u32 addr = 0;
5037+ struct cos_task_type tcb;
5038+ struct cos_task_type *tcb_ptr;
5039+ char name[2][15] = {
5040+ "WIFI ", "WIFI2 "
5041+ };
5042+
5043+ length = 2 * sizeof(struct cos_task_info_struct);
5044+ MemSectionRead(dev, (char *)&(task_info_g[0]), length, 0x02202A18);
5045+
5046+ /*while(i < length) {
5047+ task_info_g[i] = mt76_rr(dev, 0x02202A18 + i * 0x4);
5048+ i++;
5049+ }*/
5050+ km_total_time = mt76_rr(dev, 0x022051B4);
5051+ if (km_total_time == 0) {
5052+ seq_printf(s, "km_total_time zero!\n");
5053+ return;
5054+ }
5055+
5056+ seq_printf(s,"\n\n\n TASK XTIME RATIO PREMPT CNT\n");
5057+ for (idx = 0 ; idx < 2 ; idx++) {
5058+ addr = task_info_g[idx].task_id;
5059+ i = 0;
5060+ MemSectionRead(dev, (char *)&(tcb), sizeof(struct cos_task_type), addr);
5061+
5062+ length = sizeof(struct cos_task_type);
5063+
5064+ tcb_ptr = &(tcb);
5065+
5066+ if (tcb_ptr) {
5067+ seq_printf(s, " %s %d %d %d\n",
5068+ name[idx],
5069+ tcb_ptr->tc_exe_time,
5070+ (tcb_ptr->tc_exe_time*100/km_total_time),
5071+ tcb_ptr->tc_pcount);
5072+ }
5073+ }
5074+
5075+}
5076+
5077+static void mt7915_show_prog_trace(struct seq_file *s)
5078+{
5079+#define PROGRAM_TRACE_HISTORY_NUM 32
5080+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
5081+ struct cos_program_trace_t *cos_program_trace_ptr = NULL;
5082+ u32 trace_ptr = 0;
developer004e50c2023-06-29 20:33:22 +08005083+ u32 idx = 0;
developera43cc482023-04-17 15:57:28 +08005084+ u32 old_idx = 0;
5085+ u32 old_idx_addr = 0;
5086+ u32 prev_idx = 0;
5087+ u32 prev_time = 0;
5088+ u32 curr_time = 0;
5089+ u32 diff = 0;
developer004e50c2023-06-29 20:33:22 +08005090+ //u32 length = 0, i = 0;
developera43cc482023-04-17 15:57:28 +08005091+
5092+ cos_program_trace_ptr = kmalloc(PROGRAM_TRACE_HISTORY_NUM * sizeof(struct cos_program_trace_t), GFP_KERNEL);
5093+ if (!cos_program_trace_ptr) {
5094+ seq_printf(s, "can not allocate cos_program_trace_ptr memory\n");
5095+ return;
5096+ }
5097+ memset(cos_program_trace_ptr, 0, PROGRAM_TRACE_HISTORY_NUM * sizeof(struct cos_program_trace_t));
5098+
5099+ trace_ptr = mt76_rr(dev, 0x0220514C);
5100+ old_idx_addr = mt76_rr(dev, 0x02205148);
5101+
5102+ old_idx = (old_idx_addr >> 8) & 0xff;
5103+
5104+ MemSectionRead(dev, (char *)&cos_program_trace_ptr[0], PROGRAM_TRACE_HISTORY_NUM * sizeof(struct cos_program_trace_t), trace_ptr);
5105+
5106+ /*length = PROGRAM_TRACE_HISTORY_NUM * sizeof(struct cos_program_trace_t);
5107+ while(i < length) {
5108+ cos_program_trace_ptr[i] = mt76_rr(dev, trace_ptr + i * 0x4);
5109+ i++;
5110+ }*/
5111+ seq_printf(s, "\n");
5112+ seq_printf(s, " program trace:\n");
5113+ for (idx = 0 ; idx < PROGRAM_TRACE_HISTORY_NUM ; idx++) {
5114+ prev_idx = ((old_idx + 32 - 1) % 32);
5115+
5116+ seq_printf(s, " (p_%d)t_id=%x/%d, m_id=%d, LP=0x%x, name=%s, ts2=%d, ",
5117+ old_idx,
5118+ cos_program_trace_ptr[old_idx].dest_id,
5119+ cos_program_trace_ptr[old_idx].msg_sn,
5120+ cos_program_trace_ptr[old_idx].msg_id,
5121+ cos_program_trace_ptr[old_idx].LP,
5122+ cos_program_trace_ptr[old_idx].name,
5123+ cos_program_trace_ptr[old_idx].ts_gpt2);
5124+
5125+ /* diff for gpt2 */
5126+ prev_time = cos_program_trace_ptr[prev_idx].ts_gpt2;
5127+ curr_time = cos_program_trace_ptr[old_idx].ts_gpt2;
5128+
5129+ if (prev_time) {
5130+ if ((cos_program_trace_ptr[prev_idx].dest_id == cos_program_trace_ptr[old_idx].dest_id) &&
5131+ (cos_program_trace_ptr[prev_idx].msg_sn == cos_program_trace_ptr[old_idx].msg_sn)) {
5132+ if (curr_time > prev_time)
5133+ diff = curr_time - prev_time;
5134+ else
5135+ diff = 0xFFFFFFFF - prev_time + curr_time + 1;
5136+ } else
5137+ diff = 0xFFFFFFFF;
5138+ } else
5139+ diff = 0xFFFFFFFF;
5140+
5141+ if (diff == 0xFFFFFFFF)
5142+ seq_printf(s, "diff2=NA, \n");
5143+ else
5144+ seq_printf(s, "diff2=%8d\n", diff);
5145+
5146+ old_idx++;
5147+ if (old_idx >= 32)
5148+ old_idx = 0;
5149+ }
5150+ if (cos_program_trace_ptr)
5151+ kfree(cos_program_trace_ptr);
5152+}
5153+
5154+static int mt7915_fw_wm_info_read(struct seq_file *s, void *data)
5155+{
5156+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
5157+ u32 macVal = 0, g_exp_type = 0, COS_Interrupt_Count = 0;
developer004e50c2023-06-29 20:33:22 +08005158+ u8 exp_assert_proc_entry_cnt = 0, exp_assert_state = 0, g_irq_history_num = 0;
developera43cc482023-04-17 15:57:28 +08005159+ u16 processing_irqx = 0;
5160+ u32 processing_lisr = 0, Current_Task_Id = 0, Current_Task_Indx = 0;
5161+ u8 km_irq_info_idx = 0, km_eint_info_idx = 0, km_sched_info_idx = 0, g_sched_history_num = 0;
5162+ u32 km_sched_trace_ptr = 0,km_irq_trace_ptr = 0, km_total_time = 0, TaskStart[3] = {0};
5163+ bool fgIsExp = false, fgIsAssert = false;
5164+ u32 TaskEnd[3] = {0}, exp_assert_state_addr = 0, g1_exp_counter_addr = 0;
5165+ u32 g_exp_type_addr = 0, cos_interrupt_count_addr = 0;
5166+ u32 processing_irqx_addr = 0, processing_lisr_addr = 0;
5167+ u32 Current_Task_Id_addr = 0, Current_Task_Indx_addr = 0, last_dequeued_msg_id_addr = 0;
5168+ u32 km_irq_info_idx_addr = 0, km_eint_info_idx_addr = 0, km_sched_info_idx_addr = 0;
5169+ u32 g_sched_history_num_addr = 0, km_sched_trace_ptr_addr = 0;
5170+ u32 km_irq_trace_ptr_addr = 0, km_total_time_addr = 0, last_dequeued_msg_id = 0;
5171+ u32 i = 0 ,t1 = 0, t2 = 0, t3 = 0;
developer004e50c2023-06-29 20:33:22 +08005172+ u8 idx = 0, str[32], exp_type[64];
developera43cc482023-04-17 15:57:28 +08005173+ int ret;
5174+
5175+ g_exp_type_addr = 0x022050DC;
5176+ exp_assert_state_addr = 0x02204B54;
5177+ g1_exp_counter_addr = 0x02204FFC;
5178+ cos_interrupt_count_addr = 0x022001AC;
5179+ processing_irqx_addr = 0x02204EC4;
5180+ processing_lisr_addr = 0x02205010;
5181+ Current_Task_Id_addr = 0x02204FAC;
5182+ Current_Task_Indx_addr = 0x02204F4C;
5183+ last_dequeued_msg_id_addr = 0x02204F28;
5184+ km_irq_info_idx_addr = 0x0220519C;
5185+ km_eint_info_idx_addr = 0x02205194;
5186+ km_sched_info_idx_addr = 0x022051A4;
5187+ g_sched_history_num_addr = 0x022051A4;
5188+ km_sched_trace_ptr_addr = 0x022051A0;
5189+ km_irq_trace_ptr_addr = 0x02205198;
5190+ km_total_time_addr = 0x022051B4;
5191+
5192+ macVal = 0;
5193+ macVal = mt76_rr(dev, exp_assert_state_addr);
5194+ exp_assert_state = (macVal & 0xff);
5195+
5196+ macVal = 0;
5197+ macVal = mt76_rr(dev, g1_exp_counter_addr);
5198+ exp_assert_proc_entry_cnt = (macVal & 0xff);
5199+
5200+ macVal = 0;
5201+ macVal = mt76_rr(dev, g_exp_type_addr);
5202+ g_exp_type = macVal;
5203+
5204+ macVal = 0;
5205+ macVal = mt76_rr(dev, cos_interrupt_count_addr);
5206+ COS_Interrupt_Count = macVal;
5207+
5208+ macVal = 0;
5209+ macVal = mt76_rr(dev, processing_irqx_addr);
5210+ processing_irqx = (macVal & 0xffff);
5211+
5212+ macVal = 0;
5213+ macVal = mt76_rr(dev, processing_lisr_addr);
5214+ processing_lisr = macVal;
5215+
5216+ macVal = 0;
5217+ macVal = mt76_rr(dev, Current_Task_Id_addr);
5218+ Current_Task_Id = macVal;
5219+
5220+ macVal = 0;
5221+ macVal = mt76_rr(dev, Current_Task_Indx_addr);
5222+ Current_Task_Indx = macVal;
5223+
5224+ macVal = 0;
5225+ macVal = mt76_rr(dev, last_dequeued_msg_id_addr);
5226+ last_dequeued_msg_id = macVal;
5227+
5228+ macVal = 0;
5229+ macVal = mt76_rr(dev, km_eint_info_idx_addr);
5230+ km_eint_info_idx = ((macVal >> 8) & 0xff);
5231+
5232+ macVal = 0;
5233+ macVal = mt76_rr(dev, g_sched_history_num_addr);
5234+ g_sched_history_num = (macVal & 0xff);
5235+ km_sched_info_idx = ((macVal >> 8) & 0xff);
5236+
5237+ macVal = 0;
5238+ macVal = mt76_rr(dev, km_sched_trace_ptr_addr);
5239+ km_sched_trace_ptr = macVal;
5240+
5241+ macVal = 0;
5242+ macVal = mt76_rr(dev, km_irq_info_idx_addr);
5243+ g_irq_history_num = (macVal & 0xff);
5244+ km_irq_info_idx = ((macVal >> 16) & 0xff);
5245+
5246+ macVal = 0;
5247+ macVal = mt76_rr(dev, km_irq_trace_ptr_addr);
5248+ km_irq_trace_ptr = macVal;
5249+
5250+ macVal = 0;
5251+ macVal = mt76_rr(dev, km_total_time_addr);
5252+ km_total_time = macVal;
5253+
5254+ TaskStart[0] = mt76_rr(dev, 0x02202814);
5255+ TaskEnd[0] = mt76_rr(dev, 0x02202810);
5256+ TaskStart[1] = mt76_rr(dev, 0x02202984);
5257+ TaskEnd[1] = mt76_rr(dev, 0x02202980);
5258+
5259+ seq_printf(s, "================FW DBG INFO===================\n");
5260+ seq_printf(s, " exp_assert_proc_entry_cnt = 0x%x\n",
5261+ exp_assert_proc_entry_cnt);
5262+ seq_printf(s, " exp_assert_state = 0x%x\n",
5263+ exp_assert_state);
5264+
5265+ if (exp_assert_proc_entry_cnt == 0) {
5266+ ret = snprintf(exp_type, sizeof(exp_type), "%s", "exp_type : Normal");
5267+ if (mt7915_snprintf_error(sizeof(exp_type), ret)) {
5268+ seq_printf(s, " exp_type Snprintf failed!\n");
5269+ return 0;
5270+ }
5271+ } else if (exp_assert_proc_entry_cnt == 1 &&
5272+ exp_assert_state > 1 && g_exp_type == 5) {
5273+ ret = snprintf(exp_type, sizeof(exp_type), "%s", "exp_type : Assert");
5274+ if (mt7915_snprintf_error(sizeof(exp_type), ret)) {
5275+ seq_printf(s, " exp_type Snprintf failed!\n");
5276+ return 0;
5277+ }
5278+ fgIsExp = true;
5279+ fgIsAssert = true;
5280+ } else if (exp_assert_proc_entry_cnt == 1 && exp_assert_state > 1) {
5281+ ret = snprintf(exp_type, sizeof(exp_type), "%s", "exp_type : Exception");
5282+ if (mt7915_snprintf_error(sizeof(exp_type), ret)) {
5283+ seq_printf(s, " exp_type Snprintf failed!\n");
5284+ return 0;
5285+ }
5286+ fgIsExp = true;
5287+ } else if (exp_assert_proc_entry_cnt > 1) {
5288+ ret = snprintf(exp_type, sizeof(exp_type), "%s", "exp_type : Exception re-entry");
5289+ if (mt7915_snprintf_error(sizeof(exp_type), ret)) {
5290+ seq_printf(s, " exp_type Snprintf failed!\n");
5291+ return 0;
5292+ }
5293+ fgIsExp = true;
5294+ } else {
5295+ ret = snprintf(exp_type, sizeof(exp_type), "%s", "exp_type : Unknown'?");
5296+ if (mt7915_snprintf_error(sizeof(exp_type), ret)) {
5297+ seq_printf(s, " exp_type Snprintf failed!\n");
5298+ return 0;
5299+ }
5300+ }
5301+
5302+ seq_printf(s, " COS_Interrupt_Count = 0x%x\n", COS_Interrupt_Count);
5303+ seq_printf(s, " processing_irqx = 0x%x\n", processing_irqx);
5304+ seq_printf(s, " processing_lisr = 0x%x\n", processing_lisr);
5305+ seq_printf(s, " Current_Task_Id = 0x%x\n", Current_Task_Id);
5306+ seq_printf(s, " Current_Task_Indx = 0x%x\n", Current_Task_Indx);
5307+ seq_printf(s, " last_dequeued_msg_id = %d\n", last_dequeued_msg_id);
5308+
5309+ seq_printf(s, " km_irq_info_idx = 0x%x\n", km_irq_info_idx);
5310+ seq_printf(s, " km_eint_info_idx = 0x%x\n", km_eint_info_idx);
5311+ seq_printf(s, " km_sched_info_idx = 0x%x\n", km_sched_info_idx);
5312+ seq_printf(s, " g_sched_history_num = %d\n", g_sched_history_num);
5313+ seq_printf(s, " km_sched_trace_ptr = 0x%x\n", km_sched_trace_ptr);
5314+
5315+ if (fgIsExp) {
5316+ seq_printf(s, "\n <1>print sched trace\n");
5317+ if (g_sched_history_num > 60)
5318+ g_sched_history_num = 60;
5319+
5320+ idx = km_sched_info_idx;
5321+ for (i = 0 ; i < g_sched_history_num ; i++) {
5322+ t1 = mt76_rr(dev, (km_sched_trace_ptr+(idx*12)));
5323+ t2 = mt76_rr(dev, (km_sched_trace_ptr+(idx*12)+4));
5324+ t3 = mt76_rr(dev, (km_sched_trace_ptr+(idx*12)+8));
5325+ seq_printf(s, " (sched_info_%d)sched_t=0x%x, sched_start=%d, PC=0x%x\n",
5326+ idx, t1, t2, t3);
5327+ idx++;
5328+ if (idx >= g_sched_history_num)
5329+ idx = 0;
5330+ }
5331+
5332+ seq_printf(s, "\n <2>print irq trace\n");
5333+ if (g_irq_history_num > 60)
5334+ g_irq_history_num = 60;
5335+
5336+ idx = km_irq_info_idx;
5337+ for (i = 0 ; i < g_irq_history_num ; i++) {
5338+ t1 = mt76_rr(dev, (km_irq_trace_ptr+(idx*16)));
5339+ t2 = mt76_rr(dev, (km_irq_trace_ptr+(idx*16) + 4));
5340+ seq_printf(s, " (irq_info_%d)irq_t=%x, sched_start=%d\n",
5341+ idx, t1, t2);
5342+ idx++;
5343+ if (idx >= g_irq_history_num)
5344+ idx = 0;
5345+ }
5346+ }
5347+
5348+ seq_printf(s, "\n <3>task q_id.read q_id.write\n");
5349+ seq_printf(s, " (WIFI )1 0x%x 0x%x\n", TaskStart[0], TaskEnd[0]);
5350+ seq_printf(s, " (WIFI2 )2 0x%x 0x%x\n", TaskStart[1], TaskEnd[1]);
5351+ seq_printf(s, "\n <4>TASK STACK INFO (size in byte)\n");
5352+ seq_printf(s, " TASK START END SIZE PEAK INTEGRITY\n");
5353+
5354+ for (i = 0 ; i < 2 ; i++) {
5355+ t1 = mt76_rr(dev, 0x022027B8+(i*368));
5356+ t2 = mt76_rr(dev, 0x022027BC+(i*368));
5357+ t3 = mt76_rr(dev, 0x022027C4+(i*368));
5358+
5359+ if (i == 0) {
5360+ ret = snprintf(str, sizeof(str), "%s", "WIFI");
5361+ if (mt7915_snprintf_error(sizeof(str), ret)) {
5362+ seq_printf(s, " str Snprintf failed!\n");
5363+ return 0;
5364+ }
5365+ } else if (i == 1) {
5366+ ret = snprintf(str, sizeof(str), "%s", "WIFI2");
5367+ if (mt7915_snprintf_error(sizeof(str), ret)) {
5368+ seq_printf(s, " str Snprintf failed!\n");
5369+ return 0;
5370+ }
5371+ }
5372+
5373+ seq_printf(s, " %s 0x%x 0x%x %d\n",
5374+ str, t1, t2, t3);
5375+ }
5376+
5377+ seq_printf(s, "\n <5>fw state\n");
5378+ seq_printf(s, " %s\n", exp_type);
5379+ if (COS_Interrupt_Count > 0)
5380+ seq_printf(s, " FW in Interrupt CIRQ index (0x%x) CIRQ handler(0x%x)\n"
5381+ , processing_irqx, processing_lisr);
5382+ else {
5383+ if (Current_Task_Id == 0 && Current_Task_Indx == 3)
5384+ seq_printf(s, " FW in IDLE\n");
5385+
5386+ if (Current_Task_Id != 0 && Current_Task_Indx != 3)
5387+ seq_printf(s, " FW in Task , Task id(0x%x) Task index(0x%x)\n",
5388+ Current_Task_Id, Current_Task_Indx);
5389+ }
5390+
5391+ macVal = 0;
5392+ macVal= mt76_rr(dev, g1_exp_counter_addr);
5393+ seq_printf(s, " EXCP_CNT = 0x%x\n", macVal);
5394+
5395+ seq_printf(s, " EXCP_TYPE = 0x%x\n", g_exp_type);
5396+
5397+ macVal = 0;
5398+ macVal = mt76_rr(dev, 0x022050E0);
5399+ seq_printf(s, " CPU_ITYPE = 0x%x\n", macVal);
5400+
5401+ macVal = 0;
5402+ macVal = mt76_rr(dev, 0x022050E8);
5403+ seq_printf(s, " CPU_EVA = 0x%x\n", macVal);
5404+
5405+ macVal = 0;
5406+ macVal = mt76_rr(dev, 0x022050E4);
5407+ seq_printf(s, " CPU_IPC = 0x%x\n", macVal);
5408+
5409+ macVal = 0;
5410+ macVal = mt76_rr(dev, 0x7C060204);
5411+ seq_printf(s, " PC = 0x%x\n\n\n", macVal);
5412+
5413+ mt7915_show_lp_history(s, fgIsExp);
5414+ mt7915_show_irq_history(s);
5415+
5416+ seq_printf(s, "\n\n cpu ultility\n");
5417+ seq_printf(s, " Busy:%d%% Peak:%d%%\n\n",
5418+ mt76_rr(dev, 0x7C053B20), mt76_rr(dev, 0x7C053B24));
5419+
5420+ mt7915_show_msg_trace(s);
5421+ mt7915_show_sech_trace(s);
5422+ mt7915_show_prog_trace(s);
5423+ if (fgIsAssert)
5424+ mt7915_show_assert_line(s);
5425+
5426+ seq_printf(s, "============================================\n");
5427+ return 0;
5428+}
5429+
developer3fa816c2022-04-19 10:21:20 +08005430+int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir)
5431+{
5432+ struct mt7915_dev *dev = phy->dev;
5433+ u32 device_id = (dev->mt76.rev) >> 16;
5434+ int i = 0;
5435+
5436+ for (i = 0; i < ARRAY_SIZE(dbg_reg_s); i++) {
5437+ if (device_id == dbg_reg_s[i].id) {
5438+ dev->dbg_reg = &dbg_reg_s[i];
5439+ break;
5440+ }
5441+ }
5442+
5443+ mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 0);
5444+
5445+ debugfs_create_file("fw_debug_module", 0600, dir, dev,
5446+ &fops_fw_debug_module);
5447+ debugfs_create_file("fw_debug_level", 0600, dir, dev,
5448+ &fops_fw_debug_level);
5449+
developerf32dabf2022-06-01 10:59:24 +08005450+ debugfs_create_devm_seqfile(dev->mt76.dev, "sta_info", dir,
5451+ mt7915_sta_info);
developer3fa816c2022-04-19 10:21:20 +08005452+ debugfs_create_devm_seqfile(dev->mt76.dev, "wtbl_info", dir,
5453+ mt7915_wtbl_read);
5454+ debugfs_create_devm_seqfile(dev->mt76.dev, "uwtbl_info", dir,
5455+ mt7915_uwtbl_read);
5456+
5457+ debugfs_create_devm_seqfile(dev->mt76.dev, "tr_info", dir,
5458+ mt7915_trinfo_read);
5459+
5460+ debugfs_create_devm_seqfile(dev->mt76.dev, "drr_info", dir,
5461+ mt7915_drr_info);
5462+
5463+ debugfs_create_devm_seqfile(dev->mt76.dev, "ple_info", dir,
5464+ mt7915_pleinfo_read);
5465+
5466+ debugfs_create_devm_seqfile(dev->mt76.dev, "pse_info", dir,
5467+ mt7915_pseinfo_read);
5468+
5469+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info0", dir,
5470+ mt7915_mibinfo_band0);
5471+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info1", dir,
5472+ mt7915_mibinfo_band1);
5473+
5474+ debugfs_create_u32("token_idx", 0600, dir, &dev->dbg.token_idx);
5475+ debugfs_create_devm_seqfile(dev->mt76.dev, "token", dir,
5476+ mt7915_token_read);
5477+ debugfs_create_devm_seqfile(dev->mt76.dev, "token_txd", dir,
5478+ mt7915_token_txd_read);
5479+
5480+ debugfs_create_devm_seqfile(dev->mt76.dev, "amsdu_info", dir,
5481+ mt7915_amsduinfo_read);
5482+
5483+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info0", dir,
5484+ mt7915_agginfo_read_band0);
5485+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info1", dir,
5486+ mt7915_agginfo_read_band1);
5487+
5488+ debugfs_create_file("tx_amsdu", 0600, dir, dev, &fops_tx_amsdu);
5489+
5490+ debugfs_create_file("fw_wa_query", 0600, dir, dev, &fops_wa_query);
5491+ debugfs_create_file("fw_wa_set", 0600, dir, dev, &fops_wa_set);
developer8e5fecd2023-05-30 11:58:00 +08005492+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_version", dir,
5493+ mt7915_dump_version);
developer3fa816c2022-04-19 10:21:20 +08005494+ debugfs_create_file("fw_wa_debug", 0600, dir, dev, &fops_wa_debug);
developera43cc482023-04-17 15:57:28 +08005495+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_wm_info", dir,
5496+ mt7915_fw_wm_info_read);
developer3fa816c2022-04-19 10:21:20 +08005497+
5498+ debugfs_create_file("red_en", 0600, dir, dev,
5499+ &fops_red_en);
5500+ debugfs_create_file("red_show_sta", 0600, dir, dev,
5501+ &fops_red_show_sta);
5502+ debugfs_create_file("red_target_dly", 0600, dir, dev,
5503+ &fops_red_target_dly);
5504+
5505+ debugfs_create_file("txpower_level", 0400, dir, dev,
5506+ &fops_txpower_level);
5507+
developeraace7f52022-06-24 13:40:42 +08005508+ debugfs_create_u8("sku_disable", 0600, dir, &dev->dbg.sku_disable);
5509+
developer3fa816c2022-04-19 10:21:20 +08005510+ return 0;
5511+}
5512+#endif
5513diff --git a/mt7915/mtk_mcu.c b/mt7915/mtk_mcu.c
5514new file mode 100644
developer36fe7092023-09-27 12:24:47 +08005515index 00000000..143dae26
developer3fa816c2022-04-19 10:21:20 +08005516--- /dev/null
5517+++ b/mt7915/mtk_mcu.c
5518@@ -0,0 +1,51 @@
5519+#include <linux/firmware.h>
5520+#include <linux/fs.h>
5521+#include<linux/inet.h>
5522+#include "mt7915.h"
5523+#include "mcu.h"
5524+#include "mac.h"
5525+
5526+int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level)
5527+{
5528+ struct mt7915_dev *dev = phy->dev;
5529+ struct mt7915_sku_val {
5530+ u8 format_id;
5531+ u8 val;
5532+ u8 band;
5533+ u8 _rsv;
5534+ } __packed req = {
5535+ .format_id = 1,
developer2458e702022-12-13 15:52:04 +08005536+ .band = phy->mt76->band_idx,
developer3fa816c2022-04-19 10:21:20 +08005537+ .val = !!drop_level,
5538+ };
5539+ int ret;
5540+
5541+ ret = mt76_mcu_send_msg(&dev->mt76,
5542+ MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
5543+ sizeof(req), true);
5544+ if (ret)
5545+ return ret;
5546+
5547+ req.format_id = 2;
5548+ if ((drop_level > 90 && drop_level < 100) || !drop_level)
5549+ req.val = 0;
5550+ else if (drop_level > 60 && drop_level <= 90)
5551+ /* reduce Pwr for 1 dB. */
5552+ req.val = 2;
5553+ else if (drop_level > 30 && drop_level <= 60)
5554+ /* reduce Pwr for 3 dB. */
5555+ req.val = 6;
5556+ else if (drop_level > 15 && drop_level <= 30)
5557+ /* reduce Pwr for 6 dB. */
5558+ req.val = 12;
5559+ else if (drop_level > 9 && drop_level <= 15)
5560+ /* reduce Pwr for 9 dB. */
5561+ req.val = 18;
5562+ else if (drop_level > 0 && drop_level <= 9)
5563+ /* reduce Pwr for 12 dB. */
5564+ req.val = 24;
5565+
5566+ return mt76_mcu_send_msg(&dev->mt76,
5567+ MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
5568+ sizeof(req), true);
5569+}
5570diff --git a/tools/fwlog.c b/tools/fwlog.c
developer36fe7092023-09-27 12:24:47 +08005571index e5d4a105..3d51d9ec 100644
developer3fa816c2022-04-19 10:21:20 +08005572--- a/tools/fwlog.c
5573+++ b/tools/fwlog.c
5574@@ -26,7 +26,7 @@ static const char *debugfs_path(const char *phyname, const char *file)
5575 return path;
5576 }
5577
5578-static int mt76_set_fwlog_en(const char *phyname, bool en)
5579+static int mt76_set_fwlog_en(const char *phyname, bool en, char *val)
5580 {
5581 FILE *f = fopen(debugfs_path(phyname, "fw_debug_bin"), "w");
5582
5583@@ -35,7 +35,13 @@ static int mt76_set_fwlog_en(const char *phyname, bool en)
5584 return 1;
5585 }
5586
5587- fprintf(f, "7");
5588+ if (en && val)
5589+ fprintf(f, "%s", val);
5590+ else if (en)
5591+ fprintf(f, "7");
5592+ else
5593+ fprintf(f, "0");
5594+
5595 fclose(f);
5596
5597 return 0;
5598@@ -76,6 +82,7 @@ static void handle_signal(int sig)
5599
5600 int mt76_fwlog(const char *phyname, int argc, char **argv)
5601 {
5602+#define BUF_SIZE 1504
5603 struct sockaddr_in local = {
5604 .sin_family = AF_INET,
5605 .sin_addr.s_addr = INADDR_ANY,
developerf32dabf2022-06-01 10:59:24 +08005606@@ -84,9 +91,10 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
developer3fa816c2022-04-19 10:21:20 +08005607 .sin_family = AF_INET,
5608 .sin_port = htons(55688),
5609 };
5610- char buf[1504];
5611+ char *buf = calloc(BUF_SIZE, sizeof(char));
developerf32dabf2022-06-01 10:59:24 +08005612+ FILE *logfile = NULL;
developer3fa816c2022-04-19 10:21:20 +08005613 int ret = 0;
5614- int yes = 1;
5615+ /* int yes = 1; */
5616 int s, fd;
5617
5618 if (argc < 1) {
developerf32dabf2022-06-01 10:59:24 +08005619@@ -99,19 +107,28 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
5620 return 1;
5621 }
5622
5623+ if (argc == 3) {
5624+ fprintf(stdout, "start logging to file %s\n", argv[2]);
5625+ logfile = fopen(argv[2], "wb");
5626+ if (!logfile) {
5627+ perror("fopen");
5628+ return 1;
5629+ }
5630+ }
5631+
5632 s = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP);
5633 if (s < 0) {
5634 perror("socket");
developer3fa816c2022-04-19 10:21:20 +08005635 return 1;
5636 }
5637
5638- setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes));
5639+ /* setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes)); */
5640 if (bind(s, (struct sockaddr *)&local, sizeof(local)) < 0) {
5641 perror("bind");
5642 return 1;
5643 }
5644
5645- if (mt76_set_fwlog_en(phyname, true))
5646+ if (mt76_set_fwlog_en(phyname, true, argv[1]))
5647 return 1;
5648
5649 fd = open(debugfs_path(phyname, "fwlog_data"), O_RDONLY);
developerf32dabf2022-06-01 10:59:24 +08005650@@ -145,8 +162,8 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
developer3fa816c2022-04-19 10:21:20 +08005651 if (!r)
5652 continue;
5653
5654- if (len > sizeof(buf)) {
5655- fprintf(stderr, "Length error: %d > %d\n", len, (int)sizeof(buf));
5656+ if (len > BUF_SIZE) {
5657+ fprintf(stderr, "Length error: %d > %d\n", len, BUF_SIZE);
5658 ret = 1;
5659 break;
5660 }
developerf32dabf2022-06-01 10:59:24 +08005661@@ -164,14 +181,19 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
5662 break;
5663 }
5664
5665- /* send buf */
5666- sendto(s, buf, len, 0, (struct sockaddr *)&remote, sizeof(remote));
5667+ if (logfile)
5668+ fwrite(buf, 1, len, logfile);
5669+ else
5670+ /* send buf */
5671+ sendto(s, buf, len, 0, (struct sockaddr *)&remote, sizeof(remote));
5672 }
5673
developer3fa816c2022-04-19 10:21:20 +08005674 close(fd);
5675
5676 out:
5677- mt76_set_fwlog_en(phyname, false);
5678+ mt76_set_fwlog_en(phyname, false, NULL);
5679+ free(buf);
developerf32dabf2022-06-01 10:59:24 +08005680+ fclose(logfile);
developer3fa816c2022-04-19 10:21:20 +08005681
5682 return ret;
5683 }
5684--
developerdfb50982023-09-11 13:34:36 +080056852.18.0
developer3fa816c2022-04-19 10:21:20 +08005686