blob: aa3146dd488798775a4caa94103cd1ded2352fdf [file] [log] [blame]
developer004e50c2023-06-29 20:33:22 +08001From 99a1f11d07da770d1da5278ac751ccc3f44eb72f Mon Sep 17 00:00:00 2001
developeraace7f52022-06-24 13:40:42 +08002From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Wed, 22 Jun 2022 10:39:47 +0800
developer004e50c2023-06-29 20:33:22 +08004Subject: [PATCH 0999/1031] wifi: mt76: mt7915: add mtk internal debug tools
5 for mt76
developer3fa816c2022-04-19 10:21:20 +08006
7---
developerf3f5d9b2023-02-07 15:24:34 +08008 mt76_connac_mcu.h | 6 +
developer27b55252022-09-05 19:09:45 +08009 mt7915/Makefile | 2 +-
developerd5789dc2023-03-27 11:22:06 +080010 mt7915/debugfs.c | 89 +-
developer27b55252022-09-05 19:09:45 +080011 mt7915/mac.c | 14 +
12 mt7915/main.c | 4 +
developerf3f5d9b2023-02-07 15:24:34 +080013 mt7915/mcu.c | 48 +-
developer27b55252022-09-05 19:09:45 +080014 mt7915/mcu.h | 4 +
developer5eddc512023-02-13 16:01:56 +080015 mt7915/mt7915.h | 43 +
developera43cc482023-04-17 15:57:28 +080016 mt7915/mt7915_debug.h | 1418 ++++++++++++++++
developer8e5fecd2023-05-30 11:58:00 +080017 mt7915/mtk_debugfs.c | 3624 +++++++++++++++++++++++++++++++++++++++++
developer27b55252022-09-05 19:09:45 +080018 mt7915/mtk_mcu.c | 51 +
19 tools/fwlog.c | 44 +-
developer8e5fecd2023-05-30 11:58:00 +080020 12 files changed, 5328 insertions(+), 19 deletions(-)
developer27b55252022-09-05 19:09:45 +080021 create mode 100644 mt7915/mt7915_debug.h
22 create mode 100644 mt7915/mtk_debugfs.c
23 create mode 100644 mt7915/mtk_mcu.c
developer3fa816c2022-04-19 10:21:20 +080024
25diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
developer004e50c2023-06-29 20:33:22 +080026index bd0bf4b..ab3b58e 100644
developer3fa816c2022-04-19 10:21:20 +080027--- a/mt76_connac_mcu.h
28+++ b/mt76_connac_mcu.h
developer004e50c2023-06-29 20:33:22 +080029@@ -1151,6 +1151,7 @@ enum {
developer9e5bcc52022-09-27 10:30:15 +080030 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
31 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
32 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
33+ MCU_EXT_CMD_MEC_CTRL = 0x1f,
34 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
35 MCU_EXT_CMD_THERMAL_PROT = 0x23,
36 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
developer004e50c2023-06-29 20:33:22 +080037@@ -1174,6 +1175,11 @@ enum {
developer3fa816c2022-04-19 10:21:20 +080038 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
39 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
40 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
41+#ifdef MTK_DEBUG
developer3fa816c2022-04-19 10:21:20 +080042+ MCU_EXT_CMD_RED_SHOW_STA = 0x69,
43+ MCU_EXT_CMD_RED_TARGET_DELAY = 0x6A,
44+ MCU_EXT_CMD_RED_TX_RPT = 0x6B,
45+#endif
46 MCU_EXT_CMD_TXDPD_CAL = 0x60,
47 MCU_EXT_CMD_CAL_CACHE = 0x67,
developerf3f5d9b2023-02-07 15:24:34 +080048 MCU_EXT_CMD_RED_ENABLE = 0x68,
developer3fa816c2022-04-19 10:21:20 +080049diff --git a/mt7915/Makefile b/mt7915/Makefile
developer004e50c2023-06-29 20:33:22 +080050index c4dca9c..fd71141 100644
developer3fa816c2022-04-19 10:21:20 +080051--- a/mt7915/Makefile
52+++ b/mt7915/Makefile
developerf3f5d9b2023-02-07 15:24:34 +080053@@ -4,7 +4,7 @@ EXTRA_CFLAGS += -DCONFIG_MT76_LEDS
developer3fa816c2022-04-19 10:21:20 +080054 obj-$(CONFIG_MT7915E) += mt7915e.o
55
56 mt7915e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
57- debugfs.o mmio.o
58+ debugfs.o mmio.o mtk_debugfs.o mtk_mcu.o
59
60 mt7915e-$(CONFIG_NL80211_TESTMODE) += testmode.o
developerad9333b2023-05-22 15:16:16 +080061 mt7915e-$(CONFIG_MT798X_WMAC) += soc.o
developer3fa816c2022-04-19 10:21:20 +080062diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c
developer004e50c2023-06-29 20:33:22 +080063index 6c3696c..d66d104 100644
developer3fa816c2022-04-19 10:21:20 +080064--- a/mt7915/debugfs.c
65+++ b/mt7915/debugfs.c
66@@ -8,6 +8,9 @@
67 #include "mac.h"
68
69 #define FW_BIN_LOG_MAGIC 0x44e98caf
70+#ifdef MTK_DEBUG
71+#define FW_BIN_LOG_MAGIC_V2 0x44d9c99a
72+#endif
73
74 /** global debugfs **/
75
developer004e50c2023-06-29 20:33:22 +080076@@ -496,6 +499,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080077 int ret;
78
developer42b63282022-06-16 13:33:13 +080079 dev->fw.debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
developer3fa816c2022-04-19 10:21:20 +080080+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +080081+ dev->fw.debug_wm = val;
developer3fa816c2022-04-19 10:21:20 +080082+#endif
83
developer42b63282022-06-16 13:33:13 +080084 if (dev->fw.debug_bin)
developer3fa816c2022-04-19 10:21:20 +080085 val = 16;
developer004e50c2023-06-29 20:33:22 +080086@@ -520,6 +526,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080087 if (ret)
developer42b63282022-06-16 13:33:13 +080088 goto out;
developer3fa816c2022-04-19 10:21:20 +080089 }
90+#ifdef MTK_DEBUG
91+ mt7915_mcu_fw_dbg_ctrl(dev, 68, !!val);
92+#endif
93
94 /* WM CPU info record control */
95 mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0));
developer004e50c2023-06-29 20:33:22 +080096@@ -527,6 +536,12 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080097 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5));
98 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5));
99
100+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +0800101+ if (dev->fw.debug_bin & BIT(3))
developer3fa816c2022-04-19 10:21:20 +0800102+ /* use bit 7 to indicate v2 magic number */
developer42b63282022-06-16 13:33:13 +0800103+ dev->fw.debug_wm |= BIT(7);
developer3fa816c2022-04-19 10:21:20 +0800104+#endif
105+
developer42b63282022-06-16 13:33:13 +0800106 out:
107 if (ret)
108 dev->fw.debug_wm = 0;
developer004e50c2023-06-29 20:33:22 +0800109@@ -539,7 +554,11 @@ mt7915_fw_debug_wm_get(void *data, u64 *val)
developer3fa816c2022-04-19 10:21:20 +0800110 {
111 struct mt7915_dev *dev = data;
112
developer42b63282022-06-16 13:33:13 +0800113- *val = dev->fw.debug_wm;
developer3fa816c2022-04-19 10:21:20 +0800114+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +0800115+ *val = dev->fw.debug_wm & ~BIT(7);
developer3fa816c2022-04-19 10:21:20 +0800116+#else
developer42b63282022-06-16 13:33:13 +0800117+ val = dev->fw.debug_wm;
developer3fa816c2022-04-19 10:21:20 +0800118+#endif
119
120 return 0;
121 }
developer004e50c2023-06-29 20:33:22 +0800122@@ -614,16 +633,30 @@ mt7915_fw_debug_bin_set(void *data, u64 val)
developerd5789dc2023-03-27 11:22:06 +0800123 };
124 struct mt7915_dev *dev = data;
125
126- if (!dev->relay_fwlog)
127+ if (!dev->relay_fwlog && val) {
128 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir,
129 1500, 512, &relay_cb, NULL);
130- if (!dev->relay_fwlog)
131- return -ENOMEM;
132+ if (!dev->relay_fwlog)
133+ return -ENOMEM;
134+ }
135
136 dev->fw.debug_bin = val;
developer3fa816c2022-04-19 10:21:20 +0800137
138 relay_reset(dev->relay_fwlog);
139
140+#ifdef MTK_DEBUG
141+ dev->dbg.dump_mcu_pkt = val & BIT(4) ? true : false;
142+ dev->dbg.dump_txd = val & BIT(5) ? true : false;
143+ dev->dbg.dump_tx_pkt = val & BIT(6) ? true : false;
144+ dev->dbg.dump_rx_pkt = val & BIT(7) ? true : false;
145+ dev->dbg.dump_rx_raw = val & BIT(8) ? true : false;
developer3fa816c2022-04-19 10:21:20 +0800146+#endif
147+
developerd5789dc2023-03-27 11:22:06 +0800148+ if (dev->relay_fwlog && !val) {
149+ relay_close(dev->relay_fwlog);
150+ dev->relay_fwlog = NULL;
151+ }
developer42b63282022-06-16 13:33:13 +0800152+
153 return mt7915_fw_debug_wm_set(dev, dev->fw.debug_wm);
developer3fa816c2022-04-19 10:21:20 +0800154 }
155
developer004e50c2023-06-29 20:33:22 +0800156@@ -1249,6 +1282,11 @@ int mt7915_init_debugfs(struct mt7915_phy *phy)
developer3fa816c2022-04-19 10:21:20 +0800157 if (!ext_phy)
158 dev->debugfs_dir = dir;
159
160+#ifdef MTK_DEBUG
161+ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
162+ mt7915_mtk_init_debugfs(phy, dir);
163+#endif
164+
165 return 0;
166 }
167
developer004e50c2023-06-29 20:33:22 +0800168@@ -1261,6 +1299,12 @@ mt7915_debugfs_write_fwlog(struct mt7915_dev *dev, const void *hdr, int hdrlen,
developerd5789dc2023-03-27 11:22:06 +0800169 void *dest;
170
171 spin_lock_irqsave(&lock, flags);
172+
173+ if (!dev->relay_fwlog) {
174+ spin_unlock_irqrestore(&lock, flags);
175+ return;
176+ }
177+
178 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4);
179 if (dest) {
180 *(u32 *)dest = hdrlen + len;
developer004e50c2023-06-29 20:33:22 +0800181@@ -1289,17 +1333,50 @@ void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int
developer3fa816c2022-04-19 10:21:20 +0800182 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),
183 };
184
developerd5789dc2023-03-27 11:22:06 +0800185- if (!dev->relay_fwlog)
186- return;
developer3fa816c2022-04-19 10:21:20 +0800187+#ifdef MTK_DEBUG
188+ struct {
189+ __le32 magic;
190+ u8 version;
191+ u8 _rsv;
192+ __le16 serial_id;
193+ __le32 timestamp;
194+ __le16 msg_type;
195+ __le16 len;
196+ } hdr2 = {
197+ .version = 0x1,
198+ .magic = cpu_to_le32(FW_BIN_LOG_MAGIC_V2),
199+ .msg_type = PKT_TYPE_RX_FW_MONITOR,
200+ };
201+#endif
developer3fa816c2022-04-19 10:21:20 +0800202
203+#ifdef MTK_DEBUG
204+ /* old magic num */
developer42b63282022-06-16 13:33:13 +0800205+ if (!(dev->fw.debug_wm & BIT(7))) {
developer3fa816c2022-04-19 10:21:20 +0800206+ hdr.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
207+ hdr.len = *(__le16 *)data;
208+ mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
209+ } else {
210+ hdr2.serial_id = dev->dbg.fwlog_seq++;
211+ hdr2.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
212+ hdr2.len = *(__le16 *)data;
213+ mt7915_debugfs_write_fwlog(dev, &hdr2, sizeof(hdr2), data, len);
214+ }
215+#else
216 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
217 hdr.len = *(__le16 *)data;
218 mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
219+#endif
220 }
221
222 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len)
223 {
224+#ifdef MTK_DEBUG
225+ if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC &&
226+ get_unaligned_le32(data) != FW_BIN_LOG_MAGIC_V2 &&
227+ get_unaligned_le32(data) != PKT_BIN_DEBUG_MAGIC)
228+#else
229 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC)
230+#endif
231 return false;
232
233 if (dev->relay_fwlog)
234diff --git a/mt7915/mac.c b/mt7915/mac.c
developer004e50c2023-06-29 20:33:22 +0800235index 67e7b26..99cbabd 100644
developer3fa816c2022-04-19 10:21:20 +0800236--- a/mt7915/mac.c
237+++ b/mt7915/mac.c
developerad9333b2023-05-22 15:16:16 +0800238@@ -275,6 +275,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb,
developer3fa816c2022-04-19 10:21:20 +0800239 __le16 fc = 0;
240 int idx;
241
242+#ifdef MTK_DEBUG
243+ if (dev->dbg.dump_rx_raw)
244+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX_RAW, 0);
245+#endif
246 memset(status, 0, sizeof(*status));
247
developer2458e702022-12-13 15:52:04 +0800248 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->mt76->band_idx) {
developer004e50c2023-06-29 20:33:22 +0800249@@ -459,6 +463,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb,
developer3fa816c2022-04-19 10:21:20 +0800250 }
251
252 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
253+#ifdef MTK_DEBUG
254+ if (dev->dbg.dump_rx_pkt)
255+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX, hdr_gap);
256+#endif
257 if (hdr_trans && ieee80211_has_morefrags(fc)) {
developeraace7f52022-06-24 13:40:42 +0800258 struct ieee80211_vif *vif;
259 int err;
developer004e50c2023-06-29 20:33:22 +0800260@@ -796,6 +804,12 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developer3fa816c2022-04-19 10:21:20 +0800261 tx_info->buf[1].skip_unmap = true;
262 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
263
264+#ifdef MTK_DEBUG
265+ if (dev->dbg.dump_txd)
266+ mt7915_packet_log_to_host(dev, txwi, MT_TXD_SIZE, PKT_BIN_DEBUG_TXD, 0);
267+ if (dev->dbg.dump_tx_pkt)
268+ mt7915_packet_log_to_host(dev, t->skb->data, t->skb->len, PKT_BIN_DEBUG_TX, 0);
269+#endif
270 return 0;
271 }
272
developeraace7f52022-06-24 13:40:42 +0800273diff --git a/mt7915/main.c b/mt7915/main.c
developer004e50c2023-06-29 20:33:22 +0800274index 251df80..cc4ac94 100644
developeraace7f52022-06-24 13:40:42 +0800275--- a/mt7915/main.c
276+++ b/mt7915/main.c
developer2aa1e642022-12-19 11:33:22 +0800277@@ -73,7 +73,11 @@ int mt7915_run(struct ieee80211_hw *hw)
developeraace7f52022-06-24 13:40:42 +0800278 if (ret)
279 goto out;
280
281+#ifdef MTK_DEBUG
282+ ret = mt7915_mcu_set_sku_en(phy, !dev->dbg.sku_disable);
283+#else
284 ret = mt7915_mcu_set_sku_en(phy, true);
285+#endif
286 if (ret)
287 goto out;
288
developer3fa816c2022-04-19 10:21:20 +0800289diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developer004e50c2023-06-29 20:33:22 +0800290index 6cf2a3f..fbbd848 100644
developer3fa816c2022-04-19 10:21:20 +0800291--- a/mt7915/mcu.c
292+++ b/mt7915/mcu.c
developer004e50c2023-06-29 20:33:22 +0800293@@ -205,6 +205,11 @@ mt7915_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
developeraace7f52022-06-24 13:40:42 +0800294 else
295 qid = MT_MCUQ_WM;
developer3fa816c2022-04-19 10:21:20 +0800296
developer3fa816c2022-04-19 10:21:20 +0800297+#ifdef MTK_DEBUG
298+ if (dev->dbg.dump_mcu_pkt)
299+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_MCU, 0);
300+#endif
developeraace7f52022-06-24 13:40:42 +0800301+
302 return mt76_tx_queue_skb_raw(dev, mdev->q_mcu[qid], skb, 0);
303 }
304
developer004e50c2023-06-29 20:33:22 +0800305@@ -2285,7 +2290,10 @@ static int mt7915_red_set_watermark(struct mt7915_dev *dev)
developerf3f5d9b2023-02-07 15:24:34 +0800306 sizeof(req), false);
307 }
308
309-static int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled)
310+#ifndef MTK_DEBUG
311+static
312+#endif
313+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled)
314 {
315 #define RED_DISABLE 0
316 #define RED_BY_WA_ENABLE 2
developer004e50c2023-06-29 20:33:22 +0800317@@ -3349,6 +3357,8 @@ int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable)
developeraace7f52022-06-24 13:40:42 +0800318 .sku_enable = enable,
319 };
developer3fa816c2022-04-19 10:21:20 +0800320
developeraace7f52022-06-24 13:40:42 +0800321+ pr_info("%s: enable = %d\n", __func__, enable);
322+
323 return mt76_mcu_send_msg(&dev->mt76,
324 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
325 sizeof(req), true);
developer004e50c2023-06-29 20:33:22 +0800326@@ -4003,6 +4013,23 @@ out:
327 return ret;
developer3fa816c2022-04-19 10:21:20 +0800328 }
developer1eeb8e82022-05-03 14:10:10 +0800329
developer3fa816c2022-04-19 10:21:20 +0800330+#ifdef MTK_DEBUG
331+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp)
332+{
333+ struct {
334+ __le32 args[3];
335+ } req = {
336+ .args = {
337+ cpu_to_le32(a1),
338+ cpu_to_le32(a2),
339+ cpu_to_le32(a3),
340+ },
341+ };
342+
343+ return mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), wait_resp);
344+}
developer3fa816c2022-04-19 10:21:20 +0800345+#endif
developer1eeb8e82022-05-03 14:10:10 +0800346+
347 int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set)
348 {
349 struct {
developer004e50c2023-06-29 20:33:22 +0800350@@ -4031,3 +4058,22 @@ int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set)
developer9e5bcc52022-09-27 10:30:15 +0800351
352 return 0;
353 }
354+
355+#ifdef MTK_DEBUG
356+int mt7915_mcu_set_amsdu_algo(struct mt7915_dev *dev, u16 wcid, u8 enable)
357+{
358+ struct {
359+ u16 action;
360+ u8 _rsv1[2];
361+ u16 wcid;
362+ u8 enable;
363+ u8 _rsv2[5];
364+ } __packed req = {
365+ .action = cpu_to_le16(1),
366+ .wcid = cpu_to_le16(wcid),
367+ .enable = enable,
368+ };
369+
370+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MEC_CTRL), &req, sizeof(req), true);
371+}
372+#endif
developer3fa816c2022-04-19 10:21:20 +0800373diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developer004e50c2023-06-29 20:33:22 +0800374index aebacc7..daea67f 100644
developer3fa816c2022-04-19 10:21:20 +0800375--- a/mt7915/mcu.h
376+++ b/mt7915/mcu.h
developerad9333b2023-05-22 15:16:16 +0800377@@ -333,6 +333,10 @@ enum {
developer3fa816c2022-04-19 10:21:20 +0800378 MCU_WA_PARAM_PDMA_RX = 0x04,
379 MCU_WA_PARAM_CPU_UTIL = 0x0b,
380 MCU_WA_PARAM_RED = 0x0e,
381+#ifdef MTK_DEBUG
382+ MCU_WA_PARAM_RED_SHOW_STA = 0xf,
383+ MCU_WA_PARAM_RED_TARGET_DELAY = 0x10,
384+#endif
developerf3f5d9b2023-02-07 15:24:34 +0800385 MCU_WA_PARAM_RED_SETTING = 0x40,
developer3fa816c2022-04-19 10:21:20 +0800386 };
387
developer3fa816c2022-04-19 10:21:20 +0800388diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developer004e50c2023-06-29 20:33:22 +0800389index 4de3e05..b5e7c86 100644
developer3fa816c2022-04-19 10:21:20 +0800390--- a/mt7915/mt7915.h
391+++ b/mt7915/mt7915.h
392@@ -9,6 +9,7 @@
393 #include "../mt76_connac.h"
394 #include "regs.h"
395
396+#define MTK_DEBUG 1
397 #define MT7915_MAX_INTERFACES 19
developer3fa816c2022-04-19 10:21:20 +0800398 #define MT7915_WTBL_SIZE 288
developeraace7f52022-06-24 13:40:42 +0800399 #define MT7916_WTBL_SIZE 544
developer004e50c2023-06-29 20:33:22 +0800400@@ -305,6 +306,28 @@ struct mt7915_dev {
developer3fa816c2022-04-19 10:21:20 +0800401 struct reset_control *rstc;
402 void __iomem *dcm;
403 void __iomem *sku;
404+
405+#ifdef MTK_DEBUG
406+ u16 wlan_idx;
407+ struct {
408+ u32 fixed_rate;
409+ u32 l1debugfs_reg;
410+ u32 l2debugfs_reg;
411+ u32 mac_reg;
412+ u32 fw_dbg_module;
413+ u8 fw_dbg_lv;
414+ u32 bcn_total_cnt[2];
415+ u16 fwlog_seq;
416+ bool dump_mcu_pkt;
417+ bool dump_txd;
418+ bool dump_tx_pkt;
419+ bool dump_rx_pkt;
420+ bool dump_rx_raw;
421+ u32 token_idx;
developeraace7f52022-06-24 13:40:42 +0800422+ u8 sku_disable;
developer3fa816c2022-04-19 10:21:20 +0800423+ } dbg;
424+ const struct mt7915_dbg_reg_desc *dbg_reg;
425+#endif
426 };
427
428 enum {
developer004e50c2023-06-29 20:33:22 +0800429@@ -585,4 +608,24 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developerf1313102022-10-11 11:02:55 +0800430 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
431 bool pci, int *irq);
developer3fa816c2022-04-19 10:21:20 +0800432
433+#ifdef MTK_DEBUG
434+int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir);
435+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp);
436+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled);
437+void mt7915_dump_tmac_info(u8 *tmac_info);
438+int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level);
439+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len);
developer9e5bcc52022-09-27 10:30:15 +0800440+int mt7915_mcu_set_amsdu_algo(struct mt7915_dev *dev, u16 wcid, u8 enable);
developer3fa816c2022-04-19 10:21:20 +0800441+
442+#define PKT_BIN_DEBUG_MAGIC 0xc8763123
443+enum {
444+ PKT_BIN_DEBUG_MCU,
445+ PKT_BIN_DEBUG_TXD,
446+ PKT_BIN_DEBUG_TX,
447+ PKT_BIN_DEBUG_RX,
448+ PKT_BIN_DEBUG_RX_RAW,
449+};
450+
451+#endif
452+
453 #endif
454diff --git a/mt7915/mt7915_debug.h b/mt7915/mt7915_debug.h
455new file mode 100644
developer004e50c2023-06-29 20:33:22 +0800456index 0000000..fa8794f
developer3fa816c2022-04-19 10:21:20 +0800457--- /dev/null
458+++ b/mt7915/mt7915_debug.h
developera43cc482023-04-17 15:57:28 +0800459@@ -0,0 +1,1418 @@
developer3fa816c2022-04-19 10:21:20 +0800460+#ifndef __MT7915_DEBUG_H
461+#define __MT7915_DEBUG_H
462+
463+#ifdef MTK_DEBUG
464+
465+#define DBG_INVALID_BASE 0xffffffff
466+#define DBG_INVALID_OFFSET 0x0
467+
468+struct __dbg_map {
469+ u32 phys;
470+ u32 maps;
471+ u32 size;
472+};
473+
474+struct __dbg_reg {
475+ u32 base;
476+ u32 offs;
477+};
478+
479+struct __dbg_mask {
480+ u32 end;
481+ u32 start;
482+};
483+
484+enum dbg_base_rev {
485+ MT_DBG_WFDMA0_BASE,
486+ MT_DBG_WFDMA1_BASE,
487+ MT_DBG_WFDMA0_PCIE1_BASE,
488+ MT_DBG_WFDMA1_PCIE1_BASE,
489+ MT_DBG_WFDMA_EXT_CSR_BASE,
490+ MT_DBG_SWDEF_BASE,
491+ __MT_DBG_BASE_REV_MAX,
492+};
493+
494+enum dbg_reg_rev {
495+ DBG_INT_SOURCE_CSR,
496+ DBG_INT_MASK_CSR,
497+ DBG_INT1_SOURCE_CSR,
498+ DBG_INT1_MASK_CSR,
499+ DBG_TX_RING_BASE,
500+ DBG_RX_EVENT_RING_BASE,
501+ DBG_RX_STS_RING_BASE,
502+ DBG_RX_DATA_RING_BASE,
503+ DBG_DMA_ICSC_FR0,
504+ DBG_DMA_ICSC_FR1,
505+ DBG_TMAC_ICSCR0,
506+ DBG_RMAC_RXICSRPT,
507+ DBG_MIB_M0SDR0,
508+ DBG_MIB_M0SDR3,
509+ DBG_MIB_M0SDR4,
510+ DBG_MIB_M0SDR5,
511+ DBG_MIB_M0SDR7,
512+ DBG_MIB_M0SDR8,
513+ DBG_MIB_M0SDR9,
514+ DBG_MIB_M0SDR10,
515+ DBG_MIB_M0SDR11,
516+ DBG_MIB_M0SDR12,
517+ DBG_MIB_M0SDR14,
518+ DBG_MIB_M0SDR15,
519+ DBG_MIB_M0SDR16,
520+ DBG_MIB_M0SDR17,
521+ DBG_MIB_M0SDR18,
522+ DBG_MIB_M0SDR19,
523+ DBG_MIB_M0SDR20,
524+ DBG_MIB_M0SDR21,
525+ DBG_MIB_M0SDR22,
526+ DBG_MIB_M0SDR23,
527+ DBG_MIB_M0DR0,
528+ DBG_MIB_M0DR1,
529+ DBG_MIB_MUBF,
530+ DBG_MIB_M0DR6,
531+ DBG_MIB_M0DR7,
532+ DBG_MIB_M0DR8,
533+ DBG_MIB_M0DR9,
534+ DBG_MIB_M0DR10,
535+ DBG_MIB_M0DR11,
536+ DBG_MIB_M0DR12,
537+ DBG_WTBLON_WDUCR,
538+ DBG_UWTBL_WDUCR,
539+ DBG_PLE_DRR_TABLE_CTRL,
540+ DBG_PLE_DRR_TABLE_RDATA,
541+ DBG_PLE_PBUF_CTRL,
542+ DBG_PLE_QUEUE_EMPTY,
543+ DBG_PLE_FREEPG_CNT,
544+ DBG_PLE_FREEPG_HEAD_TAIL,
545+ DBG_PLE_PG_HIF_GROUP,
546+ DBG_PLE_HIF_PG_INFO,
547+ DBG_PLE_PG_HIF_TXCMD_GROUP,
548+ DBG_PLE_HIF_TXCMD_PG_INFO,
549+ DBG_PLE_PG_CPU_GROUP,
550+ DBG_PLE_CPU_PG_INFO,
551+ DBG_PLE_FL_QUE_CTRL,
552+ DBG_PLE_NATIVE_TXCMD_Q_EMPTY,
553+ DBG_PLE_TXCMD_Q_EMPTY,
554+ DBG_PLE_AC_QEMPTY,
555+ DBG_PLE_AC_OFFSET,
556+ DBG_PLE_STATION_PAUSE,
557+ DBG_PLE_DIS_STA_MAP,
558+ DBG_PSE_PBUF_CTRL,
559+ DBG_PSE_FREEPG_CNT,
560+ DBG_PSE_FREEPG_HEAD_TAIL,
561+ DBG_PSE_HIF0_PG_INFO,
562+ DBG_PSE_PG_HIF1_GROUP,
563+ DBG_PSE_HIF1_PG_INFO,
564+ DBG_PSE_PG_CPU_GROUP,
565+ DBG_PSE_CPU_PG_INFO,
566+ DBG_PSE_PG_PLE_GROUP,
567+ DBG_PSE_PLE_PG_INFO,
568+ DBG_PSE_PG_LMAC0_GROUP,
569+ DBG_PSE_LMAC0_PG_INFO,
570+ DBG_PSE_PG_LMAC1_GROUP,
571+ DBG_PSE_LMAC1_PG_INFO,
572+ DBG_PSE_PG_LMAC2_GROUP,
573+ DBG_PSE_LMAC2_PG_INFO,
574+ DBG_PSE_PG_LMAC3_GROUP,
575+ DBG_PSE_LMAC3_PG_INFO,
576+ DBG_PSE_PG_MDP_GROUP,
577+ DBG_PSE_MDP_PG_INFO,
578+ DBG_PSE_PG_PLE1_GROUP,
579+ DBG_PSE_PLE1_PG_INFO,
580+ DBG_AGG_AALCR0,
581+ DBG_AGG_AALCR1,
582+ DBG_AGG_AALCR2,
583+ DBG_AGG_AALCR3,
584+ DBG_AGG_AALCR4,
585+ DBG_AGG_B0BRR0,
586+ DBG_AGG_B1BRR0,
587+ DBG_AGG_B2BRR0,
588+ DBG_AGG_B3BRR0,
589+ DBG_AGG_AWSCR0,
590+ DBG_AGG_PCR0,
591+ DBG_AGG_TTCR0,
592+ DBG_MIB_M0ARNG0,
593+ DBG_MIB_M0DR2,
594+ DBG_MIB_M0DR13,
developer79a21a22023-01-09 13:57:39 +0800595+ DBG_WFDMA_WED_TX_CTRL,
596+ DBG_WFDMA_WED_RX_CTRL,
developer3fa816c2022-04-19 10:21:20 +0800597+ __MT_DBG_REG_REV_MAX,
598+};
599+
600+enum dbg_mask_rev {
601+ DBG_MIB_M0SDR10_RX_MDRDY_COUNT,
602+ DBG_MIB_M0SDR14_AMPDU,
603+ DBG_MIB_M0SDR15_AMPDU_ACKED,
604+ DBG_MIB_RX_FCS_ERROR_COUNT,
605+ __MT_DBG_MASK_REV_MAX,
606+};
607+
608+enum dbg_bit_rev {
609+ __MT_DBG_BIT_REV_MAX,
610+};
611+
612+static const u32 mt7915_dbg_base[] = {
613+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
614+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
615+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
616+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
617+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
618+ [MT_DBG_SWDEF_BASE] = 0x41f200,
619+};
620+
621+static const u32 mt7916_dbg_base[] = {
622+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
623+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
624+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
625+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
626+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
627+ [MT_DBG_SWDEF_BASE] = 0x411400,
628+};
629+
630+static const u32 mt7986_dbg_base[] = {
631+ [MT_DBG_WFDMA0_BASE] = 0x24000,
632+ [MT_DBG_WFDMA1_BASE] = 0x25000,
633+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0x28000,
634+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0x29000,
635+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0x27000,
636+ [MT_DBG_SWDEF_BASE] = 0x411400,
637+};
638+
639+/* mt7915 regs with different base and offset */
640+static const struct __dbg_reg mt7915_dbg_reg[] = {
developer79a21a22023-01-09 13:57:39 +0800641+ [DBG_WFDMA_WED_TX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x300 },
642+ [DBG_WFDMA_WED_RX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x400 },
developer3fa816c2022-04-19 10:21:20 +0800643+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x10 },
644+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x14 },
645+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x88 },
646+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x8c },
647+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x400 },
648+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x500 },
649+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x510 },
650+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
651+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x0f0 },
652+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x0f4 },
653+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x200 },
654+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0x618},
655+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x010},
656+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x014},
657+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x018},
658+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x01c},
659+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x024},
660+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x028},
661+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x02C},
662+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x030},
663+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x034},
664+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x038},
665+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x040},
666+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x044},
667+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x048},
668+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x04c},
669+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x050},
670+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x054},
671+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x058},
672+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x05c},
673+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x060},
674+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x064},
675+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x0a0},
676+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x0a4},
677+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x090},
678+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x0b8},
679+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x0bc},
680+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x0c0},
681+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x0c4},
682+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x0c8},
683+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x0cc},
684+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x160},
685+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x0},
686+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x0},
687+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x388},
688+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x350},
689+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
690+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x0b0},
691+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
692+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
693+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x110},
694+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x114},
695+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x120},
696+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x124},
697+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
698+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
699+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x1b0},
700+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x22c},
701+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x230},
702+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x500},
703+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x040},
704+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x400},
705+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x440},
developerf32dabf2022-06-01 10:59:24 +0800706+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
developer3fa816c2022-04-19 10:21:20 +0800707+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
708+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
709+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x114},
710+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x118},
711+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x11c},
712+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
713+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
714+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x160},
715+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x164},
716+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x170},
717+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x174},
718+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x178},
719+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
720+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x180},
721+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x184},
722+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x188},
723+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x18c},
724+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x198},
725+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x19c},
726+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x168},
727+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
728+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x048},
729+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x04c},
730+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x050},
731+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x054},
732+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x058},
733+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x100},
734+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x104},
735+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x108},
736+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x10c},
737+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x030},
738+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x040},
739+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x04c},
740+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x4b8},
741+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x0a8},
742+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x164},
743+};
744+
745+/* mt7986/mt7916 regs with different base and offset */
746+static const struct __dbg_reg mt7916_dbg_reg[] = {
developer79a21a22023-01-09 13:57:39 +0800747+ [DBG_WFDMA_WED_TX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x300 },
748+ [DBG_WFDMA_WED_RX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x400 },
developer3fa816c2022-04-19 10:21:20 +0800749+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA0_BASE, 0x200 },
750+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA0_BASE, 0x204 },
751+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x200 },
752+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x204 },
753+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x400 },
754+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
755+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x520 },
756+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x540 },
757+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x05c },
758+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x060 },
759+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x120 },
760+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0xd0 },
761+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x7d8},
762+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x698},
763+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x788},
764+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x780},
765+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x5a8},
766+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x78c},
767+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x024},
768+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x76c},
769+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x790},
770+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x558},
771+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x564},
772+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x564},
773+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x7fc},
774+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x800},
775+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x030},
776+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x5ac},
777+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x5b0},
778+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x5b4},
779+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x770},
780+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x774},
781+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x594},
782+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x598},
783+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x7ac},
784+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x658},
785+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x65c},
786+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x56c},
787+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x570},
788+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x578},
789+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x574},
790+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x654},
791+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x200},
792+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x094},
793+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x490},
794+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x470},
795+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
796+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x360},
797+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
798+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
799+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x00c},
800+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x388},
801+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x014},
802+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x390},
803+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x018},
804+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x394},
805+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x3e0},
806+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x370},
developerf32dabf2022-06-01 10:59:24 +0800807+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x36c},
developer3fa816c2022-04-19 10:21:20 +0800808+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x600},
809+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x080},
810+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x100},
811+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x180},
812+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
813+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
814+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
815+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x150},
816+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x154},
817+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
818+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x118},
819+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x158},
820+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x11c},
821+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x15c},
822+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x124},
823+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x164},
824+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x128},
825+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x168},
826+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x12c},
827+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
828+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x130},
829+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
830+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x134},
831+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x174},
832+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x120},
833+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
834+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x028},
835+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x144},
836+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x14c},
837+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x154},
838+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x02c},
839+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x08c},
840+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x148},
841+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x150},
842+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x158},
843+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x05c},
844+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x06c},
845+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x07c},
846+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x0b0},
847+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x7dc},
848+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x7ec},
849+};
850+
851+static const struct __dbg_mask mt7915_dbg_mask[] = {
852+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {25, 0},
853+ [DBG_MIB_M0SDR14_AMPDU] = {23, 0},
854+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {23, 0},
855+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {15, 0},
856+};
857+
858+static const struct __dbg_mask mt7916_dbg_mask[] = {
859+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {31, 0},
860+ [DBG_MIB_M0SDR14_AMPDU] = {31, 0},
861+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {31, 0},
862+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {31, 16},
863+};
864+
865+/* used to differentiate between generations */
866+struct mt7915_dbg_reg_desc {
867+ const u32 id;
868+ const u32 *base_rev;
869+ const struct __dbg_reg *reg_rev;
870+ const struct __dbg_mask *mask_rev;
871+};
872+
873+static const struct mt7915_dbg_reg_desc dbg_reg_s[] = {
874+ { 0x7915,
875+ mt7915_dbg_base,
876+ mt7915_dbg_reg,
877+ mt7915_dbg_mask
878+ },
879+ { 0x7906,
880+ mt7916_dbg_base,
881+ mt7916_dbg_reg,
882+ mt7916_dbg_mask
883+ },
884+ { 0x7986,
885+ mt7986_dbg_base,
886+ mt7916_dbg_reg,
887+ mt7916_dbg_mask
888+ },
889+};
890+
891+struct bin_debug_hdr {
892+ __le32 magic_num;
893+ __le16 serial_id;
894+ __le16 msg_type;
895+ __le16 len;
896+ __le16 des_len; /* descriptor len for rxd */
897+} __packed;
898+
developera43cc482023-04-17 15:57:28 +0800899+/* fw wm info related strcture */
900+struct cos_msg_trace_t {
901+ u32 dest_id;
902+ u8 msg_id;
903+ u32 pcount;
904+ u32 qread;
905+ u32 ts_enq;
906+ u32 ts_deq;
907+ u32 ts_finshq;
908+};
909+
910+struct cos_task_info_struct {
911+ u32 task_name_ptr;
912+ u32 task_qname_ptr;
913+ u32 task_priority;
914+ u16 task_stack_size;
915+ u8 task_ext_qsize;
916+ u32 task_id;
917+ u32 task_ext_qid;
918+ u32 task_main_func;
919+ u32 task_init_func;
920+};
921+
922+struct cos_program_trace_t{
923+ u32 dest_id;
924+ u32 msg_id;
925+ u32 msg_sn;
926+ u32 ts_gpt2;
927+ u32 LP;
928+ char name[12];
929+} ;
930+
931+struct cos_msg_type {
932+ u32 finish_cnt;
933+ u32 exe_time;
934+ u32 exe_peak;
935+};
936+
937+struct cos_task_type{
938+ u32 tc_stack_start;
939+ u32 tc_stack_end;
940+ u32 tc_stack_pointer;
941+ u32 tc_stack_size;
942+ u32 tc_schedule_count;
943+ u8 tc_status;
944+ u8 tc_priority;
945+ u8 tc_weight;
946+ u8 RSVD[28];
947+ u32 tc_entry_func;
948+ u32 tc_exe_start;
949+ u32 tc_exe_time;
950+ u32 tc_exe_peak;
951+ u32 tc_pcount;
952+};
953+
developer3fa816c2022-04-19 10:21:20 +0800954+#define __DBG_REG_MAP(_dev, id, ofs) ((_dev)->dbg_reg->base_rev[(id)] + (ofs))
955+#define __DBG_REG_BASE(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].base)
956+#define __DBG_REG_OFFS(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].offs)
957+
958+#define __DBG_MASK(_dev, id) GENMASK((_dev)->dbg_reg->mask_rev[(id)].end, \
959+ (_dev)->dbg_reg->mask_rev[(id)].start)
960+#define __DBG_REG(_dev, id) __DBG_REG_MAP((_dev), __DBG_REG_BASE((_dev), (id)), \
961+ __DBG_REG_OFFS((_dev), (id)))
962+
963+#define __DBG_FIELD_GET(id, _reg) (((_reg) & __DBG_MASK(dev, (id))) >> \
964+ dev->dbg_reg->mask_rev[(id)].start)
965+#define __DBG_FIELD_PREP(id, _reg) (((_reg) << dev->dbg_reg->mask_rev[(id)].start) & \
966+ __DBG_MASK(dev, (id)))
967+
968+
969+#define MT_DBG_TX_RING_BASE __DBG_REG(dev, DBG_TX_RING_BASE)
970+#define MT_DBG_RX_EVENT_RING_BASE __DBG_REG(dev, DBG_RX_EVENT_RING_BASE)
971+#define MT_DBG_RX_STS_RING_BASE __DBG_REG(dev, DBG_RX_STS_RING_BASE)
972+#define MT_DBG_RX_DATA_RING_BASE __DBG_REG(dev, DBG_RX_DATA_RING_BASE)
developer79a21a22023-01-09 13:57:39 +0800973+#define MT_DBG_WFDMA_WED_TX_CTRL_BASE __DBG_REG(dev, DBG_WFDMA_WED_TX_CTRL)
974+#define MT_DBG_WFDMA_WED_RX_CTRL_BASE __DBG_REG(dev, DBG_WFDMA_WED_RX_CTRL)
developer3fa816c2022-04-19 10:21:20 +0800975+
976+#define MT_DBG_TX_RING_CTRL(n) (MT_DBG_TX_RING_BASE + (0x10 * (n)))
977+#define MT_DBG_RX_DATA_RING_CTRL(n) (MT_DBG_RX_DATA_RING_BASE + (0x10 * (n)))
978+#define MT_DBG_RX_EVENT_RING_CTRL(n) (MT_DBG_RX_EVENT_RING_BASE + (0x10 * (n)))
979+
developer79a21a22023-01-09 13:57:39 +0800980+#define MT_DBG_WFDMA_WED_TX_CTRL(n) (MT_DBG_WFDMA_WED_TX_CTRL_BASE + (0x10 * (n)))
981+#define MT_DBG_WFDMA_WED_RX_CTRL(n) (MT_DBG_WFDMA_WED_RX_CTRL_BASE + (0x10 * (n)))
developer3fa816c2022-04-19 10:21:20 +0800982+/* WFDMA COMMON */
983+#define MT_DBG_INT_SOURCE_CSR __DBG_REG(dev, DBG_INT_SOURCE_CSR)
984+#define MT_DBG_INT_MASK_CSR __DBG_REG(dev, DBG_INT_MASK_CSR)
985+#define MT_DBG_INT1_SOURCE_CSR __DBG_REG(dev, DBG_INT1_SOURCE_CSR)
986+#define MT_DBG_INT1_MASK_CSR __DBG_REG(dev, DBG_INT1_MASK_CSR)
987+
988+/* WFDMA0 */
989+#define MT_DBG_WFDMA0(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_BASE, (_ofs))
990+
991+#define MT_DBG_WFDMA0_INT_SOURCE_CSR MT_DBG_WFDMA0(0x200)
992+#define MT_DBG_WFDMA0_INT_MASK_CSR MT_DBG_WFDMA0(0x204)
993+
994+#define MT_DBG_WFDMA0_GLO_CFG MT_DBG_WFDMA0(0x208)
995+#define MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
996+#define MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
997+#define MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK BIT(1)
998+#define MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK BIT(3)
999+
1000+
1001+/* WFDMA1 */
1002+#define MT_DBG_WFDMA1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_BASE, (_ofs))
1003+#define MT_DBG_WFDMA1_INT_SOURCE_CSR MT_DBG_WFDMA1(0x200)
1004+#define MT_DBG_WFDMA1_INT_MASK_CSR MT_DBG_WFDMA1(0x204)
1005+
1006+#define MT_DBG_WFDMA1_GLO_CFG MT_DBG_WFDMA1(0x208)
1007+
1008+#define MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
1009+#define MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
1010+#define MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK BIT(1)
1011+#define MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK BIT(3)
1012+
1013+/* WFDMA0 PCIE1 */
1014+#define MT_DBG_WFDMA0_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_PCIE1_BASE, (_ofs))
1015+
1016+#define MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA0_PCIE1(0x200)
1017+#define MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR MT_DBG_WFDMA0_PCIE1(0x204)
1018+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG MT_DBG_WFDMA0_PCIE1(0x208)
1019+#define MT_DBG_WFDMA0_PCIE1_RX1_CTRL0 MT_DBG_WFDMA1_PCIE1(0x510)
1020+
1021+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
1022+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
1023+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
1024+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
1025+
1026+/* WFDMA1 PCIE1 */
1027+#define MT_DBG_WFDMA1_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_PCIE1_BASE, (_ofs))
1028+#define MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA1_PCIE1(0x200)
1029+#define MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR MT_DBG_WFDMA1_PCIE1(0x204)
1030+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG MT_DBG_WFDMA1_PCIE1(0x208)
1031+#define MT_DBG_WFDMA1_PCIE1_TX19_CTRL0 MT_DBG_WFDMA1_PCIE1(0x330)
1032+#define MT_DBG_WFDMA1_PCIE1_RX2_CTRL0 MT_DBG_WFDMA1_PCIE1(0x520)
1033+
1034+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
1035+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
1036+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
1037+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
1038+
1039+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK BIT(2)
1040+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK BIT(0)
1041+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK BIT(3)
1042+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK BIT(1)
1043+
1044+
1045+/* WF DMA TOP: band 0(0x820E7000),band 1(0x820F7000) */
1046+#define MT_DBG_WF_DMA_BASE(_band) ((_band) ? 0x820F7000 : 0x820E7000)
1047+#define MT_DBG_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
1048+
1049+#define MT_DBG_DMA_DCR0(_band) MT_DBG_WF_DMA((_band), 0x000)
1050+#define MT_DBG_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
1051+#define MT_DBG_DMA_DCR0_RXD_G5_EN BIT(23)
1052+
1053+#define MT_DBG_DMA_ICSC_FR0(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR0))
1054+#define MT_DBG_DMA_ICSC_FR0_RXBF_EN BIT(25)
1055+#define MT_DBG_DMA_ICSC_FR0_EN BIT(24)
1056+#define MT_DBG_DMA_ICSC_FR0_TOUT_MASK GENMASK(23, 16)
1057+#define MT_DBG_DMA_ICSC_FR0_PID_MASK GENMASK(9, 8)
1058+#define MT_DBG_DMA_ICSC_FR0_QID_MASK GENMASK(6, 0)
1059+
1060+#define MT_DBG_DMA_ICSC_FR1(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR1))
1061+#define MT_DBG_DMA_ICSC_FR1_AGG_SIZE_MASK GENMASK(26, 16)
1062+#define MT_DBG_DMA_ICSC_FR1_MAX_FRAME_SIZE_MASK GENMASK(10, 0)
1063+
1064+/* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
1065+#define MT_DBG_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
1066+#define MT_DBG_WF_TMAC(_band, ofs) (MT_DBG_WF_TMAC_BASE(_band) + (ofs))
1067+
1068+#define MT_DBG_TMAC_ICSCR0(_band) MT_DBG_WF_TMAC((_band), __DBG_REG_OFFS(dev, DBG_TMAC_ICSCR0))
1069+#define MT_DBG_TMAC_ICSCR0_ICSRPT_EN BIT(0)
1070+
1071+/* RMAC: band 0(0x820E5000), band 1(0x820f5000) */
1072+#define MT_DBG_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820E5000)
1073+#define MT_DBG_WF_RMAC(_band, ofs) (MT_DBG_WF_RMAC_BASE(_band) + (ofs))
1074+
1075+#define MT_DBG_RMAC_RXICSRPT(_band) MT_DBG_WF_RMAC((_band), __DBG_REG_OFFS(dev, DBG_RMAC_RXICSRPT))
1076+#define MT_DBG_RMAC_RXICSRPT_ICSRPT_EN BIT(0)
1077+
1078+/* MIB: band 0(0x820ed000), band 1(0x820fd000) */
1079+#define MT_DBG_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
1080+#define MT_DBG_MIB(_band, ofs) (MT_DBG_MIB_BASE(_band) + (ofs))
1081+
1082+
1083+#define MT_DBG_MIB_M0SCR0(_band) MT_DBG_MIB((_band), 0x00)
1084+#define MT_DBG_MIB_M0PBSCR(_band) MT_DBG_MIB((_band), 0x04)
1085+
1086+#define MT_DBG_MIB_M0SDR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR0))
1087+#define MT_DBG_MIB_M0SDR3(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR3))
1088+#define MT_DBG_MIB_RX_FCS_ERROR_COUNT_MASK __DBG_MASK(dev, DBG_MIB_RX_FCS_ERROR_COUNT)
1089+#define MT_DBG_MIB_M0SDR4(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR4))
1090+#define MT_DBG_MIB_M0SDR5(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR5))
1091+#define MT_DBG_MIB_M0SDR6(_band) MT_DBG_MIB((_band), 0x20)
1092+#define MT_DBG_MIB_M0SDR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR7))
1093+#define MT_DBG_MIB_M0SDR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR8))
1094+#define MT_DBG_MIB_M0SDR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR9))
1095+#define MT_DBG_MIB_M0SDR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR10))
1096+#define MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK __DBG_MASK(dev, DBG_MIB_M0SDR10_RX_MDRDY_COUNT)
1097+#define MT_DBG_MIB_M0SDR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR11))
1098+
1099+#define MT_DBG_MIB_M0SDR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR12))
1100+
1101+#define MT_DBG_MIB_M0SDR14(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR14))
1102+#define MT_DBG_MIB_M0SDR14_AMPDU_MASK __DBG_MASK(dev, DBG_MIB_M0SDR14_AMPDU)
1103+#define MT_DBG_MIB_M0SDR15(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR15))
1104+#define MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK __DBG_MASK(dev, DBG_MIB_M0SDR15_AMPDU_ACKED)
1105+#define MT_DBG_MIB_M0SDR16(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR16))
1106+#define MT_DBG_MIB_M0SDR17(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR17))
1107+#define MT_DBG_MIB_M0SDR18(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR18))
1108+#define MT_DBG_MIB_M0SDR19(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR19))
1109+#define MT_DBG_MIB_M0SDR20(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR20))
1110+#define MT_DBG_MIB_M0SDR21(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR21))
1111+#define MT_DBG_MIB_M0SDR22(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR22))
1112+#define MT_DBG_MIB_M0SDR23(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR23))
1113+#define MT_DBG_MIB_M0DR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR0))
1114+#define MT_DBG_MIB_M0DR1(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR1))
1115+
1116+#define MT_DBG_MIB_MUBF(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_MUBF))
1117+#define MT_DBG_MIB_M0DR6(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR6))
1118+#define MT_DBG_MIB_M0DR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR7))
1119+#define MT_DBG_MIB_M0DR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR8))
1120+#define MT_DBG_MIB_M0DR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR9))
1121+#define MT_DBG_MIB_M0DR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR10))
1122+#define MT_DBG_MIB_M0DR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR11))
1123+ #define MT_DBG_MIB_M0DR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR12))
1124+
1125+/* WTBLON TOP: 0x820D4000/pcie(0x34000) rbus(0x434000) */
1126+#define MT_DBG_WTBLON_TOP_BASE 0x820D4000
1127+#define MT_DBG_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
1128+#define MT_DBG_WTBLON_TOP_WDUCR MT_DBG_WTBLON_TOP(__DBG_REG_OFFS(dev, DBG_WTBLON_WDUCR))
1129+#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
1130+
1131+#define WF_WTBLON_TOP_B0BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1000) // 5000
1132+#define WF_WTBLON_TOP_B0BTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1010) // 5010
1133+#define WF_WTBLON_TOP_B0BRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1020) // 5020
1134+#define WF_WTBLON_TOP_B0BRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1030) // 5030
1135+#define WF_WTBLON_TOP_B0BTDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1040) // 5040
1136+#define WF_WTBLON_TOP_B0BRDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1050) // 5050
1137+#define WF_WTBLON_TOP_B0MBTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1100) // 5100
1138+#define WF_WTBLON_TOP_B0MBTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1140) // 5140
1139+#define WF_WTBLON_TOP_B0MBRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1180) // 5180
1140+#define WF_WTBLON_TOP_B0MBRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x11C0) // 51C0
1141+
1142+#define WF_WTBLON_TOP_B1BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1800) // 5800
1143+
1144+/* WTBLON TOP: 0x820C4000/pcie(0xa8000) rbus(0x4a8000) */
1145+#define MT_DBG_UWTBL_TOP_BASE 0x820C4000
1146+#define MT_DBG_UWTBL_TOP(ofs) (MT_DBG_UWTBL_TOP_BASE + (ofs))
1147+
developerf1313102022-10-11 11:02:55 +08001148+#define MT_DBG_UWTBL_TOP_WDUCR MT_DBG_UWTBL_TOP(__DBG_REG_OFFS(dev, DBG_UWTBL_WDUCR))
developer3fa816c2022-04-19 10:21:20 +08001149+
1150+#define MT_UWTBL_TOP_WDUCR_TARGET BIT(31)
1151+#define MT_UWTBL_TOP_WDUCR_GROUP GENMASK(3, 0)
1152+
1153+
1154+/* WTBL : 0x820D8000/pcie(0x38000) rbus(0x438000) */
1155+#define MT_DBG_WTBL_BASE 0x820D8000
1156+
1157+/* PLE related CRs. */
1158+#define MT_DBG_PLE_BASE 0x820C0000
1159+#define MT_DBG_PLE(ofs) (MT_DBG_PLE_BASE + (ofs))
1160+
1161+#define MT_DBG_PLE_DRR_TAB_CTRL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_CTRL))
1162+#define MT_DBG_PLE_DRR_TAB_RD_OFS __DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_RDATA)
1163+
1164+#define MT_DBG_PLE_DRR_TABLE_RDATA0 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x0)
1165+#define MT_DBG_PLE_DRR_TABLE_RDATA1 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x4)
1166+#define MT_DBG_PLE_DRR_TABLE_RDATA2 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x8)
1167+#define MT_DBG_PLE_DRR_TABLE_RDATA3 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0xc)
1168+#define MT_DBG_PLE_DRR_TABLE_RDATA4 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x10)
1169+#define MT_DBG_PLE_DRR_TABLE_RDATA5 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x14)
1170+#define MT_DBG_PLE_DRR_TABLE_RDATA6 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x18)
1171+#define MT_DBG_PLE_DRR_TABLE_RDATA7 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS+ 0x1c)
1172+
1173+#define MT_DBG_PLE_PBUF_CTRL_ADDR MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PBUF_CTRL))
1174+#define MT_DBG_PLE_QUEUE_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_QUEUE_EMPTY))
1175+#define MT_DBG_PLE_FREEPG_CNT MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_CNT))
1176+#define MT_DBG_PLE_FREEPG_HEAD_TAIL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_HEAD_TAIL))
1177+#define MT_DBG_PLE_PG_HIF_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_GROUP))
1178+#define MT_DBG_PLE_HIF_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_PG_INFO))
1179+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_TXCMD_GROUP))
1180+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_TXCMD_PG_INFO))
1181+#define MT_DBG_PLE_PG_CPU_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_CPU_GROUP))
1182+#define MT_DBG_PLE_CPU_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_CPU_PG_INFO))
1183+#define PLE_FL_QUE_CTRL_OFFSET __DBG_REG_OFFS(dev, DBG_PLE_FL_QUE_CTRL)
1184+#define MT_DBG_PLE_FL_QUE_CTRL0 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x0)
1185+#define MT_DBG_PLE_FL_QUE_CTRL1 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x4)
1186+#define MT_DBG_PLE_FL_QUE_CTRL2 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x8)
1187+#define MT_DBG_PLE_FL_QUE_CTRL3 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0xc)
1188+#define MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_NATIVE_TXCMD_Q_EMPTY))
1189+#define MT_DBG_PLE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_TXCMD_Q_EMPTY))
1190+
1191+#define MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK BIT(31)
1192+#define MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK GENMASK(25, 17)
1193+#define MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1194+
1195+#define MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1196+#define MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1197+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1198+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1199+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK GENMASK(27, 16)
1200+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK GENMASK(11, 0)
1201+
1202+#define MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK GENMASK(27, 16)
1203+#define MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK GENMASK(11, 0)
1204+
1205+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK GENMASK(27, 16)
1206+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK GENMASK(11, 0)
1207+
1208+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
1209+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
1210+
1211+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
1212+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
1213+
1214+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1215+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1216+
1217+#define MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1218+#define MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1219+
1220+#define MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK BIT(24)
1221+#define MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK BIT(31)
1222+#define MT_DBG_PLE_FL_QUE_CTRL0_Q_BUF_QID_MASK GENMASK(30, 24)
1223+
1224+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT 24
1225+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT 10
1226+
1227+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK GENMASK(27, 16)
1228+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK GENMASK(11, 0)
1229+#define MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK GENMASK(11, 0)
1230+
1231+#define MT_DBG_PLE_STATION_PAUSE(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_STATION_PAUSE) + ((n) << 2))
1232+#define MT_DBG_PLE_DIS_STA_MAP(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DIS_STA_MAP) + ((n) << 2))
1233+#define MT_DBG_PLE_AC_QEMPTY(ac, n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_AC_QEMPTY) + \
1234+ __DBG_REG_OFFS(dev, DBG_PLE_AC_OFFSET) * (ac) + ((n) << 2))
1235+
1236+#define MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(n) MT_DBG_PLE(0x10e0 + ((n) << 2))
1237+
1238+/* pseinfo related CRs. */
1239+#define MT_DBG_PSE_BASE 0x820C8000
1240+#define MT_DBG_PSE(ofs) (MT_DBG_PSE_BASE + (ofs))
1241+
developerf32dabf2022-06-01 10:59:24 +08001242+#define MT_DBG_PSE_PBUF_CTRL MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PBUF_CTRL))
1243+#define MT_DBG_PSE_QUEUE_EMPTY MT_DBG_PSE(0x0b0)
1244+#define MT_DBG_PSE_FREEPG_CNT MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_CNT))
1245+#define MT_DBG_PSE_FREEPG_HEAD_TAIL MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_HEAD_TAIL))
1246+#define MT_DBG_PSE_PG_HIF0_GROUP MT_DBG_PSE(0x110)
1247+#define MT_DBG_PSE_HIF0_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_HIF0_PG_INFO))
1248+#define MT_DBG_PSE_PG_HIF1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_HIF1_GROUP))
1249+#define MT_DBG_PSE_HIF1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_HIF1_PG_INFO))
1250+#define MT_DBG_PSE_PG_CPU_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_CPU_GROUP))
1251+#define MT_DBG_PSE_CPU_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_CPU_PG_INFO))
1252+#define MT_DBG_PSE_PG_LMAC0_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC0_GROUP))
1253+#define MT_DBG_PSE_LMAC0_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC0_PG_INFO))
1254+#define MT_DBG_PSE_PG_LMAC1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC1_GROUP))
1255+#define MT_DBG_PSE_LMAC1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC1_PG_INFO))
1256+#define MT_DBG_PSE_PG_LMAC2_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC2_GROUP))
1257+#define MT_DBG_PSE_LMAC2_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC2_PG_INFO))
1258+#define MT_DBG_PSE_PG_PLE_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE_GROUP))
1259+#define MT_DBG_PSE_PLE_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PLE_PG_INFO))
1260+#define MT_DBG_PSE_PG_LMAC3_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC3_GROUP))
1261+#define MT_DBG_PSE_LMAC3_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC3_PG_INFO))
1262+#define MT_DBG_PSE_PG_MDP_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_MDP_GROUP))
1263+#define MT_DBG_PSE_MDP_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_MDP_PG_INFO))
1264+#define MT_DBG_PSE_PG_PLE1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE1_GROUP))
1265+#define MT_DBG_PSE_PLE1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PLE1_PG_INFO))
developer3fa816c2022-04-19 10:21:20 +08001266+
1267+#define MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK BIT(31)
1268+#define MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK GENMASK(25, 17)
1269+#define MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1270+#define MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK BIT(31)
1271+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK BIT(23)
1272+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK BIT(22)
1273+#define MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK BIT(21)
1274+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT BIT(20)
1275+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK BIT(19)
1276+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK BIT(18)
1277+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK BIT(17)
1278+#define MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK BIT(16)
1279+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK BIT(13)
1280+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK BIT(12)
1281+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK BIT(11)
1282+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK BIT(10)
1283+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK BIT(9)
1284+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK BIT(8)
1285+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK BIT(3)
1286+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK BIT(2)
1287+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK BIT(1)
1288+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK BIT(0)
1289+#define MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1290+#define MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1291+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1292+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1293+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1294+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1295+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1296+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1297+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK GENMASK(27, 16)
1298+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK GENMASK(11, 0)
1299+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK GENMASK(27, 16)
1300+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK GENMASK(11, 0)
1301+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK GENMASK(27, 16)
1302+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK GENMASK(11, 0)
1303+#define MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1304+#define MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1305+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK GENMASK(27, 16)
1306+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK GENMASK(11, 0)
1307+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1308+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1309+#define MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK GENMASK(27, 16)
1310+#define MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK GENMASK(11, 0)
1311+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK GENMASK(27, 16)
1312+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK GENMASK(11, 0)
1313+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK GENMASK(27, 16)
1314+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK GENMASK(11, 0)
1315+#define MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK GENMASK(27, 16)
1316+#define MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK GENMASK(11, 0)
1317+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK GENMASK(27, 16)
1318+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK GENMASK(11, 0)
1319+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK GENMASK(27, 16)
1320+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK GENMASK(11, 0)
1321+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK GENMASK(27, 16)
1322+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK GENMASK(11, 0)
1323+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1324+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1325+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK GENMASK(27, 16)
1326+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK GENMASK(11, 0)
1327+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1328+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1329+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK GENMASK(27, 16)
1330+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK GENMASK(11, 0)
1331+#define MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK GENMASK(27, 16)
1332+#define MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK GENMASK(11, 0)
1333+
1334+#define MT_DBG_PSE_FL_QUE_CTRL_0_ADDR MT_DBG_PLE(0x1b0)
1335+#define MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK BIT(31)
1336+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24
1337+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT 10
1338+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK GENMASK(9, 0)
1339+
1340+#define MT_DBG_PSE_FL_QUE_CTRL_2_ADDR MT_DBG_PLE(0x1b8)
1341+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK GENMASK(27, 16)
1342+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK GENMASK(11, 0)
1343+
1344+#define MT_DBG_PSE_FL_QUE_CTRL_3_ADDR MT_DBG_PLE(0x1bc)
1345+#define MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK GENMASK(11, 0)
1346+
1347+
1348+/* AGG */
1349+#define MT_DBG_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
1350+#define MT_DBG_AGG(_band, ofs) (MT_DBG_AGG_BASE(_band) + (ofs))
1351+
1352+#define MT_DBG_AGG_AALCR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR0))
1353+#define MT_DBG_AGG_AALCR1(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR1))
1354+#define MT_DBG_AGG_AALCR2(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR2))
1355+#define MT_DBG_AGG_AALCR3(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR3))
1356+#define MT_DBG_AGG_AALCR4(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR4))
1357+#define MT_DBG_AGG_B0BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B0BRR0))
1358+#define MT_DBG_AGG_B1BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B1BRR0))
1359+#define MT_DBG_AGG_B2BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B2BRR0))
1360+#define MT_DBG_AGG_B3BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B3BRR0))
1361+#define MT_DBG_AGG_AWSCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AWSCR0) + ((n) << 2))
1362+#define MT_DBG_AGG_PCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_PCR0) + ((n) << 2))
1363+#define MT_DBG_AGG_TTCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_TTCR0) + ((n) << 2))
1364+#define MT_DBG_MIB_M0ARNG(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0ARNG0) + ((n) << 2))
1365+#define MT_DBG_MIB_M0DR2(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR2) + ((n) << 2))
1366+#define MT_DBG_MIB_M0DR13(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR13) + ((n) << 2))
1367+
1368+#define MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK GENMASK(31, 24)
1369+#define MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK GENMASK(23, 16)
1370+#define MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK GENMASK(15, 8)
1371+#define MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK GENMASK(7, 0)
1372+#define MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK GENMASK(7, 0)
1373+
1374+#define MT_DBG_AGG_AWSCR0_WINSIZE3_MASK GENMASK(31, 24)
1375+#define MT_DBG_AGG_AWSCR0_WINSIZE2_MASK GENMASK(23, 16)
1376+#define MT_DBG_AGG_AWSCR0_WINSIZE1_MASK GENMASK(15, 8)
1377+#define MT_DBG_AGG_AWSCR0_WINSIZE0_MASK GENMASK(7, 0)
1378+
1379+#define MT_DBG_AGG_AWSCR1_WINSIZE7_MASK GENMASK(31, 24)
1380+#define MT_DBG_AGG_AWSCR1_WINSIZE6_MASK GENMASK(23, 16)
1381+#define MT_DBG_AGG_AWSCR1_WINSIZE5_MASK GENMASK(15, 8)
1382+#define MT_DBG_AGG_AWSCR1_WINSIZE4_MASK GENMASK(7, 0)
1383+
1384+#define MT_DBG_AGG_AWSCR2_WINSIZEB_MASK GENMASK(31, 24)
1385+#define MT_DBG_AGG_AWSCR2_WINSIZEA_MASK GENMASK(23, 16)
1386+#define MT_DBG_AGG_AWSCR2_WINSIZE9_MASK GENMASK(15, 8)
1387+#define MT_DBG_AGG_AWSCR2_WINSIZE8_MASK GENMASK(7, 0)
1388+
1389+#define MT_DBG_AGG_AWSCR3_WINSIZEE_MASK GENMASK(23, 16)
1390+#define MT_DBG_AGG_AWSCR3_WINSIZED_MASK GENMASK(15, 8)
1391+#define MT_DBG_AGG_AWSCR3_WINSIZEC_MASK GENMASK(7, 0)
1392+
1393+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK GENMASK(31, 24)
1394+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK GENMASK(23, 16)
1395+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK GENMASK(15, 8)
1396+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK GENMASK(7, 0)
1397+
1398+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK GENMASK(31, 24)
1399+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK GENMASK(23, 16)
1400+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK GENMASK(15, 8)
1401+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK GENMASK(7, 0)
1402+
1403+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK GENMASK(31, 24)
1404+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK GENMASK(23, 16)
1405+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK GENMASK(15, 8)
1406+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK GENMASK(7, 0)
1407+
1408+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK GENMASK(23, 16)
1409+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK GENMASK(15, 8)
1410+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK GENMASK(7, 0)
1411+
1412+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK GENMASK(31, 16)
1413+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK GENMASK(15, 0)
1414+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK GENMASK(31, 16)
1415+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK GENMASK(15, 0)
1416+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK GENMASK(31, 16)
1417+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK GENMASK(15, 0)
1418+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK GENMASK(31, 16)
1419+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK GENMASK(15, 0)
1420+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK GENMASK(31, 16)
1421+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK GENMASK(15, 0)
1422+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK GENMASK(31, 16)
1423+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK GENMASK(15, 0)
1424+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK GENMASK(31, 16)
1425+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK GENMASK(15, 0)
1426+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK GENMASK(31, 16)
1427+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK GENMASK(15, 0)
1428+
1429+/* mt7915 host DMA*/
1430+#define MT_DBG_INT_DMA1_R0_DONE BIT(0)
1431+#define MT_DBG_INT_DMA1_R1_DONE BIT(1)
1432+#define MT_DBG_INT_DMA1_R2_DONE BIT(2)
1433+
1434+#define MT_DBG_INT_DMA1_T16_DONE BIT(26)
1435+#define MT_DBG_INT_DMA1_T17_DONE BIT(27)
1436+#define MT_DBG_INT_DMA1_T18_DONE BIT(30)
1437+#define MT_DBG_INT_DMA1_T19_DONE BIT(31)
1438+#define MT_DBG_INT_DMA1_T20_DONE BIT(15)
1439+
1440+#define MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE BIT(16)
1441+#define MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE BIT(17)
1442+
1443+/* mt7986 host DMA */
1444+#define MT_DBG_INT_DMA0_R0_DONE BIT(0)
1445+#define MT_DBG_INT_DMA0_R1_DONE BIT(1)
1446+#define MT_DBG_INT_DMA0_R2_DONE BIT(2)
1447+#define MT_DBG_INT_DMA0_R3_DONE BIT(3)
1448+#define MT_DBG_INT_DMA0_R4_DONE BIT(22)
1449+#define MT_DBG_INT_DMA0_R5_DONE BIT(23)
1450+
1451+#define MT_DBG_INT_DMA0_T16_DONE BIT(26)
1452+#define MT_DBG_INT_DMA0_T17_DONE BIT(27)
1453+#define MT_DBG_INT_DMA0_T18_DONE BIT(30)
1454+#define MT_DBG_INT_DMA0_T19_DONE BIT(31)
1455+#define MT_DBG_INT_DMA0_T20_DONE BIT(25)
1456+
1457+/* MCU DMA */
1458+#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
1459+#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
1460+#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
1461+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
1462+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1463+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1464+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1465+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1466+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1467+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1468+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1469+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1470+
1471+#define WF_WFDMA_MCU_DMA1_BASE 0x55000000
1472+#define WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x200) // 0200
1473+#define WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0X204) // 0204
1474+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x208) // 0208
1475+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1476+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1477+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1478+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1479+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1480+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1481+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1482+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1483+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x300) // 0300
1484+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x310) // 0310
1485+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x320) // 0320
1486+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x500) // 0500
1487+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x510) // 0510
1488+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x520) // 0520
1489+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x530) // 0530
1490+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x540) // 0540
1491+
1492+#define WF_WFDMA_MCU_DMA1_PCIE1_BASE 0x59000000
1493+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x200) // 0200
1494+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0X204) // 0204
1495+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x208) // 0208
1496+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1497+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1498+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1499+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1500+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1501+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1502+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1503+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1504+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x320) // 0320
1505+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x530) // 0530
1506+
1507+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
1508+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
1509+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
1510+/* mt7986 add */
1511+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330
1512+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340
1513+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350
1514+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360
1515+
1516+
1517+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
1518+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
1519+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
1520+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
1521+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
1522+
1523+/* mt7986 add */
1524+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550
1525+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560
1526+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570
1527+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580
1528+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590
1529+
1530+/* MEM DMA */
1531+#define WF_WFDMA_MEM_DMA_BASE 0x58000000
1532+#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
1533+#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
1534+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
1535+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1536+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1537+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1538+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1539+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1540+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1541+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1542+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1543+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
1544+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
1545+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
1546+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
1547+
1548+enum resource_attr {
1549+ HIF_TX_DATA,
1550+ HIF_TX_CMD,
1551+ HIF_TX_CMD_WM, /* direct path to WMCPU, only exist for WFDMA arch with 2 CPU */
1552+ HIF_TX_FWDL,
1553+ HIF_RX_DATA,
1554+ HIF_RX_EVENT,
1555+ RING_ATTR_NUM
1556+};
1557+
1558+struct hif_pci_tx_ring_desc {
1559+ u32 hw_int_mask;
1560+ u16 ring_size;
1561+ enum resource_attr ring_attr;
1562+ u8 band_idx;
1563+ char *const ring_info;
1564+};
1565+
1566+struct hif_pci_rx_ring_desc {
1567+ u32 hw_desc_base;
1568+ u32 hw_int_mask;
1569+ u16 ring_size;
1570+ enum resource_attr ring_attr;
1571+ u16 max_rx_process_cnt;
1572+ u16 max_sw_read_idx_inc;
1573+ char *const ring_info;
developer79a21a22023-01-09 13:57:39 +08001574+ bool flags;
developer3fa816c2022-04-19 10:21:20 +08001575+};
1576+
1577+const struct hif_pci_tx_ring_desc mt7915_tx_ring_layout[] = {
1578+ {
1579+ .hw_int_mask = MT_DBG_INT_DMA1_T16_DONE,
1580+ .ring_size = 128,
1581+ .ring_attr = HIF_TX_FWDL,
1582+ .ring_info = "FWDL"
1583+ },
1584+ {
1585+ .hw_int_mask = MT_DBG_INT_DMA1_T17_DONE,
1586+ .ring_size = 256,
1587+ .ring_attr = HIF_TX_CMD_WM,
1588+ .ring_info = "cmd to WM"
1589+ },
1590+ {
1591+ .hw_int_mask = MT_DBG_INT_DMA1_T18_DONE,
1592+ .ring_size = 2048,
1593+ .ring_attr = HIF_TX_DATA,
1594+ .ring_info = "band0 TXD"
1595+ },
1596+ {
1597+ .hw_int_mask = MT_DBG_INT_DMA1_T19_DONE,
1598+ .ring_size = 2048,
1599+ .ring_attr = HIF_TX_DATA,
1600+ .ring_info = "band1 TXD"
1601+ },
1602+ {
1603+ .hw_int_mask = MT_DBG_INT_DMA1_T20_DONE,
1604+ .ring_size = 256,
1605+ .ring_attr = HIF_TX_CMD,
1606+ .ring_info = "cmd to WA"
1607+ }
1608+};
1609+
1610+const struct hif_pci_rx_ring_desc mt7915_rx_ring_layout[] = {
1611+ {
1612+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE,
1613+ .ring_size = 1536,
1614+ .ring_attr = HIF_RX_DATA,
1615+ .ring_info = "band0 RX data"
1616+ },
1617+ {
1618+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE,
1619+ .ring_size = 1536,
1620+ .ring_attr = HIF_RX_DATA,
1621+ .ring_info = "band1 RX data"
1622+ },
1623+ {
1624+ .hw_int_mask = MT_DBG_INT_DMA1_R0_DONE,
1625+ .ring_size = 512,
1626+ .ring_attr = HIF_RX_EVENT,
1627+ .ring_info = "event from WM"
1628+ },
1629+ {
1630+ .hw_int_mask = MT_DBG_INT_DMA1_R1_DONE,
1631+ .ring_size = 1024,
1632+ .ring_attr = HIF_RX_EVENT,
developer79a21a22023-01-09 13:57:39 +08001633+ .ring_info = "event from WA band0",
1634+ .flags = true
developer3fa816c2022-04-19 10:21:20 +08001635+ },
1636+ {
1637+ .hw_int_mask = MT_DBG_INT_DMA1_R2_DONE,
1638+ .ring_size = 512,
1639+ .ring_attr = HIF_RX_EVENT,
1640+ .ring_info = "event from WA band1"
1641+ }
1642+};
1643+
1644+const struct hif_pci_tx_ring_desc mt7986_tx_ring_layout[] = {
1645+ {
1646+ .hw_int_mask = MT_DBG_INT_DMA0_T16_DONE,
1647+ .ring_size = 128,
1648+ .ring_attr = HIF_TX_FWDL,
1649+ .ring_info = "FWDL"
1650+ },
1651+ {
1652+ .hw_int_mask = MT_DBG_INT_DMA0_T17_DONE,
1653+ .ring_size = 256,
1654+ .ring_attr = HIF_TX_CMD_WM,
1655+ .ring_info = "cmd to WM"
1656+ },
1657+ {
1658+ .hw_int_mask = MT_DBG_INT_DMA0_T18_DONE,
1659+ .ring_size = 2048,
1660+ .ring_attr = HIF_TX_DATA,
1661+ .ring_info = "band0 TXD"
1662+ },
1663+ {
1664+ .hw_int_mask = MT_DBG_INT_DMA0_T19_DONE,
1665+ .ring_size = 2048,
1666+ .ring_attr = HIF_TX_DATA,
1667+ .ring_info = "band1 TXD"
1668+ },
1669+ {
1670+ .hw_int_mask = MT_DBG_INT_DMA0_T20_DONE,
1671+ .ring_size = 256,
1672+ .ring_attr = HIF_TX_CMD,
1673+ .ring_info = "cmd to WA"
1674+ }
1675+};
1676+
1677+const struct hif_pci_rx_ring_desc mt7986_rx_ring_layout[] = {
1678+ {
1679+ .hw_int_mask = MT_DBG_INT_DMA0_R4_DONE,
1680+ .ring_size = 1536,
1681+ .ring_attr = HIF_RX_DATA,
1682+ .ring_info = "band0 RX data"
1683+ },
1684+ {
1685+ .hw_int_mask = MT_DBG_INT_DMA0_R5_DONE,
1686+ .ring_size = 1536,
1687+ .ring_attr = HIF_RX_DATA,
1688+ .ring_info = "band1 RX data"
1689+ },
1690+ {
1691+ .hw_int_mask = MT_DBG_INT_DMA0_R0_DONE,
1692+ .ring_size = 512,
1693+ .ring_attr = HIF_RX_EVENT,
1694+ .ring_info = "event from WM"
1695+ },
1696+ {
1697+ .hw_int_mask = MT_DBG_INT_DMA0_R1_DONE,
1698+ .ring_size = 512,
1699+ .ring_attr = HIF_RX_EVENT,
1700+ .ring_info = "event from WA"
1701+ },
1702+ {
1703+ .hw_int_mask = MT_DBG_INT_DMA0_R2_DONE,
1704+ .ring_size = 1024,
1705+ .ring_attr = HIF_RX_EVENT,
developer79a21a22023-01-09 13:57:39 +08001706+ .ring_info = "STS WA band0",
1707+ .flags = true
developer3fa816c2022-04-19 10:21:20 +08001708+ },
1709+ {
1710+ .hw_int_mask = MT_DBG_INT_DMA0_R3_DONE,
1711+ .ring_size = 512,
1712+ .ring_attr = HIF_RX_EVENT,
1713+ .ring_info = "STS WA band1"
1714+ },
1715+};
1716+
1717+/* mibinfo related CRs. */
1718+#define BN0_WF_MIB_TOP_BASE 0x820ed000
1719+#define BN1_WF_MIB_TOP_BASE 0x820fd000
1720+
1721+#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400
1722+#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x428) // D428
1723+#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x4F0) // D4F0
1724+
1725+#define BN0_WF_MIB_TOP_BSDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x688) // D688
1726+#define BN0_WF_MIB_TOP_BSDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x690) // D690
1727+
1728+#define BN0_WF_MIB_TOP_BSDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x518) // D518
1729+#define BN0_WF_MIB_TOP_BSDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x520) // D520
1730+#define BN0_WF_MIB_TOP_BSDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x528) // D528
1731+#define BN0_WF_MIB_TOP_BSDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x530) // D530
1732+#define BN0_WF_MIB_TOP_BSDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x538) // D538
1733+
1734+#define BN0_WF_MIB_TOP_BROCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5B8) // D5B8
1735+#define BN0_WF_MIB_TOP_BRBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0
1736+#define BN0_WF_MIB_TOP_BRDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x630) // D630
1737+
1738+#define BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK 0x0000FFFF // BEACONTXCOUNT[15..0]
1739+
1740+#define BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK 0x0000FFFF // RX_FIFO_FULL_COUNT[15..0]
1741+
1742+#define BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
1743+
1744+#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
1745+
1746+#define BN1_WF_MIB_TOP_BTOCR_ADDR (BN1_WF_MIB_TOP_BASE + 0x400) // D400
1747+
1748+#define BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK 0x0000FFFF // VEC_MISS_COUNT[15..0]
1749+#define BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK 0x0000FFFF // DELIMITER_FAIL_COUNT[15..0]
1750+#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
1751+
1752+#define BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK 0x0000FFFF // RX_LEN_MISMATCH[15..0]
1753+
1754+#define BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK 0x00FFFFFF // P_CCA_TIME[23..0]
1755+#define BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK 0x00FFFFFF // S_CCA_TIME[23..0]
1756+#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
1757+#define BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK 0x00FFFFFF // CCK_MDRDY_TIME[23..0]
1758+#define BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[23..0]
1759+#define BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_GREEN_MDRDY_TIME[23..0]
1760+
1761+#define BN0_WF_MIB_TOP_M0SDR22_ADDR (BN0_WF_MIB_TOP_BASE + 0x60) // D060
1762+#define BN0_WF_MIB_TOP_M0SDR23_ADDR (BN0_WF_MIB_TOP_BASE + 0x64) // D064
1763+
1764+#define BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK 0x0000FFFF // MUBF_TX_COUNT[15..0]
1765+
1766+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK 0xFFFF0000 // TX_40MHZ_CNT[31..16]
1767+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT 16
1768+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK 0x0000FFFF // TX_20MHZ_CNT[15..0]
1769+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_SHFT 0
1770+
1771+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK 0xFFFF0000 // TX_160MHZ_CNT[31..16]
1772+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT 16
1773+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK 0x0000FFFF // TX_80MHZ_CNT[15..0]
1774+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_SHFT 0
1775+
1776+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG2_CNT[31..16]
1777+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT 16
1778+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG1_CNT[15..0]
1779+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_SHFT 0
1780+
1781+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG4_CNT[31..16]
1782+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT 16
1783+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG3_CNT[15..0]
1784+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_SHFT 0
1785+
1786+#define BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK 0x0000FFFF // MU_FAIL_PPDU_CNT[15..0]
1787+
1788+#define BN0_WF_MIB_TOP_M0B0SDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x100) // D100
1789+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK 0xFFFF0000 // RTSRETRYCOUNT[31..16]
1790+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT 16
1791+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK 0x0000FFFF // RTSTXCOUNT[15..0]
1792+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_SHFT 0
1793+#define BN0_WF_MIB_TOP_M0B0SDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x104) // D104
1794+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK 0xFFFF0000 // ACKFAILCOUNT[31..16]
1795+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT 16
1796+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK 0x0000FFFF // BAMISSCOUNT[15..0]
1797+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_SHFT 0
1798+#define BN0_WF_MIB_TOP_M0B0SDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x108) // D108
1799+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK 0xFFFF0000 // FRAMERETRY2COUNT[31..16]
1800+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT 16
1801+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK 0x0000FFFF // FRAMERETRYCOUNT[15..0]
1802+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_SHFT 0
1803+#define BN0_WF_MIB_TOP_M0B0SDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x10C) // D10C
1804+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK 0x0000FFFF // FRAMERETRY3COUNT[15..0]
1805+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_SHFT 0
1806+#define BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG0_CNT[15..0]
1807+
1808+
1809+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK 0xFFFF0000 // TX_OK_COUNT2np1[31..16]
1810+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT 16
1811+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK 0x0000FFFF // TX_OK_COUNT2n[15..0]
1812+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT 0
1813+
1814+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK 0xFFFF0000 // TX_DATA_COUNT2np1[31..16]
1815+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT 16
1816+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK 0x0000FFFF // TX_DATA_COUNT2n[15..0]
1817+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT 0
1818+
1819+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK 0xFFFF0000 // RX_OK_COUNT2np1[31..16]
1820+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT 16
1821+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK 0x0000FFFF // RX_OK_COUNT2n[15..0]
1822+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT 0
1823+
1824+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK 0xFFFF0000 // RX_DATA_COUNT2np1[31..16]
1825+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT 16
1826+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK 0x0000FFFF // RX_DATA_COUNT2n[15..0]
1827+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT 0
1828+
1829+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK 0xFFFF0000 // RTSTXCOUNT2np1[31..16]
1830+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT 16
1831+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK 0x0000FFFF // RTSTXCOUNT2n[15..0]
1832+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT 0
1833+
1834+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK 0xFFFF0000 // RTSRETRYCOUNT2np1[31..16]
1835+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT 16
1836+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK 0x0000FFFF // RTSRETRYCOUNT2n[15..0]
1837+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT 0
1838+
1839+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK 0xFFFF0000 // BAMISSCOUNT2np1[31..16]
1840+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT 16
1841+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK 0x0000FFFF // BAMISSCOUNT2n[15..0]
1842+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT 0
1843+
1844+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK 0xFFFF0000 // ACKFAILCOUNT2np1[31..16]
1845+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT 16
1846+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK 0x0000FFFF // ACKFAILCOUNT2n[15..0]
1847+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT 0
1848+
1849+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK 0xFFFF0000 // FRAMERETRYCOUNT2np1[31..16]
1850+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT 16
1851+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK 0x0000FFFF // FRAMERETRYCOUNT2n[15..0]
1852+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT 0
1853+
1854+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY2COUNT2np1[31..16]
1855+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT 16
1856+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK 0x0000FFFF // FRAMERETRY2COUNT2n[15..0]
1857+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT 0
1858+
1859+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY3COUNT2np1[31..16]
1860+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT 16
1861+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK 0x0000FFFF // FRAMERETRY3COUNT2n[15..0]
1862+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT 0
1863+/* TXD */
1864+
1865+#define MT_TXD1_ETYP BIT(15)
1866+#define MT_TXD1_VLAN BIT(14)
1867+#define MT_TXD1_RMVL BIT(13)
1868+#define MT_TXD1_AMS BIT(13)
1869+#define MT_TXD1_EOSP BIT(12)
1870+#define MT_TXD1_MRD BIT(11)
1871+
1872+#define MT_TXD7_CTXD BIT(26)
1873+#define MT_TXD7_CTXD_CNT GENMASK(25, 23)
1874+#define MT_TXD7_TAT GENMASK(9, 0)
1875+
1876+#endif
1877+#endif
1878diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c
1879new file mode 100644
developer004e50c2023-06-29 20:33:22 +08001880index 0000000..70e4cb2
developer3fa816c2022-04-19 10:21:20 +08001881--- /dev/null
1882+++ b/mt7915/mtk_debugfs.c
developer8e5fecd2023-05-30 11:58:00 +08001883@@ -0,0 +1,3624 @@
developer3fa816c2022-04-19 10:21:20 +08001884+#include<linux/inet.h>
1885+#include "mt7915.h"
1886+#include "mt7915_debug.h"
1887+#include "mac.h"
1888+#include "mcu.h"
1889+
1890+#ifdef MTK_DEBUG
1891+#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
1892+#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
1893+#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \
1894+ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
1895+ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
1896+
1897+#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
1898+#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
1899+#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1900+ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
1901+ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
1902+
1903+#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
1904+#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
1905+#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1906+ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
1907+ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
1908+
1909+enum mt7915_wtbl_type {
1910+ WTBL_TYPE_LMAC, /* WTBL in LMAC */
1911+ WTBL_TYPE_UMAC, /* WTBL in UMAC */
1912+ WTBL_TYPE_KEY, /* Key Table */
1913+ MAX_NUM_WTBL_TYPE
1914+};
1915+
1916+static int mt7915_wtbl_read_raw(struct mt7915_dev *dev, u16 idx,
1917+ enum mt7915_wtbl_type type, u16 start_dw,
1918+ u16 len, void *buf)
1919+{
1920+ u32 *dest_cpy = (u32 *)buf;
1921+ u32 size_dw = len;
1922+ u32 src = 0;
1923+
1924+ if (!buf)
1925+ return 0xFF;
1926+
1927+ if (type == WTBL_TYPE_LMAC) {
1928+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1929+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1930+ src = LWTBL_IDX2BASE(idx, start_dw);
1931+ } else if (type == WTBL_TYPE_UMAC) {
1932+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1933+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1934+ src = UWTBL_IDX2BASE(idx, start_dw);
1935+ } else if (type == WTBL_TYPE_KEY) {
1936+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1937+ MT_UWTBL_TOP_WDUCR_TARGET |
1938+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1939+ src = KEYTBL_IDX2BASE(idx, start_dw);
1940+ }
1941+
1942+ while (size_dw--) {
1943+ *dest_cpy++ = mt76_rr(dev, src);
1944+ src += 4;
1945+ };
1946+
1947+ return 0;
1948+}
1949+
1950+static int mt7915_wtbl_write_raw(struct mt7915_dev *dev, u16 idx,
1951+ enum mt7915_wtbl_type type, u16 start_dw,
1952+ u32 val)
1953+{
1954+ u32 addr = 0;
1955+
1956+ if (type == WTBL_TYPE_LMAC) {
1957+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1958+ FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1959+ addr = LWTBL_IDX2BASE(idx, start_dw);
1960+ } else if (type == WTBL_TYPE_UMAC) {
1961+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1962+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1963+ addr = UWTBL_IDX2BASE(idx, start_dw);
1964+ } else if (type == WTBL_TYPE_KEY) {
1965+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1966+ MT_UWTBL_TOP_WDUCR_TARGET |
1967+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1968+ addr = KEYTBL_IDX2BASE(idx, start_dw);
1969+ }
1970+
1971+ mt76_wr(dev, addr, val);
1972+
1973+ return 0;
1974+}
1975+
1976+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len)
1977+{
1978+ struct bin_debug_hdr *hdr;
1979+ char *buf;
1980+
1981+ if (len > 1500 - sizeof(*hdr))
1982+ len = 1500 - sizeof(*hdr);
1983+
1984+ buf = kzalloc(sizeof(*hdr) + len, GFP_KERNEL);
1985+ if (!buf)
1986+ return;
1987+
1988+ hdr = (struct bin_debug_hdr *)buf;
1989+ hdr->magic_num = cpu_to_le32(PKT_BIN_DEBUG_MAGIC);
1990+ hdr->serial_id = cpu_to_le16(dev->dbg.fwlog_seq++);
1991+ hdr->msg_type = cpu_to_le16(type);
1992+ hdr->len = cpu_to_le16(len);
1993+ hdr->des_len = cpu_to_le16(des_len);
1994+
1995+ memcpy(buf + sizeof(*hdr), data, len);
1996+
1997+ mt7915_debugfs_rx_log(dev, buf, sizeof(*hdr) + len);
1998+}
1999+
2000+static int
2001+mt7915_fw_debug_module_set(void *data, u64 module)
2002+{
2003+ struct mt7915_dev *dev = data;
2004+
2005+ dev->dbg.fw_dbg_module = module;
2006+ return 0;
2007+}
2008+
2009+static int
2010+mt7915_fw_debug_module_get(void *data, u64 *module)
2011+{
2012+ struct mt7915_dev *dev = data;
2013+
2014+ *module = dev->dbg.fw_dbg_module;
2015+ return 0;
2016+}
2017+
2018+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, mt7915_fw_debug_module_get,
2019+ mt7915_fw_debug_module_set, "%lld\n");
2020+
2021+static int
2022+mt7915_fw_debug_level_set(void *data, u64 level)
2023+{
2024+ struct mt7915_dev *dev = data;
2025+
2026+ dev->dbg.fw_dbg_lv = level;
2027+ mt7915_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv);
2028+ return 0;
2029+}
2030+
2031+static int
2032+mt7915_fw_debug_level_get(void *data, u64 *level)
2033+{
2034+ struct mt7915_dev *dev = data;
2035+
2036+ *level = dev->dbg.fw_dbg_lv;
2037+ return 0;
2038+}
2039+
2040+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, mt7915_fw_debug_level_get,
2041+ mt7915_fw_debug_level_set, "%lld\n");
2042+
2043+#define MAX_TX_MODE 12
2044+static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT",
2045+ "N/A", "N/A", "N/A", "HE_SU", "HE_EXT_SU",
2046+ "HE_TRIG", "HE_MU", "N/A"};
2047+static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong",
2048+ "N/A", "2Mshort", "5.5Mshort", "11Mshort",
2049+ "N/A"};
2050+static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M",
2051+ "48M", "54M", "N/A"};
2052+static char *fcap_str[] = {"20MHz", "20/40MHz", "20/40/80MHz",
2053+ "20/40/80/160/80+80MHz"};
2054+
2055+static char *hw_rate_ofdm_str(u16 ofdm_idx)
2056+{
2057+ switch (ofdm_idx) {
2058+ case 11: /* 6M */
2059+ return HW_TX_RATE_OFDM_STR[0];
2060+
2061+ case 15: /* 9M */
2062+ return HW_TX_RATE_OFDM_STR[1];
2063+
2064+ case 10: /* 12M */
2065+ return HW_TX_RATE_OFDM_STR[2];
2066+
2067+ case 14: /* 18M */
2068+ return HW_TX_RATE_OFDM_STR[3];
2069+
2070+ case 9: /* 24M */
2071+ return HW_TX_RATE_OFDM_STR[4];
2072+
2073+ case 13: /* 36M */
2074+ return HW_TX_RATE_OFDM_STR[5];
2075+
2076+ case 8: /* 48M */
2077+ return HW_TX_RATE_OFDM_STR[6];
2078+
2079+ case 12: /* 54M */
2080+ return HW_TX_RATE_OFDM_STR[7];
2081+
2082+ default:
2083+ return HW_TX_RATE_OFDM_STR[8];
2084+ }
2085+}
2086+
2087+static char *hw_rate_str(u8 mode, u16 rate_idx)
2088+{
2089+ if (mode == 0)
2090+ return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8];
2091+ else if (mode == 1)
2092+ return hw_rate_ofdm_str(rate_idx);
2093+ else
2094+ return "MCS";
2095+}
2096+
2097+static void parse_rate(struct seq_file *s, u16 rate_idx, u16 txrate)
2098+{
2099+ u16 txmode, mcs, nss, stbc;
2100+
2101+ txmode = FIELD_GET(GENMASK(9, 6), txrate);
2102+ mcs = FIELD_GET(GENMASK(5, 0), txrate);
2103+ nss = FIELD_GET(GENMASK(12, 10), txrate);
2104+ stbc = FIELD_GET(BIT(13), txrate);
2105+
2106+ seq_printf(s, "\tRate%d(0x%x):TxMode=%d(%s), TxRate=%d(%s), Nsts=%d, STBC=%d\n",
2107+ rate_idx + 1, txrate,
2108+ txmode, (txmode < MAX_TX_MODE ? HW_TX_MODE_STR[txmode] : HW_TX_MODE_STR[MAX_TX_MODE]),
2109+ mcs, hw_rate_str(txmode, mcs), nss, stbc);
2110+}
2111+
2112+#define LWTBL_LEN_IN_DW 32
2113+#define UWTBL_LEN_IN_DW 8
2114+#define ONE_KEY_ENTRY_LEN_IN_DW 8
developerf32dabf2022-06-01 10:59:24 +08002115+static int mt7915_sta_info(struct seq_file *s, void *data)
2116+{
2117+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2118+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
2119+ u16 i = 0;
2120+
2121+ for (i=0; i < mt7915_wtbl_size(dev); i++) {
2122+ mt7915_wtbl_read_raw(dev, i, WTBL_TYPE_LMAC, 0,
2123+ LWTBL_LEN_IN_DW, lwtbl);
2124+ if (lwtbl[4] || lwtbl[5] || lwtbl[6] || lwtbl[7] || lwtbl[0] || lwtbl[1])
2125+ seq_printf(s, "wcid:%d\tAddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
2126+ i, lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
2127+ }
2128+
2129+ return 0;
2130+}
2131+
developer3fa816c2022-04-19 10:21:20 +08002132+static int mt7915_wtbl_read(struct seq_file *s, void *data)
2133+{
2134+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2135+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
2136+ int x;
2137+ u32 *addr = 0;
2138+ u32 dw_value = 0;
2139+
2140+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_LMAC, 0,
2141+ LWTBL_LEN_IN_DW, lwtbl);
2142+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
2143+ seq_printf(s, "LMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2144+ MT_DBG_WTBLON_TOP_WDUCR,
2145+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2146+ LWTBL_IDX2BASE(dev->wlan_idx, 0));
2147+ for (x = 0; x < LWTBL_LEN_IN_DW; x++) {
2148+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2149+ x,
2150+ lwtbl[x * 4 + 3],
2151+ lwtbl[x * 4 + 2],
2152+ lwtbl[x * 4 + 1],
2153+ lwtbl[x * 4]);
2154+ }
2155+
2156+ seq_printf(s, "\n\tAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
2157+ lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
2158+
2159+ // DW0, DW1
2160+ seq_printf(s, "LWTBL DW 0/1\n\t");
2161+ addr = (u32 *)&(lwtbl[0]);
2162+ dw_value = *addr;
2163+ seq_printf(s, "MUAR_IDX:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
2164+ seq_printf(s, "RCA1:%ld/ ", FIELD_GET(BIT(22), dw_value));
2165+ seq_printf(s, "KID:%lu/ ", FIELD_GET(GENMASK(24, 23), dw_value));
2166+ seq_printf(s, "RCID:%ld/ ", FIELD_GET(BIT(25), dw_value));
2167+ seq_printf(s, "FROM_DS:%ld\n\t", FIELD_GET(BIT(26), dw_value));
2168+ seq_printf(s, "TO_DS:%ld/ ", FIELD_GET(BIT(27), dw_value));
2169+ seq_printf(s, "RV:%ld/ ", FIELD_GET(BIT(28), dw_value));
2170+ seq_printf(s, "RCA2:%ld/ ", FIELD_GET(BIT(29), dw_value));
2171+ seq_printf(s, "WPI_FLAG:%ld\n", FIELD_GET(BIT(30), dw_value));
2172+
2173+ // DW2
2174+ seq_printf(s, "LWTBL DW 2\n\t");
2175+ addr = (u32 *)&(lwtbl[2*4]);
2176+ dw_value = *addr;
2177+ seq_printf(s, "AID12:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
2178+ seq_printf(s, "SU:%ld/ ", FIELD_GET(BIT(12), dw_value));
2179+ seq_printf(s, "SPP_EN:%ld/ ", FIELD_GET(BIT(13), dw_value));
2180+ seq_printf(s, "WPI_EVEN:%ld\n\t",FIELD_GET(BIT(14), dw_value));
2181+ seq_printf(s, "CIPHER:%lu/ ", FIELD_GET(GENMASK(20, 16), dw_value));
2182+ seq_printf(s, "CIPHER_IGTK:%lu/ ",FIELD_GET(GENMASK(22, 21), dw_value));
2183+ seq_printf(s, "AAD_OM:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2184+ seq_printf(s, "SW:%ld/ ", FIELD_GET(BIT(24), dw_value));
2185+ seq_printf(s, "UL:%ld/ ", FIELD_GET(BIT(25), dw_value));
2186+ seq_printf(s, "TX_POWER_SAVE:%ld\n\t", FIELD_GET(BIT(26), dw_value));
2187+ seq_printf(s, "QOS:%ld/ ", FIELD_GET(BIT(27), dw_value));
2188+ seq_printf(s, "HT:%ld/ ", FIELD_GET(BIT(28), dw_value));
2189+ seq_printf(s, "VHT:%ld/ ", FIELD_GET(BIT(29), dw_value));
2190+ seq_printf(s, "HE:%ld/ ", FIELD_GET(BIT(30), dw_value));
2191+ seq_printf(s, "MESH:%ld\n", FIELD_GET(BIT(31), dw_value));
2192+
2193+ // DW3
2194+ seq_printf(s, "LWTBL DW 3\n\t");
2195+ addr = (u32 *)&(lwtbl[3*4]);
2196+ dw_value = *addr;
2197+ seq_printf(s, "WMM_Q:%lu/ ", FIELD_GET(GENMASK(1, 0), dw_value));
2198+ seq_printf(s, "RXD_DUP_MODE:%lu\n\t", FIELD_GET(GENMASK(3, 2), dw_value));
2199+ seq_printf(s, "VLAN2ETH:%ld/ ", FIELD_GET(BIT(4), dw_value));
2200+ seq_printf(s, "BEAM_CHG:%ld/ ", FIELD_GET(BIT(5), dw_value));
2201+ seq_printf(s, "DIS_BA256:%ld\n\t", FIELD_GET(BIT(6), dw_value));
2202+ seq_printf(s, "PFMU_IDX:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2203+ seq_printf(s, "ULPF_IDX:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
2204+ seq_printf(s, "RIBF:%ld/ ", FIELD_GET(BIT(24), dw_value));
2205+ seq_printf(s, "ULPF:%ld\n\t", FIELD_GET(BIT(25), dw_value));
2206+ seq_printf(s, "IGN_FBK:%ld/ ", FIELD_GET(BIT(26), dw_value));
2207+ seq_printf(s, "TBF:%ld/ ", FIELD_GET(BIT(29), dw_value));
2208+ seq_printf(s, "TBF_VHT:%ld/ ", FIELD_GET(BIT(30), dw_value));
2209+ seq_printf(s, "TBF_HE:%ld\n", FIELD_GET(BIT(31), dw_value));
2210+
2211+ // DW4
2212+ seq_printf(s, "LWTBL DW 4\n\t");
2213+ addr = (u32 *)&(lwtbl[4*4]);
2214+ dw_value = *addr;
2215+ seq_printf(s, "ANT_ID_STS0:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2216+ seq_printf(s, "STS1:%lu/ ", FIELD_GET(GENMASK(5, 3), dw_value));
2217+ seq_printf(s, "STS2:%lu/ ", FIELD_GET(GENMASK(8, 6), dw_value));
2218+ seq_printf(s, "STS3:%lu\n\t", FIELD_GET(GENMASK(11, 9), dw_value));
2219+ seq_printf(s, "ANT_ID_STS4:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
2220+ seq_printf(s, "STS5:%lu/ ", FIELD_GET(GENMASK(17, 15), dw_value));
2221+ seq_printf(s, "STS6:%ld/ ", FIELD_GET(GENMASK(20, 18), dw_value));
2222+ seq_printf(s, "STS7:%lu\n\t", FIELD_GET(GENMASK(23, 21), dw_value));
2223+ seq_printf(s, "CASCAD:%ld/ ", FIELD_GET(BIT(24), dw_value));
2224+ seq_printf(s, "LDPC_HT:%ld/ ", FIELD_GET(BIT(25), dw_value));
2225+ seq_printf(s, "LDPC_VHT:%ld/ ", FIELD_GET(BIT(26), dw_value));
2226+ seq_printf(s, "LDPC_HE:%ld\n\t", FIELD_GET(BIT(27), dw_value));
2227+ seq_printf(s, "DIS_RHTR:%ld/ ", FIELD_GET(BIT(28), dw_value));
2228+ seq_printf(s, "ALL_ACK:%ld/ ", FIELD_GET(BIT(29), dw_value));
2229+ seq_printf(s, "DROP:%ld/ ", FIELD_GET(BIT(30), dw_value));
2230+ seq_printf(s, "ACK_EN:%ld\n", FIELD_GET(BIT(31), dw_value));
2231+
2232+ // DW5
2233+ seq_printf(s, "LWTBL DW 5\n\t");
2234+ addr = (u32 *)&(lwtbl[5*4]);
2235+ dw_value = *addr;
2236+ seq_printf(s, "AF:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2237+ seq_printf(s, "AF_HE:%lu/ ", FIELD_GET(GENMASK(4, 3), dw_value));
2238+ seq_printf(s, "RTS:%ld/ ", FIELD_GET(BIT(5), dw_value));
2239+ seq_printf(s, "SMPS:%ld/ ", FIELD_GET(BIT(6), dw_value));
2240+ seq_printf(s, "DYN_BW:%ld\n\t", FIELD_GET(BIT(7), dw_value));
2241+ seq_printf(s, "MMSS:%lu/ ", FIELD_GET(GENMASK(10, 8), dw_value));
2242+ seq_printf(s, "USR:%ld/ ", FIELD_GET(BIT(11), dw_value));
2243+ seq_printf(s, "SR_RATE:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
2244+ seq_printf(s, "SR_ABORT:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2245+ seq_printf(s, "TX_POWER_OFFSET:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
2246+ seq_printf(s, "WTBL_MPDU_SIZE:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
2247+ seq_printf(s, "PE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
2248+ seq_printf(s, "DOPPL:%ld/ ", FIELD_GET(BIT(26), dw_value));
2249+ seq_printf(s, "TXOP_PS_CAP:%ld/ ", FIELD_GET(BIT(27), dw_value));
2250+ seq_printf(s, "DONOT_UPDATE_I_PSM:%ld\n\t", FIELD_GET(BIT(28), dw_value));
2251+ seq_printf(s, "I_PSM:%ld/ ", FIELD_GET(BIT(29), dw_value));
2252+ seq_printf(s, "PSM:%ld/ ", FIELD_GET(BIT(30), dw_value));
2253+ seq_printf(s, "SKIP_TX:%ld\n", FIELD_GET(BIT(31), dw_value));
2254+
2255+ // DW6
2256+ seq_printf(s, "LWTBL DW 6\n\t");
2257+ seq_printf(s, "TID 0/1/2/3/4/5/6/7 BA_WIN_SIZE:");
2258+ addr = (u32 *)&(lwtbl[6*4]);
2259+ dw_value = *addr;
2260+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(3, 0), dw_value));
2261+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(7, 4), dw_value));
2262+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(11, 8), dw_value));
2263+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(15, 12), dw_value));
2264+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(19, 16), dw_value));
2265+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(23, 20), dw_value));
2266+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(27, 24), dw_value));
2267+ seq_printf(s, "%lu\n", FIELD_GET(GENMASK(31, 28), dw_value));
2268+
2269+ // DW7
2270+ seq_printf(s, "LWTBL DW 7\n\t");
2271+ addr = (u32 *)&(lwtbl[7*4]);
2272+ dw_value = *addr;
2273+ seq_printf(s, "CBRN:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2274+ seq_printf(s, "DBNSS_EN:%ld/ ", FIELD_GET(BIT(3), dw_value));
2275+ seq_printf(s, "BAF_EN:%ld/ ", FIELD_GET(BIT(4), dw_value));
2276+ seq_printf(s, "RDGBA:%ld\n\t", FIELD_GET(BIT(5), dw_value));
2277+ seq_printf(s, "RDG:%ld/ ", FIELD_GET(BIT(6), dw_value));
2278+ seq_printf(s, "SPE_IDX:%lu/ ", FIELD_GET(GENMASK(11, 7), dw_value));
2279+ seq_printf(s, "G2:%ld/ ", FIELD_GET(BIT(12), dw_value));
2280+ seq_printf(s, "G4:%ld/ ", FIELD_GET(BIT(13), dw_value));
2281+ seq_printf(s, "G8:%ld/ ", FIELD_GET(BIT(14), dw_value));
2282+ seq_printf(s, "G16:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2283+ seq_printf(s, "G2_LTF:%lu/ ", FIELD_GET(GENMASK(17, 16), dw_value));
2284+ seq_printf(s, "G4_LTF:%lu/ ", FIELD_GET(GENMASK(19, 18), dw_value));
2285+ seq_printf(s, "G8_LTF:%lu/ ", FIELD_GET(GENMASK(21, 20), dw_value));
2286+ seq_printf(s, "G16_LTF:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
2287+ seq_printf(s, "G2_HE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
2288+ seq_printf(s, "G4_HE:%lu/ ", FIELD_GET(GENMASK(27, 27), dw_value));
2289+ seq_printf(s, "G8_HE:%lu/ ", FIELD_GET(GENMASK(29, 28), dw_value));
2290+ seq_printf(s, "G16_HE:%lu\n", FIELD_GET(GENMASK(31, 30), dw_value));
2291+
2292+ // DW8
2293+ seq_printf(s, "LWTBL DW 8\n\t");
2294+ addr = (u32 *)&(lwtbl[8*4]);
2295+ dw_value = *addr;
2296+ seq_printf(s, "FAIL_CNT_AC0:%lu/ ", FIELD_GET(GENMASK(4, 0), dw_value));
2297+ seq_printf(s, "AC1:%lu/ ", FIELD_GET(GENMASK(9, 5), dw_value));
2298+ seq_printf(s, "AC2:%lu/ ", FIELD_GET(GENMASK(14, 10), dw_value));
2299+ seq_printf(s, "AC3:%lu\n\t", FIELD_GET(GENMASK(19, 15), dw_value));
2300+ seq_printf(s, "PARTIAL_AID:%lu/ ", FIELD_GET(GENMASK(28, 20), dw_value));
2301+ seq_printf(s, "CHK_PER:%lu\n", FIELD_GET(BIT(31), dw_value));
2302+
2303+ // DW9
2304+ seq_printf(s, "LWTBL DW 9\n\t");
2305+ addr = (u32 *)&(lwtbl[9*4]);
2306+ dw_value = *addr;
2307+ seq_printf(s, "RX_AVG_MPDU:%lu/ ", FIELD_GET(GENMASK(13, 0), dw_value));
2308+ seq_printf(s, "PRITX_SW_MODE:%ld/ ", FIELD_GET(BIT(16), dw_value));
2309+ seq_printf(s, "PRITX_PLR:%ld\n\t", FIELD_GET(BIT(17), dw_value));
2310+ seq_printf(s, "PRITX_DCM:%ld/ ", FIELD_GET(BIT(18), dw_value));
2311+ seq_printf(s, "PRITX_ER160:%ld/ ", FIELD_GET(BIT(19), dw_value));
2312+ seq_printf(s, "PRITX_ERSU:%lu\n\t", FIELD_GET(BIT(20), dw_value));
2313+ seq_printf(s, "MPDU_FAIL_CNT:%lu/ ", FIELD_GET(GENMASK(25, 23), dw_value));
2314+ seq_printf(s, "MPDU_OK_CNT:%lu/ ", FIELD_GET(GENMASK(28, 26), dw_value));
2315+ seq_printf(s, "RATE_IDX:%lu\n\t", FIELD_GET(GENMASK(31, 29), dw_value));
2316+ seq_printf(s, "FCAP:%s\n", fcap_str[FIELD_GET(GENMASK(22, 21), dw_value)]);
2317+
2318+ // DW10
2319+ seq_printf(s, "LWTBL DW 10\n");
2320+ addr = (u32 *)&(lwtbl[10*4]);
2321+ dw_value = *addr;
2322+ parse_rate(s, 0, FIELD_GET(GENMASK(13, 0), dw_value));
2323+ parse_rate(s, 1, FIELD_GET(GENMASK(29, 16), dw_value));
2324+ // DW11
2325+ seq_printf(s, "LWTBL DW 11\n");
2326+ addr = (u32 *)&(lwtbl[11*4]);
2327+ dw_value = *addr;
2328+ parse_rate(s, 2, FIELD_GET(GENMASK(13, 0), dw_value));
2329+ parse_rate(s, 3, FIELD_GET(GENMASK(29, 16), dw_value));
2330+ // DW12
2331+ seq_printf(s, "LWTBL DW 12\n");
2332+ addr = (u32 *)&(lwtbl[12*4]);
2333+ dw_value = *addr;
2334+ parse_rate(s, 4, FIELD_GET(GENMASK(13, 0), dw_value));
2335+ parse_rate(s, 5, FIELD_GET(GENMASK(29, 16), dw_value));
2336+ // DW13
2337+ seq_printf(s, "LWTBL DW 13\n");
2338+ addr = (u32 *)&(lwtbl[13*4]);
2339+ dw_value = *addr;
2340+ parse_rate(s, 6, FIELD_GET(GENMASK(13, 0), dw_value));
2341+ parse_rate(s, 7, FIELD_GET(GENMASK(29, 16), dw_value));
2342+
2343+ //DW28
2344+ seq_printf(s, "LWTBL DW 28\n\t");
2345+ addr = (u32 *)&(lwtbl[28*4]);
2346+ dw_value = *addr;
2347+ seq_printf(s, "OM_INFO:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
2348+ seq_printf(s, "OM_RXD_DUP_MODE:%u\n\t", !!(dw_value & BIT(12)) );
2349+
2350+ //DW29
2351+ seq_printf(s, "LWTBL DW 29\n");
2352+ addr = (u32 *)&(lwtbl[29*4]);
2353+ dw_value = *addr;
2354+ seq_printf(s, "USER_RSSI:%lu/ ", FIELD_GET(GENMASK(8, 0), dw_value));
2355+ seq_printf(s, "USER_SNR:%lu/ ", FIELD_GET(GENMASK(14, 9), dw_value));
2356+ seq_printf(s, "RAPID_REACTION_RATE:%lu/ ", FIELD_GET(GENMASK(26, 16), dw_value));
2357+ seq_printf(s, "HT_AMSDU(Read Only):%u/ ", !!(dw_value & BIT(30)) );
2358+ seq_printf(s, "AMSDU_CROSS_LG(Read Only):%u\n\t ", !!(dw_value & BIT(31)));
2359+
2360+ //DW30
2361+ seq_printf(s, "LWTBL DW 30\n\t");
2362+ addr = (u32 *)&(lwtbl[30*4]);
2363+ dw_value = *addr;
2364+ seq_printf(s, "RCPI 0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2365+ seq_printf(s, "RCPI 1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2366+ seq_printf(s, "RCPI 2:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
2367+ seq_printf(s, "RCPI 3:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
2368+
2369+ //DW31
2370+ seq_printf(s, "LWTBL DW 31\n\t");
2371+ addr = (u32 *)&(lwtbl[31*4]);
2372+ dw_value = *addr;
2373+ seq_printf(s, "RCPI 4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2374+ seq_printf(s, "RCPI 5:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2375+ seq_printf(s, "RCPI 6:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
2376+ seq_printf(s, "RCPI 7:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
2377+
2378+ return 0;
2379+}
2380+
2381+static int mt7915_uwtbl_read(struct seq_file *s, void *data)
2382+{
2383+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2384+ u8 uwtbl[UWTBL_LEN_IN_DW * 4] = {0};
2385+ u8 keytbl[ONE_KEY_ENTRY_LEN_IN_DW*4] = {0};
2386+ int x;
2387+ u32 *addr = 0;
2388+ u32 dw_value = 0;
2389+ u32 amsdu_len = 0;
2390+ u32 u2SN = 0;
2391+ u16 keyloc0, keyloc1;
2392+
2393+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC, 0,
2394+ UWTBL_LEN_IN_DW, uwtbl);
2395+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
2396+ seq_printf(s, "UMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
developerb8853042023-02-17 11:50:45 +08002397+ MT_DBG_UWTBL_TOP_WDUCR,
2398+ mt76_rr(dev, MT_DBG_UWTBL_TOP_BASE),
developer3fa816c2022-04-19 10:21:20 +08002399+ UWTBL_IDX2BASE(dev->wlan_idx, 0));
2400+ for (x = 0; x < UWTBL_LEN_IN_DW; x++) {
2401+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2402+ x,
2403+ uwtbl[x * 4 + 3],
2404+ uwtbl[x * 4 + 2],
2405+ uwtbl[x * 4 + 1],
2406+ uwtbl[x * 4]);
2407+ }
2408+
2409+ /* UMAC WTBL DW 0 */
2410+ seq_printf(s, "\nUWTBL PN\n\t");
2411+ addr = (u32 *)&(uwtbl[0]);
2412+ dw_value = *addr;
2413+ seq_printf(s, "PN0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2414+ seq_printf(s, "PN1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2415+ seq_printf(s, "PN2:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
2416+ seq_printf(s, "PN3:%lu/ ", FIELD_GET(GENMASK(31, 24), dw_value));
2417+
2418+ addr = (u32 *)&(uwtbl[1 * 4]);
2419+ dw_value = *addr;
2420+ seq_printf(s, "PN4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2421+ seq_printf(s, "PN5:%lu\n", FIELD_GET(GENMASK(15, 8), dw_value));
2422+
2423+ /* UMAC WTBL DW SN part */
2424+ seq_printf(s, "\nUWTBL SN\n");
2425+ addr = (u32 *)&(uwtbl[2 * 4]);
2426+ dw_value = *addr;
2427+ seq_printf(s, "TID0_AC0_SN:%lu\n", FIELD_GET(GENMASK(11, 0), dw_value));
2428+ seq_printf(s, "TID1_AC1_SN:%lu\n", FIELD_GET(GENMASK(23, 12), dw_value));
2429+
2430+ u2SN = FIELD_GET(GENMASK(31, 24), dw_value);
2431+ addr = (u32 *)&(uwtbl[3 * 4]);
2432+ dw_value = *addr;
2433+ u2SN |= FIELD_GET(GENMASK(3, 0), dw_value);
2434+ seq_printf(s, "TID2_AC2_SN:%u\n", u2SN);
2435+ seq_printf(s, "TID3_AC3_SN:%lu\n", FIELD_GET(GENMASK(15, 4), dw_value));
2436+ seq_printf(s, "TID4_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
2437+
2438+ u2SN = FIELD_GET(GENMASK(31, 28), dw_value);
2439+ addr = (u32 *)&(uwtbl[4 * 4]);
2440+ dw_value = *addr;
2441+ u2SN |= FIELD_GET(GENMASK(7, 0), dw_value);
2442+ seq_printf(s, "TID5_SN:%u\n", u2SN);
2443+ seq_printf(s, "TID6_SN:%lu\n", FIELD_GET(GENMASK(19, 8), dw_value));
2444+ seq_printf(s, "TID7_SN:%lu\n", FIELD_GET(GENMASK(31, 20), dw_value));
2445+
2446+ addr = (u32 *)&(uwtbl[1 * 4]);
2447+ dw_value = *addr;
2448+ seq_printf(s, "COM_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
2449+
2450+ /* UMAC WTBL DW 0 */
2451+ seq_printf(s, "\nUWTBL others\n");
2452+
2453+ addr = (u32 *)&(uwtbl[5 * 4]);
2454+ dw_value = *addr;
2455+ keyloc0 = FIELD_GET(GENMASK(10, 0), dw_value);
2456+ keyloc1 = FIELD_GET(GENMASK(26, 16), dw_value);
2457+ seq_printf(s, "\tKey Loc 1/2:%lu/%lu\n",
2458+ FIELD_GET(GENMASK(10, 0), dw_value),
2459+ FIELD_GET(GENMASK(26, 16), dw_value));
2460+ seq_printf(s, "\tUWTBL_QOS:%lu\n", FIELD_GET(BIT(27), dw_value));
2461+ seq_printf(s, "\tUWTBL_HT_VHT_HE:%lu\n", FIELD_GET(BIT(28), dw_value));
2462+
2463+ addr = (u32 *)&(uwtbl[6*4]);
2464+ dw_value = *addr;
2465+ seq_printf(s, "\tHW AMSDU Enable:%lu\n", FIELD_GET(BIT(9), dw_value));
2466+
2467+ amsdu_len = FIELD_GET(GENMASK(5, 0), dw_value);
2468+ if (amsdu_len == 0)
2469+ seq_printf(s, "\tHW AMSDU Len:invalid (WTBL value=0x%x)\n", amsdu_len);
2470+ else if (amsdu_len == 1)
2471+ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
2472+ 1,
2473+ 255,
2474+ amsdu_len);
2475+ else
2476+ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
2477+ 256 * (amsdu_len - 1),
2478+ 256 * (amsdu_len - 1) + 255,
2479+ amsdu_len
2480+ );
2481+ seq_printf(s, "\tHW AMSDU Num:%lu (WTBL value=0x%lx)\n",
2482+ FIELD_GET(GENMASK(8, 6), dw_value) + 1,
2483+ FIELD_GET(GENMASK(8, 6), dw_value));
2484+
2485+ /* Parse KEY link */
2486+ seq_printf(s, "\n\tkeyloc0:%d\n", keyloc0);
2487+ if(keyloc0 != GENMASK(10, 0)) {
2488+ mt7915_wtbl_read_raw(dev, keyloc0, WTBL_TYPE_KEY,
2489+ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
2490+ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
developerb8853042023-02-17 11:50:45 +08002491+ MT_DBG_UWTBL_TOP_WDUCR,
2492+ mt76_rr(dev, MT_DBG_UWTBL_TOP_BASE),
developer3fa816c2022-04-19 10:21:20 +08002493+ KEYTBL_IDX2BASE(keyloc0, 0));
2494+
2495+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
2496+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2497+ x,
2498+ keytbl[x * 4 + 3],
2499+ keytbl[x * 4 + 2],
2500+ keytbl[x * 4 + 1],
2501+ keytbl[x * 4]);
2502+ }
2503+ }
2504+
2505+ seq_printf(s, "\n\tkeyloc1:%d\n", keyloc1);
2506+ if(keyloc1 != GENMASK(26, 16)) {
2507+ mt7915_wtbl_read_raw(dev, keyloc1, WTBL_TYPE_KEY,
2508+ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
2509+ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
developerb8853042023-02-17 11:50:45 +08002510+ MT_DBG_UWTBL_TOP_WDUCR,
2511+ mt76_rr(dev, MT_DBG_UWTBL_TOP_BASE),
developer3fa816c2022-04-19 10:21:20 +08002512+ KEYTBL_IDX2BASE(keyloc1, 0));
2513+
2514+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
2515+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2516+ x,
2517+ keytbl[x * 4 + 3],
2518+ keytbl[x * 4 + 2],
2519+ keytbl[x * 4 + 1],
2520+ keytbl[x * 4]);
2521+ }
2522+ }
2523+ return 0;
2524+}
2525+
2526+static void
2527+dump_dma_tx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
2528+{
2529+ u32 base, cnt, cidx, didx, queue_cnt;
2530+
2531+ base= mt76_rr(dev, ring_base);
2532+ cnt = mt76_rr(dev, ring_base + 4);
2533+ cidx = mt76_rr(dev, ring_base + 8);
2534+ didx = mt76_rr(dev, ring_base + 12);
2535+ queue_cnt = (cidx >= didx) ? (cidx - didx) : (cidx - didx + cnt);
2536+
2537+ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
2538+}
2539+
2540+static void
2541+dump_dma_rx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
2542+{
2543+ u32 base, cnt, cidx, didx, queue_cnt;
2544+
2545+ base= mt76_rr(dev, ring_base);
2546+ cnt = mt76_rr(dev, ring_base + 4);
2547+ cidx = mt76_rr(dev, ring_base + 8);
2548+ didx = mt76_rr(dev, ring_base + 12);
2549+ queue_cnt = (didx > cidx) ? (didx - cidx - 1) : (didx - cidx + cnt - 1);
2550+
2551+ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
2552+}
2553+
2554+static void
2555+mt7915_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2556+{
2557+ u32 sys_ctrl[10] = {};
2558+
2559+ /* HOST DMA */
2560+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
2561+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
2562+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
2563+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
2564+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_INT_SOURCE_CSR);
2565+ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_INT_MASK_CSR);
2566+ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
2567+ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_GLO_CFG);
2568+ seq_printf(s, "HOST_DMA Configuration\n");
2569+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2570+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2571+ seq_printf(s, "%10s %10x %10x\n",
2572+ "Merge", sys_ctrl[0], sys_ctrl[1]);
2573+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2574+ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
2575+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
2576+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
2577+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
2578+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
2579+
2580+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2581+ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
2582+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
2583+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
2584+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[7]),
2585+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[7]));
2586+
2587+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT1_SOURCE_CSR);
2588+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT1_MASK_CSR);
2589+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR);
2590+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR);
2591+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR);
2592+ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR);
2593+ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_GLO_CFG);
2594+ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_GLO_CFG);
2595+ seq_printf(s, "%10s %10x %10x\n",
2596+ "MergeP1", sys_ctrl[0], sys_ctrl[1]);
2597+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2598+ "DMA0P1", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
2599+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
2600+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
2601+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
2602+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
2603+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2604+ "DMA1P1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
2605+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
2606+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
2607+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[7]),
2608+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[7]));
2609+
2610+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2611+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2612+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2613+ dump_dma_rx_ring_info(s, dev, "R0:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2614+ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
2615+
2616+ seq_printf(s, "HOST_DMA0 PCIe 1 Ring Configuration\n");
2617+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2618+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2619+ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", MT_DBG_WFDMA0_PCIE1_RX1_CTRL0);
2620+
2621+ seq_printf(s, "HOST_DMA1 Ring Configuration\n");
2622+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2623+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2624+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
2625+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
developer79a21a22023-01-09 13:57:39 +08002626+ if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
2627+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(0));
2628+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(1));
2629+ } else {
2630+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
2631+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
2632+ }
developer3fa816c2022-04-19 10:21:20 +08002633+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
2634+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_EVENT_RING_CTRL(0));
developer79a21a22023-01-09 13:57:39 +08002635+ if (mtk_wed_device_active(&dev->mt76.mmio.wed))
2636+ dump_dma_rx_ring_info(s, dev, "R1:TxDone(WA2H)", MT_DBG_WFDMA_WED_RX_CTRL(1));
2637+ else
2638+ dump_dma_rx_ring_info(s, dev, "R1:Event0(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
developer3fa816c2022-04-19 10:21:20 +08002639+ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
2640+
2641+ seq_printf(s, "HOST_DMA1 PCIe 1 Ring Configuration\n");
2642+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2643+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2644+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA1_PCIE1_TX19_CTRL0);
2645+ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", MT_DBG_WFDMA1_PCIE1_RX2_CTRL0);
2646+}
2647+
2648+static void
2649+mt7915_show_mcu_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2650+{
2651+ u32 sys_ctrl[9] = {};
2652+
2653+ /* MCU DMA information */
2654+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2655+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2656+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2657+
2658+ sys_ctrl[3] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR);
2659+ sys_ctrl[4] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR);
2660+ sys_ctrl[5] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR);
2661+ sys_ctrl[6] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR);
2662+ sys_ctrl[7] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR);
2663+ sys_ctrl[8] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR);
2664+
2665+ seq_printf(s, "MCU_DMA Configuration\n");
2666+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2667+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2668+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2669+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2670+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2671+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2672+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2673+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2674+
2675+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2676+ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[3],
2677+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2678+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2679+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2680+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2681+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2682+ "DMA1P1", sys_ctrl[7], sys_ctrl[8], sys_ctrl[6],
2683+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2684+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2685+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2686+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2687+
2688+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2689+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2690+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2691+ dump_dma_tx_ring_info(s, dev, "T0:TXD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2692+ dump_dma_tx_ring_info(s, dev, "T1:TXCMD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2693+ dump_dma_tx_ring_info(s, dev, "T2:TXD(WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2694+ dump_dma_rx_ring_info(s, dev, "R0:Data(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2695+ dump_dma_rx_ring_info(s, dev, "R1:TxDone(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2696+ dump_dma_rx_ring_info(s, dev, "R2:SPL(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2697+ dump_dma_rx_ring_info(s, dev, "R3:TxDone(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2698+ dump_dma_rx_ring_info(s, dev, "R4:TXS(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2699+
2700+ seq_printf(s, "MCU_DMA1 Ring Configuration\n");
2701+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2702+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2703+ dump_dma_tx_ring_info(s, dev, "T0:Event(WM2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR);
2704+ dump_dma_tx_ring_info(s, dev, "T1:Event0(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR);
2705+ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR);
2706+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR);
2707+ dump_dma_rx_ring_info(s, dev, "R1:Cmd(H2WM)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR);
2708+ dump_dma_rx_ring_info(s, dev, "R2:TXD0(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR);
2709+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR);
2710+ dump_dma_rx_ring_info(s, dev, "R4:Cmd(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR);
2711+
2712+ seq_printf(s, "MCU_DMA1 PCIe 1 Ring Configuration\n");
2713+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2714+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2715+ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR);
2716+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR);
2717+}
2718+
2719+static void
2720+mt7986_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2721+{
2722+ u32 sys_ctrl[5] = {};
2723+
2724+ /* HOST DMA */
2725+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
2726+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
2727+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
2728+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
2729+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
2730+
2731+ seq_printf(s, "HOST_DMA Configuration\n");
2732+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2733+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2734+ seq_printf(s, "%10s %10x %10x\n",
2735+ "Merge", sys_ctrl[0], sys_ctrl[1]);
2736+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2737+ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[4],
2738+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK, sys_ctrl[4]),
2739+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK, sys_ctrl[4]),
2740+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK, sys_ctrl[4]),
2741+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK, sys_ctrl[4]));
2742+
2743+
2744+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2745+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2746+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2747+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
2748+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
developer79a21a22023-01-09 13:57:39 +08002749+
2750+ if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed)) {
2751+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(0));
2752+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(1));
2753+ } else {
2754+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
2755+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
2756+ }
2757+
developer3fa816c2022-04-19 10:21:20 +08002758+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
2759+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2760+ dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
developer79a21a22023-01-09 13:57:39 +08002761+ if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed))
2762+ dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_WFDMA_WED_RX_CTRL(1));
2763+ else
2764+ dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
developer3fa816c2022-04-19 10:21:20 +08002765+ dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(3));
2766+ dump_dma_rx_ring_info(s, dev, "R4:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2767+ dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
2768+}
2769+
2770+static void
2771+mt7986_show_mcu_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2772+{
2773+ u32 sys_ctrl[3] = {};
2774+
2775+ /* MCU DMA information */
2776+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2777+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2778+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2779+
2780+ seq_printf(s, "MCU_DMA Configuration\n");
2781+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2782+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2783+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2784+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2785+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2786+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2787+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2788+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2789+
2790+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2791+ seq_printf(s, "%22s %10s %10s %10s %10s %10s\n",
2792+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2793+ dump_dma_tx_ring_info(s, dev, "T0:Event (WM2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2794+ dump_dma_tx_ring_info(s, dev, "T1:Event (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2795+ dump_dma_tx_ring_info(s, dev, "T2:TxDone (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2796+ dump_dma_tx_ring_info(s, dev, "T3:TxDone1 (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR);
2797+ dump_dma_tx_ring_info(s, dev, "T4:TXD (WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR);
2798+ dump_dma_tx_ring_info(s, dev, "T5:TXCMD (WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR);
2799+ dump_dma_tx_ring_info(s, dev, "T6:TXD (WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR);
2800+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2801+ dump_dma_rx_ring_info(s, dev, "R1:Cmd (H2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2802+ dump_dma_rx_ring_info(s, dev, "R2:TXD (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2803+ dump_dma_rx_ring_info(s, dev, "R3:TXD1 (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2804+ dump_dma_rx_ring_info(s, dev, "R4:Cmd (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2805+ dump_dma_rx_ring_info(s, dev, "R5:Data (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR);
2806+ dump_dma_rx_ring_info(s, dev, "R6:TxDone/STS (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR);
2807+ dump_dma_rx_ring_info(s, dev, "R7:RPT (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR);
2808+ dump_dma_rx_ring_info(s, dev, "R8:TxDone/STS (MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR);
2809+ dump_dma_rx_ring_info(s, dev, "R9:Data1 (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR);
2810+
2811+}
2812+
2813+static void
2814+mt7915_show_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2815+{
2816+ u32 sys_ctrl[10] = {};
2817+
2818+ if(is_mt7915(&dev->mt76)) {
2819+ mt7915_show_host_dma_info(s, dev);
2820+ mt7915_show_mcu_dma_info(s, dev);
2821+ } else {
2822+ mt7986_show_host_dma_info(s, dev);
2823+ mt7986_show_mcu_dma_info(s, dev);
2824+ }
2825+
2826+ /* MEM DMA information */
2827+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR);
2828+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR);
2829+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR);
2830+
2831+ seq_printf(s, "MEM_DMA Configuration\n");
2832+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2833+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2834+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2835+ "MEM", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2836+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2837+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2838+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2839+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2840+
2841+ seq_printf(s, "MEM_DMA Ring Configuration\n");
2842+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2843+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2844+ dump_dma_tx_ring_info(s, dev, "T0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR);
2845+ dump_dma_tx_ring_info(s, dev, "T1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR);
2846+ dump_dma_rx_ring_info(s, dev, "R0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR);
2847+ dump_dma_rx_ring_info(s, dev, "R1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR);
2848+}
2849+
2850+static int mt7915_trinfo_read(struct seq_file *s, void *data)
2851+{
2852+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2853+ const struct hif_pci_tx_ring_desc *tx_ring_layout;
2854+ const struct hif_pci_rx_ring_desc *rx_ring_layout;
developer79a21a22023-01-09 13:57:39 +08002855+ struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
developer3fa816c2022-04-19 10:21:20 +08002856+ u32 tx_ring_num, rx_ring_num;
2857+ u32 tbase[5], tcnt[5];
2858+ u32 tcidx[5], tdidx[5];
2859+ u32 rbase[6], rcnt[6];
2860+ u32 rcidx[6], rdidx[6];
2861+ int idx;
developer79a21a22023-01-09 13:57:39 +08002862+ bool flags = false;
developer3fa816c2022-04-19 10:21:20 +08002863+
2864+ if(is_mt7915(&dev->mt76)) {
2865+ tx_ring_layout = &mt7915_tx_ring_layout[0];
2866+ rx_ring_layout = &mt7915_rx_ring_layout[0];
2867+ tx_ring_num = ARRAY_SIZE(mt7915_tx_ring_layout);
2868+ rx_ring_num = ARRAY_SIZE(mt7915_rx_ring_layout);
2869+ } else {
2870+ tx_ring_layout = &mt7986_tx_ring_layout[0];
2871+ rx_ring_layout = &mt7986_rx_ring_layout[0];
2872+ tx_ring_num = ARRAY_SIZE(mt7986_tx_ring_layout);
2873+ rx_ring_num = ARRAY_SIZE(mt7986_rx_ring_layout);
2874+ }
2875+
2876+ for (idx = 0; idx < tx_ring_num; idx++) {
developer79a21a22023-01-09 13:57:39 +08002877+ if (mtk_wed_device_active(wed) &&
2878+ (tx_ring_layout[idx].ring_attr == HIF_TX_DATA)) {
2879+ struct mt76_phy *phy = dev->mt76.phys[MT_BAND0];
2880+ struct mt76_phy *ext_phy = dev->mt76.phys[MT_BAND1];
2881+ struct mt76_queue *q;
2882+
2883+ tbase[idx] = tcnt[idx] = tcidx[idx] = tdidx[idx] = 0;
2884+
2885+ if (!phy)
2886+ continue;
2887+
2888+ if (flags && !ext_phy)
2889+ continue;
2890+
2891+ if (flags && ext_phy)
2892+ phy = ext_phy;
2893+
2894+ q = phy->q_tx[0];
2895+
2896+ if (q->wed_regs) {
2897+ tbase[idx] = mtk_wed_device_reg_read(wed, q->wed_regs);
2898+ tcnt[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x04);
2899+ tcidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x08);
2900+ tdidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x0c);
2901+ }
2902+
2903+ flags = true;
2904+ } else {
2905+ tbase[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx));
2906+ tcnt[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x04);
2907+ tcidx[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x08);
2908+ tdidx[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x0c);}
developer3fa816c2022-04-19 10:21:20 +08002909+ }
2910+
2911+ for (idx = 0; idx < rx_ring_num; idx++) {
developer79a21a22023-01-09 13:57:39 +08002912+ if (rx_ring_layout[idx].ring_attr == HIF_RX_DATA) {
2913+ if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) {
2914+ struct mt76_queue *q = &dev->mt76.q_rx[MT_RXQ_MAIN];
2915+
2916+ rbase[idx] = rcnt[idx] = rcidx[idx] = rdidx[idx] = 0;
2917+
2918+ if (idx == 1)
2919+ q = &dev->mt76.q_rx[MT_RXQ_BAND1];
2920+
2921+ if (q->wed_regs) {
2922+ rbase[idx] = mtk_wed_device_reg_read(wed, q->wed_regs);
2923+ rcnt[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x04);
2924+ rcidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x08);
2925+ rdidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x0c);
2926+ }
2927+ } else {
2928+ rbase[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx));
2929+ rcnt[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x04);
2930+ rcidx[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x08);
2931+ rdidx[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x0c);
2932+ }
developer3fa816c2022-04-19 10:21:20 +08002933+ } else {
developer79a21a22023-01-09 13:57:39 +08002934+ if (mtk_wed_device_active(wed) && rx_ring_layout[idx].flags) {
2935+ struct mt76_queue *q = &dev->mt76.q_rx[MT_RXQ_MAIN_WA];
2936+
2937+ if (is_mt7915(&dev->mt76))
2938+ q = &dev->mt76.q_rx[MT_RXQ_MCU_WA];
2939+
2940+ rbase[idx] = mtk_wed_device_reg_read(wed, q->wed_regs);
2941+ rcnt[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x04);
2942+ rcidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x08);
2943+ rdidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x0c);
2944+
2945+ } else {
2946+ rbase[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2));
2947+ rcnt[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x04);
2948+ rcidx[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x08);
2949+ rdidx[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x0c);
2950+ }
developer3fa816c2022-04-19 10:21:20 +08002951+ }
2952+ }
2953+
2954+ seq_printf(s, "=================================================\n");
2955+ seq_printf(s, "TxRing Configuration\n");
2956+ seq_printf(s, "%4s %10s %8s %1s %6s %6s %6s %6s\n",
2957+ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
2958+ "QCnt");
2959+ for (idx = 0; idx < tx_ring_num; idx++) {
2960+ u32 queue_cnt;
2961+
2962+ queue_cnt = (tcidx[idx] >= tdidx[idx]) ?
2963+ (tcidx[idx] - tdidx[idx]) :
2964+ (tcidx[idx] - tdidx[idx] + tcnt[idx]);
2965+ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
2966+ idx, tx_ring_layout[idx].ring_info,
2967+ MT_DBG_TX_RING_CTRL(idx), tbase[idx],
2968+ tcnt[idx], tcidx[idx], tdidx[idx], queue_cnt);
2969+ }
2970+
2971+ seq_printf(s, "RxRing Configuration\n");
2972+ seq_printf(s, "%4s %10s %8s %10s %6s %6s %6s %6s\n",
2973+ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
2974+ "QCnt");
2975+
2976+ for (idx = 0; idx < rx_ring_num; idx++) {
2977+ u32 queue_cnt;
2978+
2979+ queue_cnt = (rdidx[idx] > rcidx[idx]) ?
2980+ (rdidx[idx] - rcidx[idx] - 1) :
2981+ (rdidx[idx] - rcidx[idx] + rcnt[idx] - 1);
2982+ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
2983+ idx, rx_ring_layout[idx].ring_info,
2984+ (idx < 2) ? MT_DBG_RX_DATA_RING_CTRL(idx): MT_DBG_RX_EVENT_RING_CTRL(idx - 2),
2985+ rbase[idx], rcnt[idx], rcidx[idx], rdidx[idx], queue_cnt);
2986+ }
2987+
2988+ mt7915_show_dma_info(s, dev);
2989+ return 0;
2990+}
2991+
2992+static int mt7915_drr_info(struct seq_file *s, void *data)
2993+{
2994+#define DL_AC_START 0x00
2995+#define DL_AC_END 0x0F
2996+#define UL_AC_START 0x10
2997+#define UL_AC_END 0x1F
2998+
2999+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3000+ u32 drr_sta_status[16];
3001+ u32 drr_ctrl_def_val = 0x80220000, drr_ctrl_val = 0;
3002+ bool is_show = false;
3003+ int idx, sta_line = 0, sta_no = 0, max_sta_line = (mt7915_wtbl_size(dev) + 31) / 32;
3004+ seq_printf(s, "DRR Table STA Info:\n");
3005+
3006+ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
3007+ is_show = true;
3008+ drr_ctrl_val = (drr_ctrl_def_val | idx);
3009+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3010+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3011+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3012+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3013+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3014+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3015+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3016+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3017+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3018+
3019+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
3020+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1 << 10);
3021+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3022+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3023+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3024+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3025+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3026+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3027+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3028+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3029+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3030+ }
3031+ if (!is_mt7915(&dev->mt76))
3032+ max_sta_line = 8;
3033+
3034+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
3035+ if (drr_sta_status[sta_line] > 0) {
3036+ for (sta_no = 0; sta_no < 32; sta_no++) {
3037+ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
3038+ if (is_show) {
3039+ seq_printf(s, "\n DL AC%02d Queue Non-Empty STA:\n", idx);
3040+ is_show = false;
3041+ }
3042+ seq_printf(s, "%d ", sta_no + (sta_line * 32));
3043+ }
3044+ }
3045+ }
3046+ }
3047+ }
3048+
3049+ for (idx = UL_AC_START; idx <= UL_AC_END; idx++) {
3050+ is_show = true;
3051+ drr_ctrl_val = (drr_ctrl_def_val | idx);
3052+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3053+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3054+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3055+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3056+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3057+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3058+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3059+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3060+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3061+
3062+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
3063+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1 << 10);
3064+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3065+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3066+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3067+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3068+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3069+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3070+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3071+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3072+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3073+ }
3074+
3075+ if (!is_mt7915(&dev->mt76))
3076+ max_sta_line = 8;
3077+
3078+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
3079+ if (drr_sta_status[sta_line] > 0) {
3080+ for (sta_no = 0; sta_no < 32; sta_no++) {
3081+ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
3082+ if (is_show) {
3083+ seq_printf(s, "\n UL AC%02d Queue Non-Empty STA:\n", idx);
3084+ is_show = false;
3085+ }
3086+ seq_printf(s, "%d ", sta_no + (sta_line * 32));
3087+ }
3088+ }
3089+ }
3090+ }
3091+ }
3092+
3093+ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
3094+ drr_ctrl_def_val = 0x80420000;
3095+ drr_ctrl_val = (drr_ctrl_def_val | idx);
3096+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3097+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3098+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3099+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3100+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3101+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3102+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3103+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3104+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3105+
3106+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
3107+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1<<10);
3108+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3109+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3110+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3111+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3112+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3113+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3114+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3115+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3116+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3117+ }
3118+
3119+ seq_printf(s, "\nBSSGrp[%d]:\n", idx);
3120+ if (!is_mt7915(&dev->mt76))
3121+ max_sta_line = 8;
3122+
3123+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
3124+ seq_printf(s, "0x%08x ", drr_sta_status[sta_line]);
3125+
3126+ if ((sta_line % 4) == 3)
3127+ seq_printf(s, "\n");
3128+ }
3129+ }
3130+
3131+ return 0;
3132+}
3133+
developerf32dabf2022-06-01 10:59:24 +08003134+#define CR_NUM_OF_AC 17
developer3fa816c2022-04-19 10:21:20 +08003135+
3136+typedef enum _ENUM_UMAC_PORT_T {
3137+ ENUM_UMAC_HIF_PORT_0 = 0,
3138+ ENUM_UMAC_CPU_PORT_1 = 1,
3139+ ENUM_UMAC_LMAC_PORT_2 = 2,
3140+ ENUM_PLE_CTRL_PSE_PORT_3 = 3,
3141+ ENUM_UMAC_PSE_PLE_PORT_TOTAL_NUM = 4
3142+} ENUM_UMAC_PORT_T, *P_ENUM_UMAC_PORT_T;
3143+
3144+/* N9 MCU QUEUE LIST */
3145+typedef enum _ENUM_UMAC_CPU_P_QUEUE_T {
3146+ ENUM_UMAC_CTX_Q_0 = 0,
3147+ ENUM_UMAC_CTX_Q_1 = 1,
3148+ ENUM_UMAC_CTX_Q_2 = 2,
3149+ ENUM_UMAC_CTX_Q_3 = 3,
3150+ ENUM_UMAC_CRX = 0,
3151+ ENUM_UMAC_CIF_QUEUE_TOTAL_NUM = 4
3152+} ENUM_UMAC_CPU_P_QUEUE_T, *P_ENUM_UMAC_CPU_P_QUEUE_T;
3153+
3154+/* LMAC PLE TX QUEUE LIST */
3155+typedef enum _ENUM_UMAC_LMAC_PLE_TX_P_QUEUE_T {
3156+ ENUM_UMAC_LMAC_PLE_TX_Q_00 = 0x00,
3157+ ENUM_UMAC_LMAC_PLE_TX_Q_01 = 0x01,
3158+ ENUM_UMAC_LMAC_PLE_TX_Q_02 = 0x02,
3159+ ENUM_UMAC_LMAC_PLE_TX_Q_03 = 0x03,
3160+
3161+ ENUM_UMAC_LMAC_PLE_TX_Q_10 = 0x04,
3162+ ENUM_UMAC_LMAC_PLE_TX_Q_11 = 0x05,
3163+ ENUM_UMAC_LMAC_PLE_TX_Q_12 = 0x06,
3164+ ENUM_UMAC_LMAC_PLE_TX_Q_13 = 0x07,
3165+
3166+ ENUM_UMAC_LMAC_PLE_TX_Q_20 = 0x08,
3167+ ENUM_UMAC_LMAC_PLE_TX_Q_21 = 0x09,
3168+ ENUM_UMAC_LMAC_PLE_TX_Q_22 = 0x0a,
3169+ ENUM_UMAC_LMAC_PLE_TX_Q_23 = 0x0b,
3170+
3171+ ENUM_UMAC_LMAC_PLE_TX_Q_30 = 0x0c,
3172+ ENUM_UMAC_LMAC_PLE_TX_Q_31 = 0x0d,
3173+ ENUM_UMAC_LMAC_PLE_TX_Q_32 = 0x0e,
3174+ ENUM_UMAC_LMAC_PLE_TX_Q_33 = 0x0f,
3175+
3176+ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 = 0x10,
3177+ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0 = 0x11,
3178+ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0 = 0x12,
3179+ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0 = 0x13,
3180+
3181+ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 = 0x14,
3182+ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1 = 0x15,
3183+ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1 = 0x16,
3184+ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1 = 0x17,
3185+ ENUM_UMAC_LMAC_PLE_TX_Q_NAF = 0x18,
3186+ ENUM_UMAC_LMAC_PLE_TX_Q_NBCN = 0x19,
3187+ ENUM_UMAC_LMAC_PLE_TX_Q_RELEASE = 0x1f, /* DE suggests not to use 0x1f, it's only for hw free queue */
3188+ ENUM_UMAC_LMAC_QUEUE_TOTAL_NUM = 24,
3189+
3190+} ENUM_UMAC_LMAC_TX_P_QUEUE_T, *P_ENUM_UMAC_LMAC_TX_P_QUEUE_T;
3191+
3192+typedef struct _EMPTY_QUEUE_INFO_T {
3193+ char *QueueName;
3194+ u32 Portid;
3195+ u32 Queueid;
3196+} EMPTY_QUEUE_INFO_T, *P_EMPTY_QUEUE_INFO_T;
3197+
3198+static EMPTY_QUEUE_INFO_T ple_queue_empty_info[] = {
3199+ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
3200+ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
3201+ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
3202+ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
3203+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
3204+ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0}, /* Q16 */
3205+ {"BMC Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0},
3206+ {"BCN Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0},
3207+ {"PSMP Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0},
3208+ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1},
3209+ {"BMC Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1},
3210+ {"BCN Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1},
3211+ {"PSMP Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1},
3212+ {"NAF Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NAF},
3213+ {"NBCN Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NBCN},
3214+ {NULL, 0, 0}, {NULL, 0, 0}, /* 18, 19 not defined */
3215+ {"FIXFID Q", ENUM_UMAC_LMAC_PORT_2, 0x1a},
3216+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
3217+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 21~29 not defined */
3218+ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7e},
3219+ {"RLS2 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7f}
3220+};
3221+
3222+static EMPTY_QUEUE_INFO_T ple_txcmd_queue_empty_info[] = {
3223+ {"AC00Q", ENUM_UMAC_LMAC_PORT_2, 0x40},
3224+ {"AC01Q", ENUM_UMAC_LMAC_PORT_2, 0x41},
3225+ {"AC02Q", ENUM_UMAC_LMAC_PORT_2, 0x42},
3226+ {"AC03Q", ENUM_UMAC_LMAC_PORT_2, 0x43},
3227+ {"AC10Q", ENUM_UMAC_LMAC_PORT_2, 0x44},
3228+ {"AC11Q", ENUM_UMAC_LMAC_PORT_2, 0x45},
3229+ {"AC12Q", ENUM_UMAC_LMAC_PORT_2, 0x46},
3230+ {"AC13Q", ENUM_UMAC_LMAC_PORT_2, 0x47},
3231+ {"AC20Q", ENUM_UMAC_LMAC_PORT_2, 0x48},
3232+ {"AC21Q", ENUM_UMAC_LMAC_PORT_2, 0x49},
3233+ {"AC22Q", ENUM_UMAC_LMAC_PORT_2, 0x4a},
3234+ {"AC23Q", ENUM_UMAC_LMAC_PORT_2, 0x4b},
3235+ {"AC30Q", ENUM_UMAC_LMAC_PORT_2, 0x4c},
3236+ {"AC31Q", ENUM_UMAC_LMAC_PORT_2, 0x4d},
3237+ {"AC32Q", ENUM_UMAC_LMAC_PORT_2, 0x4e},
3238+ {"AC33Q", ENUM_UMAC_LMAC_PORT_2, 0x4f},
3239+ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, 0x50},
3240+ {"TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x51},
3241+ {"TWT TSF-TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x52},
3242+ {"TWT DL Q0", ENUM_UMAC_LMAC_PORT_2, 0x53},
3243+ {"TWT UL Q0", ENUM_UMAC_LMAC_PORT_2, 0x54},
3244+ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, 0x55},
3245+ {"TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x56},
3246+ {"TWT TSF-TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x57},
3247+ {"TWT DL Q1", ENUM_UMAC_LMAC_PORT_2, 0x58},
3248+ {"TWT UL Q1", ENUM_UMAC_LMAC_PORT_2, 0x59},
3249+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
3250+};
3251+
3252+
3253+
3254+static char* sta_ctrl_reg[] = {"ENABLE", "DISABLE", "PAUSE"};
3255+static u32 chip_show_sta_acq_info(struct seq_file *s, struct mt7915_dev *dev, u32 *ple_stat,
3256+ u32 *sta_pause, u32 *dis_sta_map,
3257+ u32 dumptxd)
3258+{
3259+ int i, j;
3260+ u32 total_nonempty_cnt = 0;
3261+ u32 ac_num = 9, all_ac_num;
3262+
3263+ /* TDO: ac_num = 16 for mt7986 */
developerf32dabf2022-06-01 10:59:24 +08003264+ if (!is_mt7915(&dev->mt76))
3265+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003266+
3267+ all_ac_num = ac_num * 4;
3268+
3269+ for (j = 0; j < all_ac_num; j++) { /* show AC Q info */
3270+ for (i = 0; i < 32; i++) {
3271+ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
developerf32dabf2022-06-01 10:59:24 +08003272+ u32 hfid, tfid, pktcnt, ac_n = j / ac_num, ctrl = 0;
developer3fa816c2022-04-19 10:21:20 +08003273+ u32 sta_num = i + (j % ac_num) * 32, fl_que_ctrl[3] = {0};
3274+ //struct wifi_dev *wdev = wdev_search_by_wcid(pAd, sta_num);
3275+ u32 wmmidx = 0;
3276+ struct mt7915_sta *msta;
3277+ struct mt76_wcid *wcid;
3278+ struct ieee80211_sta *sta = NULL;
3279+
3280+ wcid = rcu_dereference(dev->mt76.wcid[sta_num]);
3281+ sta = wcid_to_sta(wcid);
3282+ if (!sta) {
3283+ printk("ERROR!! no found STA wcid=%d\n", sta_num);
developerf32dabf2022-06-01 10:59:24 +08003284+ continue;
developer3fa816c2022-04-19 10:21:20 +08003285+ }
3286+ msta = container_of(wcid, struct mt7915_sta, wcid);
3287+ wmmidx = msta->vif->mt76.wmm_idx;
3288+
developerf32dabf2022-06-01 10:59:24 +08003289+ seq_printf(s, "\tSTA%d AC%d: ", sta_num, ac_n);
developer3fa816c2022-04-19 10:21:20 +08003290+
3291+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3292+ fl_que_ctrl[0] |= (ENUM_UMAC_LMAC_PORT_2 << MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
developerf32dabf2022-06-01 10:59:24 +08003293+ fl_que_ctrl[0] |= (ac_n << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
developer3fa816c2022-04-19 10:21:20 +08003294+ fl_que_ctrl[0] |= sta_num;
3295+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3296+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3297+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3298+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3299+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3300+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3301+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x",
3302+ tfid, hfid, pktcnt);
3303+
3304+ if (((sta_pause[j % 6] & 0x1 << i) >> i) == 1)
3305+ ctrl = 2;
3306+
3307+ if (((dis_sta_map[j % 6] & 0x1 << i) >> i) == 1)
3308+ ctrl = 1;
3309+
3310+ seq_printf(s, " ctrl = %s", sta_ctrl_reg[ctrl]);
3311+ seq_printf(s, " (wmmidx=%d)\n", wmmidx);
3312+
3313+ total_nonempty_cnt++;
3314+
3315+ // TODO
3316+ //if (pktcnt > 0 && dumptxd > 0)
3317+ // ShowTXDInfo(pAd, hfid);
3318+ }
3319+ }
3320+ }
3321+
3322+ return total_nonempty_cnt;
3323+}
3324+
3325+static void chip_show_txcmdq_info(struct seq_file *s, struct mt7915_dev *dev, u32 ple_txcmd_stat)
3326+{
3327+ int i;
3328+
3329+ seq_printf(s, "Nonempty TXCMD Q info:\n");
developerf32dabf2022-06-01 10:59:24 +08003330+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003331+ if (((ple_txcmd_stat & (0x1 << i)) >> i) == 0) {
3332+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3333+
3334+ if (ple_txcmd_queue_empty_info[i].QueueName != NULL) {
3335+ seq_printf(s, "\t%s: ", ple_txcmd_queue_empty_info[i].QueueName);
3336+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3337+ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Portid <<
3338+ MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
3339+ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Queueid <<
3340+ MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
3341+ } else
3342+ continue;
3343+
3344+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3345+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3346+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3347+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3348+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3349+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3350+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3351+ tfid, hfid, pktcnt);
3352+ }
3353+ }
3354+}
3355+
3356+static void chip_get_ple_acq_stat(struct mt7915_dev *dev, u32 *ple_stat)
3357+{
3358+ int i;
3359+ int cr_num = 9, all_cr_num;
3360+ u32 ac , index;
3361+
3362+ /* TDO: cr_num = 16 for mt7986 */
developer3fa816c2022-04-19 10:21:20 +08003363+ if(!is_mt7915(&dev->mt76))
developerf32dabf2022-06-01 10:59:24 +08003364+ cr_num = 17;
3365+
developer3fa816c2022-04-19 10:21:20 +08003366+ all_cr_num = cr_num * 4;
3367+
3368+ ple_stat[0] = mt76_rr(dev, MT_DBG_PLE_QUEUE_EMPTY);
3369+
3370+ for(i = 0; i < all_cr_num; i++) {
3371+ ac = i / cr_num;
3372+ index = i % cr_num;
3373+ ple_stat[i + 1] =
3374+ mt76_rr(dev, MT_DBG_PLE_AC_QEMPTY(ac, index));
3375+
3376+ }
3377+}
3378+
3379+static void chip_get_dis_sta_map(struct mt7915_dev *dev, u32 *dis_sta_map)
3380+{
3381+ int i;
developerf32dabf2022-06-01 10:59:24 +08003382+ u32 ac_num = 9;
3383+
3384+ /* TDO: ac_num = 16 for mt7986 */
3385+ if (!is_mt7915(&dev->mt76))
3386+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003387+
developerf32dabf2022-06-01 10:59:24 +08003388+ for(i = 0; i < ac_num; i++) {
developer3fa816c2022-04-19 10:21:20 +08003389+ dis_sta_map[i] = mt76_rr(dev, MT_DBG_PLE_DIS_STA_MAP(i));
3390+ }
3391+}
3392+
3393+static void chip_get_sta_pause(struct mt7915_dev *dev, u32 *sta_pause)
3394+{
3395+ int i;
developerf32dabf2022-06-01 10:59:24 +08003396+ u32 ac_num = 9;
developer3fa816c2022-04-19 10:21:20 +08003397+
developerf32dabf2022-06-01 10:59:24 +08003398+ /* TDO: ac_num = 16 for mt7986 */
3399+ if (!is_mt7915(&dev->mt76))
3400+ ac_num = 17;
3401+
3402+ for(i = 0; i < ac_num; i++) {
developer3fa816c2022-04-19 10:21:20 +08003403+ sta_pause[i] = mt76_rr(dev, MT_DBG_PLE_STATION_PAUSE(i));
3404+ }
3405+}
3406+
3407+static int mt7915_pleinfo_read(struct seq_file *s, void *data)
3408+{
3409+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3410+ u32 ple_buf_ctrl, pg_sz, pg_num;
developerf32dabf2022-06-01 10:59:24 +08003411+ u32 ple_stat[70] = {0}, pg_flow_ctrl[8] = {0};
developer3fa816c2022-04-19 10:21:20 +08003412+ u32 ple_native_txcmd_stat;
3413+ u32 ple_txcmd_stat;
3414+ u32 sta_pause[CR_NUM_OF_AC] = {0}, dis_sta_map[CR_NUM_OF_AC] = {0};
3415+ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail, hif_max_q, hif_min_q;
3416+ u32 rpg_hif, upg_hif, cpu_max_q, cpu_min_q, rpg_cpu, upg_cpu;
3417+ int i, j;
3418+ u32 ac_num = 9, all_ac_num;
3419+
3420+ /* TDO: ac_num = 16 for mt7986 */
developerf32dabf2022-06-01 10:59:24 +08003421+ if (!is_mt7915(&dev->mt76))
3422+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003423+
3424+ all_ac_num = ac_num * 4;
3425+
3426+ ple_buf_ctrl = mt76_rr(dev, MT_DBG_PLE_PBUF_CTRL_ADDR);
3427+ chip_get_ple_acq_stat(dev, ple_stat);
3428+ ple_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_TXCMD_Q_EMPTY);
3429+ ple_native_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY);
3430+ pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PLE_FREEPG_CNT);
3431+ pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FREEPG_HEAD_TAIL);
3432+ pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_GROUP);
3433+ pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PLE_HIF_PG_INFO);
3434+ pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PLE_PG_CPU_GROUP);
3435+ pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PLE_CPU_PG_INFO);
3436+ pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_TXCMD_GROUP);
3437+ pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PLE_HIF_TXCMD_PG_INFO);
3438+ chip_get_dis_sta_map(dev, dis_sta_map);
3439+ chip_get_sta_pause(dev, sta_pause);
3440+
3441+ seq_printf(s, "PLE Configuration Info:\n");
3442+ seq_printf(s, "\tPacket Buffer Control(0x%x): 0x%08x\n",
3443+ MT_DBG_PLE_PBUF_CTRL_ADDR, ple_buf_ctrl);
3444+
3445+ pg_sz = FIELD_GET(MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK, ple_buf_ctrl);
3446+ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n",
3447+ pg_sz, (pg_sz == 1 ? 128 : 64));
3448+ seq_printf(s, "\t\tPage Offset=%ld(in unit of 2KB)\n",
3449+ FIELD_GET(MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK, ple_buf_ctrl));
3450+
3451+ pg_num = FIELD_GET(MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK, ple_buf_ctrl);
3452+ seq_printf(s, "\t\tTotal Page=%d pages\n", pg_num);
3453+
3454+ /* Page Flow Control */
3455+ seq_printf(s, "PLE Page Flow Control:\n");
3456+ seq_printf(s, "\tFree page counter(0x%x): 0x%08x\n",
3457+ MT_DBG_PLE_FREEPG_CNT, pg_flow_ctrl[0]);
3458+ fpg_cnt = FIELD_GET(MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK, pg_flow_ctrl[0]);
3459+
3460+ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3461+ ffa_cnt = FIELD_GET(MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK, pg_flow_ctrl[0]);
3462+
3463+ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3464+ seq_printf(s, "\tFree page head and tail(0x%x): 0x%08x\n",
3465+ MT_DBG_PLE_FREEPG_HEAD_TAIL, pg_flow_ctrl[1]);
3466+
3467+ fpg_head = FIELD_GET(MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK, pg_flow_ctrl[1]);
3468+ fpg_tail = FIELD_GET(MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK, pg_flow_ctrl[1]);
3469+ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3470+ seq_printf(s, "\tReserved page counter of HIF group(0x%x): 0x%08x\n",
3471+ MT_DBG_PLE_PG_HIF_GROUP, pg_flow_ctrl[2]);
3472+ seq_printf(s, "\tHIF group page status(0x%x): 0x%08x\n",
3473+ MT_DBG_PLE_HIF_PG_INFO, pg_flow_ctrl[3]);
3474+
3475+ hif_min_q = FIELD_GET(MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK, pg_flow_ctrl[2]);
3476+ hif_max_q = FIELD_GET(MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK, pg_flow_ctrl[2]);
3477+ seq_printf(s, "\t\tThe max/min quota pages of HIF group=0x%03x/0x%03x\n", hif_max_q, hif_min_q);
3478+
3479+ rpg_hif = FIELD_GET(MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK, pg_flow_ctrl[3]);
3480+ upg_hif = FIELD_GET(MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK, pg_flow_ctrl[3]);
3481+ seq_printf(s, "\t\tThe used/reserved pages of HIF group=0x%03x/0x%03x\n", upg_hif, rpg_hif);
3482+
3483+ seq_printf(s, "\tReserved page counter of HIF_TXCMD group(0x%x): 0x%08x\n",
3484+ MT_DBG_PLE_PG_HIF_TXCMD_GROUP, pg_flow_ctrl[6]);
3485+ seq_printf(s, "\tHIF_TXCMD group page status(0x%x): 0x%08x\n",
3486+ MT_DBG_PLE_HIF_TXCMD_PG_INFO, pg_flow_ctrl[7]);
3487+ cpu_min_q = FIELD_GET(MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
developerf32dabf2022-06-01 10:59:24 +08003488+ cpu_max_q = FIELD_GET(MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK, pg_flow_ctrl[6]);
developer3fa816c2022-04-19 10:21:20 +08003489+ seq_printf(s, "\t\tThe max/min quota pages of HIF_TXCMD group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
3490+
3491+ rpg_cpu = FIELD_GET(MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK, pg_flow_ctrl[7]);
3492+ upg_cpu = FIELD_GET(MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK, pg_flow_ctrl[7]);
3493+ seq_printf(s, "\t\tThe used/reserved pages of HIF_TXCMD group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
3494+
developerf32dabf2022-06-01 10:59:24 +08003495+ seq_printf(s, "\tReserved page counter of CPU group(0x%x): 0x%08x\n",
3496+ MT_DBG_PLE_PG_CPU_GROUP, pg_flow_ctrl[4]);
3497+ seq_printf(s, "\tCPU group page status(0x%x): 0x%08x\n",
3498+ MT_DBG_PLE_CPU_PG_INFO, pg_flow_ctrl[5]);
developer3fa816c2022-04-19 10:21:20 +08003499+ cpu_min_q = FIELD_GET(MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK, pg_flow_ctrl[4]);
3500+ cpu_max_q = FIELD_GET(MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK, pg_flow_ctrl[4]);
3501+ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
3502+
3503+ rpg_cpu = FIELD_GET(MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK, pg_flow_ctrl[5]);
3504+ upg_cpu = FIELD_GET(MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK, pg_flow_ctrl[5]);
3505+ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
3506+
3507+ if ((ple_stat[0] & MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK) == 0) {
3508+ for (j = 0; j < all_ac_num; j++) {
3509+ if (j % ac_num == 0) {
3510+ seq_printf(s, "\n\tNonempty AC%d Q of STA#: ", j / ac_num);
3511+ }
3512+
developerf32dabf2022-06-01 10:59:24 +08003513+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003514+ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
3515+ seq_printf(s, "%d ", i + (j % ac_num) * 32);
3516+ }
3517+ }
3518+ }
3519+
3520+ seq_printf(s, "\n");
3521+ }
3522+
3523+ seq_printf(s, "non-native/native txcmd queue empty = %d/%d\n", ple_txcmd_stat, ple_native_txcmd_stat);
3524+
3525+ seq_printf(s, "Nonempty Q info:\n");
3526+
developerf32dabf2022-06-01 10:59:24 +08003527+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003528+ if (((ple_stat[0] & (0x1 << i)) >> i) == 0) {
3529+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3530+
3531+ if (ple_queue_empty_info[i].QueueName != NULL) {
3532+ seq_printf(s, "\t%s: ", ple_queue_empty_info[i].QueueName);
3533+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3534+ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Portid << MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
3535+ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Queueid << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
3536+ } else
3537+ continue;
3538+
3539+ if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 &&
3540+ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0)
3541+ /* band0 set TGID 0, bit31 = 0 */
3542+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x0);
3543+ else if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 &&
3544+ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1)
3545+ /* band1 set TGID 1, bit31 = 1 */
3546+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x80000000);
3547+
3548+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3549+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3550+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3551+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3552+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3553+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3554+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3555+ tfid, hfid, pktcnt);
3556+
3557+ /* TODO */
3558+ //if (pktcnt > 0 && dumptxd > 0)
3559+ // ShowTXDInfo(pAd, hfid);
3560+ }
3561+ }
3562+
3563+ chip_show_sta_acq_info(s, dev, ple_stat, sta_pause, dis_sta_map, 0/*dumptxd*/);
3564+ chip_show_txcmdq_info(s, dev, ple_native_txcmd_stat);
3565+
3566+ return 0;
3567+}
3568+
3569+typedef enum _ENUM_UMAC_PLE_CTRL_P3_QUEUE_T {
3570+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1E = 0x1e,
3571+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1F = 0x1f,
3572+ ENUM_UMAC_PLE_CTRL_P3_TOTAL_NUM = 2
3573+} ENUM_UMAC_PLE_CTRL_P3_QUEUE_T, *P_ENUM_UMAC_PLE_CTRL_P3_QUEUE_T;
3574+
3575+static EMPTY_QUEUE_INFO_T pse_queue_empty_info[] = {
3576+ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
3577+ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
3578+ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
3579+ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
3580+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
3581+ {"HIF Q0", ENUM_UMAC_HIF_PORT_0, 0}, /* Q8 */
3582+ {"HIF Q1", ENUM_UMAC_HIF_PORT_0, 1},
3583+ {"HIF Q2", ENUM_UMAC_HIF_PORT_0, 2},
3584+ {"HIF Q3", ENUM_UMAC_HIF_PORT_0, 3},
3585+ {"HIF Q4", ENUM_UMAC_HIF_PORT_0, 4},
3586+ {"HIF Q5", ENUM_UMAC_HIF_PORT_0, 5},
3587+ {NULL, 0, 0}, {NULL, 0, 0}, /* 14~15 not defined */
3588+ {"LMAC Q", ENUM_UMAC_LMAC_PORT_2, 0},
3589+ {"MDP TX Q", ENUM_UMAC_LMAC_PORT_2, 1},
3590+ {"MDP RX Q", ENUM_UMAC_LMAC_PORT_2, 2},
3591+ {"SEC TX Q", ENUM_UMAC_LMAC_PORT_2, 3},
3592+ {"SEC RX Q", ENUM_UMAC_LMAC_PORT_2, 4},
3593+ {"SFD_PARK Q", ENUM_UMAC_LMAC_PORT_2, 5},
3594+ {"MDP_TXIOC Q", ENUM_UMAC_LMAC_PORT_2, 6},
3595+ {"MDP_RXIOC Q", ENUM_UMAC_LMAC_PORT_2, 7},
3596+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 24~30 not defined */
3597+ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, ENUM_UMAC_PLE_CTRL_P3_Q_0X1F}
3598+};
3599+
3600+static int mt7915_pseinfo_read(struct seq_file *s, void *data)
3601+{
3602+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3603+ u32 pse_buf_ctrl, pg_sz, pg_num;
3604+ u32 pse_stat, pg_flow_ctrl[22] = {0};
3605+ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail;
3606+ u32 max_q, min_q, rsv_pg, used_pg;
3607+ int i;
3608+
3609+ pse_buf_ctrl = mt76_rr(dev, MT_DBG_PSE_PBUF_CTRL);
3610+ pse_stat = mt76_rr(dev, MT_DBG_PSE_QUEUE_EMPTY);
3611+ pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PSE_FREEPG_CNT);
3612+ pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PSE_FREEPG_HEAD_TAIL);
3613+ pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PSE_PG_HIF0_GROUP);
3614+ pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PSE_HIF0_PG_INFO);
3615+ pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PSE_PG_HIF1_GROUP);
3616+ pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PSE_HIF1_PG_INFO);
3617+ pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PSE_PG_CPU_GROUP);
3618+ pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PSE_CPU_PG_INFO);
3619+ pg_flow_ctrl[8] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC0_GROUP);
3620+ pg_flow_ctrl[9] = mt76_rr(dev, MT_DBG_PSE_LMAC0_PG_INFO);
3621+ pg_flow_ctrl[10] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC1_GROUP);
3622+ pg_flow_ctrl[11] = mt76_rr(dev, MT_DBG_PSE_LMAC1_PG_INFO);
3623+ pg_flow_ctrl[12] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC2_GROUP);
3624+ pg_flow_ctrl[13] = mt76_rr(dev, MT_DBG_PSE_LMAC2_PG_INFO);
3625+ pg_flow_ctrl[14] = mt76_rr(dev, MT_DBG_PSE_PG_PLE_GROUP);
3626+ pg_flow_ctrl[15] = mt76_rr(dev, MT_DBG_PSE_PLE_PG_INFO);
3627+ pg_flow_ctrl[16] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC3_GROUP);
3628+ pg_flow_ctrl[17] = mt76_rr(dev, MT_DBG_PSE_LMAC3_PG_INFO);
3629+ pg_flow_ctrl[18] = mt76_rr(dev, MT_DBG_PSE_PG_MDP_GROUP);
3630+ pg_flow_ctrl[19] = mt76_rr(dev, MT_DBG_PSE_MDP_PG_INFO);
3631+ pg_flow_ctrl[20] = mt76_rr(dev, MT_DBG_PSE_PG_PLE1_GROUP);
3632+ pg_flow_ctrl[21] = mt76_rr(dev,MT_DBG_PSE_PLE1_PG_INFO);
3633+
3634+ /* Configuration Info */
3635+ seq_printf(s, "PSE Configuration Info:\n");
3636+ seq_printf(s, "\tPacket Buffer Control(0x82068014): 0x%08x\n", pse_buf_ctrl);
3637+ pg_sz = FIELD_GET(MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK, pse_buf_ctrl);
3638+
3639+ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n", pg_sz, (pg_sz == 1 ? 256 : 128));
3640+ seq_printf(s, "\t\tPage Offset=%ld(in unit of 64KB)\n",
3641+ FIELD_GET(MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK, pse_buf_ctrl));
3642+ pg_num = FIELD_GET(MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK, pse_buf_ctrl);
3643+
3644+ seq_printf(s, "\t\tTotal page numbers=%d pages\n", pg_num);
3645+
3646+ /* Page Flow Control */
3647+ seq_printf(s, "PSE Page Flow Control:\n");
3648+ seq_printf(s, "\tFree page counter(0x82068100): 0x%08x\n", pg_flow_ctrl[0]);
3649+ fpg_cnt = FIELD_GET(MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK, pg_flow_ctrl[0]);
3650+ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3651+
3652+ ffa_cnt = FIELD_GET(MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK, pg_flow_ctrl[0]);
3653+ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3654+
3655+ seq_printf(s, "\tFree page head and tail(0x82068104): 0x%08x\n", pg_flow_ctrl[1]);
3656+ fpg_head = FIELD_GET(MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK, pg_flow_ctrl[1]);
3657+
3658+ fpg_tail = FIELD_GET(MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK, pg_flow_ctrl[1]);
3659+ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3660+ seq_printf(s, "\tReserved page counter of HIF0 group(0x82068110): 0x%08x\n", pg_flow_ctrl[2]);
3661+ seq_printf(s, "\tHIF0 group page status(0x82068114): 0x%08x\n", pg_flow_ctrl[3]);
3662+ min_q = FIELD_GET(MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK, pg_flow_ctrl[2]);
3663+ max_q = FIELD_GET(MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK, pg_flow_ctrl[2]);
3664+ seq_printf(s, "\t\tThe max/min quota pages of HIF0 group=0x%03x/0x%03x\n", max_q, min_q);
3665+ rsv_pg = FIELD_GET(MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK, pg_flow_ctrl[3]);;
3666+ used_pg = FIELD_GET(MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK, pg_flow_ctrl[3]);
3667+ seq_printf(s, "\t\tThe used/reserved pages of HIF0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3668+ seq_printf(s, "\tReserved page counter of HIF1 group(0x82068118): 0x%08x\n", pg_flow_ctrl[4]);
3669+ seq_printf(s, "\tHIF1 group page status(0x8206811c): 0x%08x\n", pg_flow_ctrl[5]);
3670+ min_q = FIELD_GET(MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK, pg_flow_ctrl[4]);
3671+ max_q = FIELD_GET(MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK, pg_flow_ctrl[4]);
3672+ seq_printf(s, "\t\tThe max/min quota pages of HIF1 group=0x%03x/0x%03x\n", max_q, min_q);
3673+ rsv_pg = FIELD_GET(MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK, pg_flow_ctrl[5]);
3674+ used_pg = FIELD_GET(MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK, pg_flow_ctrl[5]);
3675+
3676+ seq_printf(s, "\t\tThe used/reserved pages of HIF1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3677+ seq_printf(s, "\tReserved page counter of CPU group(0x82068150): 0x%08x\n", pg_flow_ctrl[6]);
3678+ seq_printf(s, "\tCPU group page status(0x82068154): 0x%08x\n", pg_flow_ctrl[7]);
3679+ min_q = FIELD_GET(MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
3680+ max_q = FIELD_GET(MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK, pg_flow_ctrl[6]);
3681+ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", max_q, min_q);
3682+ rsv_pg = FIELD_GET(MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK, pg_flow_ctrl[7]);
3683+ used_pg = FIELD_GET(MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK, pg_flow_ctrl[7]);
3684+ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3685+ seq_printf(s, "\tReserved page counter of LMAC0 group(0x82068170): 0x%08x\n", pg_flow_ctrl[8]);
3686+ seq_printf(s, "\tLMAC0 group page status(0x82068174): 0x%08x\n", pg_flow_ctrl[9]);
3687+ min_q = FIELD_GET(MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK, pg_flow_ctrl[8]);
3688+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK, pg_flow_ctrl[8]);
3689+ seq_printf(s, "\t\tThe max/min quota pages of LMAC0 group=0x%03x/0x%03x\n", max_q, min_q);
3690+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK, pg_flow_ctrl[9]);
3691+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK, pg_flow_ctrl[9]);
3692+ seq_printf(s, "\t\tThe used/reserved pages of LMAC0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3693+ seq_printf(s, "\tReserved page counter of LMAC1 group(0x82068178): 0x%08x\n", pg_flow_ctrl[10]);
3694+ seq_printf(s, "\tLMAC1 group page status(0x8206817c): 0x%08x\n", pg_flow_ctrl[11]);
3695+ min_q = FIELD_GET(MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK, pg_flow_ctrl[10]);
3696+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK, pg_flow_ctrl[10]);
3697+ seq_printf(s, "\t\tThe max/min quota pages of LMAC1 group=0x%03x/0x%03x\n", max_q, min_q);
3698+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK, pg_flow_ctrl[11]);
3699+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK, pg_flow_ctrl[11]);
3700+ seq_printf(s, "\t\tThe used/reserved pages of LMAC1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3701+ seq_printf(s, "\tReserved page counter of LMAC2 group(0x82068180): 0x%08x\n", pg_flow_ctrl[11]);
3702+ seq_printf(s, "\tLMAC2 group page status(0x82068184): 0x%08x\n", pg_flow_ctrl[12]);
3703+ min_q = FIELD_GET(MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK, pg_flow_ctrl[12]);
3704+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK, pg_flow_ctrl[12]);
3705+ seq_printf(s, "\t\tThe max/min quota pages of LMAC2 group=0x%03x/0x%03x\n", max_q, min_q);
3706+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK, pg_flow_ctrl[13]);
3707+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK, pg_flow_ctrl[13]);
3708+ seq_printf(s, "\t\tThe used/reserved pages of LMAC2 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3709+
3710+ seq_printf(s, "\tReserved page counter of LMAC3 group(0x82068188): 0x%08x\n", pg_flow_ctrl[16]);
3711+ seq_printf(s, "\tLMAC3 group page status(0x8206818c): 0x%08x\n", pg_flow_ctrl[17]);
3712+ min_q = FIELD_GET(MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK, pg_flow_ctrl[16]);
3713+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK, pg_flow_ctrl[16]);
3714+ seq_printf(s, "\t\tThe max/min quota pages of LMAC3 group=0x%03x/0x%03x\n", max_q, min_q);
3715+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK, pg_flow_ctrl[17]);
3716+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK, pg_flow_ctrl[17]);
3717+ seq_printf(s, "\t\tThe used/reserved pages of LMAC3 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3718+
3719+ seq_printf(s, "\tReserved page counter of PLE group(0x82068160): 0x%08x\n", pg_flow_ctrl[14]);
3720+ seq_printf(s, "\tPLE group page status(0x82068164): 0x%08x\n", pg_flow_ctrl[15]);
3721+ min_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK, pg_flow_ctrl[14]);
3722+ max_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK, pg_flow_ctrl[14]);
3723+ seq_printf(s, "\t\tThe max/min quota pages of PLE group=0x%03x/0x%03x\n", max_q, min_q);
3724+ rsv_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK, pg_flow_ctrl[15]);
3725+ used_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK, pg_flow_ctrl[15]);
3726+ seq_printf(s, "\t\tThe used/reserved pages of PLE group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3727+
3728+ seq_printf(s, "\tReserved page counter of PLE1 group(0x82068168): 0x%08x\n", pg_flow_ctrl[14]);
3729+ seq_printf(s, "\tPLE1 group page status(0x8206816c): 0x%08x\n", pg_flow_ctrl[15]);
3730+ min_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK, pg_flow_ctrl[20]);
3731+ max_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK, pg_flow_ctrl[20]);
3732+ seq_printf(s, "\t\tThe max/min quota pages of PLE1 group=0x%03x/0x%03x\n", max_q, min_q);
3733+ rsv_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK, pg_flow_ctrl[21]);
3734+ used_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK, pg_flow_ctrl[21]);
3735+ seq_printf(s, "\t\tThe used/reserved pages of PLE1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3736+
3737+ seq_printf(s, "\tReserved page counter of MDP group(0x82068198): 0x%08x\n", pg_flow_ctrl[18]);
3738+ seq_printf(s, "\tMDP group page status(0x8206819c): 0x%08x\n", pg_flow_ctrl[19]);
3739+ min_q = FIELD_GET(MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK, pg_flow_ctrl[18]);
3740+ max_q = FIELD_GET(MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK, pg_flow_ctrl[18]);
3741+ seq_printf(s, "\t\tThe max/min quota pages of MDP group=0x%03x/0x%03x\n", max_q, min_q);
3742+ rsv_pg = FIELD_GET(MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK, pg_flow_ctrl[19]);
3743+ used_pg = FIELD_GET(MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK, pg_flow_ctrl[19]);
3744+ seq_printf(s, "\t\tThe used/reserved pages of MDP group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3745+
3746+ /* Queue Empty Status */
3747+ seq_printf(s, "PSE Queue Empty Status:\n");
3748+ seq_printf(s, "\tQUEUE_EMPTY(0x820680b0): 0x%08x\n", pse_stat);
3749+ seq_printf(s, "\t\tCPU Q0/1/2/3 empty=%ld/%ld/%ld/%ld\n",
3750+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK, pse_stat),
3751+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK, pse_stat),
3752+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK, pse_stat),
3753+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK, pse_stat));
3754+
3755+ seq_printf(s, "\t\tHIF Q0/1/2/3/4/5 empty=%ld/%ld/%ld/%ld/%ld/%ld\n",
3756+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK, pse_stat),
3757+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK, pse_stat),
3758+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK, pse_stat),
3759+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK, pse_stat),
3760+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK, pse_stat),
3761+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK, pse_stat));
3762+
3763+ seq_printf(s, "\t\tLMAC TX Q empty=%ld\n",
3764+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK, pse_stat));
3765+ seq_printf(s, "\t\tMDP TX Q/RX Q empty=%ld/%ld\n",
3766+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK, pse_stat),
3767+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK, pse_stat));
3768+ seq_printf(s, "\t\tSEC TX Q/RX Q empty=%ld/%ld\n",
3769+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK, pse_stat),
3770+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT, pse_stat));
3771+ seq_printf(s, "\t\tSFD PARK Q empty=%ld\n",
3772+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK, pse_stat));
3773+ seq_printf(s, "\t\tMDP TXIOC Q/RXIOC Q empty=%ld/%ld\n",
3774+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK, pse_stat),
3775+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK, pse_stat));
3776+ seq_printf(s, "\t\tRLS Q empty=%ld\n",
3777+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK, pse_stat));
3778+ seq_printf(s, "Nonempty Q info:\n");
3779+
3780+ for (i = 0; i < 31; i++) {
3781+ if (((pse_stat & (0x1 << i)) >> i) == 0) {
3782+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3783+
3784+ if (pse_queue_empty_info[i].QueueName != NULL) {
3785+ seq_printf(s, "\t%s: ", pse_queue_empty_info[i].QueueName);
3786+ fl_que_ctrl[0] |= MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK;
3787+ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Portid << MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT);
3788+ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Queueid << MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT);
3789+ } else
3790+ continue;
3791+
3792+ fl_que_ctrl[0] |= (0x1 << 31);
3793+
3794+ mt76_wr(dev, MT_DBG_PSE_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]);
3795+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PSE_FL_QUE_CTRL_2_ADDR);
3796+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PSE_FL_QUE_CTRL_3_ADDR);
3797+
3798+ hfid = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK, fl_que_ctrl[1]);
3799+ tfid = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK, fl_que_ctrl[1]);
3800+ pktcnt = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK, fl_que_ctrl[2]);
3801+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3802+ tfid, hfid, pktcnt);
3803+ }
3804+ }
3805+
3806+ return 0;
3807+}
3808+
3809+static int mt7915_mibinfo_read_per_band(struct seq_file *s, int band_idx)
3810+{
3811+#define BSS_NUM 4
3812+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3813+ u32 mac_val0, mac_val, mac_val1, idx, band_offset = 0;
3814+ u32 msdr6, msdr7, msdr8, msdr9, msdr10, msdr16, msdr17, msdr18, msdr19, msdr20, msdr21;
3815+ u32 mbxsdr[BSS_NUM][7];
3816+ u32 mbtcr[16], mbtbcr[16], mbrcr[16], mbrbcr[16];
3817+ u32 btcr[BSS_NUM], btbcr[BSS_NUM], brcr[BSS_NUM], brbcr[BSS_NUM], btdcr[BSS_NUM], brdcr[BSS_NUM];
3818+ u32 mu_cnt[5];
3819+ u32 ampdu_cnt[3];
3820+ unsigned long per;
3821+
3822+ seq_printf(s, "Band %d MIB Status\n", band_idx);
3823+ seq_printf(s, "===============================\n");
3824+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SCR0(band_idx));
3825+ seq_printf(s, "MIB Status Control=0x%x\n", mac_val);
3826+ if (is_mt7915(&dev->mt76)) {
3827+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0PBSCR(band_idx));
3828+ seq_printf(s, "MIB Per-BSS Status Control=0x%x\n", mac_val);
3829+ }
3830+
3831+ msdr6 = mt76_rr(dev, MT_DBG_MIB_M0SDR6(band_idx));
3832+ msdr7 = mt76_rr(dev, MT_DBG_MIB_M0SDR7(band_idx));
3833+ msdr8 = mt76_rr(dev, MT_DBG_MIB_M0SDR8(band_idx));
3834+ msdr9 = mt76_rr(dev, MT_DBG_MIB_M0SDR9(band_idx));
3835+ msdr10 = mt76_rr(dev, MT_DBG_MIB_M0SDR10(band_idx));
3836+ msdr16 = mt76_rr(dev, MT_DBG_MIB_M0SDR16(band_idx));
3837+ msdr17 = mt76_rr(dev, MT_DBG_MIB_M0SDR17(band_idx));
3838+ msdr18 = mt76_rr(dev, MT_DBG_MIB_M0SDR18(band_idx));
3839+ msdr19 = mt76_rr(dev, MT_DBG_MIB_M0SDR19(band_idx));
3840+ msdr20 = mt76_rr(dev, MT_DBG_MIB_M0SDR20(band_idx));
3841+ msdr21 = mt76_rr(dev, MT_DBG_MIB_M0SDR21(band_idx));
3842+ ampdu_cnt[0] = mt76_rr(dev, MT_DBG_MIB_M0SDR12(band_idx));
3843+ ampdu_cnt[1] = mt76_rr(dev, MT_DBG_MIB_M0SDR14(band_idx));
3844+ ampdu_cnt[2] = mt76_rr(dev, MT_DBG_MIB_M0SDR15(band_idx));
3845+ ampdu_cnt[1] &= MT_DBG_MIB_M0SDR14_AMPDU_MASK;
3846+ ampdu_cnt[2] &= MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK;
3847+
3848+ seq_printf(s, "===Phy/Timing Related Counters===\n");
3849+ seq_printf(s, "\tChannelIdleCnt=0x%x\n", msdr6 & BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK);
3850+ seq_printf(s, "\tCCA_NAV_Tx_Time=0x%x\n", msdr9 & BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK);
3851+ seq_printf(s, "\tRx_MDRDY_CNT=0x%lx\n", msdr10 & MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK);
3852+ seq_printf(s, "\tCCK_MDRDY_TIME=0x%x, OFDM_MDRDY_TIME=0x%x, OFDM_GREEN_MDRDY_TIME=0x%x\n",
3853+ msdr19 & BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK,
3854+ msdr20 & BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK,
3855+ msdr21 & BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK);
3856+ seq_printf(s, "\tPrim CCA Time=0x%x\n", msdr16 & BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK);
3857+ seq_printf(s, "\tSec CCA Time=0x%x\n", msdr17 & BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK);
3858+ seq_printf(s, "\tPrim ED Time=0x%x\n", msdr18 & BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK);
3859+
3860+ seq_printf(s, "===Tx Related Counters(Generic)===\n");
3861+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR0(band_idx));
3862+ dev->dbg.bcn_total_cnt[band_idx] += (mac_val & BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK);
3863+ seq_printf(s, "\tBeaconTxCnt=0x%x\n",dev->dbg.bcn_total_cnt[band_idx]);
3864+ dev->dbg.bcn_total_cnt[band_idx] = 0;
3865+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR0(band_idx));
3866+ seq_printf(s, "\tTx 20MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK);
3867+ seq_printf(s, "\tTx 40MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT);
3868+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR1(band_idx));
3869+ seq_printf(s, "\tTx 80MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK);
3870+ seq_printf(s, "\tTx 160MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT);
3871+ seq_printf(s, "\tAMPDU Cnt=0x%x\n", ampdu_cnt[0]);
3872+ seq_printf(s, "\tAMPDU MPDU Cnt=0x%x\n", ampdu_cnt[1]);
3873+ seq_printf(s, "\tAMPDU MPDU Ack Cnt=0x%x\n", ampdu_cnt[2]);
3874+ per = (ampdu_cnt[2] == 0 ? 0 : 1000 * (ampdu_cnt[1] - ampdu_cnt[2]) / ampdu_cnt[1]);
3875+ seq_printf(s, "\tAMPDU MPDU PER=%ld.%1ld%%\n", per / 10, per % 10);
3876+
3877+ seq_printf(s, "===MU Related Counters===\n");
3878+ mu_cnt[0] = mt76_rr(dev, MT_DBG_MIB_MUBF(band_idx));
3879+ mu_cnt[1] = mt76_rr(dev, MT_DBG_MIB_M0DR8(band_idx));
3880+ mu_cnt[2] = mt76_rr(dev, MT_DBG_MIB_M0DR9(band_idx));
3881+ mu_cnt[3] = mt76_rr(dev, MT_DBG_MIB_M0DR10(band_idx));
3882+ mu_cnt[4] = mt76_rr(dev, MT_DBG_MIB_M0DR11(band_idx));
3883+ seq_printf(s, "\tMUBF_TX_COUNT=0x%x\n", mu_cnt[0] & BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK);
3884+ seq_printf(s, "\tMU_TX_MPDU_COUNT(Ok+Fail)=0x%x\n", mu_cnt[1]);
3885+ seq_printf(s, "\tMU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[2]);
3886+ seq_printf(s, "\tMU_TO_SU_PPDU_COUNT=0x%x\n", mu_cnt[3] & BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK);
3887+ seq_printf(s, "\tSU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[4]);
3888+
3889+ seq_printf(s, "===Rx Related Counters(Generic)===\n");
3890+ seq_printf(s, "\tVector Mismacth Cnt=0x%x\n", msdr7 & BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK);
3891+ seq_printf(s, "\tDelimiter Fail Cnt=0x%x\n", msdr8 & BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK);
3892+
3893+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR3(band_idx));
3894+ seq_printf(s, "\tRxFCSErrCnt=0x%lx\n", __DBG_FIELD_GET(DBG_MIB_RX_FCS_ERROR_COUNT, mac_val));
3895+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR4(band_idx));
3896+ seq_printf(s, "\tRxFifoFullCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK));
3897+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR11(band_idx));
3898+ seq_printf(s, "\tRxLenMismatch=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK));
3899+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR5(band_idx));
3900+ seq_printf(s, "\tRxMPDUCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK));
3901+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR22(band_idx));
3902+ seq_printf(s, "\tRx AMPDU Cnt=0x%x\n", mac_val);
3903+ /* TODO: shiang-MT7615, is MIB_M0SDR23 used for Rx total byte count for all or just AMPDU only??? */
3904+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR23(band_idx));
3905+ seq_printf(s, "\tRx Total ByteCnt=0x%x\n", mac_val);
3906+
3907+ if (is_mt7915(&dev->mt76)) {
3908+ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;//check
3909+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3910+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
3911+
3912+ for (idx = 0; idx < BSS_NUM; idx++) {
3913+ btcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTCRn_ADDR + band_offset + idx * 4);
3914+ btbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTBCRn_ADDR + band_offset + idx * 4);
3915+ brcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRCRn_ADDR + band_offset + idx * 4);
3916+ brbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRBCRn_ADDR + band_offset + idx * 4);
3917+ btdcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTDCRn_ADDR + band_offset + idx * 4);
3918+ brdcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRDCRn_ADDR + band_offset + idx * 4);
3919+ }
3920+
3921+ for (idx = 0; idx < BSS_NUM; idx++) {
3922+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3923+ idx, btcr[idx], btdcr[idx], btbcr[idx],
3924+ brcr[idx], brdcr[idx], brbcr[idx]);
3925+ }
3926+
3927+ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
3928+ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
3929+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3930+
3931+ for (idx = 0; idx < BSS_NUM; idx++) {
3932+ mbxsdr[idx][0] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR0_ADDR + band_offset + idx * 0x10);
3933+ mbxsdr[idx][1] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR1_ADDR + band_offset + idx * 0x10);
3934+ mbxsdr[idx][2] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR2_ADDR + band_offset + idx * 0x10);
3935+ mbxsdr[idx][3] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR3_ADDR + band_offset + idx * 0x10);
3936+ }
3937+
3938+ for (idx = 0; idx < BSS_NUM; idx++) {
3939+ seq_printf(s, "%d:\t0x%08x/0x%08x 0x%08x \t 0x%08x \t 0x%08x/0x%08x/0x%08x\n",
3940+ idx, (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK),
3941+ (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT,
3942+ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK),
3943+ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT,
3944+ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK),
3945+ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT,
3946+ (mbxsdr[idx][3] & BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK));
3947+ }
3948+
3949+ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;
3950+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3951+ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
3952+
3953+ for (idx = 0; idx < 16; idx++) {
3954+ mbtcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBTCRn_ADDR + band_offset + idx * 4);
3955+ mbtbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBTBCRn_ADDR + band_offset + idx * 4);
3956+ mbrcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBRCRn_ADDR + band_offset + idx * 4);
3957+ mbrbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBRBCRn_ADDR + band_offset + idx * 4);
3958+ }
3959+
3960+ for (idx = 0; idx < 16; idx++) {
3961+ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
3962+ idx, mbtcr[idx], mbtbcr[idx], mbrcr[idx], mbrbcr[idx]);
3963+ }
3964+ return 0;
3965+ } else {
3966+ u32 btocr[BSS_NUM], mbtocr[16],mbrocr[16], brocr[BSS_NUM];
3967+ u8 bss_nums = BSS_NUM;
3968+
3969+ band_offset = (BN1_WF_MIB_TOP_BTOCR_ADDR - BN0_WF_MIB_TOP_BTOCR_ADDR) * band_idx;
3970+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3971+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
3972+
3973+ for (idx = 0; idx < BSS_NUM; idx++) {
3974+ btocr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (idx >> 1) * 4));
3975+ btdcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTDCR_ADDR + band_offset + (idx >> 1) * 4));
3976+ btbcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (idx * 4)));
3977+ brocr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BROCR_ADDR + band_offset + (idx >> 1) * 4));
3978+ brdcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BRDCR_ADDR + band_offset + (idx >> 1) * 4));
3979+ brbcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BRBCR_ADDR + band_offset + (idx * 4)));
3980+
3981+ if ((idx % 2) == 0) {
3982+ btocr[idx] = ((btocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT);
3983+ btdcr[idx] = ((btdcr[idx] & BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT);
3984+ brocr[idx] = ((brocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT);
3985+ brdcr[idx] = ((brdcr[idx] & BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT);
3986+ } else {
3987+ btocr[idx] = ((btocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT);
3988+ btdcr[idx] = ((btdcr[idx] & BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT);
3989+ brocr[idx] = ((brocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT);
3990+ brdcr[idx] = ((brdcr[idx] & BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT);
3991+ }
3992+ }
3993+
3994+ for (idx = 0; idx < BSS_NUM; idx++) {
3995+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3996+ idx, btocr[idx], btdcr[idx], btbcr[idx], brocr[idx], brdcr[idx], brbcr[idx]);
3997+ }
3998+
3999+ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
4000+ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
4001+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
4002+
4003+ for (idx = 0; idx < BSS_NUM; idx++) {
4004+ mbxsdr[idx][0] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR0_ADDR + band_offset + ((idx >> 1) * 4));
4005+ mbxsdr[idx][1] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR1_ADDR + band_offset + ((idx >> 1) * 4));
4006+ mbxsdr[idx][2] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR2_ADDR + band_offset + ((idx >> 1) * 4));
4007+ mbxsdr[idx][3] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR3_ADDR + band_offset + ((idx >> 1) * 4));
4008+ mbxsdr[idx][4] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR4_ADDR + band_offset + ((idx >> 1) * 4));
4009+ mbxsdr[idx][5] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR5_ADDR + band_offset + ((idx >> 1) * 4));
4010+ mbxsdr[idx][6] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR6_ADDR + band_offset + ((idx >> 1) * 4));
4011+
4012+ if ((idx % 2) == 0) {
4013+ mbxsdr[idx][0] = ((mbxsdr[idx][0] & BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT);
4014+ mbxsdr[idx][1] = ((mbxsdr[idx][1] & BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT);
4015+ mbxsdr[idx][2] = ((mbxsdr[idx][2] & BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT);
4016+ mbxsdr[idx][3] = ((mbxsdr[idx][3] & BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT);
4017+ mbxsdr[idx][4] = ((mbxsdr[idx][4] & BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT);
4018+ mbxsdr[idx][5] = ((mbxsdr[idx][5] & BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT);
4019+ mbxsdr[idx][6] = ((mbxsdr[idx][6] & BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT);
4020+ } else {
4021+ mbxsdr[idx][0] = ((mbxsdr[idx][0] & BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT);
4022+ mbxsdr[idx][1] = ((mbxsdr[idx][1] & BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT);
4023+ mbxsdr[idx][2] = ((mbxsdr[idx][2] & BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT);
4024+ mbxsdr[idx][3] = ((mbxsdr[idx][3] & BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT);
4025+ mbxsdr[idx][4] = ((mbxsdr[idx][4] & BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT);
4026+ mbxsdr[idx][5] = ((mbxsdr[idx][5] & BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT);
4027+ mbxsdr[idx][6] = ((mbxsdr[idx][6] & BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT);
4028+ }
4029+ }
4030+
4031+ for (idx = 0; idx < BSS_NUM; idx++) {
4032+ seq_printf(s, "%d:\t0x%x/0x%x 0x%x \t 0x%x \t 0x%x/0x%x/0x%x\n",
4033+ idx,
4034+ mbxsdr[idx][0], mbxsdr[idx][1], mbxsdr[idx][2], mbxsdr[idx][3],
4035+ mbxsdr[idx][4], mbxsdr[idx][5], mbxsdr[idx][6]);
4036+ }
4037+
4038+ band_offset = (BN1_WF_MIB_TOP_BTOCR_ADDR - BN0_WF_MIB_TOP_BTOCR_ADDR) * band_idx;
4039+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
4040+ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
4041+
4042+ for (idx = 0; idx < 16; idx++) {
4043+ mbtocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + ((idx >> 1) * 4)));
4044+ mbtbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + (idx * 4)));
4045+ mbrocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BROCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + ((idx >> 1) * 4)));
4046+ mbrbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BRBCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + (idx * 4)));
4047+
4048+ if ((idx % 2) == 0) {
4049+ mbtocr[idx] = ((mbtocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT);
4050+ mbrocr[idx] = ((mbrocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT);
4051+ } else {
4052+ mbtocr[idx] = ((mbtocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT);
4053+ mbrocr[idx] = ((mbrocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT);
4054+ }
4055+ }
4056+
4057+ for (idx = 0; idx < 16; idx++) {
4058+ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
4059+ idx, mbtocr[idx], mbtbcr[idx], mbrocr[idx], mbrbcr[idx]);
4060+ }
4061+ }
4062+
4063+ seq_printf(s, "===Dummy delimiter insertion result===\n");
4064+ mac_val0 = mt76_rr(dev, MT_DBG_MIB_M0DR11(band_idx));
4065+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR6(band_idx));
4066+ mac_val1 = mt76_rr(dev, MT_DBG_MIB_M0DR7(band_idx));
4067+ seq_printf(s, "Range0 = %d\t Range1 = %d\t Range2 = %d\t Range3 = %d\t Range4 = %d\n",
4068+ (mac_val0 & BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK),
4069+ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK),
4070+ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT,
4071+ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK),
4072+ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT);
4073+
4074+ return 0;
4075+}
4076+
4077+static int mt7915_mibinfo_band0(struct seq_file *s, void *data)
4078+{
4079+ mt7915_mibinfo_read_per_band(s, 0);
4080+ return 0;
4081+}
4082+
4083+static int mt7915_mibinfo_band1(struct seq_file *s, void *data)
4084+{
4085+ mt7915_mibinfo_read_per_band(s, 1);
4086+ return 0;
4087+}
4088+
4089+static int mt7915_token_read(struct seq_file *s, void *data)
4090+{
4091+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4092+ int id, count = 0;
4093+ struct mt76_txwi_cache *txwi;
4094+
4095+ seq_printf(s, "Cut through token:\n");
4096+ spin_lock_bh(&dev->mt76.token_lock);
4097+ idr_for_each_entry(&dev->mt76.token, txwi, id) {
4098+ seq_printf(s, "%4d ", id);
4099+ count++;
4100+ if (count % 8 == 0)
4101+ seq_printf(s, "\n");
4102+ }
4103+ spin_unlock_bh(&dev->mt76.token_lock);
4104+ seq_printf(s, "\n");
4105+
4106+ return 0;
4107+}
4108+
4109+struct txd_l {
4110+ u32 txd_0;
4111+ u32 txd_1;
4112+ u32 txd_2;
4113+ u32 txd_3;
4114+ u32 txd_4;
4115+ u32 txd_5;
4116+ u32 txd_6;
4117+ u32 txd_7;
4118+} __packed;
4119+
4120+char *pkt_ft_str[] = {"cut_through", "store_forward", "cmd", "PDA_FW_Download"};
4121+char *hdr_fmt_str[] = {
4122+ "Non-80211-Frame",
4123+ "Command-Frame",
4124+ "Normal-80211-Frame",
4125+ "enhanced-80211-Frame",
4126+};
4127+/* TMAC_TXD_1.hdr_format */
4128+#define TMI_HDR_FT_NON_80211 0x0
4129+#define TMI_HDR_FT_CMD 0x1
4130+#define TMI_HDR_FT_NOR_80211 0x2
4131+#define TMI_HDR_FT_ENH_80211 0x3
4132+
4133+void mt7915_dump_tmac_info(u8 *tmac_info)
4134+{
4135+ struct txd_l *txd = (struct txd_l *)tmac_info;
4136+
4137+ printk("txd raw data: size=%d\n", MT_TXD_SIZE);
4138+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, tmac_info, MT_TXD_SIZE, false);
4139+
4140+ printk("TMAC_TXD Fields:\n");
4141+ printk("\tTMAC_TXD_0:\n");
4142+
4143+ /* DW0 */
4144+ /* TX Byte Count [15:0] */
4145+ printk("\t\tTxByteCnt = %ld\n", FIELD_GET(MT_TXD0_TX_BYTES, txd->txd_0));
4146+
4147+ /* PKT_FT: Packet Format [24:23] */
4148+ printk("\t\tpkt_ft = %ld(%s)\n",
4149+ FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0),
4150+ pkt_ft_str[FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0)]);
4151+
4152+ /* Q_IDX [31:25] */
4153+ printk("\t\tQueID =0x%lx\n", FIELD_GET(MT_TXD0_Q_IDX, txd->txd_0));
4154+
4155+ printk("\tTMAC_TXD_1:\n");
4156+
4157+ /* DW1 */
4158+ /* WLAN Indec [9:0] */
4159+ printk("\t\tWlan Index = %ld\n", FIELD_GET(MT_TXD1_WLAN_IDX, txd->txd_1));
4160+
4161+ /* VTA [10] */
4162+ printk("\t\tVTA = %d\n", ((txd->txd_1 & MT_TXD1_VTA) ? 1 : 0));
4163+
4164+ /* HF: Header Format [17:16] */
4165+ printk("\t\tHdrFmt = %ld(%s)\n",
4166+ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1),
4167+ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1) < 4 ?
4168+ hdr_fmt_str[FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)] : "N/A");
4169+
4170+ switch (FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)) {
4171+ case TMI_HDR_FT_NON_80211:
4172+ /* MRD [11], EOSP [12], RMVL [13], VLAN [14], ETYPE [15] */
4173+ printk("\t\t\tMRD = %d, EOSP = %d,\
4174+ RMVL = %d, VLAN = %d, ETYP = %d\n",
4175+ (txd->txd_1 & MT_TXD1_MRD) ? 1 : 0,
4176+ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
4177+ (txd->txd_1 & MT_TXD1_RMVL) ? 1 : 0,
4178+ (txd->txd_1 & MT_TXD1_VLAN) ? 1 : 0,
4179+ (txd->txd_1 & MT_TXD1_ETYP) ? 1 : 0);
4180+ break;
4181+ case TMI_HDR_FT_NOR_80211:
4182+ /* HEADER_LENGTH [15:11] */
4183+ printk("\t\t\tHeader Len = %ld(WORD)\n", FIELD_GET(MT_TXD1_HDR_INFO, txd->txd_1));
4184+ break;
4185+
4186+ case TMI_HDR_FT_ENH_80211:
4187+ /* EOSP [12], AMS [13] */
4188+ printk("\t\t\tEOSP = %d, AMS = %d\n",
4189+ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
4190+ (txd->txd_1 & MT_TXD1_AMS) ? 1 : 0);
4191+ break;
4192+ }
4193+
4194+ /* Header Padding [19:18] */
4195+ printk("\t\tHdrPad = %ld\n", FIELD_GET(MT_TXD1_HDR_PAD, txd->txd_1));
4196+
4197+ /* TID [22:20] */
4198+ printk("\t\tTID = %ld\n", FIELD_GET(MT_TXD1_TID, txd->txd_1));
4199+
4200+
4201+ /* UtxB/AMSDU_C/AMSDU [23] */
4202+ printk("\t\tamsdu = %d\n", ((txd->txd_1 & MT_TXD1_AMSDU) ? 1 : 0));
4203+
4204+ /* OM [29:24] */
4205+ printk("\t\town_mac = %ld\n", FIELD_GET(MT_TXD1_OWN_MAC, txd->txd_1));
4206+
4207+
4208+ /* TGID [30] */
4209+ printk("\t\tTGID = %d\n", ((txd->txd_1 & MT_TXD1_TGID) ? 1 : 0));
4210+
4211+
4212+ /* FT [31] */
4213+ printk("\t\tTxDFormatType = %d\n", (txd->txd_1 & MT_TXD1_LONG_FORMAT) ? 1 : 0);
4214+
4215+ printk("\tTMAC_TXD_2:\n");
4216+ /* DW2 */
4217+ /* Subtype [3:0] */
4218+ printk("\t\tsub_type = %ld\n", FIELD_GET(MT_TXD2_SUB_TYPE, txd->txd_2));
4219+
4220+ /* Type[5:4] */
4221+ printk("\t\tfrm_type = %ld\n", FIELD_GET(MT_TXD2_FRAME_TYPE, txd->txd_2));
4222+
4223+ /* NDP [6] */
4224+ printk("\t\tNDP = %d\n", ((txd->txd_2 & MT_TXD2_NDP) ? 1 : 0));
4225+
4226+ /* NDPA [7] */
4227+ printk("\t\tNDPA = %d\n", ((txd->txd_2 & MT_TXD2_NDPA) ? 1 : 0));
4228+
4229+ /* SD [8] */
4230+ printk("\t\tSounding = %d\n", ((txd->txd_2 & MT_TXD2_SOUNDING) ? 1 : 0));
4231+
4232+ /* RTS [9] */
4233+ printk("\t\tRTS = %d\n", ((txd->txd_2 & MT_TXD2_RTS) ? 1 : 0));
4234+
4235+ /* BM [10] */
4236+ printk("\t\tbc_mc_pkt = %d\n", ((txd->txd_2 & MT_TXD2_MULTICAST) ? 1 : 0));
4237+
4238+ /* B [11] */
4239+ printk("\t\tBIP = %d\n", ((txd->txd_2 & MT_TXD2_BIP) ? 1 : 0));
4240+
4241+ /* DU [12] */
4242+ printk("\t\tDuration = %d\n", ((txd->txd_2 & MT_TXD2_DURATION) ? 1 : 0));
4243+
4244+ /* HE [13] */
4245+ printk("\t\tHE(HTC Exist) = %d\n", ((txd->txd_2 & MT_TXD2_HTC_VLD) ? 1 : 0));
4246+
4247+ /* FRAG [15:14] */
4248+ printk("\t\tFRAG = %ld\n", FIELD_GET(MT_TXD2_FRAG, txd->txd_2));
4249+
4250+
4251+ /* Remaining Life Time [23:16]*/
4252+ printk("\t\tReamingLife/MaxTx time = %ld (unit: 64TU)\n",
4253+ FIELD_GET(MT_TXD2_MAX_TX_TIME, txd->txd_2));
4254+
4255+ /* Power Offset [29:24] */
4256+ printk("\t\tpwr_offset = %ld\n", FIELD_GET(MT_TXD2_POWER_OFFSET, txd->txd_2));
4257+
4258+ /* FRM [30] */
4259+ printk("\t\tfix rate mode = %d\n", (txd->txd_2 & MT_TXD2_FIXED_RATE) ? 1 : 0);
4260+
4261+ /* FR[31] */
4262+ printk("\t\tfix rate = %d\n", (txd->txd_2 & MT_TXD2_FIX_RATE) ? 1 : 0);
4263+
4264+
4265+ printk("\tTMAC_TXD_3:\n");
4266+
4267+ /* DW3 */
4268+ /* NA [0] */
4269+ printk("\t\tNoAck = %d\n", (txd->txd_3 & MT_TXD3_NO_ACK) ? 1 : 0);
4270+
4271+ /* PF [1] */
4272+ printk("\t\tPF = %d\n", (txd->txd_3 & MT_TXD3_PROTECT_FRAME) ? 1 : 0);
4273+
4274+ /* EMRD [2] */
4275+ printk("\t\tEMRD = %d\n", (txd->txd_3 & MT_TXD3_EMRD) ? 1 : 0);
4276+
4277+ /* EEOSP [3] */
4278+ printk("\t\tEEOSP = %d\n", (txd->txd_3 & MT_TXD3_EEOSP) ? 1 : 0);
4279+
4280+ /* DAS [4] */
4281+ printk("\t\tda_select = %d\n", (txd->txd_3 & MT_TXD3_DAS) ? 1 : 0);
4282+
4283+ /* TM [5] */
4284+ printk("\t\ttm = %d\n", (txd->txd_3 & MT_TXD3_TIMING_MEASURE) ? 1 : 0);
4285+
4286+ /* TX Count [10:6] */
4287+ printk("\t\ttx_cnt = %ld\n", FIELD_GET(MT_TXD3_TX_COUNT, txd->txd_3));
4288+
4289+ /* Remaining TX Count [15:11] */
4290+ printk("\t\tremain_tx_cnt = %ld\n", FIELD_GET(MT_TXD3_REM_TX_COUNT, txd->txd_3));
4291+
4292+ /* SN [27:16] */
4293+ printk("\t\tsn = %ld\n", FIELD_GET(MT_TXD3_SEQ, txd->txd_3));
4294+
4295+ /* BA_DIS [28] */
4296+ printk("\t\tba dis = %d\n", (txd->txd_3 & MT_TXD3_BA_DISABLE) ? 1 : 0);
4297+
4298+ /* Power Management [29] */
4299+ printk("\t\tpwr_mgmt = 0x%x\n", (txd->txd_3 & MT_TXD3_SW_POWER_MGMT) ? 1 : 0);
4300+
4301+ /* PN_VLD [30] */
4302+ printk("\t\tpn_vld = %d\n", (txd->txd_3 & MT_TXD3_PN_VALID) ? 1 : 0);
4303+
4304+ /* SN_VLD [31] */
4305+ printk("\t\tsn_vld = %d\n", (txd->txd_3 & MT_TXD3_SN_VALID) ? 1 : 0);
4306+
4307+
4308+ /* DW4 */
4309+ printk("\tTMAC_TXD_4:\n");
4310+
4311+ /* PN_LOW [31:0] */
4312+ printk("\t\tpn_low = 0x%lx\n", FIELD_GET(MT_TXD4_PN_LOW, txd->txd_4));
4313+
4314+
4315+ /* DW5 */
4316+ printk("\tTMAC_TXD_5:\n");
4317+
4318+ /* PID [7:0] */
4319+ printk("\t\tpid = %ld\n", FIELD_GET(MT_TXD5_PID, txd->txd_5));
4320+
4321+ /* TXSFM [8] */
4322+ printk("\t\ttx_status_fmt = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_FMT) ? 1 : 0);
4323+
4324+ /* TXS2M [9] */
4325+ printk("\t\ttx_status_2_mcu = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_MCU) ? 1 : 0);
4326+
4327+ /* TXS2H [10] */
4328+ printk("\t\ttx_status_2_host = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_HOST) ? 1 : 0);
4329+
4330+ /* ADD_BA [14] */
4331+ printk("\t\tADD_BA = %d\n", (txd->txd_5 & MT_TXD5_ADD_BA) ? 1 : 0);
4332+
4333+ /* MD [15] */
4334+ printk("\t\tMD = %d\n", (txd->txd_5 & MT_TXD5_MD) ? 1 : 0);
4335+
4336+ /* PN_HIGH [31:16] */
4337+ printk("\t\tpn_high = 0x%lx\n", FIELD_GET(MT_TXD5_PN_HIGH, txd->txd_5));
4338+
4339+ /* DW6 */
4340+ printk("\tTMAC_TXD_6:\n");
4341+
4342+ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4343+ /* Fixed BandWidth mode [2:0] */
developer2aa1e642022-12-19 11:33:22 +08004344+ printk("\t\tbw = %ld\n",
4345+ FIELD_GET(MT_TXD6_BW, txd->txd_6) | (txd->txd_6 & MT_TXD6_FIXED_BW));
developer3fa816c2022-04-19 10:21:20 +08004346+
4347+ /* DYN_BW [3] */
4348+ printk("\t\tdyn_bw = %d\n", (txd->txd_6 & MT_TXD6_DYN_BW) ? 1 : 0);
4349+
4350+ /* ANT_ID [7:4] */
4351+ printk("\t\tant_id = %ld\n", FIELD_GET(MT_TXD6_ANT_ID, txd->txd_6));
4352+
4353+ /* SPE_IDX_SEL [10] */
4354+ printk("\t\tspe_idx_sel = %d\n", (txd->txd_6 & MT_TXD6_SPE_ID_IDX) ? 1 : 0);
4355+
4356+ /* LDPC [11] */
4357+ printk("\t\tldpc = %d\n", (txd->txd_6 & MT_TXD6_LDPC) ? 1 : 0);
4358+
4359+ /* HELTF Type[13:12] */
4360+ printk("\t\tHELTF Type = %ld\n", FIELD_GET(MT_TXD6_HELTF, txd->txd_6));
4361+
4362+ /* GI Type [15:14] */
4363+ printk("\t\tGI = %ld\n", FIELD_GET(MT_TXD6_SGI, txd->txd_6));
4364+
4365+ /* Rate to be Fixed [29:16] */
4366+ printk("\t\ttx_rate = 0x%lx\n", FIELD_GET(MT_TXD6_TX_RATE, txd->txd_6));
4367+ }
4368+
4369+ /* TXEBF [30] */
4370+ printk("\t\ttxebf = %d\n", (txd->txd_6 & MT_TXD6_TX_EBF) ? 1 : 0);
4371+
4372+ /* TXIBF [31] */
4373+ printk("\t\ttxibf = %d\n", (txd->txd_6 & MT_TXD6_TX_IBF) ? 1 : 0);
4374+
4375+ /* DW7 */
4376+ printk("\tTMAC_TXD_7:\n");
4377+
4378+ if ((txd->txd_1 & MT_TXD1_VTA) == 0) {
4379+ /* SW Tx Time [9:0] */
4380+ printk("\t\tsw_tx_time = %ld\n", FIELD_GET(MT_TXD7_TX_TIME, txd->txd_7));
4381+ } else {
4382+ /* TXD Arrival Time [9:0] */
4383+ printk("\t\tat = %ld\n", FIELD_GET(MT_TXD7_TAT, txd->txd_7));
4384+ }
4385+
4386+ /* HW_AMSDU_CAP [10] */
4387+ printk("\t\thw amsdu cap = %d\n",(txd->txd_7 & MT_TXD7_HW_AMSDU) ? 1 : 0);
4388+
4389+ /* SPE_IDX [15:11] */
4390+ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4391+ printk("\t\tspe_idx = 0x%lx\n", FIELD_GET(MT_TXD7_SPE_IDX, txd->txd_7));
4392+ }
4393+
4394+ /* PSE_FID [27:16] */
4395+ printk("\t\tpse_fid = 0x%lx\n", FIELD_GET(MT_TXD7_PSE_FID, txd->txd_7));
4396+
4397+ /* Subtype [19:16] */
4398+ printk("\t\tpp_sub_type=%ld\n", FIELD_GET(MT_TXD7_SUB_TYPE, txd->txd_7));
4399+
4400+ /* Type [21:20] */
4401+ printk("\t\tpp_type=%ld\n", FIELD_GET(MT_TXD7_TYPE, txd->txd_7));
4402+
4403+ /* CTXD_CNT [25:23] */
4404+ printk("\t\tctxd cnt=0x%lx\n", FIELD_GET(MT_TXD7_CTXD_CNT, txd->txd_7));
4405+
4406+ /* CTXD [26] */
4407+ printk("\t\tctxd = %d\n", (txd->txd_7 & MT_TXD7_CTXD) ? 1 : 0);
4408+
4409+ /* I [28] */
4410+ printk("\t\ti = %d\n", (txd->txd_7 & MT_TXD7_IP_SUM) ? 1 : 0);
4411+
4412+ /* UT [29] */
4413+ printk("\t\tUT = %d\n", (txd->txd_7 & MT_TXD7_UDP_TCP_SUM) ? 1 : 0);
4414+
4415+ /* TXDLEN [31:30] */
4416+ printk("\t\t txd len= %ld\n", FIELD_GET(MT_TXD7_TXD_LEN, txd->txd_7));
4417+}
4418+
4419+
4420+static int mt7915_token_txd_read(struct seq_file *s, void *data)
4421+{
4422+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4423+ struct mt76_txwi_cache *t;
4424+ u8* txwi;
4425+
4426+ seq_printf(s, "\n");
4427+ spin_lock_bh(&dev->mt76.token_lock);
4428+
4429+ t = idr_find(&dev->mt76.token, dev->dbg.token_idx);
4430+
4431+ spin_unlock_bh(&dev->mt76.token_lock);
4432+ if (t != NULL) {
4433+ struct mt76_dev *mdev = &dev->mt76;
4434+ txwi = ((u8*)(t)) - (mdev->drv->txwi_size);
4435+ mt7915_dump_tmac_info((u8*) txwi);
4436+ seq_printf(s, "\n");
4437+ printk("[SKB]\n");
4438+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)t->skb->data, t->skb->len, false);
4439+ seq_printf(s, "\n");
4440+ }
4441+ return 0;
4442+}
4443+
4444+static int mt7915_amsduinfo_read(struct seq_file *s, void *data)
4445+{
4446+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4447+ u32 ple_stat[8] = {0}, total_amsdu = 0;
4448+ u8 i;
4449+
4450+ for (i = 0; i < 8; i++)
4451+ ple_stat[i] = mt76_rr(dev, MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(i));
4452+
4453+ seq_printf(s, "TXD counter status of MSDU:\n");
4454+
4455+ for (i = 0; i < 8; i++)
4456+ total_amsdu += ple_stat[i];
4457+
4458+ for (i = 0; i < 8; i++) {
4459+ seq_printf(s, "AMSDU pack count of %d MSDU in TXD: 0x%x ", i + 1, ple_stat[i]);
4460+ if (total_amsdu != 0)
4461+ seq_printf(s, "(%d%%)\n", ple_stat[i] * 100 / total_amsdu);
4462+ else
4463+ seq_printf(s, "\n");
4464+ }
4465+
4466+ return 0;
4467+
4468+}
4469+
4470+static int mt7915_agginfo_read_per_band(struct seq_file *s, int band_idx)
4471+{
4472+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4473+ u32 value, idx, agg_rang_sel[15], ampdu_cnt[11], total_ampdu = 0;
4474+
4475+ seq_printf(s, "Band %d AGG Status\n", band_idx);
4476+ seq_printf(s, "===============================\n");
4477+ value = mt76_rr(dev, MT_DBG_AGG_AALCR0(band_idx));
4478+ seq_printf(s, "AC00 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4479+ seq_printf(s, "AC01 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4480+ seq_printf(s, "AC02 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4481+ seq_printf(s, "AC03 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4482+
4483+ value = mt76_rr(dev, MT_DBG_AGG_AALCR1(band_idx));
4484+ seq_printf(s, "AC10 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4485+ seq_printf(s, "AC11 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4486+ seq_printf(s, "AC12 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4487+ seq_printf(s, "AC13 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4488+
4489+ value = mt76_rr(dev, MT_DBG_AGG_AALCR2(band_idx));
4490+ seq_printf(s, "AC20 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4491+ seq_printf(s, "AC21 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4492+ seq_printf(s, "AC22 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4493+ seq_printf(s, "AC23 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4494+
4495+ value = mt76_rr(dev, MT_DBG_AGG_AALCR3(band_idx));
4496+ seq_printf(s, "AC30 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4497+ seq_printf(s, "AC31 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4498+ seq_printf(s, "AC32 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4499+ seq_printf(s, "AC33 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4500+
4501+ value = mt76_rr(dev, MT_DBG_AGG_AALCR4(band_idx));
4502+ seq_printf(s, "ALTX Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK, value));
4503+
4504+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 0));
4505+ seq_printf(s, "Winsize0 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE0_MASK, value));
4506+ seq_printf(s, "Winsize1 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE1_MASK, value));
4507+ seq_printf(s, "Winsize2 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE2_MASK, value));
4508+ seq_printf(s, "Winsize3 limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE3_MASK, value));
4509+
4510+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 1));
4511+ seq_printf(s, "Winsize4 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE4_MASK, value));
4512+ seq_printf(s, "Winsize5 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE5_MASK, value));
4513+ seq_printf(s, "Winsize6 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE6_MASK, value));
4514+ seq_printf(s, "Winsize7 limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE7_MASK, value));
4515+
4516+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 2));
4517+ seq_printf(s, "Winsize8 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZE8_MASK, value));
4518+ seq_printf(s, "Winsize9 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZE9_MASK, value));
4519+ seq_printf(s, "WinsizeA limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZEA_MASK, value));
4520+ seq_printf(s, "WinsizeB limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZEB_MASK, value));
4521+
4522+
4523+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 3));
4524+ seq_printf(s, "WinsizeC limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZEC_MASK, value));
4525+ seq_printf(s, "WinsizeD limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZED_MASK, value));
4526+ seq_printf(s, "WinsizeE limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZEE_MASK, value));
4527+
4528+ seq_printf(s, "===AMPDU Related Counters===\n");
4529+
4530+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 0));
4531+ agg_rang_sel[0] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK, value);
4532+ agg_rang_sel[1] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK, value);
4533+ agg_rang_sel[2] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK, value);
4534+ agg_rang_sel[3] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK, value);
4535+
4536+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 1));
4537+ agg_rang_sel[4] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK, value);
4538+ agg_rang_sel[5] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK, value);
4539+ agg_rang_sel[6] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK, value);
4540+ agg_rang_sel[7] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK, value);
4541+
4542+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 2));
4543+ agg_rang_sel[8] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK, value);
4544+ agg_rang_sel[9] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK, value);
4545+ agg_rang_sel[10] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK, value);
4546+ agg_rang_sel[11] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK, value);
4547+
4548+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 3));
4549+ agg_rang_sel[12] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK, value);
4550+ agg_rang_sel[13] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK, value);
4551+ agg_rang_sel[14] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK, value);
4552+
4553+ /* Need to add 1 after read from AGG_RANG_SEL CR */
4554+ for (idx = 0; idx < 15; idx++)
4555+ agg_rang_sel[idx]++;
4556+
4557+ ampdu_cnt[3] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 0));
4558+ ampdu_cnt[4] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 1));
4559+ ampdu_cnt[5] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 2));
4560+ ampdu_cnt[6] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 3));
4561+ ampdu_cnt[7] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 0));
4562+ ampdu_cnt[8] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 1));
4563+ ampdu_cnt[9] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 2));
4564+ ampdu_cnt[10] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 3));
4565+
4566+ seq_printf(s, "\tTx Agg Range: \t%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d\n",
4567+ agg_rang_sel[0],
4568+ agg_rang_sel[0] + 1, agg_rang_sel[1],
4569+ agg_rang_sel[1] + 1, agg_rang_sel[2],
4570+ agg_rang_sel[2] + 1, agg_rang_sel[3],
4571+ agg_rang_sel[3] + 1, agg_rang_sel[4],
4572+ agg_rang_sel[4] + 1, agg_rang_sel[5],
4573+ agg_rang_sel[5] + 1, agg_rang_sel[6],
4574+ agg_rang_sel[6] + 1, agg_rang_sel[7]);
4575+
4576+#define BIT_0_to_15_MASK 0x0000FFFF
4577+#define BIT_15_to_31_MASK 0xFFFF0000
4578+#define SHFIT_16_BIT 16
4579+
4580+ for (idx = 3; idx < 11; idx++)
4581+ total_ampdu = total_ampdu + (ampdu_cnt[idx] & BIT_0_to_15_MASK) + ((ampdu_cnt[idx] & BIT_15_to_31_MASK) >> SHFIT_16_BIT);
4582+
4583+ seq_printf(s, "\t\t\t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx\n",
4584+ (ampdu_cnt[3]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK,
4585+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[3]),
4586+ (ampdu_cnt[4]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK,
4587+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[4]),
4588+ (ampdu_cnt[5]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK,
4589+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[5]),
4590+ (ampdu_cnt[6]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK,
4591+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[6]));
4592+
4593+ if (total_ampdu != 0) {
4594+ seq_printf(s, "\t\t\t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%)\n",
4595+ ((ampdu_cnt[3]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK) * 100 / total_ampdu,
4596+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[3]) * 100 / total_ampdu,
4597+ ((ampdu_cnt[4]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK) * 100 / total_ampdu,
4598+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[4]) * 100 / total_ampdu,
4599+ ((ampdu_cnt[5]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK) * 100 / total_ampdu,
4600+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[5]) * 100 / total_ampdu,
4601+ ((ampdu_cnt[6]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK) * 100 / total_ampdu,
4602+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[6]) * 100 / total_ampdu);
4603+ }
4604+
4605+ seq_printf(s, "\t\t\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~256\n",
4606+ agg_rang_sel[7] + 1, agg_rang_sel[8],
4607+ agg_rang_sel[8] + 1, agg_rang_sel[9],
4608+ agg_rang_sel[9] + 1, agg_rang_sel[10],
4609+ agg_rang_sel[10] + 1, agg_rang_sel[11],
4610+ agg_rang_sel[11] + 1, agg_rang_sel[12],
4611+ agg_rang_sel[12] + 1, agg_rang_sel[13],
4612+ agg_rang_sel[13] + 1, agg_rang_sel[14],
4613+ agg_rang_sel[14] + 1);
4614+
4615+ seq_printf(s, "\t\t\t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx\n",
4616+ (ampdu_cnt[7]) & MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK,
4617+ FIELD_GET(MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK, ampdu_cnt[7]),
4618+ (ampdu_cnt[8]) & MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK,
4619+ FIELD_GET(MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK, ampdu_cnt[8]),
4620+ (ampdu_cnt[9]) & MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK,
4621+ FIELD_GET(MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK, ampdu_cnt[9]),
4622+ (ampdu_cnt[10]) & MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK,
4623+ FIELD_GET(MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK, ampdu_cnt[10]));
4624+
4625+ if (total_ampdu != 0) {
4626+ seq_printf(s, "\t\t\t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%)\n",
4627+ ((ampdu_cnt[7]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK) * 100 / total_ampdu,
4628+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[7]) * 100 / total_ampdu,
4629+ ((ampdu_cnt[8]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK) * 100 / total_ampdu,
4630+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[8]) * 100 / total_ampdu,
4631+ ((ampdu_cnt[9]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK) * 100 / total_ampdu,
4632+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[9]) * 100 / total_ampdu,
4633+ ((ampdu_cnt[10]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK) * 100 / total_ampdu,
4634+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[10]) * 100 / total_ampdu);
4635+ }
4636+
4637+ return 0;
4638+}
4639+
4640+static int mt7915_agginfo_read_band0(struct seq_file *s, void *data)
4641+{
4642+ mt7915_agginfo_read_per_band(s, 0);
4643+ return 0;
4644+}
4645+
4646+static int mt7915_agginfo_read_band1(struct seq_file *s, void *data)
4647+{
4648+ mt7915_agginfo_read_per_band(s, 1);
4649+ return 0;
4650+}
4651+
4652+/*usage: <en> <num> <len>
4653+ en: BIT(16) 0: sw amsdu 1: hw amsdu
4654+ num: GENMASK(15, 8) range 1-8
4655+ len: GENMASK(7, 0) unit: 256 bytes */
4656+static int mt7915_sta_tx_amsdu_set(void *data, u64 tx_amsdu)
4657+{
4658+/* UWTBL DW 6 */
4659+#define WTBL_AMSDU_LEN_MASK GENMASK(5, 0)
4660+#define WTBL_AMSDU_NUM_MASK GENMASK(8, 6)
4661+#define WTBL_AMSDU_EN_MASK BIT(9)
4662+#define UWTBL_HW_AMSDU_DW 6
4663+
4664+ struct mt7915_dev *dev = data;
4665+ u32 len = FIELD_GET(GENMASK(7, 0), tx_amsdu);
4666+ u32 num = FIELD_GET(GENMASK(15, 8), tx_amsdu);
4667+ u32 uwtbl;
4668+
developer9e5bcc52022-09-27 10:30:15 +08004669+ mt7915_mcu_set_amsdu_algo(dev, dev->wlan_idx, 0);
4670+
developer3fa816c2022-04-19 10:21:20 +08004671+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC,
4672+ UWTBL_HW_AMSDU_DW, 1, &uwtbl);
4673+
4674+ if (len) {
4675+ uwtbl &= ~WTBL_AMSDU_LEN_MASK;
4676+ uwtbl |= FIELD_PREP(WTBL_AMSDU_LEN_MASK, len);
4677+ }
4678+
4679+ uwtbl &= ~WTBL_AMSDU_NUM_MASK;
4680+ uwtbl |= FIELD_PREP(WTBL_AMSDU_NUM_MASK, num);
4681+
4682+ if (tx_amsdu & BIT(16))
4683+ uwtbl |= WTBL_AMSDU_EN_MASK;
4684+
4685+ mt7915_wtbl_write_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC,
4686+ UWTBL_HW_AMSDU_DW, uwtbl);
4687+
4688+ return 0;
4689+}
4690+
4691+DEFINE_DEBUGFS_ATTRIBUTE(fops_tx_amsdu, NULL,
4692+ mt7915_sta_tx_amsdu_set, "%llx\n");
4693+
4694+static int mt7915_red_enable_set(void *data, u64 en)
4695+{
4696+ struct mt7915_dev *dev = data;
4697+
4698+ return mt7915_mcu_set_red(dev, en);
4699+}
4700+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_en, NULL,
4701+ mt7915_red_enable_set, "%llx\n");
4702+
4703+static int mt7915_red_show_sta_set(void *data, u64 wlan_idx)
4704+{
4705+ struct mt7915_dev *dev = data;
4706+
4707+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
4708+ MCU_WA_PARAM_RED_SHOW_STA,
4709+ wlan_idx, 0, true);
4710+
4711+ return 0;
4712+}
4713+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_show_sta, NULL,
4714+ mt7915_red_show_sta_set, "%llx\n");
4715+
4716+static int mt7915_red_target_dly_set(void *data, u64 delay)
4717+{
4718+ struct mt7915_dev *dev = data;
4719+
4720+ if (delay > 0 && delay <= 32767)
4721+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
4722+ MCU_WA_PARAM_RED_TARGET_DELAY,
4723+ delay, 0, true);
4724+
4725+ return 0;
4726+}
4727+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_target_dly, NULL,
4728+ mt7915_red_target_dly_set, "%llx\n");
4729+
4730+static int
4731+mt7915_txpower_level_set(void *data, u64 val)
4732+{
4733+ struct mt7915_dev *dev = data;
4734+ struct mt7915_phy *ext_phy = mt7915_ext_phy(dev);
4735+ mt7915_mcu_set_txpower_level(&dev->phy, val);
4736+ if (ext_phy)
4737+ mt7915_mcu_set_txpower_level(ext_phy, val);
4738+
4739+ return 0;
4740+}
4741+
4742+DEFINE_DEBUGFS_ATTRIBUTE(fops_txpower_level, NULL,
4743+ mt7915_txpower_level_set, "%lld\n");
4744+
4745+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_set */
4746+static int
4747+mt7915_wa_set(void *data, u64 val)
4748+{
4749+ struct mt7915_dev *dev = data;
4750+ u32 arg1, arg2, arg3;
4751+
4752+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
4753+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
4754+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
4755+
4756+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), arg1, arg2, arg3, false);
4757+
4758+ return 0;
4759+}
4760+
4761+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_set, NULL, mt7915_wa_set,
4762+ "0x%llx\n");
4763+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_query */
4764+static int
4765+mt7915_wa_query(void *data, u64 val)
4766+{
4767+ struct mt7915_dev *dev = data;
4768+ u32 arg1, arg2, arg3;
4769+
4770+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
4771+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
4772+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
4773+
4774+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY), arg1, arg2, arg3, false);
4775+
4776+ return 0;
4777+}
4778+
4779+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_query, NULL, mt7915_wa_query,
4780+ "0x%llx\n");
4781+/* set wa debug level
4782+ usage:
4783+ echo 0x[arg] > fw_wa_debug
4784+ bit0 : DEBUG_WIFI_TX
4785+ bit1 : DEBUG_CMD_EVENT
4786+ bit2 : DEBUG_RED
4787+ bit3 : DEBUG_WARN
4788+ bit4 : DEBUG_WIFI_RX
4789+ bit5 : DEBUG_TIME_STAMP
4790+ bit6 : DEBUG_TX_FREE_DONE_EVENT
4791+ bit12 : DEBUG_WIFI_TXD */
4792+static int
4793+mt7915_wa_debug(void *data, u64 val)
4794+{
4795+ struct mt7915_dev *dev = data;
4796+ u32 arg;
4797+
4798+ arg = FIELD_GET(GENMASK_ULL(15, 0), val);
4799+
4800+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(DEBUG), arg, 0, 0, false);
4801+
4802+ return 0;
4803+}
4804+
4805+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_debug, NULL, mt7915_wa_debug,
4806+ "0x%llx\n");
4807+
developer8e5fecd2023-05-30 11:58:00 +08004808+static int mt7915_dump_version(struct seq_file *s, void *data)
4809+{
4810+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4811+ struct mt76_dev *mdev = NULL;
4812+ seq_printf(s, "Version: 2.2.11.0\n");
4813+
4814+ if (!test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state))
4815+ return 0;
4816+
4817+ mdev = &dev->mt76;
4818+ seq_printf(s, "Rom Patch Build Time: %.16s\n", mdev->patch_hdr->build_date);
4819+ seq_printf(s, "WM Patch Build Time: %.16s\n", mdev->wm_hdr->build_date);
4820+ seq_printf(s, "WA Patch Build Time: %.16s\n", mdev->wa_hdr->build_date);
4821+ return 0;
4822+}
4823+
developera43cc482023-04-17 15:57:28 +08004824+static inline int mt7915_snprintf_error(size_t size, int res)
4825+{
4826+ return res < 0 || (unsigned int) res >= size;
4827+}
4828+
4829+static void mt7915_show_lp_history(struct seq_file *s, bool fgIsExp)
4830+{
4831+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4832+ u32 macVal = 0, gpr_log_idx = 0, oldest_idx = 0;
4833+ u32 idx = 0, i = 0;
4834+
4835+ if (!fgIsExp) {
4836+ /* disable LP recored */
4837+ macVal = mt76_rr(dev, 0x89050200);
4838+ macVal &= (~0x1);
4839+ mt76_wr(dev, 0x89050200, macVal);
4840+ udelay(100);
4841+ }
4842+
4843+ macVal = 0;
4844+ macVal = mt76_rr(dev, 0x89050200);
4845+ gpr_log_idx = ((macVal >> 16) & 0x1f);
4846+ oldest_idx = gpr_log_idx + 2;
4847+
4848+ seq_printf(s, " lp history (from old to new):\n");
4849+ for (i = 0; i < 16; i++) {
4850+ idx = ((oldest_idx + 2*i + 1)%32);
4851+ macVal = mt76_rr(dev, (0x89050204 + idx*4));
4852+ seq_printf(s, " %d: 0x%x\n", i, macVal);
4853+ }
4854+
4855+ if (!fgIsExp) {
4856+ /* enable LP recored */
4857+ macVal = mt76_rr(dev, 0x89050200);
4858+ macVal |= 0x1;
4859+ mt76_wr(dev, 0x89050200, macVal);
4860+ }
4861+}
4862+
4863+static void mt7915_show_irq_history(struct seq_file *s)
4864+{
4865+#define SYSIRQ_INTERRUPT_HISTORY_NUM 10
4866+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4867+ u32 macVal = 0;
4868+ u32 i = 0;
4869+ u32 start = 0;
4870+ u32 idx = 0;
4871+ u8 ucIrqDisIdx = 0;
4872+ u8 ucIrqResIdx = 0;
4873+ u32 irq_dis_time[10];
4874+ u32 irq_dis_lp[10];
4875+ u32 irq_res_time[10];
4876+ u32 irq_res_lp[10];
4877+
4878+ macVal = 0;
4879+ macVal = mt76_rr(dev, 0x022051C0);
4880+ ucIrqResIdx = (macVal & 0xff);
4881+ ucIrqDisIdx = ((macVal >> 8) & 0xff);
4882+
4883+ seq_printf(s, "\n\n\n Irq Idx (Dis=%d Res=%d):\n",
4884+ ucIrqDisIdx, ucIrqResIdx);
4885+
4886+ start = mt76_rr(dev, 0x022051C8);
4887+ for (i = 0; i < SYSIRQ_INTERRUPT_HISTORY_NUM; i++) {
4888+ macVal = mt76_rr(dev, (start + (i * 8)));
4889+ irq_dis_time[i] = macVal;
4890+ macVal = mt76_rr(dev, (start + (i * 8) + 4));
4891+ irq_dis_lp[i] = macVal;
4892+ }
4893+
4894+ start = mt76_rr(dev, 0x022051C4);
4895+
4896+ for (i = 0; i < SYSIRQ_INTERRUPT_HISTORY_NUM; i++) {
4897+ macVal = mt76_rr(dev, (start + (i * 8)));
4898+ irq_res_time[i] = macVal;
4899+ macVal = mt76_rr(dev, (start + (i * 8) + 4));
4900+ irq_res_lp[i] = macVal;
4901+ }
4902+
4903+ seq_printf(s, "\n Dis Irq history (from old to new):\n");
4904+ for (i = 0; i < SYSIRQ_INTERRUPT_HISTORY_NUM; i++) {
4905+ idx = (i + ucIrqDisIdx) % SYSIRQ_INTERRUPT_HISTORY_NUM;
4906+ seq_printf(s, " [%d].LP = 0x%x time=%u\n",
4907+ idx, irq_dis_lp[idx], irq_dis_time[idx]);
4908+ }
4909+
4910+ seq_printf(s, "\n Restore Irq history (from old to new):\n");
4911+ for (i = 0; i < SYSIRQ_INTERRUPT_HISTORY_NUM; i++) {
4912+ idx = (i + ucIrqResIdx) % SYSIRQ_INTERRUPT_HISTORY_NUM;
4913+ seq_printf(s, " [%d].LP = 0x%x time=%u\n",
4914+ idx, irq_res_lp[idx], irq_res_time[idx]);
4915+ }
4916+}
4917+
4918+static void MemSectionRead(struct mt7915_dev *dev, char *buf, u32 length, u32 addr)
4919+{
4920+ int idx = 0;
4921+ u32 *ptr =(u32 *)buf;
4922+
4923+ while (idx < length) {
4924+ *ptr = mt76_rr(dev, (addr + idx));
4925+ idx += 4;
4926+ ptr++;
4927+ }
4928+}
4929+
4930+static void mt7915_show_msg_trace(struct seq_file *s)
4931+{
4932+#define MSG_HISTORY_NUM 64
4933+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4934+ struct cos_msg_trace_t *msg_trace = NULL;
4935+ u32 ptr_addr = 0;
4936+ u32 length = 0;
developer004e50c2023-06-29 20:33:22 +08004937+ u32 idx = 0;
developera43cc482023-04-17 15:57:28 +08004938+ u32 cnt = 0;
4939+ u32 msg_history_num = 0;
4940+
4941+ msg_trace = kmalloc(MSG_HISTORY_NUM * sizeof(struct cos_msg_trace_t), GFP_KERNEL);
4942+ if (!msg_trace) {
4943+ seq_printf(s, "can not allocate cmd msg_trace\n");
4944+ return;
4945+ }
4946+
4947+ memset(msg_trace, 0, MSG_HISTORY_NUM * sizeof(struct cos_msg_trace_t));
4948+
4949+ ptr_addr = mt76_rr(dev, 0x02205188);
4950+ msg_history_num = mt76_rr(dev, 0x0220518C);
4951+
4952+ idx = (msg_history_num >> 8) & 0xff;
4953+ msg_history_num = msg_history_num & 0xff;
4954+
4955+ if (idx >= msg_history_num) {
4956+ kfree(msg_trace);
4957+ return;
4958+ }
4959+
4960+ length = msg_history_num * sizeof(struct cos_msg_trace_t);
4961+ MemSectionRead(dev, (char *)&(msg_trace[0]), length, ptr_addr);
4962+ seq_printf(s,"\n");
4963+ seq_printf(s, " msg trace:\n");
4964+ seq_printf(s, " format: t_id=task_id/task_prempt_cnt/msg_read_idx\n");
4965+
4966+ while (1) {
4967+ seq_printf(s, " (m_%d)t_id=%x/%d/%d, m_id=%d, ts_en=%u, ts_de = %u, ts_fin=%u, wait=%d, exe=%d\n",
4968+ idx,
4969+ msg_trace[idx].dest_id,
4970+ msg_trace[idx].pcount,
4971+ msg_trace[idx].qread,
4972+ msg_trace[idx].msg_id,
4973+ msg_trace[idx].ts_enq,
4974+ msg_trace[idx].ts_deq,
4975+ msg_trace[idx].ts_finshq,
4976+ (msg_trace[idx].ts_deq - msg_trace[idx].ts_enq),
4977+ (msg_trace[idx].ts_finshq - msg_trace[idx].ts_deq));
4978+
4979+ if (++idx >= msg_history_num)
4980+ idx = 0;
4981+
4982+ if (++cnt >= msg_history_num)
4983+ break;
4984+ }
4985+ if (msg_trace)
4986+ kfree(msg_trace);
4987+}
4988+
4989+static int mt7915_show_assert_line(struct seq_file *s)
4990+{
4991+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4992+ char *msg;
4993+ u32 addr;
4994+ u32 macVal = 0;
4995+ char *ptr;
4996+ char idx;
4997+
4998+ msg = kmalloc(256, GFP_KERNEL);
4999+ if (!msg)
5000+ return 0;
5001+
5002+ memset(msg, 0, 256);
5003+ addr = 0x00400000;
5004+ ptr = msg;
5005+ for (idx = 0 ; idx < 32; idx++) {
5006+ macVal = 0;
5007+ macVal = mt76_rr(dev, addr);
5008+ memcpy(ptr, &macVal, 4);
5009+ addr += 4;
5010+ ptr += 4;
5011+ }
5012+
5013+ *ptr = 0;
5014+ seq_printf(s,"\n\n");
5015+ seq_printf(s," Assert line\n");
5016+ seq_printf(s," %s\n", msg);
5017+ if (msg)
5018+ kfree(msg);
5019+
5020+ return 0;
5021+}
5022+
5023+
5024+static void mt7915_show_sech_trace(struct seq_file *s)
5025+{
5026+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
5027+ struct cos_task_info_struct task_info_g[2];
5028+ u32 length = 0, i = 0;
5029+ u32 idx = 0;
5030+ u32 km_total_time = 0;
5031+ u32 addr = 0;
5032+ struct cos_task_type tcb;
5033+ struct cos_task_type *tcb_ptr;
5034+ char name[2][15] = {
5035+ "WIFI ", "WIFI2 "
5036+ };
5037+
5038+ length = 2 * sizeof(struct cos_task_info_struct);
5039+ MemSectionRead(dev, (char *)&(task_info_g[0]), length, 0x02202A18);
5040+
5041+ /*while(i < length) {
5042+ task_info_g[i] = mt76_rr(dev, 0x02202A18 + i * 0x4);
5043+ i++;
5044+ }*/
5045+ km_total_time = mt76_rr(dev, 0x022051B4);
5046+ if (km_total_time == 0) {
5047+ seq_printf(s, "km_total_time zero!\n");
5048+ return;
5049+ }
5050+
5051+ seq_printf(s,"\n\n\n TASK XTIME RATIO PREMPT CNT\n");
5052+ for (idx = 0 ; idx < 2 ; idx++) {
5053+ addr = task_info_g[idx].task_id;
5054+ i = 0;
5055+ MemSectionRead(dev, (char *)&(tcb), sizeof(struct cos_task_type), addr);
5056+
5057+ length = sizeof(struct cos_task_type);
5058+
5059+ tcb_ptr = &(tcb);
5060+
5061+ if (tcb_ptr) {
5062+ seq_printf(s, " %s %d %d %d\n",
5063+ name[idx],
5064+ tcb_ptr->tc_exe_time,
5065+ (tcb_ptr->tc_exe_time*100/km_total_time),
5066+ tcb_ptr->tc_pcount);
5067+ }
5068+ }
5069+
5070+}
5071+
5072+static void mt7915_show_prog_trace(struct seq_file *s)
5073+{
5074+#define PROGRAM_TRACE_HISTORY_NUM 32
5075+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
5076+ struct cos_program_trace_t *cos_program_trace_ptr = NULL;
5077+ u32 trace_ptr = 0;
developer004e50c2023-06-29 20:33:22 +08005078+ u32 idx = 0;
developera43cc482023-04-17 15:57:28 +08005079+ u32 old_idx = 0;
5080+ u32 old_idx_addr = 0;
5081+ u32 prev_idx = 0;
5082+ u32 prev_time = 0;
5083+ u32 curr_time = 0;
5084+ u32 diff = 0;
developer004e50c2023-06-29 20:33:22 +08005085+ //u32 length = 0, i = 0;
developera43cc482023-04-17 15:57:28 +08005086+
5087+ cos_program_trace_ptr = kmalloc(PROGRAM_TRACE_HISTORY_NUM * sizeof(struct cos_program_trace_t), GFP_KERNEL);
5088+ if (!cos_program_trace_ptr) {
5089+ seq_printf(s, "can not allocate cos_program_trace_ptr memory\n");
5090+ return;
5091+ }
5092+ memset(cos_program_trace_ptr, 0, PROGRAM_TRACE_HISTORY_NUM * sizeof(struct cos_program_trace_t));
5093+
5094+ trace_ptr = mt76_rr(dev, 0x0220514C);
5095+ old_idx_addr = mt76_rr(dev, 0x02205148);
5096+
5097+ old_idx = (old_idx_addr >> 8) & 0xff;
5098+
5099+ MemSectionRead(dev, (char *)&cos_program_trace_ptr[0], PROGRAM_TRACE_HISTORY_NUM * sizeof(struct cos_program_trace_t), trace_ptr);
5100+
5101+ /*length = PROGRAM_TRACE_HISTORY_NUM * sizeof(struct cos_program_trace_t);
5102+ while(i < length) {
5103+ cos_program_trace_ptr[i] = mt76_rr(dev, trace_ptr + i * 0x4);
5104+ i++;
5105+ }*/
5106+ seq_printf(s, "\n");
5107+ seq_printf(s, " program trace:\n");
5108+ for (idx = 0 ; idx < PROGRAM_TRACE_HISTORY_NUM ; idx++) {
5109+ prev_idx = ((old_idx + 32 - 1) % 32);
5110+
5111+ seq_printf(s, " (p_%d)t_id=%x/%d, m_id=%d, LP=0x%x, name=%s, ts2=%d, ",
5112+ old_idx,
5113+ cos_program_trace_ptr[old_idx].dest_id,
5114+ cos_program_trace_ptr[old_idx].msg_sn,
5115+ cos_program_trace_ptr[old_idx].msg_id,
5116+ cos_program_trace_ptr[old_idx].LP,
5117+ cos_program_trace_ptr[old_idx].name,
5118+ cos_program_trace_ptr[old_idx].ts_gpt2);
5119+
5120+ /* diff for gpt2 */
5121+ prev_time = cos_program_trace_ptr[prev_idx].ts_gpt2;
5122+ curr_time = cos_program_trace_ptr[old_idx].ts_gpt2;
5123+
5124+ if (prev_time) {
5125+ if ((cos_program_trace_ptr[prev_idx].dest_id == cos_program_trace_ptr[old_idx].dest_id) &&
5126+ (cos_program_trace_ptr[prev_idx].msg_sn == cos_program_trace_ptr[old_idx].msg_sn)) {
5127+ if (curr_time > prev_time)
5128+ diff = curr_time - prev_time;
5129+ else
5130+ diff = 0xFFFFFFFF - prev_time + curr_time + 1;
5131+ } else
5132+ diff = 0xFFFFFFFF;
5133+ } else
5134+ diff = 0xFFFFFFFF;
5135+
5136+ if (diff == 0xFFFFFFFF)
5137+ seq_printf(s, "diff2=NA, \n");
5138+ else
5139+ seq_printf(s, "diff2=%8d\n", diff);
5140+
5141+ old_idx++;
5142+ if (old_idx >= 32)
5143+ old_idx = 0;
5144+ }
5145+ if (cos_program_trace_ptr)
5146+ kfree(cos_program_trace_ptr);
5147+}
5148+
5149+static int mt7915_fw_wm_info_read(struct seq_file *s, void *data)
5150+{
5151+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
5152+ u32 macVal = 0, g_exp_type = 0, COS_Interrupt_Count = 0;
developer004e50c2023-06-29 20:33:22 +08005153+ u8 exp_assert_proc_entry_cnt = 0, exp_assert_state = 0, g_irq_history_num = 0;
developera43cc482023-04-17 15:57:28 +08005154+ u16 processing_irqx = 0;
5155+ u32 processing_lisr = 0, Current_Task_Id = 0, Current_Task_Indx = 0;
5156+ u8 km_irq_info_idx = 0, km_eint_info_idx = 0, km_sched_info_idx = 0, g_sched_history_num = 0;
5157+ u32 km_sched_trace_ptr = 0,km_irq_trace_ptr = 0, km_total_time = 0, TaskStart[3] = {0};
5158+ bool fgIsExp = false, fgIsAssert = false;
5159+ u32 TaskEnd[3] = {0}, exp_assert_state_addr = 0, g1_exp_counter_addr = 0;
5160+ u32 g_exp_type_addr = 0, cos_interrupt_count_addr = 0;
5161+ u32 processing_irqx_addr = 0, processing_lisr_addr = 0;
5162+ u32 Current_Task_Id_addr = 0, Current_Task_Indx_addr = 0, last_dequeued_msg_id_addr = 0;
5163+ u32 km_irq_info_idx_addr = 0, km_eint_info_idx_addr = 0, km_sched_info_idx_addr = 0;
5164+ u32 g_sched_history_num_addr = 0, km_sched_trace_ptr_addr = 0;
5165+ u32 km_irq_trace_ptr_addr = 0, km_total_time_addr = 0, last_dequeued_msg_id = 0;
5166+ u32 i = 0 ,t1 = 0, t2 = 0, t3 = 0;
developer004e50c2023-06-29 20:33:22 +08005167+ u8 idx = 0, str[32], exp_type[64];
developera43cc482023-04-17 15:57:28 +08005168+ int ret;
5169+
5170+ g_exp_type_addr = 0x022050DC;
5171+ exp_assert_state_addr = 0x02204B54;
5172+ g1_exp_counter_addr = 0x02204FFC;
5173+ cos_interrupt_count_addr = 0x022001AC;
5174+ processing_irqx_addr = 0x02204EC4;
5175+ processing_lisr_addr = 0x02205010;
5176+ Current_Task_Id_addr = 0x02204FAC;
5177+ Current_Task_Indx_addr = 0x02204F4C;
5178+ last_dequeued_msg_id_addr = 0x02204F28;
5179+ km_irq_info_idx_addr = 0x0220519C;
5180+ km_eint_info_idx_addr = 0x02205194;
5181+ km_sched_info_idx_addr = 0x022051A4;
5182+ g_sched_history_num_addr = 0x022051A4;
5183+ km_sched_trace_ptr_addr = 0x022051A0;
5184+ km_irq_trace_ptr_addr = 0x02205198;
5185+ km_total_time_addr = 0x022051B4;
5186+
5187+ macVal = 0;
5188+ macVal = mt76_rr(dev, exp_assert_state_addr);
5189+ exp_assert_state = (macVal & 0xff);
5190+
5191+ macVal = 0;
5192+ macVal = mt76_rr(dev, g1_exp_counter_addr);
5193+ exp_assert_proc_entry_cnt = (macVal & 0xff);
5194+
5195+ macVal = 0;
5196+ macVal = mt76_rr(dev, g_exp_type_addr);
5197+ g_exp_type = macVal;
5198+
5199+ macVal = 0;
5200+ macVal = mt76_rr(dev, cos_interrupt_count_addr);
5201+ COS_Interrupt_Count = macVal;
5202+
5203+ macVal = 0;
5204+ macVal = mt76_rr(dev, processing_irqx_addr);
5205+ processing_irqx = (macVal & 0xffff);
5206+
5207+ macVal = 0;
5208+ macVal = mt76_rr(dev, processing_lisr_addr);
5209+ processing_lisr = macVal;
5210+
5211+ macVal = 0;
5212+ macVal = mt76_rr(dev, Current_Task_Id_addr);
5213+ Current_Task_Id = macVal;
5214+
5215+ macVal = 0;
5216+ macVal = mt76_rr(dev, Current_Task_Indx_addr);
5217+ Current_Task_Indx = macVal;
5218+
5219+ macVal = 0;
5220+ macVal = mt76_rr(dev, last_dequeued_msg_id_addr);
5221+ last_dequeued_msg_id = macVal;
5222+
5223+ macVal = 0;
5224+ macVal = mt76_rr(dev, km_eint_info_idx_addr);
5225+ km_eint_info_idx = ((macVal >> 8) & 0xff);
5226+
5227+ macVal = 0;
5228+ macVal = mt76_rr(dev, g_sched_history_num_addr);
5229+ g_sched_history_num = (macVal & 0xff);
5230+ km_sched_info_idx = ((macVal >> 8) & 0xff);
5231+
5232+ macVal = 0;
5233+ macVal = mt76_rr(dev, km_sched_trace_ptr_addr);
5234+ km_sched_trace_ptr = macVal;
5235+
5236+ macVal = 0;
5237+ macVal = mt76_rr(dev, km_irq_info_idx_addr);
5238+ g_irq_history_num = (macVal & 0xff);
5239+ km_irq_info_idx = ((macVal >> 16) & 0xff);
5240+
5241+ macVal = 0;
5242+ macVal = mt76_rr(dev, km_irq_trace_ptr_addr);
5243+ km_irq_trace_ptr = macVal;
5244+
5245+ macVal = 0;
5246+ macVal = mt76_rr(dev, km_total_time_addr);
5247+ km_total_time = macVal;
5248+
5249+ TaskStart[0] = mt76_rr(dev, 0x02202814);
5250+ TaskEnd[0] = mt76_rr(dev, 0x02202810);
5251+ TaskStart[1] = mt76_rr(dev, 0x02202984);
5252+ TaskEnd[1] = mt76_rr(dev, 0x02202980);
5253+
5254+ seq_printf(s, "================FW DBG INFO===================\n");
5255+ seq_printf(s, " exp_assert_proc_entry_cnt = 0x%x\n",
5256+ exp_assert_proc_entry_cnt);
5257+ seq_printf(s, " exp_assert_state = 0x%x\n",
5258+ exp_assert_state);
5259+
5260+ if (exp_assert_proc_entry_cnt == 0) {
5261+ ret = snprintf(exp_type, sizeof(exp_type), "%s", "exp_type : Normal");
5262+ if (mt7915_snprintf_error(sizeof(exp_type), ret)) {
5263+ seq_printf(s, " exp_type Snprintf failed!\n");
5264+ return 0;
5265+ }
5266+ } else if (exp_assert_proc_entry_cnt == 1 &&
5267+ exp_assert_state > 1 && g_exp_type == 5) {
5268+ ret = snprintf(exp_type, sizeof(exp_type), "%s", "exp_type : Assert");
5269+ if (mt7915_snprintf_error(sizeof(exp_type), ret)) {
5270+ seq_printf(s, " exp_type Snprintf failed!\n");
5271+ return 0;
5272+ }
5273+ fgIsExp = true;
5274+ fgIsAssert = true;
5275+ } else if (exp_assert_proc_entry_cnt == 1 && exp_assert_state > 1) {
5276+ ret = snprintf(exp_type, sizeof(exp_type), "%s", "exp_type : Exception");
5277+ if (mt7915_snprintf_error(sizeof(exp_type), ret)) {
5278+ seq_printf(s, " exp_type Snprintf failed!\n");
5279+ return 0;
5280+ }
5281+ fgIsExp = true;
5282+ } else if (exp_assert_proc_entry_cnt > 1) {
5283+ ret = snprintf(exp_type, sizeof(exp_type), "%s", "exp_type : Exception re-entry");
5284+ if (mt7915_snprintf_error(sizeof(exp_type), ret)) {
5285+ seq_printf(s, " exp_type Snprintf failed!\n");
5286+ return 0;
5287+ }
5288+ fgIsExp = true;
5289+ } else {
5290+ ret = snprintf(exp_type, sizeof(exp_type), "%s", "exp_type : Unknown'?");
5291+ if (mt7915_snprintf_error(sizeof(exp_type), ret)) {
5292+ seq_printf(s, " exp_type Snprintf failed!\n");
5293+ return 0;
5294+ }
5295+ }
5296+
5297+ seq_printf(s, " COS_Interrupt_Count = 0x%x\n", COS_Interrupt_Count);
5298+ seq_printf(s, " processing_irqx = 0x%x\n", processing_irqx);
5299+ seq_printf(s, " processing_lisr = 0x%x\n", processing_lisr);
5300+ seq_printf(s, " Current_Task_Id = 0x%x\n", Current_Task_Id);
5301+ seq_printf(s, " Current_Task_Indx = 0x%x\n", Current_Task_Indx);
5302+ seq_printf(s, " last_dequeued_msg_id = %d\n", last_dequeued_msg_id);
5303+
5304+ seq_printf(s, " km_irq_info_idx = 0x%x\n", km_irq_info_idx);
5305+ seq_printf(s, " km_eint_info_idx = 0x%x\n", km_eint_info_idx);
5306+ seq_printf(s, " km_sched_info_idx = 0x%x\n", km_sched_info_idx);
5307+ seq_printf(s, " g_sched_history_num = %d\n", g_sched_history_num);
5308+ seq_printf(s, " km_sched_trace_ptr = 0x%x\n", km_sched_trace_ptr);
5309+
5310+ if (fgIsExp) {
5311+ seq_printf(s, "\n <1>print sched trace\n");
5312+ if (g_sched_history_num > 60)
5313+ g_sched_history_num = 60;
5314+
5315+ idx = km_sched_info_idx;
5316+ for (i = 0 ; i < g_sched_history_num ; i++) {
5317+ t1 = mt76_rr(dev, (km_sched_trace_ptr+(idx*12)));
5318+ t2 = mt76_rr(dev, (km_sched_trace_ptr+(idx*12)+4));
5319+ t3 = mt76_rr(dev, (km_sched_trace_ptr+(idx*12)+8));
5320+ seq_printf(s, " (sched_info_%d)sched_t=0x%x, sched_start=%d, PC=0x%x\n",
5321+ idx, t1, t2, t3);
5322+ idx++;
5323+ if (idx >= g_sched_history_num)
5324+ idx = 0;
5325+ }
5326+
5327+ seq_printf(s, "\n <2>print irq trace\n");
5328+ if (g_irq_history_num > 60)
5329+ g_irq_history_num = 60;
5330+
5331+ idx = km_irq_info_idx;
5332+ for (i = 0 ; i < g_irq_history_num ; i++) {
5333+ t1 = mt76_rr(dev, (km_irq_trace_ptr+(idx*16)));
5334+ t2 = mt76_rr(dev, (km_irq_trace_ptr+(idx*16) + 4));
5335+ seq_printf(s, " (irq_info_%d)irq_t=%x, sched_start=%d\n",
5336+ idx, t1, t2);
5337+ idx++;
5338+ if (idx >= g_irq_history_num)
5339+ idx = 0;
5340+ }
5341+ }
5342+
5343+ seq_printf(s, "\n <3>task q_id.read q_id.write\n");
5344+ seq_printf(s, " (WIFI )1 0x%x 0x%x\n", TaskStart[0], TaskEnd[0]);
5345+ seq_printf(s, " (WIFI2 )2 0x%x 0x%x\n", TaskStart[1], TaskEnd[1]);
5346+ seq_printf(s, "\n <4>TASK STACK INFO (size in byte)\n");
5347+ seq_printf(s, " TASK START END SIZE PEAK INTEGRITY\n");
5348+
5349+ for (i = 0 ; i < 2 ; i++) {
5350+ t1 = mt76_rr(dev, 0x022027B8+(i*368));
5351+ t2 = mt76_rr(dev, 0x022027BC+(i*368));
5352+ t3 = mt76_rr(dev, 0x022027C4+(i*368));
5353+
5354+ if (i == 0) {
5355+ ret = snprintf(str, sizeof(str), "%s", "WIFI");
5356+ if (mt7915_snprintf_error(sizeof(str), ret)) {
5357+ seq_printf(s, " str Snprintf failed!\n");
5358+ return 0;
5359+ }
5360+ } else if (i == 1) {
5361+ ret = snprintf(str, sizeof(str), "%s", "WIFI2");
5362+ if (mt7915_snprintf_error(sizeof(str), ret)) {
5363+ seq_printf(s, " str Snprintf failed!\n");
5364+ return 0;
5365+ }
5366+ }
5367+
5368+ seq_printf(s, " %s 0x%x 0x%x %d\n",
5369+ str, t1, t2, t3);
5370+ }
5371+
5372+ seq_printf(s, "\n <5>fw state\n");
5373+ seq_printf(s, " %s\n", exp_type);
5374+ if (COS_Interrupt_Count > 0)
5375+ seq_printf(s, " FW in Interrupt CIRQ index (0x%x) CIRQ handler(0x%x)\n"
5376+ , processing_irqx, processing_lisr);
5377+ else {
5378+ if (Current_Task_Id == 0 && Current_Task_Indx == 3)
5379+ seq_printf(s, " FW in IDLE\n");
5380+
5381+ if (Current_Task_Id != 0 && Current_Task_Indx != 3)
5382+ seq_printf(s, " FW in Task , Task id(0x%x) Task index(0x%x)\n",
5383+ Current_Task_Id, Current_Task_Indx);
5384+ }
5385+
5386+ macVal = 0;
5387+ macVal= mt76_rr(dev, g1_exp_counter_addr);
5388+ seq_printf(s, " EXCP_CNT = 0x%x\n", macVal);
5389+
5390+ seq_printf(s, " EXCP_TYPE = 0x%x\n", g_exp_type);
5391+
5392+ macVal = 0;
5393+ macVal = mt76_rr(dev, 0x022050E0);
5394+ seq_printf(s, " CPU_ITYPE = 0x%x\n", macVal);
5395+
5396+ macVal = 0;
5397+ macVal = mt76_rr(dev, 0x022050E8);
5398+ seq_printf(s, " CPU_EVA = 0x%x\n", macVal);
5399+
5400+ macVal = 0;
5401+ macVal = mt76_rr(dev, 0x022050E4);
5402+ seq_printf(s, " CPU_IPC = 0x%x\n", macVal);
5403+
5404+ macVal = 0;
5405+ macVal = mt76_rr(dev, 0x7C060204);
5406+ seq_printf(s, " PC = 0x%x\n\n\n", macVal);
5407+
5408+ mt7915_show_lp_history(s, fgIsExp);
5409+ mt7915_show_irq_history(s);
5410+
5411+ seq_printf(s, "\n\n cpu ultility\n");
5412+ seq_printf(s, " Busy:%d%% Peak:%d%%\n\n",
5413+ mt76_rr(dev, 0x7C053B20), mt76_rr(dev, 0x7C053B24));
5414+
5415+ mt7915_show_msg_trace(s);
5416+ mt7915_show_sech_trace(s);
5417+ mt7915_show_prog_trace(s);
5418+ if (fgIsAssert)
5419+ mt7915_show_assert_line(s);
5420+
5421+ seq_printf(s, "============================================\n");
5422+ return 0;
5423+}
5424+
developer3fa816c2022-04-19 10:21:20 +08005425+int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir)
5426+{
5427+ struct mt7915_dev *dev = phy->dev;
5428+ u32 device_id = (dev->mt76.rev) >> 16;
5429+ int i = 0;
5430+
5431+ for (i = 0; i < ARRAY_SIZE(dbg_reg_s); i++) {
5432+ if (device_id == dbg_reg_s[i].id) {
5433+ dev->dbg_reg = &dbg_reg_s[i];
5434+ break;
5435+ }
5436+ }
5437+
5438+ mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 0);
5439+
5440+ debugfs_create_file("fw_debug_module", 0600, dir, dev,
5441+ &fops_fw_debug_module);
5442+ debugfs_create_file("fw_debug_level", 0600, dir, dev,
5443+ &fops_fw_debug_level);
5444+
developerf32dabf2022-06-01 10:59:24 +08005445+ debugfs_create_devm_seqfile(dev->mt76.dev, "sta_info", dir,
5446+ mt7915_sta_info);
developer3fa816c2022-04-19 10:21:20 +08005447+ debugfs_create_devm_seqfile(dev->mt76.dev, "wtbl_info", dir,
5448+ mt7915_wtbl_read);
5449+ debugfs_create_devm_seqfile(dev->mt76.dev, "uwtbl_info", dir,
5450+ mt7915_uwtbl_read);
5451+
5452+ debugfs_create_devm_seqfile(dev->mt76.dev, "tr_info", dir,
5453+ mt7915_trinfo_read);
5454+
5455+ debugfs_create_devm_seqfile(dev->mt76.dev, "drr_info", dir,
5456+ mt7915_drr_info);
5457+
5458+ debugfs_create_devm_seqfile(dev->mt76.dev, "ple_info", dir,
5459+ mt7915_pleinfo_read);
5460+
5461+ debugfs_create_devm_seqfile(dev->mt76.dev, "pse_info", dir,
5462+ mt7915_pseinfo_read);
5463+
5464+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info0", dir,
5465+ mt7915_mibinfo_band0);
5466+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info1", dir,
5467+ mt7915_mibinfo_band1);
5468+
5469+ debugfs_create_u32("token_idx", 0600, dir, &dev->dbg.token_idx);
5470+ debugfs_create_devm_seqfile(dev->mt76.dev, "token", dir,
5471+ mt7915_token_read);
5472+ debugfs_create_devm_seqfile(dev->mt76.dev, "token_txd", dir,
5473+ mt7915_token_txd_read);
5474+
5475+ debugfs_create_devm_seqfile(dev->mt76.dev, "amsdu_info", dir,
5476+ mt7915_amsduinfo_read);
5477+
5478+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info0", dir,
5479+ mt7915_agginfo_read_band0);
5480+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info1", dir,
5481+ mt7915_agginfo_read_band1);
5482+
5483+ debugfs_create_file("tx_amsdu", 0600, dir, dev, &fops_tx_amsdu);
5484+
5485+ debugfs_create_file("fw_wa_query", 0600, dir, dev, &fops_wa_query);
5486+ debugfs_create_file("fw_wa_set", 0600, dir, dev, &fops_wa_set);
developer8e5fecd2023-05-30 11:58:00 +08005487+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_version", dir,
5488+ mt7915_dump_version);
developer3fa816c2022-04-19 10:21:20 +08005489+ debugfs_create_file("fw_wa_debug", 0600, dir, dev, &fops_wa_debug);
developera43cc482023-04-17 15:57:28 +08005490+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_wm_info", dir,
5491+ mt7915_fw_wm_info_read);
developer3fa816c2022-04-19 10:21:20 +08005492+
5493+ debugfs_create_file("red_en", 0600, dir, dev,
5494+ &fops_red_en);
5495+ debugfs_create_file("red_show_sta", 0600, dir, dev,
5496+ &fops_red_show_sta);
5497+ debugfs_create_file("red_target_dly", 0600, dir, dev,
5498+ &fops_red_target_dly);
5499+
5500+ debugfs_create_file("txpower_level", 0400, dir, dev,
5501+ &fops_txpower_level);
5502+
developeraace7f52022-06-24 13:40:42 +08005503+ debugfs_create_u8("sku_disable", 0600, dir, &dev->dbg.sku_disable);
5504+
developer3fa816c2022-04-19 10:21:20 +08005505+ return 0;
5506+}
5507+#endif
5508diff --git a/mt7915/mtk_mcu.c b/mt7915/mtk_mcu.c
5509new file mode 100644
developer004e50c2023-06-29 20:33:22 +08005510index 0000000..143dae2
developer3fa816c2022-04-19 10:21:20 +08005511--- /dev/null
5512+++ b/mt7915/mtk_mcu.c
5513@@ -0,0 +1,51 @@
5514+#include <linux/firmware.h>
5515+#include <linux/fs.h>
5516+#include<linux/inet.h>
5517+#include "mt7915.h"
5518+#include "mcu.h"
5519+#include "mac.h"
5520+
5521+int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level)
5522+{
5523+ struct mt7915_dev *dev = phy->dev;
5524+ struct mt7915_sku_val {
5525+ u8 format_id;
5526+ u8 val;
5527+ u8 band;
5528+ u8 _rsv;
5529+ } __packed req = {
5530+ .format_id = 1,
developer2458e702022-12-13 15:52:04 +08005531+ .band = phy->mt76->band_idx,
developer3fa816c2022-04-19 10:21:20 +08005532+ .val = !!drop_level,
5533+ };
5534+ int ret;
5535+
5536+ ret = mt76_mcu_send_msg(&dev->mt76,
5537+ MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
5538+ sizeof(req), true);
5539+ if (ret)
5540+ return ret;
5541+
5542+ req.format_id = 2;
5543+ if ((drop_level > 90 && drop_level < 100) || !drop_level)
5544+ req.val = 0;
5545+ else if (drop_level > 60 && drop_level <= 90)
5546+ /* reduce Pwr for 1 dB. */
5547+ req.val = 2;
5548+ else if (drop_level > 30 && drop_level <= 60)
5549+ /* reduce Pwr for 3 dB. */
5550+ req.val = 6;
5551+ else if (drop_level > 15 && drop_level <= 30)
5552+ /* reduce Pwr for 6 dB. */
5553+ req.val = 12;
5554+ else if (drop_level > 9 && drop_level <= 15)
5555+ /* reduce Pwr for 9 dB. */
5556+ req.val = 18;
5557+ else if (drop_level > 0 && drop_level <= 9)
5558+ /* reduce Pwr for 12 dB. */
5559+ req.val = 24;
5560+
5561+ return mt76_mcu_send_msg(&dev->mt76,
5562+ MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
5563+ sizeof(req), true);
5564+}
5565diff --git a/tools/fwlog.c b/tools/fwlog.c
developer004e50c2023-06-29 20:33:22 +08005566index e5d4a10..3d51d9e 100644
developer3fa816c2022-04-19 10:21:20 +08005567--- a/tools/fwlog.c
5568+++ b/tools/fwlog.c
5569@@ -26,7 +26,7 @@ static const char *debugfs_path(const char *phyname, const char *file)
5570 return path;
5571 }
5572
5573-static int mt76_set_fwlog_en(const char *phyname, bool en)
5574+static int mt76_set_fwlog_en(const char *phyname, bool en, char *val)
5575 {
5576 FILE *f = fopen(debugfs_path(phyname, "fw_debug_bin"), "w");
5577
5578@@ -35,7 +35,13 @@ static int mt76_set_fwlog_en(const char *phyname, bool en)
5579 return 1;
5580 }
5581
5582- fprintf(f, "7");
5583+ if (en && val)
5584+ fprintf(f, "%s", val);
5585+ else if (en)
5586+ fprintf(f, "7");
5587+ else
5588+ fprintf(f, "0");
5589+
5590 fclose(f);
5591
5592 return 0;
5593@@ -76,6 +82,7 @@ static void handle_signal(int sig)
5594
5595 int mt76_fwlog(const char *phyname, int argc, char **argv)
5596 {
5597+#define BUF_SIZE 1504
5598 struct sockaddr_in local = {
5599 .sin_family = AF_INET,
5600 .sin_addr.s_addr = INADDR_ANY,
developerf32dabf2022-06-01 10:59:24 +08005601@@ -84,9 +91,10 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
developer3fa816c2022-04-19 10:21:20 +08005602 .sin_family = AF_INET,
5603 .sin_port = htons(55688),
5604 };
5605- char buf[1504];
5606+ char *buf = calloc(BUF_SIZE, sizeof(char));
developerf32dabf2022-06-01 10:59:24 +08005607+ FILE *logfile = NULL;
developer3fa816c2022-04-19 10:21:20 +08005608 int ret = 0;
5609- int yes = 1;
5610+ /* int yes = 1; */
5611 int s, fd;
5612
5613 if (argc < 1) {
developerf32dabf2022-06-01 10:59:24 +08005614@@ -99,19 +107,28 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
5615 return 1;
5616 }
5617
5618+ if (argc == 3) {
5619+ fprintf(stdout, "start logging to file %s\n", argv[2]);
5620+ logfile = fopen(argv[2], "wb");
5621+ if (!logfile) {
5622+ perror("fopen");
5623+ return 1;
5624+ }
5625+ }
5626+
5627 s = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP);
5628 if (s < 0) {
5629 perror("socket");
developer3fa816c2022-04-19 10:21:20 +08005630 return 1;
5631 }
5632
5633- setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes));
5634+ /* setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes)); */
5635 if (bind(s, (struct sockaddr *)&local, sizeof(local)) < 0) {
5636 perror("bind");
5637 return 1;
5638 }
5639
5640- if (mt76_set_fwlog_en(phyname, true))
5641+ if (mt76_set_fwlog_en(phyname, true, argv[1]))
5642 return 1;
5643
5644 fd = open(debugfs_path(phyname, "fwlog_data"), O_RDONLY);
developerf32dabf2022-06-01 10:59:24 +08005645@@ -145,8 +162,8 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
developer3fa816c2022-04-19 10:21:20 +08005646 if (!r)
5647 continue;
5648
5649- if (len > sizeof(buf)) {
5650- fprintf(stderr, "Length error: %d > %d\n", len, (int)sizeof(buf));
5651+ if (len > BUF_SIZE) {
5652+ fprintf(stderr, "Length error: %d > %d\n", len, BUF_SIZE);
5653 ret = 1;
5654 break;
5655 }
developerf32dabf2022-06-01 10:59:24 +08005656@@ -164,14 +181,19 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
5657 break;
5658 }
5659
5660- /* send buf */
5661- sendto(s, buf, len, 0, (struct sockaddr *)&remote, sizeof(remote));
5662+ if (logfile)
5663+ fwrite(buf, 1, len, logfile);
5664+ else
5665+ /* send buf */
5666+ sendto(s, buf, len, 0, (struct sockaddr *)&remote, sizeof(remote));
5667 }
5668
developer3fa816c2022-04-19 10:21:20 +08005669 close(fd);
5670
5671 out:
5672- mt76_set_fwlog_en(phyname, false);
5673+ mt76_set_fwlog_en(phyname, false, NULL);
5674+ free(buf);
developerf32dabf2022-06-01 10:59:24 +08005675+ fclose(logfile);
developer3fa816c2022-04-19 10:21:20 +08005676
5677 return ret;
5678 }
5679--
developera43cc482023-04-17 15:57:28 +080056802.18.0
developer3fa816c2022-04-19 10:21:20 +08005681