blob: 2ebf9841e9020f76fb532df2631fa2461352864b [file] [log] [blame]
developerf3f5d9b2023-02-07 15:24:34 +08001From c1c5febad5b40bba3026976061a2d6c234f8ad25 Mon Sep 17 00:00:00 2001
developeraace7f52022-06-24 13:40:42 +08002From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Wed, 22 Jun 2022 10:39:47 +0800
developer2aa1e642022-12-19 11:33:22 +08004Subject: [PATCH 1001/1009] mt76: mt7915: add mtk internal debug tools for mt76
developer3fa816c2022-04-19 10:21:20 +08005
6---
developerf3f5d9b2023-02-07 15:24:34 +08007 mt76_connac_mcu.h | 6 +
developer27b55252022-09-05 19:09:45 +08008 mt7915/Makefile | 2 +-
9 mt7915/debugfs.c | 73 +-
10 mt7915/mac.c | 14 +
11 mt7915/main.c | 4 +
developerf3f5d9b2023-02-07 15:24:34 +080012 mt7915/mcu.c | 48 +-
developer27b55252022-09-05 19:09:45 +080013 mt7915/mcu.h | 4 +
developer9e5bcc52022-09-27 10:30:15 +080014 mt7915/mt7915.h | 44 +
developer79a21a22023-01-09 13:57:39 +080015 mt7915/mt7915_debug.h | 1363 +++++++++++++++++++
16 mt7915/mtk_debugfs.c | 3003 +++++++++++++++++++++++++++++++++++++++++
developer27b55252022-09-05 19:09:45 +080017 mt7915/mtk_mcu.c | 51 +
18 tools/fwlog.c | 44 +-
developerf3f5d9b2023-02-07 15:24:34 +080019 12 files changed, 4642 insertions(+), 14 deletions(-)
developer27b55252022-09-05 19:09:45 +080020 create mode 100644 mt7915/mt7915_debug.h
21 create mode 100644 mt7915/mtk_debugfs.c
22 create mode 100644 mt7915/mtk_mcu.c
developer3fa816c2022-04-19 10:21:20 +080023
24diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
developerf3f5d9b2023-02-07 15:24:34 +080025index a5e6ee4d..cbe0c52a 100644
developer3fa816c2022-04-19 10:21:20 +080026--- a/mt76_connac_mcu.h
27+++ b/mt76_connac_mcu.h
developerf3f5d9b2023-02-07 15:24:34 +080028@@ -1151,6 +1151,7 @@ enum {
developer9e5bcc52022-09-27 10:30:15 +080029 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
30 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
31 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
32+ MCU_EXT_CMD_MEC_CTRL = 0x1f,
33 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
34 MCU_EXT_CMD_THERMAL_PROT = 0x23,
35 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
developerf3f5d9b2023-02-07 15:24:34 +080036@@ -1174,6 +1175,11 @@ enum {
developer3fa816c2022-04-19 10:21:20 +080037 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
38 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
39 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
40+#ifdef MTK_DEBUG
developer3fa816c2022-04-19 10:21:20 +080041+ MCU_EXT_CMD_RED_SHOW_STA = 0x69,
42+ MCU_EXT_CMD_RED_TARGET_DELAY = 0x6A,
43+ MCU_EXT_CMD_RED_TX_RPT = 0x6B,
44+#endif
45 MCU_EXT_CMD_TXDPD_CAL = 0x60,
46 MCU_EXT_CMD_CAL_CACHE = 0x67,
developerf3f5d9b2023-02-07 15:24:34 +080047 MCU_EXT_CMD_RED_ENABLE = 0x68,
developer3fa816c2022-04-19 10:21:20 +080048diff --git a/mt7915/Makefile b/mt7915/Makefile
developerf3f5d9b2023-02-07 15:24:34 +080049index f033116c..cbcb64be 100644
developer3fa816c2022-04-19 10:21:20 +080050--- a/mt7915/Makefile
51+++ b/mt7915/Makefile
developerf3f5d9b2023-02-07 15:24:34 +080052@@ -4,7 +4,7 @@ EXTRA_CFLAGS += -DCONFIG_MT76_LEDS
developer3fa816c2022-04-19 10:21:20 +080053 obj-$(CONFIG_MT7915E) += mt7915e.o
54
55 mt7915e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
56- debugfs.o mmio.o
57+ debugfs.o mmio.o mtk_debugfs.o mtk_mcu.o
58
59 mt7915e-$(CONFIG_NL80211_TESTMODE) += testmode.o
60 mt7915e-$(CONFIG_MT7986_WMAC) += soc.o
developer3fa816c2022-04-19 10:21:20 +080061diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c
developerf3f5d9b2023-02-07 15:24:34 +080062index 5a46813a..f1f3f2f3 100644
developer3fa816c2022-04-19 10:21:20 +080063--- a/mt7915/debugfs.c
64+++ b/mt7915/debugfs.c
65@@ -8,6 +8,9 @@
66 #include "mac.h"
67
68 #define FW_BIN_LOG_MAGIC 0x44e98caf
69+#ifdef MTK_DEBUG
70+#define FW_BIN_LOG_MAGIC_V2 0x44d9c99a
71+#endif
72
73 /** global debugfs **/
74
developer2cbf2fb2022-11-16 12:20:48 +080075@@ -504,6 +507,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080076 int ret;
77
developer42b63282022-06-16 13:33:13 +080078 dev->fw.debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
developer3fa816c2022-04-19 10:21:20 +080079+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +080080+ dev->fw.debug_wm = val;
developer3fa816c2022-04-19 10:21:20 +080081+#endif
82
developer42b63282022-06-16 13:33:13 +080083 if (dev->fw.debug_bin)
developer3fa816c2022-04-19 10:21:20 +080084 val = 16;
developer2cbf2fb2022-11-16 12:20:48 +080085@@ -528,6 +534,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080086 if (ret)
developer42b63282022-06-16 13:33:13 +080087 goto out;
developer3fa816c2022-04-19 10:21:20 +080088 }
89+#ifdef MTK_DEBUG
90+ mt7915_mcu_fw_dbg_ctrl(dev, 68, !!val);
91+#endif
92
93 /* WM CPU info record control */
94 mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0));
developer2cbf2fb2022-11-16 12:20:48 +080095@@ -535,6 +544,12 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +080096 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5));
97 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5));
98
99+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +0800100+ if (dev->fw.debug_bin & BIT(3))
developer3fa816c2022-04-19 10:21:20 +0800101+ /* use bit 7 to indicate v2 magic number */
developer42b63282022-06-16 13:33:13 +0800102+ dev->fw.debug_wm |= BIT(7);
developer3fa816c2022-04-19 10:21:20 +0800103+#endif
104+
developer42b63282022-06-16 13:33:13 +0800105 out:
106 if (ret)
107 dev->fw.debug_wm = 0;
developer2cbf2fb2022-11-16 12:20:48 +0800108@@ -547,7 +562,11 @@ mt7915_fw_debug_wm_get(void *data, u64 *val)
developer3fa816c2022-04-19 10:21:20 +0800109 {
110 struct mt7915_dev *dev = data;
111
developer42b63282022-06-16 13:33:13 +0800112- *val = dev->fw.debug_wm;
developer3fa816c2022-04-19 10:21:20 +0800113+#ifdef MTK_DEBUG
developer42b63282022-06-16 13:33:13 +0800114+ *val = dev->fw.debug_wm & ~BIT(7);
developer3fa816c2022-04-19 10:21:20 +0800115+#else
developer42b63282022-06-16 13:33:13 +0800116+ val = dev->fw.debug_wm;
developer3fa816c2022-04-19 10:21:20 +0800117+#endif
118
119 return 0;
120 }
developer2cbf2fb2022-11-16 12:20:48 +0800121@@ -632,6 +651,17 @@ mt7915_fw_debug_bin_set(void *data, u64 val)
developer3fa816c2022-04-19 10:21:20 +0800122
123 relay_reset(dev->relay_fwlog);
124
125+#ifdef MTK_DEBUG
126+ dev->dbg.dump_mcu_pkt = val & BIT(4) ? true : false;
127+ dev->dbg.dump_txd = val & BIT(5) ? true : false;
128+ dev->dbg.dump_tx_pkt = val & BIT(6) ? true : false;
129+ dev->dbg.dump_rx_pkt = val & BIT(7) ? true : false;
130+ dev->dbg.dump_rx_raw = val & BIT(8) ? true : false;
131+ if (!(val & GENMASK(3, 0)))
132+ return 0;
133+#endif
134+
developer42b63282022-06-16 13:33:13 +0800135+
136 return mt7915_fw_debug_wm_set(dev, dev->fw.debug_wm);
developer3fa816c2022-04-19 10:21:20 +0800137 }
138
developer2458e702022-12-13 15:52:04 +0800139@@ -1257,6 +1287,11 @@ int mt7915_init_debugfs(struct mt7915_phy *phy)
developer3fa816c2022-04-19 10:21:20 +0800140 if (!ext_phy)
141 dev->debugfs_dir = dir;
142
143+#ifdef MTK_DEBUG
144+ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
145+ mt7915_mtk_init_debugfs(phy, dir);
146+#endif
147+
148 return 0;
149 }
150
developer2458e702022-12-13 15:52:04 +0800151@@ -1297,17 +1332,53 @@ void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int
developer3fa816c2022-04-19 10:21:20 +0800152 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),
153 };
154
155+#ifdef MTK_DEBUG
156+ struct {
157+ __le32 magic;
158+ u8 version;
159+ u8 _rsv;
160+ __le16 serial_id;
161+ __le32 timestamp;
162+ __le16 msg_type;
163+ __le16 len;
164+ } hdr2 = {
165+ .version = 0x1,
166+ .magic = cpu_to_le32(FW_BIN_LOG_MAGIC_V2),
167+ .msg_type = PKT_TYPE_RX_FW_MONITOR,
168+ };
169+#endif
170+
171 if (!dev->relay_fwlog)
172 return;
173
174+#ifdef MTK_DEBUG
175+ /* old magic num */
developer42b63282022-06-16 13:33:13 +0800176+ if (!(dev->fw.debug_wm & BIT(7))) {
developer3fa816c2022-04-19 10:21:20 +0800177+ hdr.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
178+ hdr.len = *(__le16 *)data;
179+ mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
180+ } else {
181+ hdr2.serial_id = dev->dbg.fwlog_seq++;
182+ hdr2.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
183+ hdr2.len = *(__le16 *)data;
184+ mt7915_debugfs_write_fwlog(dev, &hdr2, sizeof(hdr2), data, len);
185+ }
186+#else
187 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
188 hdr.len = *(__le16 *)data;
189 mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
190+#endif
191 }
192
193 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len)
194 {
195+#ifdef MTK_DEBUG
196+ if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC &&
197+ get_unaligned_le32(data) != FW_BIN_LOG_MAGIC_V2 &&
198+ get_unaligned_le32(data) != PKT_BIN_DEBUG_MAGIC)
199+#else
200 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC)
201+#endif
202 return false;
203
204 if (dev->relay_fwlog)
205diff --git a/mt7915/mac.c b/mt7915/mac.c
developerf3f5d9b2023-02-07 15:24:34 +0800206index 97ca55d2..1ba4096d 100644
developer3fa816c2022-04-19 10:21:20 +0800207--- a/mt7915/mac.c
208+++ b/mt7915/mac.c
developerf3f5d9b2023-02-07 15:24:34 +0800209@@ -299,6 +299,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb,
developer3fa816c2022-04-19 10:21:20 +0800210 __le16 fc = 0;
211 int idx;
212
213+#ifdef MTK_DEBUG
214+ if (dev->dbg.dump_rx_raw)
215+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX_RAW, 0);
216+#endif
217 memset(status, 0, sizeof(*status));
218
developer2458e702022-12-13 15:52:04 +0800219 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->mt76->band_idx) {
developerf3f5d9b2023-02-07 15:24:34 +0800220@@ -482,6 +486,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb,
developer3fa816c2022-04-19 10:21:20 +0800221 }
222
223 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
224+#ifdef MTK_DEBUG
225+ if (dev->dbg.dump_rx_pkt)
226+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX, hdr_gap);
227+#endif
228 if (hdr_trans && ieee80211_has_morefrags(fc)) {
developeraace7f52022-06-24 13:40:42 +0800229 struct ieee80211_vif *vif;
230 int err;
developerf3f5d9b2023-02-07 15:24:34 +0800231@@ -819,6 +827,12 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
developer3fa816c2022-04-19 10:21:20 +0800232 tx_info->buf[1].skip_unmap = true;
233 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
234
235+#ifdef MTK_DEBUG
236+ if (dev->dbg.dump_txd)
237+ mt7915_packet_log_to_host(dev, txwi, MT_TXD_SIZE, PKT_BIN_DEBUG_TXD, 0);
238+ if (dev->dbg.dump_tx_pkt)
239+ mt7915_packet_log_to_host(dev, t->skb->data, t->skb->len, PKT_BIN_DEBUG_TX, 0);
240+#endif
241 return 0;
242 }
243
developeraace7f52022-06-24 13:40:42 +0800244diff --git a/mt7915/main.c b/mt7915/main.c
developerf3f5d9b2023-02-07 15:24:34 +0800245index 3bbccbdf..94ecded5 100644
developeraace7f52022-06-24 13:40:42 +0800246--- a/mt7915/main.c
247+++ b/mt7915/main.c
developer2aa1e642022-12-19 11:33:22 +0800248@@ -73,7 +73,11 @@ int mt7915_run(struct ieee80211_hw *hw)
developeraace7f52022-06-24 13:40:42 +0800249 if (ret)
250 goto out;
251
252+#ifdef MTK_DEBUG
253+ ret = mt7915_mcu_set_sku_en(phy, !dev->dbg.sku_disable);
254+#else
255 ret = mt7915_mcu_set_sku_en(phy, true);
256+#endif
257 if (ret)
258 goto out;
259
developer3fa816c2022-04-19 10:21:20 +0800260diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developerf3f5d9b2023-02-07 15:24:34 +0800261index f151ce86..ff718f78 100644
developer3fa816c2022-04-19 10:21:20 +0800262--- a/mt7915/mcu.c
263+++ b/mt7915/mcu.c
developer3d5faf22022-11-29 18:07:22 +0800264@@ -199,6 +199,11 @@ mt7915_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
developeraace7f52022-06-24 13:40:42 +0800265 else
266 qid = MT_MCUQ_WM;
developer3fa816c2022-04-19 10:21:20 +0800267
developer3fa816c2022-04-19 10:21:20 +0800268+#ifdef MTK_DEBUG
269+ if (dev->dbg.dump_mcu_pkt)
270+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_MCU, 0);
271+#endif
developeraace7f52022-06-24 13:40:42 +0800272+
273 return mt76_tx_queue_skb_raw(dev, mdev->q_mcu[qid], skb, 0);
274 }
275
developerf3f5d9b2023-02-07 15:24:34 +0800276@@ -2315,7 +2320,10 @@ static int mt7915_red_set_watermark(struct mt7915_dev *dev)
277 sizeof(req), false);
278 }
279
280-static int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled)
281+#ifndef MTK_DEBUG
282+static
283+#endif
284+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled)
285 {
286 #define RED_DISABLE 0
287 #define RED_BY_WA_ENABLE 2
288@@ -3377,6 +3385,8 @@ int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable)
developeraace7f52022-06-24 13:40:42 +0800289 .sku_enable = enable,
290 };
developer3fa816c2022-04-19 10:21:20 +0800291
developeraace7f52022-06-24 13:40:42 +0800292+ pr_info("%s: enable = %d\n", __func__, enable);
293+
294 return mt76_mcu_send_msg(&dev->mt76,
295 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
296 sizeof(req), true);
developerf3f5d9b2023-02-07 15:24:34 +0800297@@ -3814,6 +3824,23 @@ int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev,
developer3fa816c2022-04-19 10:21:20 +0800298 &req, sizeof(req), true);
299 }
developer1eeb8e82022-05-03 14:10:10 +0800300
developer3fa816c2022-04-19 10:21:20 +0800301+#ifdef MTK_DEBUG
302+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp)
303+{
304+ struct {
305+ __le32 args[3];
306+ } req = {
307+ .args = {
308+ cpu_to_le32(a1),
309+ cpu_to_le32(a2),
310+ cpu_to_le32(a3),
311+ },
312+ };
313+
314+ return mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), wait_resp);
315+}
developer3fa816c2022-04-19 10:21:20 +0800316+#endif
developer1eeb8e82022-05-03 14:10:10 +0800317+
318 int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set)
319 {
320 struct {
developerf3f5d9b2023-02-07 15:24:34 +0800321@@ -3842,3 +3869,22 @@ int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set)
developer9e5bcc52022-09-27 10:30:15 +0800322
323 return 0;
324 }
325+
326+#ifdef MTK_DEBUG
327+int mt7915_mcu_set_amsdu_algo(struct mt7915_dev *dev, u16 wcid, u8 enable)
328+{
329+ struct {
330+ u16 action;
331+ u8 _rsv1[2];
332+ u16 wcid;
333+ u8 enable;
334+ u8 _rsv2[5];
335+ } __packed req = {
336+ .action = cpu_to_le16(1),
337+ .wcid = cpu_to_le16(wcid),
338+ .enable = enable,
339+ };
340+
341+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MEC_CTRL), &req, sizeof(req), true);
342+}
343+#endif
developer3fa816c2022-04-19 10:21:20 +0800344diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developerf3f5d9b2023-02-07 15:24:34 +0800345index b9ea297f..da863601 100644
developer3fa816c2022-04-19 10:21:20 +0800346--- a/mt7915/mcu.h
347+++ b/mt7915/mcu.h
developer2458e702022-12-13 15:52:04 +0800348@@ -278,6 +278,10 @@ enum {
developer3fa816c2022-04-19 10:21:20 +0800349 MCU_WA_PARAM_PDMA_RX = 0x04,
350 MCU_WA_PARAM_CPU_UTIL = 0x0b,
351 MCU_WA_PARAM_RED = 0x0e,
352+#ifdef MTK_DEBUG
353+ MCU_WA_PARAM_RED_SHOW_STA = 0xf,
354+ MCU_WA_PARAM_RED_TARGET_DELAY = 0x10,
355+#endif
developerf3f5d9b2023-02-07 15:24:34 +0800356 MCU_WA_PARAM_RED_SETTING = 0x40,
developer3fa816c2022-04-19 10:21:20 +0800357 };
358
developer3fa816c2022-04-19 10:21:20 +0800359diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developerf3f5d9b2023-02-07 15:24:34 +0800360index 3cbfb9b6..19880099 100644
developer3fa816c2022-04-19 10:21:20 +0800361--- a/mt7915/mt7915.h
362+++ b/mt7915/mt7915.h
363@@ -9,6 +9,7 @@
364 #include "../mt76_connac.h"
365 #include "regs.h"
366
367+#define MTK_DEBUG 1
368 #define MT7915_MAX_INTERFACES 19
developer3fa816c2022-04-19 10:21:20 +0800369 #define MT7915_WTBL_SIZE 288
developeraace7f52022-06-24 13:40:42 +0800370 #define MT7916_WTBL_SIZE 544
developerf3f5d9b2023-02-07 15:24:34 +0800371@@ -373,6 +374,29 @@ struct mt7915_dev {
developer3fa816c2022-04-19 10:21:20 +0800372 struct reset_control *rstc;
373 void __iomem *dcm;
374 void __iomem *sku;
375+
376+#ifdef MTK_DEBUG
377+ u16 wlan_idx;
378+ struct {
379+ u32 fixed_rate;
380+ u32 l1debugfs_reg;
381+ u32 l2debugfs_reg;
382+ u32 mac_reg;
383+ u32 fw_dbg_module;
384+ u8 fw_dbg_lv;
385+ u32 bcn_total_cnt[2];
386+ u16 fwlog_seq;
387+ bool dump_mcu_pkt;
388+ bool dump_txd;
389+ bool dump_tx_pkt;
390+ bool dump_rx_pkt;
391+ bool dump_rx_raw;
392+ u32 token_idx;
developeraace7f52022-06-24 13:40:42 +0800393+ u8 sku_disable;
394+ u8 muru_onoff;
developer3fa816c2022-04-19 10:21:20 +0800395+ } dbg;
396+ const struct mt7915_dbg_reg_desc *dbg_reg;
397+#endif
398 };
399
400 enum {
developerf3f5d9b2023-02-07 15:24:34 +0800401@@ -651,4 +675,24 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developerf1313102022-10-11 11:02:55 +0800402 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr,
403 bool pci, int *irq);
developer3fa816c2022-04-19 10:21:20 +0800404
405+#ifdef MTK_DEBUG
406+int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir);
407+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp);
408+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled);
409+void mt7915_dump_tmac_info(u8 *tmac_info);
410+int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level);
411+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len);
developer9e5bcc52022-09-27 10:30:15 +0800412+int mt7915_mcu_set_amsdu_algo(struct mt7915_dev *dev, u16 wcid, u8 enable);
developer3fa816c2022-04-19 10:21:20 +0800413+
414+#define PKT_BIN_DEBUG_MAGIC 0xc8763123
415+enum {
416+ PKT_BIN_DEBUG_MCU,
417+ PKT_BIN_DEBUG_TXD,
418+ PKT_BIN_DEBUG_TX,
419+ PKT_BIN_DEBUG_RX,
420+ PKT_BIN_DEBUG_RX_RAW,
421+};
422+
423+#endif
424+
425 #endif
426diff --git a/mt7915/mt7915_debug.h b/mt7915/mt7915_debug.h
427new file mode 100644
developerf3f5d9b2023-02-07 15:24:34 +0800428index 00000000..ca553dca
developer3fa816c2022-04-19 10:21:20 +0800429--- /dev/null
430+++ b/mt7915/mt7915_debug.h
developer79a21a22023-01-09 13:57:39 +0800431@@ -0,0 +1,1363 @@
developer3fa816c2022-04-19 10:21:20 +0800432+#ifndef __MT7915_DEBUG_H
433+#define __MT7915_DEBUG_H
434+
435+#ifdef MTK_DEBUG
436+
437+#define DBG_INVALID_BASE 0xffffffff
438+#define DBG_INVALID_OFFSET 0x0
439+
440+struct __dbg_map {
441+ u32 phys;
442+ u32 maps;
443+ u32 size;
444+};
445+
446+struct __dbg_reg {
447+ u32 base;
448+ u32 offs;
449+};
450+
451+struct __dbg_mask {
452+ u32 end;
453+ u32 start;
454+};
455+
456+enum dbg_base_rev {
457+ MT_DBG_WFDMA0_BASE,
458+ MT_DBG_WFDMA1_BASE,
459+ MT_DBG_WFDMA0_PCIE1_BASE,
460+ MT_DBG_WFDMA1_PCIE1_BASE,
461+ MT_DBG_WFDMA_EXT_CSR_BASE,
462+ MT_DBG_SWDEF_BASE,
463+ __MT_DBG_BASE_REV_MAX,
464+};
465+
466+enum dbg_reg_rev {
467+ DBG_INT_SOURCE_CSR,
468+ DBG_INT_MASK_CSR,
469+ DBG_INT1_SOURCE_CSR,
470+ DBG_INT1_MASK_CSR,
471+ DBG_TX_RING_BASE,
472+ DBG_RX_EVENT_RING_BASE,
473+ DBG_RX_STS_RING_BASE,
474+ DBG_RX_DATA_RING_BASE,
475+ DBG_DMA_ICSC_FR0,
476+ DBG_DMA_ICSC_FR1,
477+ DBG_TMAC_ICSCR0,
478+ DBG_RMAC_RXICSRPT,
479+ DBG_MIB_M0SDR0,
480+ DBG_MIB_M0SDR3,
481+ DBG_MIB_M0SDR4,
482+ DBG_MIB_M0SDR5,
483+ DBG_MIB_M0SDR7,
484+ DBG_MIB_M0SDR8,
485+ DBG_MIB_M0SDR9,
486+ DBG_MIB_M0SDR10,
487+ DBG_MIB_M0SDR11,
488+ DBG_MIB_M0SDR12,
489+ DBG_MIB_M0SDR14,
490+ DBG_MIB_M0SDR15,
491+ DBG_MIB_M0SDR16,
492+ DBG_MIB_M0SDR17,
493+ DBG_MIB_M0SDR18,
494+ DBG_MIB_M0SDR19,
495+ DBG_MIB_M0SDR20,
496+ DBG_MIB_M0SDR21,
497+ DBG_MIB_M0SDR22,
498+ DBG_MIB_M0SDR23,
499+ DBG_MIB_M0DR0,
500+ DBG_MIB_M0DR1,
501+ DBG_MIB_MUBF,
502+ DBG_MIB_M0DR6,
503+ DBG_MIB_M0DR7,
504+ DBG_MIB_M0DR8,
505+ DBG_MIB_M0DR9,
506+ DBG_MIB_M0DR10,
507+ DBG_MIB_M0DR11,
508+ DBG_MIB_M0DR12,
509+ DBG_WTBLON_WDUCR,
510+ DBG_UWTBL_WDUCR,
511+ DBG_PLE_DRR_TABLE_CTRL,
512+ DBG_PLE_DRR_TABLE_RDATA,
513+ DBG_PLE_PBUF_CTRL,
514+ DBG_PLE_QUEUE_EMPTY,
515+ DBG_PLE_FREEPG_CNT,
516+ DBG_PLE_FREEPG_HEAD_TAIL,
517+ DBG_PLE_PG_HIF_GROUP,
518+ DBG_PLE_HIF_PG_INFO,
519+ DBG_PLE_PG_HIF_TXCMD_GROUP,
520+ DBG_PLE_HIF_TXCMD_PG_INFO,
521+ DBG_PLE_PG_CPU_GROUP,
522+ DBG_PLE_CPU_PG_INFO,
523+ DBG_PLE_FL_QUE_CTRL,
524+ DBG_PLE_NATIVE_TXCMD_Q_EMPTY,
525+ DBG_PLE_TXCMD_Q_EMPTY,
526+ DBG_PLE_AC_QEMPTY,
527+ DBG_PLE_AC_OFFSET,
528+ DBG_PLE_STATION_PAUSE,
529+ DBG_PLE_DIS_STA_MAP,
530+ DBG_PSE_PBUF_CTRL,
531+ DBG_PSE_FREEPG_CNT,
532+ DBG_PSE_FREEPG_HEAD_TAIL,
533+ DBG_PSE_HIF0_PG_INFO,
534+ DBG_PSE_PG_HIF1_GROUP,
535+ DBG_PSE_HIF1_PG_INFO,
536+ DBG_PSE_PG_CPU_GROUP,
537+ DBG_PSE_CPU_PG_INFO,
538+ DBG_PSE_PG_PLE_GROUP,
539+ DBG_PSE_PLE_PG_INFO,
540+ DBG_PSE_PG_LMAC0_GROUP,
541+ DBG_PSE_LMAC0_PG_INFO,
542+ DBG_PSE_PG_LMAC1_GROUP,
543+ DBG_PSE_LMAC1_PG_INFO,
544+ DBG_PSE_PG_LMAC2_GROUP,
545+ DBG_PSE_LMAC2_PG_INFO,
546+ DBG_PSE_PG_LMAC3_GROUP,
547+ DBG_PSE_LMAC3_PG_INFO,
548+ DBG_PSE_PG_MDP_GROUP,
549+ DBG_PSE_MDP_PG_INFO,
550+ DBG_PSE_PG_PLE1_GROUP,
551+ DBG_PSE_PLE1_PG_INFO,
552+ DBG_AGG_AALCR0,
553+ DBG_AGG_AALCR1,
554+ DBG_AGG_AALCR2,
555+ DBG_AGG_AALCR3,
556+ DBG_AGG_AALCR4,
557+ DBG_AGG_B0BRR0,
558+ DBG_AGG_B1BRR0,
559+ DBG_AGG_B2BRR0,
560+ DBG_AGG_B3BRR0,
561+ DBG_AGG_AWSCR0,
562+ DBG_AGG_PCR0,
563+ DBG_AGG_TTCR0,
564+ DBG_MIB_M0ARNG0,
565+ DBG_MIB_M0DR2,
566+ DBG_MIB_M0DR13,
developer79a21a22023-01-09 13:57:39 +0800567+ DBG_WFDMA_WED_TX_CTRL,
568+ DBG_WFDMA_WED_RX_CTRL,
developer3fa816c2022-04-19 10:21:20 +0800569+ __MT_DBG_REG_REV_MAX,
570+};
571+
572+enum dbg_mask_rev {
573+ DBG_MIB_M0SDR10_RX_MDRDY_COUNT,
574+ DBG_MIB_M0SDR14_AMPDU,
575+ DBG_MIB_M0SDR15_AMPDU_ACKED,
576+ DBG_MIB_RX_FCS_ERROR_COUNT,
577+ __MT_DBG_MASK_REV_MAX,
578+};
579+
580+enum dbg_bit_rev {
581+ __MT_DBG_BIT_REV_MAX,
582+};
583+
584+static const u32 mt7915_dbg_base[] = {
585+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
586+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
587+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
588+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
589+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
590+ [MT_DBG_SWDEF_BASE] = 0x41f200,
591+};
592+
593+static const u32 mt7916_dbg_base[] = {
594+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
595+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
596+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
597+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
598+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
599+ [MT_DBG_SWDEF_BASE] = 0x411400,
600+};
601+
602+static const u32 mt7986_dbg_base[] = {
603+ [MT_DBG_WFDMA0_BASE] = 0x24000,
604+ [MT_DBG_WFDMA1_BASE] = 0x25000,
605+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0x28000,
606+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0x29000,
607+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0x27000,
608+ [MT_DBG_SWDEF_BASE] = 0x411400,
609+};
610+
611+/* mt7915 regs with different base and offset */
612+static const struct __dbg_reg mt7915_dbg_reg[] = {
developer79a21a22023-01-09 13:57:39 +0800613+ [DBG_WFDMA_WED_TX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x300 },
614+ [DBG_WFDMA_WED_RX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x400 },
developer3fa816c2022-04-19 10:21:20 +0800615+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x10 },
616+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x14 },
617+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x88 },
618+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x8c },
619+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x400 },
620+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x500 },
621+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x510 },
622+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
623+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x0f0 },
624+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x0f4 },
625+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x200 },
626+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0x618},
627+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x010},
628+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x014},
629+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x018},
630+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x01c},
631+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x024},
632+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x028},
633+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x02C},
634+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x030},
635+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x034},
636+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x038},
637+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x040},
638+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x044},
639+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x048},
640+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x04c},
641+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x050},
642+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x054},
643+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x058},
644+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x05c},
645+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x060},
646+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x064},
647+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x0a0},
648+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x0a4},
649+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x090},
650+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x0b8},
651+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x0bc},
652+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x0c0},
653+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x0c4},
654+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x0c8},
655+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x0cc},
656+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x160},
657+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x0},
658+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x0},
659+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x388},
660+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x350},
661+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
662+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x0b0},
663+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
664+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
665+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x110},
666+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x114},
667+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x120},
668+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x124},
669+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
670+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
671+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x1b0},
672+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x22c},
673+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x230},
674+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x500},
675+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x040},
676+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x400},
677+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x440},
developerf32dabf2022-06-01 10:59:24 +0800678+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
developer3fa816c2022-04-19 10:21:20 +0800679+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
680+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
681+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x114},
682+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x118},
683+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x11c},
684+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
685+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
686+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x160},
687+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x164},
688+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x170},
689+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x174},
690+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x178},
691+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
692+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x180},
693+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x184},
694+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x188},
695+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x18c},
696+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x198},
697+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x19c},
698+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x168},
699+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
700+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x048},
701+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x04c},
702+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x050},
703+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x054},
704+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x058},
705+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x100},
706+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x104},
707+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x108},
708+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x10c},
709+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x030},
710+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x040},
711+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x04c},
712+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x4b8},
713+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x0a8},
714+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x164},
715+};
716+
717+/* mt7986/mt7916 regs with different base and offset */
718+static const struct __dbg_reg mt7916_dbg_reg[] = {
developer79a21a22023-01-09 13:57:39 +0800719+ [DBG_WFDMA_WED_TX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x300 },
720+ [DBG_WFDMA_WED_RX_CTRL] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x400 },
developer3fa816c2022-04-19 10:21:20 +0800721+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA0_BASE, 0x200 },
722+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA0_BASE, 0x204 },
723+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x200 },
724+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x204 },
725+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x400 },
726+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
727+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x520 },
728+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x540 },
729+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x05c },
730+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x060 },
731+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x120 },
732+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0xd0 },
733+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x7d8},
734+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x698},
735+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x788},
736+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x780},
737+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x5a8},
738+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x78c},
739+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x024},
740+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x76c},
741+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x790},
742+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x558},
743+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x564},
744+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x564},
745+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x7fc},
746+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x800},
747+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x030},
748+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x5ac},
749+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x5b0},
750+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x5b4},
751+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x770},
752+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x774},
753+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x594},
754+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x598},
755+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x7ac},
756+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x658},
757+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x65c},
758+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x56c},
759+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x570},
760+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x578},
761+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x574},
762+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x654},
763+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x200},
764+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x094},
765+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x490},
766+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x470},
767+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
768+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x360},
769+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
770+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
771+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x00c},
772+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x388},
773+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x014},
774+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x390},
775+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x018},
776+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x394},
777+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x3e0},
778+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x370},
developerf32dabf2022-06-01 10:59:24 +0800779+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x36c},
developer3fa816c2022-04-19 10:21:20 +0800780+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x600},
781+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x080},
782+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x100},
783+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x180},
784+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
785+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
786+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
787+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x150},
788+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x154},
789+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
790+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x118},
791+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x158},
792+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x11c},
793+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x15c},
794+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x124},
795+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x164},
796+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x128},
797+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x168},
798+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x12c},
799+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
800+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x130},
801+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
802+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x134},
803+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x174},
804+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x120},
805+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
806+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x028},
807+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x144},
808+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x14c},
809+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x154},
810+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x02c},
811+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x08c},
812+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x148},
813+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x150},
814+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x158},
815+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x05c},
816+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x06c},
817+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x07c},
818+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x0b0},
819+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x7dc},
820+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x7ec},
821+};
822+
823+static const struct __dbg_mask mt7915_dbg_mask[] = {
824+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {25, 0},
825+ [DBG_MIB_M0SDR14_AMPDU] = {23, 0},
826+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {23, 0},
827+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {15, 0},
828+};
829+
830+static const struct __dbg_mask mt7916_dbg_mask[] = {
831+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {31, 0},
832+ [DBG_MIB_M0SDR14_AMPDU] = {31, 0},
833+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {31, 0},
834+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {31, 16},
835+};
836+
837+/* used to differentiate between generations */
838+struct mt7915_dbg_reg_desc {
839+ const u32 id;
840+ const u32 *base_rev;
841+ const struct __dbg_reg *reg_rev;
842+ const struct __dbg_mask *mask_rev;
843+};
844+
845+static const struct mt7915_dbg_reg_desc dbg_reg_s[] = {
846+ { 0x7915,
847+ mt7915_dbg_base,
848+ mt7915_dbg_reg,
849+ mt7915_dbg_mask
850+ },
851+ { 0x7906,
852+ mt7916_dbg_base,
853+ mt7916_dbg_reg,
854+ mt7916_dbg_mask
855+ },
856+ { 0x7986,
857+ mt7986_dbg_base,
858+ mt7916_dbg_reg,
859+ mt7916_dbg_mask
860+ },
861+};
862+
863+struct bin_debug_hdr {
864+ __le32 magic_num;
865+ __le16 serial_id;
866+ __le16 msg_type;
867+ __le16 len;
868+ __le16 des_len; /* descriptor len for rxd */
869+} __packed;
870+
871+#define __DBG_REG_MAP(_dev, id, ofs) ((_dev)->dbg_reg->base_rev[(id)] + (ofs))
872+#define __DBG_REG_BASE(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].base)
873+#define __DBG_REG_OFFS(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].offs)
874+
875+#define __DBG_MASK(_dev, id) GENMASK((_dev)->dbg_reg->mask_rev[(id)].end, \
876+ (_dev)->dbg_reg->mask_rev[(id)].start)
877+#define __DBG_REG(_dev, id) __DBG_REG_MAP((_dev), __DBG_REG_BASE((_dev), (id)), \
878+ __DBG_REG_OFFS((_dev), (id)))
879+
880+#define __DBG_FIELD_GET(id, _reg) (((_reg) & __DBG_MASK(dev, (id))) >> \
881+ dev->dbg_reg->mask_rev[(id)].start)
882+#define __DBG_FIELD_PREP(id, _reg) (((_reg) << dev->dbg_reg->mask_rev[(id)].start) & \
883+ __DBG_MASK(dev, (id)))
884+
885+
886+#define MT_DBG_TX_RING_BASE __DBG_REG(dev, DBG_TX_RING_BASE)
887+#define MT_DBG_RX_EVENT_RING_BASE __DBG_REG(dev, DBG_RX_EVENT_RING_BASE)
888+#define MT_DBG_RX_STS_RING_BASE __DBG_REG(dev, DBG_RX_STS_RING_BASE)
889+#define MT_DBG_RX_DATA_RING_BASE __DBG_REG(dev, DBG_RX_DATA_RING_BASE)
developer79a21a22023-01-09 13:57:39 +0800890+#define MT_DBG_WFDMA_WED_TX_CTRL_BASE __DBG_REG(dev, DBG_WFDMA_WED_TX_CTRL)
891+#define MT_DBG_WFDMA_WED_RX_CTRL_BASE __DBG_REG(dev, DBG_WFDMA_WED_RX_CTRL)
developer3fa816c2022-04-19 10:21:20 +0800892+
893+#define MT_DBG_TX_RING_CTRL(n) (MT_DBG_TX_RING_BASE + (0x10 * (n)))
894+#define MT_DBG_RX_DATA_RING_CTRL(n) (MT_DBG_RX_DATA_RING_BASE + (0x10 * (n)))
895+#define MT_DBG_RX_EVENT_RING_CTRL(n) (MT_DBG_RX_EVENT_RING_BASE + (0x10 * (n)))
896+
developer79a21a22023-01-09 13:57:39 +0800897+#define MT_DBG_WFDMA_WED_TX_CTRL(n) (MT_DBG_WFDMA_WED_TX_CTRL_BASE + (0x10 * (n)))
898+#define MT_DBG_WFDMA_WED_RX_CTRL(n) (MT_DBG_WFDMA_WED_RX_CTRL_BASE + (0x10 * (n)))
developer3fa816c2022-04-19 10:21:20 +0800899+/* WFDMA COMMON */
900+#define MT_DBG_INT_SOURCE_CSR __DBG_REG(dev, DBG_INT_SOURCE_CSR)
901+#define MT_DBG_INT_MASK_CSR __DBG_REG(dev, DBG_INT_MASK_CSR)
902+#define MT_DBG_INT1_SOURCE_CSR __DBG_REG(dev, DBG_INT1_SOURCE_CSR)
903+#define MT_DBG_INT1_MASK_CSR __DBG_REG(dev, DBG_INT1_MASK_CSR)
904+
905+/* WFDMA0 */
906+#define MT_DBG_WFDMA0(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_BASE, (_ofs))
907+
908+#define MT_DBG_WFDMA0_INT_SOURCE_CSR MT_DBG_WFDMA0(0x200)
909+#define MT_DBG_WFDMA0_INT_MASK_CSR MT_DBG_WFDMA0(0x204)
910+
911+#define MT_DBG_WFDMA0_GLO_CFG MT_DBG_WFDMA0(0x208)
912+#define MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
913+#define MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
914+#define MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK BIT(1)
915+#define MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK BIT(3)
916+
917+
918+/* WFDMA1 */
919+#define MT_DBG_WFDMA1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_BASE, (_ofs))
920+#define MT_DBG_WFDMA1_INT_SOURCE_CSR MT_DBG_WFDMA1(0x200)
921+#define MT_DBG_WFDMA1_INT_MASK_CSR MT_DBG_WFDMA1(0x204)
922+
923+#define MT_DBG_WFDMA1_GLO_CFG MT_DBG_WFDMA1(0x208)
924+
925+#define MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
926+#define MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
927+#define MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK BIT(1)
928+#define MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK BIT(3)
929+
930+/* WFDMA0 PCIE1 */
931+#define MT_DBG_WFDMA0_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_PCIE1_BASE, (_ofs))
932+
933+#define MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA0_PCIE1(0x200)
934+#define MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR MT_DBG_WFDMA0_PCIE1(0x204)
935+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG MT_DBG_WFDMA0_PCIE1(0x208)
936+#define MT_DBG_WFDMA0_PCIE1_RX1_CTRL0 MT_DBG_WFDMA1_PCIE1(0x510)
937+
938+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
939+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
940+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
941+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
942+
943+/* WFDMA1 PCIE1 */
944+#define MT_DBG_WFDMA1_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_PCIE1_BASE, (_ofs))
945+#define MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA1_PCIE1(0x200)
946+#define MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR MT_DBG_WFDMA1_PCIE1(0x204)
947+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG MT_DBG_WFDMA1_PCIE1(0x208)
948+#define MT_DBG_WFDMA1_PCIE1_TX19_CTRL0 MT_DBG_WFDMA1_PCIE1(0x330)
949+#define MT_DBG_WFDMA1_PCIE1_RX2_CTRL0 MT_DBG_WFDMA1_PCIE1(0x520)
950+
951+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
952+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
953+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
954+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
955+
956+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK BIT(2)
957+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK BIT(0)
958+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK BIT(3)
959+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK BIT(1)
960+
961+
962+/* WF DMA TOP: band 0(0x820E7000),band 1(0x820F7000) */
963+#define MT_DBG_WF_DMA_BASE(_band) ((_band) ? 0x820F7000 : 0x820E7000)
964+#define MT_DBG_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
965+
966+#define MT_DBG_DMA_DCR0(_band) MT_DBG_WF_DMA((_band), 0x000)
967+#define MT_DBG_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
968+#define MT_DBG_DMA_DCR0_RXD_G5_EN BIT(23)
969+
970+#define MT_DBG_DMA_ICSC_FR0(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR0))
971+#define MT_DBG_DMA_ICSC_FR0_RXBF_EN BIT(25)
972+#define MT_DBG_DMA_ICSC_FR0_EN BIT(24)
973+#define MT_DBG_DMA_ICSC_FR0_TOUT_MASK GENMASK(23, 16)
974+#define MT_DBG_DMA_ICSC_FR0_PID_MASK GENMASK(9, 8)
975+#define MT_DBG_DMA_ICSC_FR0_QID_MASK GENMASK(6, 0)
976+
977+#define MT_DBG_DMA_ICSC_FR1(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR1))
978+#define MT_DBG_DMA_ICSC_FR1_AGG_SIZE_MASK GENMASK(26, 16)
979+#define MT_DBG_DMA_ICSC_FR1_MAX_FRAME_SIZE_MASK GENMASK(10, 0)
980+
981+/* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
982+#define MT_DBG_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
983+#define MT_DBG_WF_TMAC(_band, ofs) (MT_DBG_WF_TMAC_BASE(_band) + (ofs))
984+
985+#define MT_DBG_TMAC_ICSCR0(_band) MT_DBG_WF_TMAC((_band), __DBG_REG_OFFS(dev, DBG_TMAC_ICSCR0))
986+#define MT_DBG_TMAC_ICSCR0_ICSRPT_EN BIT(0)
987+
988+/* RMAC: band 0(0x820E5000), band 1(0x820f5000) */
989+#define MT_DBG_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820E5000)
990+#define MT_DBG_WF_RMAC(_band, ofs) (MT_DBG_WF_RMAC_BASE(_band) + (ofs))
991+
992+#define MT_DBG_RMAC_RXICSRPT(_band) MT_DBG_WF_RMAC((_band), __DBG_REG_OFFS(dev, DBG_RMAC_RXICSRPT))
993+#define MT_DBG_RMAC_RXICSRPT_ICSRPT_EN BIT(0)
994+
995+/* MIB: band 0(0x820ed000), band 1(0x820fd000) */
996+#define MT_DBG_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
997+#define MT_DBG_MIB(_band, ofs) (MT_DBG_MIB_BASE(_band) + (ofs))
998+
999+
1000+#define MT_DBG_MIB_M0SCR0(_band) MT_DBG_MIB((_band), 0x00)
1001+#define MT_DBG_MIB_M0PBSCR(_band) MT_DBG_MIB((_band), 0x04)
1002+
1003+#define MT_DBG_MIB_M0SDR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR0))
1004+#define MT_DBG_MIB_M0SDR3(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR3))
1005+#define MT_DBG_MIB_RX_FCS_ERROR_COUNT_MASK __DBG_MASK(dev, DBG_MIB_RX_FCS_ERROR_COUNT)
1006+#define MT_DBG_MIB_M0SDR4(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR4))
1007+#define MT_DBG_MIB_M0SDR5(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR5))
1008+#define MT_DBG_MIB_M0SDR6(_band) MT_DBG_MIB((_band), 0x20)
1009+#define MT_DBG_MIB_M0SDR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR7))
1010+#define MT_DBG_MIB_M0SDR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR8))
1011+#define MT_DBG_MIB_M0SDR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR9))
1012+#define MT_DBG_MIB_M0SDR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR10))
1013+#define MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK __DBG_MASK(dev, DBG_MIB_M0SDR10_RX_MDRDY_COUNT)
1014+#define MT_DBG_MIB_M0SDR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR11))
1015+
1016+#define MT_DBG_MIB_M0SDR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR12))
1017+
1018+#define MT_DBG_MIB_M0SDR14(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR14))
1019+#define MT_DBG_MIB_M0SDR14_AMPDU_MASK __DBG_MASK(dev, DBG_MIB_M0SDR14_AMPDU)
1020+#define MT_DBG_MIB_M0SDR15(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR15))
1021+#define MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK __DBG_MASK(dev, DBG_MIB_M0SDR15_AMPDU_ACKED)
1022+#define MT_DBG_MIB_M0SDR16(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR16))
1023+#define MT_DBG_MIB_M0SDR17(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR17))
1024+#define MT_DBG_MIB_M0SDR18(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR18))
1025+#define MT_DBG_MIB_M0SDR19(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR19))
1026+#define MT_DBG_MIB_M0SDR20(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR20))
1027+#define MT_DBG_MIB_M0SDR21(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR21))
1028+#define MT_DBG_MIB_M0SDR22(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR22))
1029+#define MT_DBG_MIB_M0SDR23(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR23))
1030+#define MT_DBG_MIB_M0DR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR0))
1031+#define MT_DBG_MIB_M0DR1(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR1))
1032+
1033+#define MT_DBG_MIB_MUBF(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_MUBF))
1034+#define MT_DBG_MIB_M0DR6(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR6))
1035+#define MT_DBG_MIB_M0DR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR7))
1036+#define MT_DBG_MIB_M0DR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR8))
1037+#define MT_DBG_MIB_M0DR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR9))
1038+#define MT_DBG_MIB_M0DR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR10))
1039+#define MT_DBG_MIB_M0DR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR11))
1040+ #define MT_DBG_MIB_M0DR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR12))
1041+
1042+/* WTBLON TOP: 0x820D4000/pcie(0x34000) rbus(0x434000) */
1043+#define MT_DBG_WTBLON_TOP_BASE 0x820D4000
1044+#define MT_DBG_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
1045+#define MT_DBG_WTBLON_TOP_WDUCR MT_DBG_WTBLON_TOP(__DBG_REG_OFFS(dev, DBG_WTBLON_WDUCR))
1046+#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
1047+
1048+#define WF_WTBLON_TOP_B0BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1000) // 5000
1049+#define WF_WTBLON_TOP_B0BTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1010) // 5010
1050+#define WF_WTBLON_TOP_B0BRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1020) // 5020
1051+#define WF_WTBLON_TOP_B0BRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1030) // 5030
1052+#define WF_WTBLON_TOP_B0BTDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1040) // 5040
1053+#define WF_WTBLON_TOP_B0BRDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1050) // 5050
1054+#define WF_WTBLON_TOP_B0MBTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1100) // 5100
1055+#define WF_WTBLON_TOP_B0MBTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1140) // 5140
1056+#define WF_WTBLON_TOP_B0MBRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1180) // 5180
1057+#define WF_WTBLON_TOP_B0MBRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x11C0) // 51C0
1058+
1059+#define WF_WTBLON_TOP_B1BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1800) // 5800
1060+
1061+/* WTBLON TOP: 0x820C4000/pcie(0xa8000) rbus(0x4a8000) */
1062+#define MT_DBG_UWTBL_TOP_BASE 0x820C4000
1063+#define MT_DBG_UWTBL_TOP(ofs) (MT_DBG_UWTBL_TOP_BASE + (ofs))
1064+
developerf1313102022-10-11 11:02:55 +08001065+#define MT_DBG_UWTBL_TOP_WDUCR MT_DBG_UWTBL_TOP(__DBG_REG_OFFS(dev, DBG_UWTBL_WDUCR))
developer3fa816c2022-04-19 10:21:20 +08001066+
1067+#define MT_UWTBL_TOP_WDUCR_TARGET BIT(31)
1068+#define MT_UWTBL_TOP_WDUCR_GROUP GENMASK(3, 0)
1069+
1070+
1071+/* WTBL : 0x820D8000/pcie(0x38000) rbus(0x438000) */
1072+#define MT_DBG_WTBL_BASE 0x820D8000
1073+
1074+/* PLE related CRs. */
1075+#define MT_DBG_PLE_BASE 0x820C0000
1076+#define MT_DBG_PLE(ofs) (MT_DBG_PLE_BASE + (ofs))
1077+
1078+#define MT_DBG_PLE_DRR_TAB_CTRL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_CTRL))
1079+#define MT_DBG_PLE_DRR_TAB_RD_OFS __DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_RDATA)
1080+
1081+#define MT_DBG_PLE_DRR_TABLE_RDATA0 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x0)
1082+#define MT_DBG_PLE_DRR_TABLE_RDATA1 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x4)
1083+#define MT_DBG_PLE_DRR_TABLE_RDATA2 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x8)
1084+#define MT_DBG_PLE_DRR_TABLE_RDATA3 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0xc)
1085+#define MT_DBG_PLE_DRR_TABLE_RDATA4 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x10)
1086+#define MT_DBG_PLE_DRR_TABLE_RDATA5 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x14)
1087+#define MT_DBG_PLE_DRR_TABLE_RDATA6 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x18)
1088+#define MT_DBG_PLE_DRR_TABLE_RDATA7 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS+ 0x1c)
1089+
1090+#define MT_DBG_PLE_PBUF_CTRL_ADDR MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PBUF_CTRL))
1091+#define MT_DBG_PLE_QUEUE_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_QUEUE_EMPTY))
1092+#define MT_DBG_PLE_FREEPG_CNT MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_CNT))
1093+#define MT_DBG_PLE_FREEPG_HEAD_TAIL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_HEAD_TAIL))
1094+#define MT_DBG_PLE_PG_HIF_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_GROUP))
1095+#define MT_DBG_PLE_HIF_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_PG_INFO))
1096+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_TXCMD_GROUP))
1097+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_TXCMD_PG_INFO))
1098+#define MT_DBG_PLE_PG_CPU_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_CPU_GROUP))
1099+#define MT_DBG_PLE_CPU_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_CPU_PG_INFO))
1100+#define PLE_FL_QUE_CTRL_OFFSET __DBG_REG_OFFS(dev, DBG_PLE_FL_QUE_CTRL)
1101+#define MT_DBG_PLE_FL_QUE_CTRL0 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x0)
1102+#define MT_DBG_PLE_FL_QUE_CTRL1 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x4)
1103+#define MT_DBG_PLE_FL_QUE_CTRL2 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x8)
1104+#define MT_DBG_PLE_FL_QUE_CTRL3 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0xc)
1105+#define MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_NATIVE_TXCMD_Q_EMPTY))
1106+#define MT_DBG_PLE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_TXCMD_Q_EMPTY))
1107+
1108+#define MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK BIT(31)
1109+#define MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK GENMASK(25, 17)
1110+#define MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1111+
1112+#define MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1113+#define MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1114+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1115+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1116+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK GENMASK(27, 16)
1117+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK GENMASK(11, 0)
1118+
1119+#define MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK GENMASK(27, 16)
1120+#define MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK GENMASK(11, 0)
1121+
1122+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK GENMASK(27, 16)
1123+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK GENMASK(11, 0)
1124+
1125+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
1126+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
1127+
1128+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
1129+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
1130+
1131+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1132+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1133+
1134+#define MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1135+#define MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1136+
1137+#define MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK BIT(24)
1138+#define MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK BIT(31)
1139+#define MT_DBG_PLE_FL_QUE_CTRL0_Q_BUF_QID_MASK GENMASK(30, 24)
1140+
1141+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT 24
1142+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT 10
1143+
1144+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK GENMASK(27, 16)
1145+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK GENMASK(11, 0)
1146+#define MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK GENMASK(11, 0)
1147+
1148+#define MT_DBG_PLE_STATION_PAUSE(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_STATION_PAUSE) + ((n) << 2))
1149+#define MT_DBG_PLE_DIS_STA_MAP(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DIS_STA_MAP) + ((n) << 2))
1150+#define MT_DBG_PLE_AC_QEMPTY(ac, n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_AC_QEMPTY) + \
1151+ __DBG_REG_OFFS(dev, DBG_PLE_AC_OFFSET) * (ac) + ((n) << 2))
1152+
1153+#define MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(n) MT_DBG_PLE(0x10e0 + ((n) << 2))
1154+
1155+/* pseinfo related CRs. */
1156+#define MT_DBG_PSE_BASE 0x820C8000
1157+#define MT_DBG_PSE(ofs) (MT_DBG_PSE_BASE + (ofs))
1158+
developerf32dabf2022-06-01 10:59:24 +08001159+#define MT_DBG_PSE_PBUF_CTRL MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PBUF_CTRL))
1160+#define MT_DBG_PSE_QUEUE_EMPTY MT_DBG_PSE(0x0b0)
1161+#define MT_DBG_PSE_FREEPG_CNT MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_CNT))
1162+#define MT_DBG_PSE_FREEPG_HEAD_TAIL MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_HEAD_TAIL))
1163+#define MT_DBG_PSE_PG_HIF0_GROUP MT_DBG_PSE(0x110)
1164+#define MT_DBG_PSE_HIF0_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_HIF0_PG_INFO))
1165+#define MT_DBG_PSE_PG_HIF1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_HIF1_GROUP))
1166+#define MT_DBG_PSE_HIF1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_HIF1_PG_INFO))
1167+#define MT_DBG_PSE_PG_CPU_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_CPU_GROUP))
1168+#define MT_DBG_PSE_CPU_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_CPU_PG_INFO))
1169+#define MT_DBG_PSE_PG_LMAC0_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC0_GROUP))
1170+#define MT_DBG_PSE_LMAC0_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC0_PG_INFO))
1171+#define MT_DBG_PSE_PG_LMAC1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC1_GROUP))
1172+#define MT_DBG_PSE_LMAC1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC1_PG_INFO))
1173+#define MT_DBG_PSE_PG_LMAC2_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC2_GROUP))
1174+#define MT_DBG_PSE_LMAC2_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC2_PG_INFO))
1175+#define MT_DBG_PSE_PG_PLE_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE_GROUP))
1176+#define MT_DBG_PSE_PLE_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PLE_PG_INFO))
1177+#define MT_DBG_PSE_PG_LMAC3_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC3_GROUP))
1178+#define MT_DBG_PSE_LMAC3_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC3_PG_INFO))
1179+#define MT_DBG_PSE_PG_MDP_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_MDP_GROUP))
1180+#define MT_DBG_PSE_MDP_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_MDP_PG_INFO))
1181+#define MT_DBG_PSE_PG_PLE1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE1_GROUP))
1182+#define MT_DBG_PSE_PLE1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PLE1_PG_INFO))
developer3fa816c2022-04-19 10:21:20 +08001183+
1184+#define MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK BIT(31)
1185+#define MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK GENMASK(25, 17)
1186+#define MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1187+#define MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK BIT(31)
1188+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK BIT(23)
1189+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK BIT(22)
1190+#define MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK BIT(21)
1191+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT BIT(20)
1192+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK BIT(19)
1193+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK BIT(18)
1194+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK BIT(17)
1195+#define MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK BIT(16)
1196+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK BIT(13)
1197+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK BIT(12)
1198+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK BIT(11)
1199+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK BIT(10)
1200+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK BIT(9)
1201+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK BIT(8)
1202+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK BIT(3)
1203+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK BIT(2)
1204+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK BIT(1)
1205+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK BIT(0)
1206+#define MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1207+#define MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1208+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1209+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1210+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1211+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1212+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1213+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1214+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK GENMASK(27, 16)
1215+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK GENMASK(11, 0)
1216+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK GENMASK(27, 16)
1217+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK GENMASK(11, 0)
1218+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK GENMASK(27, 16)
1219+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK GENMASK(11, 0)
1220+#define MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1221+#define MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1222+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK GENMASK(27, 16)
1223+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK GENMASK(11, 0)
1224+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1225+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1226+#define MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK GENMASK(27, 16)
1227+#define MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK GENMASK(11, 0)
1228+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK GENMASK(27, 16)
1229+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK GENMASK(11, 0)
1230+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK GENMASK(27, 16)
1231+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK GENMASK(11, 0)
1232+#define MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK GENMASK(27, 16)
1233+#define MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK GENMASK(11, 0)
1234+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK GENMASK(27, 16)
1235+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK GENMASK(11, 0)
1236+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK GENMASK(27, 16)
1237+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK GENMASK(11, 0)
1238+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK GENMASK(27, 16)
1239+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK GENMASK(11, 0)
1240+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1241+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1242+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK GENMASK(27, 16)
1243+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK GENMASK(11, 0)
1244+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1245+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1246+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK GENMASK(27, 16)
1247+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK GENMASK(11, 0)
1248+#define MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK GENMASK(27, 16)
1249+#define MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK GENMASK(11, 0)
1250+
1251+#define MT_DBG_PSE_FL_QUE_CTRL_0_ADDR MT_DBG_PLE(0x1b0)
1252+#define MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK BIT(31)
1253+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24
1254+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT 10
1255+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK GENMASK(9, 0)
1256+
1257+#define MT_DBG_PSE_FL_QUE_CTRL_2_ADDR MT_DBG_PLE(0x1b8)
1258+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK GENMASK(27, 16)
1259+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK GENMASK(11, 0)
1260+
1261+#define MT_DBG_PSE_FL_QUE_CTRL_3_ADDR MT_DBG_PLE(0x1bc)
1262+#define MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK GENMASK(11, 0)
1263+
1264+
1265+/* AGG */
1266+#define MT_DBG_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
1267+#define MT_DBG_AGG(_band, ofs) (MT_DBG_AGG_BASE(_band) + (ofs))
1268+
1269+#define MT_DBG_AGG_AALCR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR0))
1270+#define MT_DBG_AGG_AALCR1(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR1))
1271+#define MT_DBG_AGG_AALCR2(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR2))
1272+#define MT_DBG_AGG_AALCR3(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR3))
1273+#define MT_DBG_AGG_AALCR4(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR4))
1274+#define MT_DBG_AGG_B0BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B0BRR0))
1275+#define MT_DBG_AGG_B1BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B1BRR0))
1276+#define MT_DBG_AGG_B2BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B2BRR0))
1277+#define MT_DBG_AGG_B3BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B3BRR0))
1278+#define MT_DBG_AGG_AWSCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AWSCR0) + ((n) << 2))
1279+#define MT_DBG_AGG_PCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_PCR0) + ((n) << 2))
1280+#define MT_DBG_AGG_TTCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_TTCR0) + ((n) << 2))
1281+#define MT_DBG_MIB_M0ARNG(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0ARNG0) + ((n) << 2))
1282+#define MT_DBG_MIB_M0DR2(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR2) + ((n) << 2))
1283+#define MT_DBG_MIB_M0DR13(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR13) + ((n) << 2))
1284+
1285+#define MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK GENMASK(31, 24)
1286+#define MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK GENMASK(23, 16)
1287+#define MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK GENMASK(15, 8)
1288+#define MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK GENMASK(7, 0)
1289+#define MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK GENMASK(7, 0)
1290+
1291+#define MT_DBG_AGG_AWSCR0_WINSIZE3_MASK GENMASK(31, 24)
1292+#define MT_DBG_AGG_AWSCR0_WINSIZE2_MASK GENMASK(23, 16)
1293+#define MT_DBG_AGG_AWSCR0_WINSIZE1_MASK GENMASK(15, 8)
1294+#define MT_DBG_AGG_AWSCR0_WINSIZE0_MASK GENMASK(7, 0)
1295+
1296+#define MT_DBG_AGG_AWSCR1_WINSIZE7_MASK GENMASK(31, 24)
1297+#define MT_DBG_AGG_AWSCR1_WINSIZE6_MASK GENMASK(23, 16)
1298+#define MT_DBG_AGG_AWSCR1_WINSIZE5_MASK GENMASK(15, 8)
1299+#define MT_DBG_AGG_AWSCR1_WINSIZE4_MASK GENMASK(7, 0)
1300+
1301+#define MT_DBG_AGG_AWSCR2_WINSIZEB_MASK GENMASK(31, 24)
1302+#define MT_DBG_AGG_AWSCR2_WINSIZEA_MASK GENMASK(23, 16)
1303+#define MT_DBG_AGG_AWSCR2_WINSIZE9_MASK GENMASK(15, 8)
1304+#define MT_DBG_AGG_AWSCR2_WINSIZE8_MASK GENMASK(7, 0)
1305+
1306+#define MT_DBG_AGG_AWSCR3_WINSIZEE_MASK GENMASK(23, 16)
1307+#define MT_DBG_AGG_AWSCR3_WINSIZED_MASK GENMASK(15, 8)
1308+#define MT_DBG_AGG_AWSCR3_WINSIZEC_MASK GENMASK(7, 0)
1309+
1310+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK GENMASK(31, 24)
1311+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK GENMASK(23, 16)
1312+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK GENMASK(15, 8)
1313+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK GENMASK(7, 0)
1314+
1315+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK GENMASK(31, 24)
1316+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK GENMASK(23, 16)
1317+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK GENMASK(15, 8)
1318+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK GENMASK(7, 0)
1319+
1320+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK GENMASK(31, 24)
1321+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK GENMASK(23, 16)
1322+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK GENMASK(15, 8)
1323+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK GENMASK(7, 0)
1324+
1325+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK GENMASK(23, 16)
1326+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK GENMASK(15, 8)
1327+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK GENMASK(7, 0)
1328+
1329+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK GENMASK(31, 16)
1330+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK GENMASK(15, 0)
1331+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK GENMASK(31, 16)
1332+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK GENMASK(15, 0)
1333+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK GENMASK(31, 16)
1334+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK GENMASK(15, 0)
1335+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK GENMASK(31, 16)
1336+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK GENMASK(15, 0)
1337+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK GENMASK(31, 16)
1338+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK GENMASK(15, 0)
1339+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK GENMASK(31, 16)
1340+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK GENMASK(15, 0)
1341+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK GENMASK(31, 16)
1342+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK GENMASK(15, 0)
1343+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK GENMASK(31, 16)
1344+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK GENMASK(15, 0)
1345+
1346+/* mt7915 host DMA*/
1347+#define MT_DBG_INT_DMA1_R0_DONE BIT(0)
1348+#define MT_DBG_INT_DMA1_R1_DONE BIT(1)
1349+#define MT_DBG_INT_DMA1_R2_DONE BIT(2)
1350+
1351+#define MT_DBG_INT_DMA1_T16_DONE BIT(26)
1352+#define MT_DBG_INT_DMA1_T17_DONE BIT(27)
1353+#define MT_DBG_INT_DMA1_T18_DONE BIT(30)
1354+#define MT_DBG_INT_DMA1_T19_DONE BIT(31)
1355+#define MT_DBG_INT_DMA1_T20_DONE BIT(15)
1356+
1357+#define MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE BIT(16)
1358+#define MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE BIT(17)
1359+
1360+/* mt7986 host DMA */
1361+#define MT_DBG_INT_DMA0_R0_DONE BIT(0)
1362+#define MT_DBG_INT_DMA0_R1_DONE BIT(1)
1363+#define MT_DBG_INT_DMA0_R2_DONE BIT(2)
1364+#define MT_DBG_INT_DMA0_R3_DONE BIT(3)
1365+#define MT_DBG_INT_DMA0_R4_DONE BIT(22)
1366+#define MT_DBG_INT_DMA0_R5_DONE BIT(23)
1367+
1368+#define MT_DBG_INT_DMA0_T16_DONE BIT(26)
1369+#define MT_DBG_INT_DMA0_T17_DONE BIT(27)
1370+#define MT_DBG_INT_DMA0_T18_DONE BIT(30)
1371+#define MT_DBG_INT_DMA0_T19_DONE BIT(31)
1372+#define MT_DBG_INT_DMA0_T20_DONE BIT(25)
1373+
1374+/* MCU DMA */
1375+#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
1376+#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
1377+#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
1378+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
1379+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1380+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1381+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1382+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1383+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1384+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1385+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1386+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1387+
1388+#define WF_WFDMA_MCU_DMA1_BASE 0x55000000
1389+#define WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x200) // 0200
1390+#define WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0X204) // 0204
1391+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x208) // 0208
1392+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1393+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1394+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1395+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1396+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1397+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1398+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1399+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1400+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x300) // 0300
1401+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x310) // 0310
1402+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x320) // 0320
1403+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x500) // 0500
1404+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x510) // 0510
1405+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x520) // 0520
1406+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x530) // 0530
1407+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x540) // 0540
1408+
1409+#define WF_WFDMA_MCU_DMA1_PCIE1_BASE 0x59000000
1410+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x200) // 0200
1411+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0X204) // 0204
1412+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x208) // 0208
1413+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1414+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1415+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1416+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1417+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1418+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1419+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1420+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1421+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x320) // 0320
1422+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x530) // 0530
1423+
1424+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
1425+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
1426+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
1427+/* mt7986 add */
1428+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330
1429+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340
1430+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350
1431+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360
1432+
1433+
1434+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
1435+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
1436+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
1437+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
1438+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
1439+
1440+/* mt7986 add */
1441+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550
1442+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560
1443+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570
1444+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580
1445+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590
1446+
1447+/* MEM DMA */
1448+#define WF_WFDMA_MEM_DMA_BASE 0x58000000
1449+#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
1450+#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
1451+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
1452+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1453+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1454+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1455+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1456+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1457+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1458+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1459+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1460+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
1461+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
1462+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
1463+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
1464+
1465+enum resource_attr {
1466+ HIF_TX_DATA,
1467+ HIF_TX_CMD,
1468+ HIF_TX_CMD_WM, /* direct path to WMCPU, only exist for WFDMA arch with 2 CPU */
1469+ HIF_TX_FWDL,
1470+ HIF_RX_DATA,
1471+ HIF_RX_EVENT,
1472+ RING_ATTR_NUM
1473+};
1474+
1475+struct hif_pci_tx_ring_desc {
1476+ u32 hw_int_mask;
1477+ u16 ring_size;
1478+ enum resource_attr ring_attr;
1479+ u8 band_idx;
1480+ char *const ring_info;
1481+};
1482+
1483+struct hif_pci_rx_ring_desc {
1484+ u32 hw_desc_base;
1485+ u32 hw_int_mask;
1486+ u16 ring_size;
1487+ enum resource_attr ring_attr;
1488+ u16 max_rx_process_cnt;
1489+ u16 max_sw_read_idx_inc;
1490+ char *const ring_info;
developer79a21a22023-01-09 13:57:39 +08001491+ bool flags;
developer3fa816c2022-04-19 10:21:20 +08001492+};
1493+
1494+const struct hif_pci_tx_ring_desc mt7915_tx_ring_layout[] = {
1495+ {
1496+ .hw_int_mask = MT_DBG_INT_DMA1_T16_DONE,
1497+ .ring_size = 128,
1498+ .ring_attr = HIF_TX_FWDL,
1499+ .ring_info = "FWDL"
1500+ },
1501+ {
1502+ .hw_int_mask = MT_DBG_INT_DMA1_T17_DONE,
1503+ .ring_size = 256,
1504+ .ring_attr = HIF_TX_CMD_WM,
1505+ .ring_info = "cmd to WM"
1506+ },
1507+ {
1508+ .hw_int_mask = MT_DBG_INT_DMA1_T18_DONE,
1509+ .ring_size = 2048,
1510+ .ring_attr = HIF_TX_DATA,
1511+ .ring_info = "band0 TXD"
1512+ },
1513+ {
1514+ .hw_int_mask = MT_DBG_INT_DMA1_T19_DONE,
1515+ .ring_size = 2048,
1516+ .ring_attr = HIF_TX_DATA,
1517+ .ring_info = "band1 TXD"
1518+ },
1519+ {
1520+ .hw_int_mask = MT_DBG_INT_DMA1_T20_DONE,
1521+ .ring_size = 256,
1522+ .ring_attr = HIF_TX_CMD,
1523+ .ring_info = "cmd to WA"
1524+ }
1525+};
1526+
1527+const struct hif_pci_rx_ring_desc mt7915_rx_ring_layout[] = {
1528+ {
1529+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE,
1530+ .ring_size = 1536,
1531+ .ring_attr = HIF_RX_DATA,
1532+ .ring_info = "band0 RX data"
1533+ },
1534+ {
1535+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE,
1536+ .ring_size = 1536,
1537+ .ring_attr = HIF_RX_DATA,
1538+ .ring_info = "band1 RX data"
1539+ },
1540+ {
1541+ .hw_int_mask = MT_DBG_INT_DMA1_R0_DONE,
1542+ .ring_size = 512,
1543+ .ring_attr = HIF_RX_EVENT,
1544+ .ring_info = "event from WM"
1545+ },
1546+ {
1547+ .hw_int_mask = MT_DBG_INT_DMA1_R1_DONE,
1548+ .ring_size = 1024,
1549+ .ring_attr = HIF_RX_EVENT,
developer79a21a22023-01-09 13:57:39 +08001550+ .ring_info = "event from WA band0",
1551+ .flags = true
developer3fa816c2022-04-19 10:21:20 +08001552+ },
1553+ {
1554+ .hw_int_mask = MT_DBG_INT_DMA1_R2_DONE,
1555+ .ring_size = 512,
1556+ .ring_attr = HIF_RX_EVENT,
1557+ .ring_info = "event from WA band1"
1558+ }
1559+};
1560+
1561+const struct hif_pci_tx_ring_desc mt7986_tx_ring_layout[] = {
1562+ {
1563+ .hw_int_mask = MT_DBG_INT_DMA0_T16_DONE,
1564+ .ring_size = 128,
1565+ .ring_attr = HIF_TX_FWDL,
1566+ .ring_info = "FWDL"
1567+ },
1568+ {
1569+ .hw_int_mask = MT_DBG_INT_DMA0_T17_DONE,
1570+ .ring_size = 256,
1571+ .ring_attr = HIF_TX_CMD_WM,
1572+ .ring_info = "cmd to WM"
1573+ },
1574+ {
1575+ .hw_int_mask = MT_DBG_INT_DMA0_T18_DONE,
1576+ .ring_size = 2048,
1577+ .ring_attr = HIF_TX_DATA,
1578+ .ring_info = "band0 TXD"
1579+ },
1580+ {
1581+ .hw_int_mask = MT_DBG_INT_DMA0_T19_DONE,
1582+ .ring_size = 2048,
1583+ .ring_attr = HIF_TX_DATA,
1584+ .ring_info = "band1 TXD"
1585+ },
1586+ {
1587+ .hw_int_mask = MT_DBG_INT_DMA0_T20_DONE,
1588+ .ring_size = 256,
1589+ .ring_attr = HIF_TX_CMD,
1590+ .ring_info = "cmd to WA"
1591+ }
1592+};
1593+
1594+const struct hif_pci_rx_ring_desc mt7986_rx_ring_layout[] = {
1595+ {
1596+ .hw_int_mask = MT_DBG_INT_DMA0_R4_DONE,
1597+ .ring_size = 1536,
1598+ .ring_attr = HIF_RX_DATA,
1599+ .ring_info = "band0 RX data"
1600+ },
1601+ {
1602+ .hw_int_mask = MT_DBG_INT_DMA0_R5_DONE,
1603+ .ring_size = 1536,
1604+ .ring_attr = HIF_RX_DATA,
1605+ .ring_info = "band1 RX data"
1606+ },
1607+ {
1608+ .hw_int_mask = MT_DBG_INT_DMA0_R0_DONE,
1609+ .ring_size = 512,
1610+ .ring_attr = HIF_RX_EVENT,
1611+ .ring_info = "event from WM"
1612+ },
1613+ {
1614+ .hw_int_mask = MT_DBG_INT_DMA0_R1_DONE,
1615+ .ring_size = 512,
1616+ .ring_attr = HIF_RX_EVENT,
1617+ .ring_info = "event from WA"
1618+ },
1619+ {
1620+ .hw_int_mask = MT_DBG_INT_DMA0_R2_DONE,
1621+ .ring_size = 1024,
1622+ .ring_attr = HIF_RX_EVENT,
developer79a21a22023-01-09 13:57:39 +08001623+ .ring_info = "STS WA band0",
1624+ .flags = true
developer3fa816c2022-04-19 10:21:20 +08001625+ },
1626+ {
1627+ .hw_int_mask = MT_DBG_INT_DMA0_R3_DONE,
1628+ .ring_size = 512,
1629+ .ring_attr = HIF_RX_EVENT,
1630+ .ring_info = "STS WA band1"
1631+ },
1632+};
1633+
1634+/* mibinfo related CRs. */
1635+#define BN0_WF_MIB_TOP_BASE 0x820ed000
1636+#define BN1_WF_MIB_TOP_BASE 0x820fd000
1637+
1638+#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400
1639+#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x428) // D428
1640+#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x4F0) // D4F0
1641+
1642+#define BN0_WF_MIB_TOP_BSDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x688) // D688
1643+#define BN0_WF_MIB_TOP_BSDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x690) // D690
1644+
1645+#define BN0_WF_MIB_TOP_BSDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x518) // D518
1646+#define BN0_WF_MIB_TOP_BSDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x520) // D520
1647+#define BN0_WF_MIB_TOP_BSDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x528) // D528
1648+#define BN0_WF_MIB_TOP_BSDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x530) // D530
1649+#define BN0_WF_MIB_TOP_BSDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x538) // D538
1650+
1651+#define BN0_WF_MIB_TOP_BROCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5B8) // D5B8
1652+#define BN0_WF_MIB_TOP_BRBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0
1653+#define BN0_WF_MIB_TOP_BRDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x630) // D630
1654+
1655+#define BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK 0x0000FFFF // BEACONTXCOUNT[15..0]
1656+
1657+#define BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK 0x0000FFFF // RX_FIFO_FULL_COUNT[15..0]
1658+
1659+#define BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
1660+
1661+#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
1662+
1663+#define BN1_WF_MIB_TOP_BTOCR_ADDR (BN1_WF_MIB_TOP_BASE + 0x400) // D400
1664+
1665+#define BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK 0x0000FFFF // VEC_MISS_COUNT[15..0]
1666+#define BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK 0x0000FFFF // DELIMITER_FAIL_COUNT[15..0]
1667+#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
1668+
1669+#define BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK 0x0000FFFF // RX_LEN_MISMATCH[15..0]
1670+
1671+#define BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK 0x00FFFFFF // P_CCA_TIME[23..0]
1672+#define BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK 0x00FFFFFF // S_CCA_TIME[23..0]
1673+#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
1674+#define BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK 0x00FFFFFF // CCK_MDRDY_TIME[23..0]
1675+#define BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[23..0]
1676+#define BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_GREEN_MDRDY_TIME[23..0]
1677+
1678+#define BN0_WF_MIB_TOP_M0SDR22_ADDR (BN0_WF_MIB_TOP_BASE + 0x60) // D060
1679+#define BN0_WF_MIB_TOP_M0SDR23_ADDR (BN0_WF_MIB_TOP_BASE + 0x64) // D064
1680+
1681+#define BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK 0x0000FFFF // MUBF_TX_COUNT[15..0]
1682+
1683+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK 0xFFFF0000 // TX_40MHZ_CNT[31..16]
1684+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT 16
1685+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK 0x0000FFFF // TX_20MHZ_CNT[15..0]
1686+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_SHFT 0
1687+
1688+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK 0xFFFF0000 // TX_160MHZ_CNT[31..16]
1689+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT 16
1690+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK 0x0000FFFF // TX_80MHZ_CNT[15..0]
1691+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_SHFT 0
1692+
1693+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG2_CNT[31..16]
1694+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT 16
1695+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG1_CNT[15..0]
1696+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_SHFT 0
1697+
1698+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG4_CNT[31..16]
1699+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT 16
1700+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG3_CNT[15..0]
1701+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_SHFT 0
1702+
1703+#define BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK 0x0000FFFF // MU_FAIL_PPDU_CNT[15..0]
1704+
1705+#define BN0_WF_MIB_TOP_M0B0SDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x100) // D100
1706+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK 0xFFFF0000 // RTSRETRYCOUNT[31..16]
1707+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT 16
1708+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK 0x0000FFFF // RTSTXCOUNT[15..0]
1709+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_SHFT 0
1710+#define BN0_WF_MIB_TOP_M0B0SDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x104) // D104
1711+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK 0xFFFF0000 // ACKFAILCOUNT[31..16]
1712+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT 16
1713+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK 0x0000FFFF // BAMISSCOUNT[15..0]
1714+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_SHFT 0
1715+#define BN0_WF_MIB_TOP_M0B0SDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x108) // D108
1716+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK 0xFFFF0000 // FRAMERETRY2COUNT[31..16]
1717+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT 16
1718+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK 0x0000FFFF // FRAMERETRYCOUNT[15..0]
1719+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_SHFT 0
1720+#define BN0_WF_MIB_TOP_M0B0SDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x10C) // D10C
1721+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK 0x0000FFFF // FRAMERETRY3COUNT[15..0]
1722+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_SHFT 0
1723+#define BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG0_CNT[15..0]
1724+
1725+
1726+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK 0xFFFF0000 // TX_OK_COUNT2np1[31..16]
1727+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT 16
1728+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK 0x0000FFFF // TX_OK_COUNT2n[15..0]
1729+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT 0
1730+
1731+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK 0xFFFF0000 // TX_DATA_COUNT2np1[31..16]
1732+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT 16
1733+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK 0x0000FFFF // TX_DATA_COUNT2n[15..0]
1734+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT 0
1735+
1736+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK 0xFFFF0000 // RX_OK_COUNT2np1[31..16]
1737+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT 16
1738+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK 0x0000FFFF // RX_OK_COUNT2n[15..0]
1739+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT 0
1740+
1741+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK 0xFFFF0000 // RX_DATA_COUNT2np1[31..16]
1742+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT 16
1743+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK 0x0000FFFF // RX_DATA_COUNT2n[15..0]
1744+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT 0
1745+
1746+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK 0xFFFF0000 // RTSTXCOUNT2np1[31..16]
1747+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT 16
1748+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK 0x0000FFFF // RTSTXCOUNT2n[15..0]
1749+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT 0
1750+
1751+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK 0xFFFF0000 // RTSRETRYCOUNT2np1[31..16]
1752+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT 16
1753+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK 0x0000FFFF // RTSRETRYCOUNT2n[15..0]
1754+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT 0
1755+
1756+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK 0xFFFF0000 // BAMISSCOUNT2np1[31..16]
1757+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT 16
1758+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK 0x0000FFFF // BAMISSCOUNT2n[15..0]
1759+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT 0
1760+
1761+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK 0xFFFF0000 // ACKFAILCOUNT2np1[31..16]
1762+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT 16
1763+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK 0x0000FFFF // ACKFAILCOUNT2n[15..0]
1764+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT 0
1765+
1766+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK 0xFFFF0000 // FRAMERETRYCOUNT2np1[31..16]
1767+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT 16
1768+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK 0x0000FFFF // FRAMERETRYCOUNT2n[15..0]
1769+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT 0
1770+
1771+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY2COUNT2np1[31..16]
1772+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT 16
1773+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK 0x0000FFFF // FRAMERETRY2COUNT2n[15..0]
1774+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT 0
1775+
1776+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY3COUNT2np1[31..16]
1777+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT 16
1778+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK 0x0000FFFF // FRAMERETRY3COUNT2n[15..0]
1779+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT 0
1780+/* TXD */
1781+
1782+#define MT_TXD1_ETYP BIT(15)
1783+#define MT_TXD1_VLAN BIT(14)
1784+#define MT_TXD1_RMVL BIT(13)
1785+#define MT_TXD1_AMS BIT(13)
1786+#define MT_TXD1_EOSP BIT(12)
1787+#define MT_TXD1_MRD BIT(11)
1788+
1789+#define MT_TXD7_CTXD BIT(26)
1790+#define MT_TXD7_CTXD_CNT GENMASK(25, 23)
1791+#define MT_TXD7_TAT GENMASK(9, 0)
1792+
1793+#endif
1794+#endif
1795diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c
1796new file mode 100644
developerf3f5d9b2023-02-07 15:24:34 +08001797index 00000000..4fb845b0
developer3fa816c2022-04-19 10:21:20 +08001798--- /dev/null
1799+++ b/mt7915/mtk_debugfs.c
developer79a21a22023-01-09 13:57:39 +08001800@@ -0,0 +1,3003 @@
developer3fa816c2022-04-19 10:21:20 +08001801+#include<linux/inet.h>
1802+#include "mt7915.h"
1803+#include "mt7915_debug.h"
1804+#include "mac.h"
1805+#include "mcu.h"
1806+
1807+#ifdef MTK_DEBUG
1808+#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
1809+#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
1810+#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \
1811+ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
1812+ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
1813+
1814+#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
1815+#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
1816+#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1817+ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
1818+ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
1819+
1820+#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
1821+#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
1822+#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1823+ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
1824+ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
1825+
1826+enum mt7915_wtbl_type {
1827+ WTBL_TYPE_LMAC, /* WTBL in LMAC */
1828+ WTBL_TYPE_UMAC, /* WTBL in UMAC */
1829+ WTBL_TYPE_KEY, /* Key Table */
1830+ MAX_NUM_WTBL_TYPE
1831+};
1832+
1833+static int mt7915_wtbl_read_raw(struct mt7915_dev *dev, u16 idx,
1834+ enum mt7915_wtbl_type type, u16 start_dw,
1835+ u16 len, void *buf)
1836+{
1837+ u32 *dest_cpy = (u32 *)buf;
1838+ u32 size_dw = len;
1839+ u32 src = 0;
1840+
1841+ if (!buf)
1842+ return 0xFF;
1843+
1844+ if (type == WTBL_TYPE_LMAC) {
1845+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1846+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1847+ src = LWTBL_IDX2BASE(idx, start_dw);
1848+ } else if (type == WTBL_TYPE_UMAC) {
1849+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1850+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1851+ src = UWTBL_IDX2BASE(idx, start_dw);
1852+ } else if (type == WTBL_TYPE_KEY) {
1853+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1854+ MT_UWTBL_TOP_WDUCR_TARGET |
1855+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1856+ src = KEYTBL_IDX2BASE(idx, start_dw);
1857+ }
1858+
1859+ while (size_dw--) {
1860+ *dest_cpy++ = mt76_rr(dev, src);
1861+ src += 4;
1862+ };
1863+
1864+ return 0;
1865+}
1866+
1867+static int mt7915_wtbl_write_raw(struct mt7915_dev *dev, u16 idx,
1868+ enum mt7915_wtbl_type type, u16 start_dw,
1869+ u32 val)
1870+{
1871+ u32 addr = 0;
1872+
1873+ if (type == WTBL_TYPE_LMAC) {
1874+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1875+ FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1876+ addr = LWTBL_IDX2BASE(idx, start_dw);
1877+ } else if (type == WTBL_TYPE_UMAC) {
1878+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1879+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1880+ addr = UWTBL_IDX2BASE(idx, start_dw);
1881+ } else if (type == WTBL_TYPE_KEY) {
1882+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1883+ MT_UWTBL_TOP_WDUCR_TARGET |
1884+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1885+ addr = KEYTBL_IDX2BASE(idx, start_dw);
1886+ }
1887+
1888+ mt76_wr(dev, addr, val);
1889+
1890+ return 0;
1891+}
1892+
1893+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len)
1894+{
1895+ struct bin_debug_hdr *hdr;
1896+ char *buf;
1897+
1898+ if (len > 1500 - sizeof(*hdr))
1899+ len = 1500 - sizeof(*hdr);
1900+
1901+ buf = kzalloc(sizeof(*hdr) + len, GFP_KERNEL);
1902+ if (!buf)
1903+ return;
1904+
1905+ hdr = (struct bin_debug_hdr *)buf;
1906+ hdr->magic_num = cpu_to_le32(PKT_BIN_DEBUG_MAGIC);
1907+ hdr->serial_id = cpu_to_le16(dev->dbg.fwlog_seq++);
1908+ hdr->msg_type = cpu_to_le16(type);
1909+ hdr->len = cpu_to_le16(len);
1910+ hdr->des_len = cpu_to_le16(des_len);
1911+
1912+ memcpy(buf + sizeof(*hdr), data, len);
1913+
1914+ mt7915_debugfs_rx_log(dev, buf, sizeof(*hdr) + len);
1915+}
1916+
1917+static int
1918+mt7915_fw_debug_module_set(void *data, u64 module)
1919+{
1920+ struct mt7915_dev *dev = data;
1921+
1922+ dev->dbg.fw_dbg_module = module;
1923+ return 0;
1924+}
1925+
1926+static int
1927+mt7915_fw_debug_module_get(void *data, u64 *module)
1928+{
1929+ struct mt7915_dev *dev = data;
1930+
1931+ *module = dev->dbg.fw_dbg_module;
1932+ return 0;
1933+}
1934+
1935+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, mt7915_fw_debug_module_get,
1936+ mt7915_fw_debug_module_set, "%lld\n");
1937+
1938+static int
1939+mt7915_fw_debug_level_set(void *data, u64 level)
1940+{
1941+ struct mt7915_dev *dev = data;
1942+
1943+ dev->dbg.fw_dbg_lv = level;
1944+ mt7915_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv);
1945+ return 0;
1946+}
1947+
1948+static int
1949+mt7915_fw_debug_level_get(void *data, u64 *level)
1950+{
1951+ struct mt7915_dev *dev = data;
1952+
1953+ *level = dev->dbg.fw_dbg_lv;
1954+ return 0;
1955+}
1956+
1957+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, mt7915_fw_debug_level_get,
1958+ mt7915_fw_debug_level_set, "%lld\n");
1959+
1960+#define MAX_TX_MODE 12
1961+static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT",
1962+ "N/A", "N/A", "N/A", "HE_SU", "HE_EXT_SU",
1963+ "HE_TRIG", "HE_MU", "N/A"};
1964+static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong",
1965+ "N/A", "2Mshort", "5.5Mshort", "11Mshort",
1966+ "N/A"};
1967+static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M",
1968+ "48M", "54M", "N/A"};
1969+static char *fcap_str[] = {"20MHz", "20/40MHz", "20/40/80MHz",
1970+ "20/40/80/160/80+80MHz"};
1971+
1972+static char *hw_rate_ofdm_str(u16 ofdm_idx)
1973+{
1974+ switch (ofdm_idx) {
1975+ case 11: /* 6M */
1976+ return HW_TX_RATE_OFDM_STR[0];
1977+
1978+ case 15: /* 9M */
1979+ return HW_TX_RATE_OFDM_STR[1];
1980+
1981+ case 10: /* 12M */
1982+ return HW_TX_RATE_OFDM_STR[2];
1983+
1984+ case 14: /* 18M */
1985+ return HW_TX_RATE_OFDM_STR[3];
1986+
1987+ case 9: /* 24M */
1988+ return HW_TX_RATE_OFDM_STR[4];
1989+
1990+ case 13: /* 36M */
1991+ return HW_TX_RATE_OFDM_STR[5];
1992+
1993+ case 8: /* 48M */
1994+ return HW_TX_RATE_OFDM_STR[6];
1995+
1996+ case 12: /* 54M */
1997+ return HW_TX_RATE_OFDM_STR[7];
1998+
1999+ default:
2000+ return HW_TX_RATE_OFDM_STR[8];
2001+ }
2002+}
2003+
2004+static char *hw_rate_str(u8 mode, u16 rate_idx)
2005+{
2006+ if (mode == 0)
2007+ return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8];
2008+ else if (mode == 1)
2009+ return hw_rate_ofdm_str(rate_idx);
2010+ else
2011+ return "MCS";
2012+}
2013+
2014+static void parse_rate(struct seq_file *s, u16 rate_idx, u16 txrate)
2015+{
2016+ u16 txmode, mcs, nss, stbc;
2017+
2018+ txmode = FIELD_GET(GENMASK(9, 6), txrate);
2019+ mcs = FIELD_GET(GENMASK(5, 0), txrate);
2020+ nss = FIELD_GET(GENMASK(12, 10), txrate);
2021+ stbc = FIELD_GET(BIT(13), txrate);
2022+
2023+ seq_printf(s, "\tRate%d(0x%x):TxMode=%d(%s), TxRate=%d(%s), Nsts=%d, STBC=%d\n",
2024+ rate_idx + 1, txrate,
2025+ txmode, (txmode < MAX_TX_MODE ? HW_TX_MODE_STR[txmode] : HW_TX_MODE_STR[MAX_TX_MODE]),
2026+ mcs, hw_rate_str(txmode, mcs), nss, stbc);
2027+}
2028+
2029+#define LWTBL_LEN_IN_DW 32
2030+#define UWTBL_LEN_IN_DW 8
2031+#define ONE_KEY_ENTRY_LEN_IN_DW 8
developerf32dabf2022-06-01 10:59:24 +08002032+static int mt7915_sta_info(struct seq_file *s, void *data)
2033+{
2034+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2035+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
2036+ u16 i = 0;
2037+
2038+ for (i=0; i < mt7915_wtbl_size(dev); i++) {
2039+ mt7915_wtbl_read_raw(dev, i, WTBL_TYPE_LMAC, 0,
2040+ LWTBL_LEN_IN_DW, lwtbl);
2041+ if (lwtbl[4] || lwtbl[5] || lwtbl[6] || lwtbl[7] || lwtbl[0] || lwtbl[1])
2042+ seq_printf(s, "wcid:%d\tAddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
2043+ i, lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
2044+ }
2045+
2046+ return 0;
2047+}
2048+
developer3fa816c2022-04-19 10:21:20 +08002049+static int mt7915_wtbl_read(struct seq_file *s, void *data)
2050+{
2051+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2052+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
2053+ int x;
2054+ u32 *addr = 0;
2055+ u32 dw_value = 0;
2056+
2057+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_LMAC, 0,
2058+ LWTBL_LEN_IN_DW, lwtbl);
2059+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
2060+ seq_printf(s, "LMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2061+ MT_DBG_WTBLON_TOP_WDUCR,
2062+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2063+ LWTBL_IDX2BASE(dev->wlan_idx, 0));
2064+ for (x = 0; x < LWTBL_LEN_IN_DW; x++) {
2065+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2066+ x,
2067+ lwtbl[x * 4 + 3],
2068+ lwtbl[x * 4 + 2],
2069+ lwtbl[x * 4 + 1],
2070+ lwtbl[x * 4]);
2071+ }
2072+
2073+ seq_printf(s, "\n\tAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
2074+ lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
2075+
2076+ // DW0, DW1
2077+ seq_printf(s, "LWTBL DW 0/1\n\t");
2078+ addr = (u32 *)&(lwtbl[0]);
2079+ dw_value = *addr;
2080+ seq_printf(s, "MUAR_IDX:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
2081+ seq_printf(s, "RCA1:%ld/ ", FIELD_GET(BIT(22), dw_value));
2082+ seq_printf(s, "KID:%lu/ ", FIELD_GET(GENMASK(24, 23), dw_value));
2083+ seq_printf(s, "RCID:%ld/ ", FIELD_GET(BIT(25), dw_value));
2084+ seq_printf(s, "FROM_DS:%ld\n\t", FIELD_GET(BIT(26), dw_value));
2085+ seq_printf(s, "TO_DS:%ld/ ", FIELD_GET(BIT(27), dw_value));
2086+ seq_printf(s, "RV:%ld/ ", FIELD_GET(BIT(28), dw_value));
2087+ seq_printf(s, "RCA2:%ld/ ", FIELD_GET(BIT(29), dw_value));
2088+ seq_printf(s, "WPI_FLAG:%ld\n", FIELD_GET(BIT(30), dw_value));
2089+
2090+ // DW2
2091+ seq_printf(s, "LWTBL DW 2\n\t");
2092+ addr = (u32 *)&(lwtbl[2*4]);
2093+ dw_value = *addr;
2094+ seq_printf(s, "AID12:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
2095+ seq_printf(s, "SU:%ld/ ", FIELD_GET(BIT(12), dw_value));
2096+ seq_printf(s, "SPP_EN:%ld/ ", FIELD_GET(BIT(13), dw_value));
2097+ seq_printf(s, "WPI_EVEN:%ld\n\t",FIELD_GET(BIT(14), dw_value));
2098+ seq_printf(s, "CIPHER:%lu/ ", FIELD_GET(GENMASK(20, 16), dw_value));
2099+ seq_printf(s, "CIPHER_IGTK:%lu/ ",FIELD_GET(GENMASK(22, 21), dw_value));
2100+ seq_printf(s, "AAD_OM:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2101+ seq_printf(s, "SW:%ld/ ", FIELD_GET(BIT(24), dw_value));
2102+ seq_printf(s, "UL:%ld/ ", FIELD_GET(BIT(25), dw_value));
2103+ seq_printf(s, "TX_POWER_SAVE:%ld\n\t", FIELD_GET(BIT(26), dw_value));
2104+ seq_printf(s, "QOS:%ld/ ", FIELD_GET(BIT(27), dw_value));
2105+ seq_printf(s, "HT:%ld/ ", FIELD_GET(BIT(28), dw_value));
2106+ seq_printf(s, "VHT:%ld/ ", FIELD_GET(BIT(29), dw_value));
2107+ seq_printf(s, "HE:%ld/ ", FIELD_GET(BIT(30), dw_value));
2108+ seq_printf(s, "MESH:%ld\n", FIELD_GET(BIT(31), dw_value));
2109+
2110+ // DW3
2111+ seq_printf(s, "LWTBL DW 3\n\t");
2112+ addr = (u32 *)&(lwtbl[3*4]);
2113+ dw_value = *addr;
2114+ seq_printf(s, "WMM_Q:%lu/ ", FIELD_GET(GENMASK(1, 0), dw_value));
2115+ seq_printf(s, "RXD_DUP_MODE:%lu\n\t", FIELD_GET(GENMASK(3, 2), dw_value));
2116+ seq_printf(s, "VLAN2ETH:%ld/ ", FIELD_GET(BIT(4), dw_value));
2117+ seq_printf(s, "BEAM_CHG:%ld/ ", FIELD_GET(BIT(5), dw_value));
2118+ seq_printf(s, "DIS_BA256:%ld\n\t", FIELD_GET(BIT(6), dw_value));
2119+ seq_printf(s, "PFMU_IDX:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2120+ seq_printf(s, "ULPF_IDX:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
2121+ seq_printf(s, "RIBF:%ld/ ", FIELD_GET(BIT(24), dw_value));
2122+ seq_printf(s, "ULPF:%ld\n\t", FIELD_GET(BIT(25), dw_value));
2123+ seq_printf(s, "IGN_FBK:%ld/ ", FIELD_GET(BIT(26), dw_value));
2124+ seq_printf(s, "TBF:%ld/ ", FIELD_GET(BIT(29), dw_value));
2125+ seq_printf(s, "TBF_VHT:%ld/ ", FIELD_GET(BIT(30), dw_value));
2126+ seq_printf(s, "TBF_HE:%ld\n", FIELD_GET(BIT(31), dw_value));
2127+
2128+ // DW4
2129+ seq_printf(s, "LWTBL DW 4\n\t");
2130+ addr = (u32 *)&(lwtbl[4*4]);
2131+ dw_value = *addr;
2132+ seq_printf(s, "ANT_ID_STS0:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2133+ seq_printf(s, "STS1:%lu/ ", FIELD_GET(GENMASK(5, 3), dw_value));
2134+ seq_printf(s, "STS2:%lu/ ", FIELD_GET(GENMASK(8, 6), dw_value));
2135+ seq_printf(s, "STS3:%lu\n\t", FIELD_GET(GENMASK(11, 9), dw_value));
2136+ seq_printf(s, "ANT_ID_STS4:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
2137+ seq_printf(s, "STS5:%lu/ ", FIELD_GET(GENMASK(17, 15), dw_value));
2138+ seq_printf(s, "STS6:%ld/ ", FIELD_GET(GENMASK(20, 18), dw_value));
2139+ seq_printf(s, "STS7:%lu\n\t", FIELD_GET(GENMASK(23, 21), dw_value));
2140+ seq_printf(s, "CASCAD:%ld/ ", FIELD_GET(BIT(24), dw_value));
2141+ seq_printf(s, "LDPC_HT:%ld/ ", FIELD_GET(BIT(25), dw_value));
2142+ seq_printf(s, "LDPC_VHT:%ld/ ", FIELD_GET(BIT(26), dw_value));
2143+ seq_printf(s, "LDPC_HE:%ld\n\t", FIELD_GET(BIT(27), dw_value));
2144+ seq_printf(s, "DIS_RHTR:%ld/ ", FIELD_GET(BIT(28), dw_value));
2145+ seq_printf(s, "ALL_ACK:%ld/ ", FIELD_GET(BIT(29), dw_value));
2146+ seq_printf(s, "DROP:%ld/ ", FIELD_GET(BIT(30), dw_value));
2147+ seq_printf(s, "ACK_EN:%ld\n", FIELD_GET(BIT(31), dw_value));
2148+
2149+ // DW5
2150+ seq_printf(s, "LWTBL DW 5\n\t");
2151+ addr = (u32 *)&(lwtbl[5*4]);
2152+ dw_value = *addr;
2153+ seq_printf(s, "AF:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2154+ seq_printf(s, "AF_HE:%lu/ ", FIELD_GET(GENMASK(4, 3), dw_value));
2155+ seq_printf(s, "RTS:%ld/ ", FIELD_GET(BIT(5), dw_value));
2156+ seq_printf(s, "SMPS:%ld/ ", FIELD_GET(BIT(6), dw_value));
2157+ seq_printf(s, "DYN_BW:%ld\n\t", FIELD_GET(BIT(7), dw_value));
2158+ seq_printf(s, "MMSS:%lu/ ", FIELD_GET(GENMASK(10, 8), dw_value));
2159+ seq_printf(s, "USR:%ld/ ", FIELD_GET(BIT(11), dw_value));
2160+ seq_printf(s, "SR_RATE:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
2161+ seq_printf(s, "SR_ABORT:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2162+ seq_printf(s, "TX_POWER_OFFSET:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
2163+ seq_printf(s, "WTBL_MPDU_SIZE:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
2164+ seq_printf(s, "PE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
2165+ seq_printf(s, "DOPPL:%ld/ ", FIELD_GET(BIT(26), dw_value));
2166+ seq_printf(s, "TXOP_PS_CAP:%ld/ ", FIELD_GET(BIT(27), dw_value));
2167+ seq_printf(s, "DONOT_UPDATE_I_PSM:%ld\n\t", FIELD_GET(BIT(28), dw_value));
2168+ seq_printf(s, "I_PSM:%ld/ ", FIELD_GET(BIT(29), dw_value));
2169+ seq_printf(s, "PSM:%ld/ ", FIELD_GET(BIT(30), dw_value));
2170+ seq_printf(s, "SKIP_TX:%ld\n", FIELD_GET(BIT(31), dw_value));
2171+
2172+ // DW6
2173+ seq_printf(s, "LWTBL DW 6\n\t");
2174+ seq_printf(s, "TID 0/1/2/3/4/5/6/7 BA_WIN_SIZE:");
2175+ addr = (u32 *)&(lwtbl[6*4]);
2176+ dw_value = *addr;
2177+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(3, 0), dw_value));
2178+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(7, 4), dw_value));
2179+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(11, 8), dw_value));
2180+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(15, 12), dw_value));
2181+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(19, 16), dw_value));
2182+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(23, 20), dw_value));
2183+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(27, 24), dw_value));
2184+ seq_printf(s, "%lu\n", FIELD_GET(GENMASK(31, 28), dw_value));
2185+
2186+ // DW7
2187+ seq_printf(s, "LWTBL DW 7\n\t");
2188+ addr = (u32 *)&(lwtbl[7*4]);
2189+ dw_value = *addr;
2190+ seq_printf(s, "CBRN:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2191+ seq_printf(s, "DBNSS_EN:%ld/ ", FIELD_GET(BIT(3), dw_value));
2192+ seq_printf(s, "BAF_EN:%ld/ ", FIELD_GET(BIT(4), dw_value));
2193+ seq_printf(s, "RDGBA:%ld\n\t", FIELD_GET(BIT(5), dw_value));
2194+ seq_printf(s, "RDG:%ld/ ", FIELD_GET(BIT(6), dw_value));
2195+ seq_printf(s, "SPE_IDX:%lu/ ", FIELD_GET(GENMASK(11, 7), dw_value));
2196+ seq_printf(s, "G2:%ld/ ", FIELD_GET(BIT(12), dw_value));
2197+ seq_printf(s, "G4:%ld/ ", FIELD_GET(BIT(13), dw_value));
2198+ seq_printf(s, "G8:%ld/ ", FIELD_GET(BIT(14), dw_value));
2199+ seq_printf(s, "G16:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2200+ seq_printf(s, "G2_LTF:%lu/ ", FIELD_GET(GENMASK(17, 16), dw_value));
2201+ seq_printf(s, "G4_LTF:%lu/ ", FIELD_GET(GENMASK(19, 18), dw_value));
2202+ seq_printf(s, "G8_LTF:%lu/ ", FIELD_GET(GENMASK(21, 20), dw_value));
2203+ seq_printf(s, "G16_LTF:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
2204+ seq_printf(s, "G2_HE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
2205+ seq_printf(s, "G4_HE:%lu/ ", FIELD_GET(GENMASK(27, 27), dw_value));
2206+ seq_printf(s, "G8_HE:%lu/ ", FIELD_GET(GENMASK(29, 28), dw_value));
2207+ seq_printf(s, "G16_HE:%lu\n", FIELD_GET(GENMASK(31, 30), dw_value));
2208+
2209+ // DW8
2210+ seq_printf(s, "LWTBL DW 8\n\t");
2211+ addr = (u32 *)&(lwtbl[8*4]);
2212+ dw_value = *addr;
2213+ seq_printf(s, "FAIL_CNT_AC0:%lu/ ", FIELD_GET(GENMASK(4, 0), dw_value));
2214+ seq_printf(s, "AC1:%lu/ ", FIELD_GET(GENMASK(9, 5), dw_value));
2215+ seq_printf(s, "AC2:%lu/ ", FIELD_GET(GENMASK(14, 10), dw_value));
2216+ seq_printf(s, "AC3:%lu\n\t", FIELD_GET(GENMASK(19, 15), dw_value));
2217+ seq_printf(s, "PARTIAL_AID:%lu/ ", FIELD_GET(GENMASK(28, 20), dw_value));
2218+ seq_printf(s, "CHK_PER:%lu\n", FIELD_GET(BIT(31), dw_value));
2219+
2220+ // DW9
2221+ seq_printf(s, "LWTBL DW 9\n\t");
2222+ addr = (u32 *)&(lwtbl[9*4]);
2223+ dw_value = *addr;
2224+ seq_printf(s, "RX_AVG_MPDU:%lu/ ", FIELD_GET(GENMASK(13, 0), dw_value));
2225+ seq_printf(s, "PRITX_SW_MODE:%ld/ ", FIELD_GET(BIT(16), dw_value));
2226+ seq_printf(s, "PRITX_PLR:%ld\n\t", FIELD_GET(BIT(17), dw_value));
2227+ seq_printf(s, "PRITX_DCM:%ld/ ", FIELD_GET(BIT(18), dw_value));
2228+ seq_printf(s, "PRITX_ER160:%ld/ ", FIELD_GET(BIT(19), dw_value));
2229+ seq_printf(s, "PRITX_ERSU:%lu\n\t", FIELD_GET(BIT(20), dw_value));
2230+ seq_printf(s, "MPDU_FAIL_CNT:%lu/ ", FIELD_GET(GENMASK(25, 23), dw_value));
2231+ seq_printf(s, "MPDU_OK_CNT:%lu/ ", FIELD_GET(GENMASK(28, 26), dw_value));
2232+ seq_printf(s, "RATE_IDX:%lu\n\t", FIELD_GET(GENMASK(31, 29), dw_value));
2233+ seq_printf(s, "FCAP:%s\n", fcap_str[FIELD_GET(GENMASK(22, 21), dw_value)]);
2234+
2235+ // DW10
2236+ seq_printf(s, "LWTBL DW 10\n");
2237+ addr = (u32 *)&(lwtbl[10*4]);
2238+ dw_value = *addr;
2239+ parse_rate(s, 0, FIELD_GET(GENMASK(13, 0), dw_value));
2240+ parse_rate(s, 1, FIELD_GET(GENMASK(29, 16), dw_value));
2241+ // DW11
2242+ seq_printf(s, "LWTBL DW 11\n");
2243+ addr = (u32 *)&(lwtbl[11*4]);
2244+ dw_value = *addr;
2245+ parse_rate(s, 2, FIELD_GET(GENMASK(13, 0), dw_value));
2246+ parse_rate(s, 3, FIELD_GET(GENMASK(29, 16), dw_value));
2247+ // DW12
2248+ seq_printf(s, "LWTBL DW 12\n");
2249+ addr = (u32 *)&(lwtbl[12*4]);
2250+ dw_value = *addr;
2251+ parse_rate(s, 4, FIELD_GET(GENMASK(13, 0), dw_value));
2252+ parse_rate(s, 5, FIELD_GET(GENMASK(29, 16), dw_value));
2253+ // DW13
2254+ seq_printf(s, "LWTBL DW 13\n");
2255+ addr = (u32 *)&(lwtbl[13*4]);
2256+ dw_value = *addr;
2257+ parse_rate(s, 6, FIELD_GET(GENMASK(13, 0), dw_value));
2258+ parse_rate(s, 7, FIELD_GET(GENMASK(29, 16), dw_value));
2259+
2260+ //DW28
2261+ seq_printf(s, "LWTBL DW 28\n\t");
2262+ addr = (u32 *)&(lwtbl[28*4]);
2263+ dw_value = *addr;
2264+ seq_printf(s, "OM_INFO:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
2265+ seq_printf(s, "OM_RXD_DUP_MODE:%u\n\t", !!(dw_value & BIT(12)) );
2266+
2267+ //DW29
2268+ seq_printf(s, "LWTBL DW 29\n");
2269+ addr = (u32 *)&(lwtbl[29*4]);
2270+ dw_value = *addr;
2271+ seq_printf(s, "USER_RSSI:%lu/ ", FIELD_GET(GENMASK(8, 0), dw_value));
2272+ seq_printf(s, "USER_SNR:%lu/ ", FIELD_GET(GENMASK(14, 9), dw_value));
2273+ seq_printf(s, "RAPID_REACTION_RATE:%lu/ ", FIELD_GET(GENMASK(26, 16), dw_value));
2274+ seq_printf(s, "HT_AMSDU(Read Only):%u/ ", !!(dw_value & BIT(30)) );
2275+ seq_printf(s, "AMSDU_CROSS_LG(Read Only):%u\n\t ", !!(dw_value & BIT(31)));
2276+
2277+ //DW30
2278+ seq_printf(s, "LWTBL DW 30\n\t");
2279+ addr = (u32 *)&(lwtbl[30*4]);
2280+ dw_value = *addr;
2281+ seq_printf(s, "RCPI 0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2282+ seq_printf(s, "RCPI 1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2283+ seq_printf(s, "RCPI 2:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
2284+ seq_printf(s, "RCPI 3:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
2285+
2286+ //DW31
2287+ seq_printf(s, "LWTBL DW 31\n\t");
2288+ addr = (u32 *)&(lwtbl[31*4]);
2289+ dw_value = *addr;
2290+ seq_printf(s, "RCPI 4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2291+ seq_printf(s, "RCPI 5:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2292+ seq_printf(s, "RCPI 6:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
2293+ seq_printf(s, "RCPI 7:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
2294+
2295+ return 0;
2296+}
2297+
2298+static int mt7915_uwtbl_read(struct seq_file *s, void *data)
2299+{
2300+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2301+ u8 uwtbl[UWTBL_LEN_IN_DW * 4] = {0};
2302+ u8 keytbl[ONE_KEY_ENTRY_LEN_IN_DW*4] = {0};
2303+ int x;
2304+ u32 *addr = 0;
2305+ u32 dw_value = 0;
2306+ u32 amsdu_len = 0;
2307+ u32 u2SN = 0;
2308+ u16 keyloc0, keyloc1;
2309+
2310+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC, 0,
2311+ UWTBL_LEN_IN_DW, uwtbl);
2312+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
2313+ seq_printf(s, "UMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2314+ MT_DBG_WTBLON_TOP_WDUCR,
2315+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2316+ UWTBL_IDX2BASE(dev->wlan_idx, 0));
2317+ for (x = 0; x < UWTBL_LEN_IN_DW; x++) {
2318+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2319+ x,
2320+ uwtbl[x * 4 + 3],
2321+ uwtbl[x * 4 + 2],
2322+ uwtbl[x * 4 + 1],
2323+ uwtbl[x * 4]);
2324+ }
2325+
2326+ /* UMAC WTBL DW 0 */
2327+ seq_printf(s, "\nUWTBL PN\n\t");
2328+ addr = (u32 *)&(uwtbl[0]);
2329+ dw_value = *addr;
2330+ seq_printf(s, "PN0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2331+ seq_printf(s, "PN1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2332+ seq_printf(s, "PN2:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
2333+ seq_printf(s, "PN3:%lu/ ", FIELD_GET(GENMASK(31, 24), dw_value));
2334+
2335+ addr = (u32 *)&(uwtbl[1 * 4]);
2336+ dw_value = *addr;
2337+ seq_printf(s, "PN4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2338+ seq_printf(s, "PN5:%lu\n", FIELD_GET(GENMASK(15, 8), dw_value));
2339+
2340+ /* UMAC WTBL DW SN part */
2341+ seq_printf(s, "\nUWTBL SN\n");
2342+ addr = (u32 *)&(uwtbl[2 * 4]);
2343+ dw_value = *addr;
2344+ seq_printf(s, "TID0_AC0_SN:%lu\n", FIELD_GET(GENMASK(11, 0), dw_value));
2345+ seq_printf(s, "TID1_AC1_SN:%lu\n", FIELD_GET(GENMASK(23, 12), dw_value));
2346+
2347+ u2SN = FIELD_GET(GENMASK(31, 24), dw_value);
2348+ addr = (u32 *)&(uwtbl[3 * 4]);
2349+ dw_value = *addr;
2350+ u2SN |= FIELD_GET(GENMASK(3, 0), dw_value);
2351+ seq_printf(s, "TID2_AC2_SN:%u\n", u2SN);
2352+ seq_printf(s, "TID3_AC3_SN:%lu\n", FIELD_GET(GENMASK(15, 4), dw_value));
2353+ seq_printf(s, "TID4_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
2354+
2355+ u2SN = FIELD_GET(GENMASK(31, 28), dw_value);
2356+ addr = (u32 *)&(uwtbl[4 * 4]);
2357+ dw_value = *addr;
2358+ u2SN |= FIELD_GET(GENMASK(7, 0), dw_value);
2359+ seq_printf(s, "TID5_SN:%u\n", u2SN);
2360+ seq_printf(s, "TID6_SN:%lu\n", FIELD_GET(GENMASK(19, 8), dw_value));
2361+ seq_printf(s, "TID7_SN:%lu\n", FIELD_GET(GENMASK(31, 20), dw_value));
2362+
2363+ addr = (u32 *)&(uwtbl[1 * 4]);
2364+ dw_value = *addr;
2365+ seq_printf(s, "COM_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
2366+
2367+ /* UMAC WTBL DW 0 */
2368+ seq_printf(s, "\nUWTBL others\n");
2369+
2370+ addr = (u32 *)&(uwtbl[5 * 4]);
2371+ dw_value = *addr;
2372+ keyloc0 = FIELD_GET(GENMASK(10, 0), dw_value);
2373+ keyloc1 = FIELD_GET(GENMASK(26, 16), dw_value);
2374+ seq_printf(s, "\tKey Loc 1/2:%lu/%lu\n",
2375+ FIELD_GET(GENMASK(10, 0), dw_value),
2376+ FIELD_GET(GENMASK(26, 16), dw_value));
2377+ seq_printf(s, "\tUWTBL_QOS:%lu\n", FIELD_GET(BIT(27), dw_value));
2378+ seq_printf(s, "\tUWTBL_HT_VHT_HE:%lu\n", FIELD_GET(BIT(28), dw_value));
2379+
2380+ addr = (u32 *)&(uwtbl[6*4]);
2381+ dw_value = *addr;
2382+ seq_printf(s, "\tHW AMSDU Enable:%lu\n", FIELD_GET(BIT(9), dw_value));
2383+
2384+ amsdu_len = FIELD_GET(GENMASK(5, 0), dw_value);
2385+ if (amsdu_len == 0)
2386+ seq_printf(s, "\tHW AMSDU Len:invalid (WTBL value=0x%x)\n", amsdu_len);
2387+ else if (amsdu_len == 1)
2388+ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
2389+ 1,
2390+ 255,
2391+ amsdu_len);
2392+ else
2393+ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
2394+ 256 * (amsdu_len - 1),
2395+ 256 * (amsdu_len - 1) + 255,
2396+ amsdu_len
2397+ );
2398+ seq_printf(s, "\tHW AMSDU Num:%lu (WTBL value=0x%lx)\n",
2399+ FIELD_GET(GENMASK(8, 6), dw_value) + 1,
2400+ FIELD_GET(GENMASK(8, 6), dw_value));
2401+
2402+ /* Parse KEY link */
2403+ seq_printf(s, "\n\tkeyloc0:%d\n", keyloc0);
2404+ if(keyloc0 != GENMASK(10, 0)) {
2405+ mt7915_wtbl_read_raw(dev, keyloc0, WTBL_TYPE_KEY,
2406+ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
2407+ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2408+ MT_DBG_WTBLON_TOP_WDUCR,
2409+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2410+ KEYTBL_IDX2BASE(keyloc0, 0));
2411+
2412+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
2413+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2414+ x,
2415+ keytbl[x * 4 + 3],
2416+ keytbl[x * 4 + 2],
2417+ keytbl[x * 4 + 1],
2418+ keytbl[x * 4]);
2419+ }
2420+ }
2421+
2422+ seq_printf(s, "\n\tkeyloc1:%d\n", keyloc1);
2423+ if(keyloc1 != GENMASK(26, 16)) {
2424+ mt7915_wtbl_read_raw(dev, keyloc1, WTBL_TYPE_KEY,
2425+ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
2426+ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2427+ MT_DBG_WTBLON_TOP_WDUCR,
2428+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2429+ KEYTBL_IDX2BASE(keyloc1, 0));
2430+
2431+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
2432+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2433+ x,
2434+ keytbl[x * 4 + 3],
2435+ keytbl[x * 4 + 2],
2436+ keytbl[x * 4 + 1],
2437+ keytbl[x * 4]);
2438+ }
2439+ }
2440+ return 0;
2441+}
2442+
2443+static void
2444+dump_dma_tx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
2445+{
2446+ u32 base, cnt, cidx, didx, queue_cnt;
2447+
2448+ base= mt76_rr(dev, ring_base);
2449+ cnt = mt76_rr(dev, ring_base + 4);
2450+ cidx = mt76_rr(dev, ring_base + 8);
2451+ didx = mt76_rr(dev, ring_base + 12);
2452+ queue_cnt = (cidx >= didx) ? (cidx - didx) : (cidx - didx + cnt);
2453+
2454+ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
2455+}
2456+
2457+static void
2458+dump_dma_rx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
2459+{
2460+ u32 base, cnt, cidx, didx, queue_cnt;
2461+
2462+ base= mt76_rr(dev, ring_base);
2463+ cnt = mt76_rr(dev, ring_base + 4);
2464+ cidx = mt76_rr(dev, ring_base + 8);
2465+ didx = mt76_rr(dev, ring_base + 12);
2466+ queue_cnt = (didx > cidx) ? (didx - cidx - 1) : (didx - cidx + cnt - 1);
2467+
2468+ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
2469+}
2470+
2471+static void
2472+mt7915_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2473+{
2474+ u32 sys_ctrl[10] = {};
2475+
2476+ /* HOST DMA */
2477+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
2478+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
2479+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
2480+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
2481+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_INT_SOURCE_CSR);
2482+ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_INT_MASK_CSR);
2483+ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
2484+ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_GLO_CFG);
2485+ seq_printf(s, "HOST_DMA Configuration\n");
2486+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2487+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2488+ seq_printf(s, "%10s %10x %10x\n",
2489+ "Merge", sys_ctrl[0], sys_ctrl[1]);
2490+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2491+ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
2492+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
2493+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
2494+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
2495+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
2496+
2497+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2498+ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
2499+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
2500+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
2501+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[7]),
2502+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[7]));
2503+
2504+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT1_SOURCE_CSR);
2505+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT1_MASK_CSR);
2506+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR);
2507+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR);
2508+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR);
2509+ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR);
2510+ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_GLO_CFG);
2511+ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_GLO_CFG);
2512+ seq_printf(s, "%10s %10x %10x\n",
2513+ "MergeP1", sys_ctrl[0], sys_ctrl[1]);
2514+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2515+ "DMA0P1", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
2516+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
2517+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
2518+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
2519+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
2520+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2521+ "DMA1P1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
2522+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
2523+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
2524+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[7]),
2525+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[7]));
2526+
2527+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2528+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2529+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2530+ dump_dma_rx_ring_info(s, dev, "R0:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2531+ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
2532+
2533+ seq_printf(s, "HOST_DMA0 PCIe 1 Ring Configuration\n");
2534+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2535+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2536+ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", MT_DBG_WFDMA0_PCIE1_RX1_CTRL0);
2537+
2538+ seq_printf(s, "HOST_DMA1 Ring Configuration\n");
2539+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2540+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2541+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
2542+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
developer79a21a22023-01-09 13:57:39 +08002543+ if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
2544+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(0));
2545+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(1));
2546+ } else {
2547+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
2548+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
2549+ }
developer3fa816c2022-04-19 10:21:20 +08002550+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
2551+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_EVENT_RING_CTRL(0));
developer79a21a22023-01-09 13:57:39 +08002552+ if (mtk_wed_device_active(&dev->mt76.mmio.wed))
2553+ dump_dma_rx_ring_info(s, dev, "R1:TxDone(WA2H)", MT_DBG_WFDMA_WED_RX_CTRL(1));
2554+ else
2555+ dump_dma_rx_ring_info(s, dev, "R1:Event0(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
developer3fa816c2022-04-19 10:21:20 +08002556+ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
2557+
2558+ seq_printf(s, "HOST_DMA1 PCIe 1 Ring Configuration\n");
2559+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2560+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2561+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA1_PCIE1_TX19_CTRL0);
2562+ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", MT_DBG_WFDMA1_PCIE1_RX2_CTRL0);
2563+}
2564+
2565+static void
2566+mt7915_show_mcu_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2567+{
2568+ u32 sys_ctrl[9] = {};
2569+
2570+ /* MCU DMA information */
2571+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2572+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2573+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2574+
2575+ sys_ctrl[3] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR);
2576+ sys_ctrl[4] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR);
2577+ sys_ctrl[5] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR);
2578+ sys_ctrl[6] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR);
2579+ sys_ctrl[7] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR);
2580+ sys_ctrl[8] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR);
2581+
2582+ seq_printf(s, "MCU_DMA Configuration\n");
2583+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2584+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2585+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2586+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2587+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2588+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2589+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2590+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2591+
2592+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2593+ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[3],
2594+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2595+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2596+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2597+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2598+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2599+ "DMA1P1", sys_ctrl[7], sys_ctrl[8], sys_ctrl[6],
2600+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2601+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2602+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2603+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2604+
2605+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2606+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2607+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2608+ dump_dma_tx_ring_info(s, dev, "T0:TXD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2609+ dump_dma_tx_ring_info(s, dev, "T1:TXCMD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2610+ dump_dma_tx_ring_info(s, dev, "T2:TXD(WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2611+ dump_dma_rx_ring_info(s, dev, "R0:Data(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2612+ dump_dma_rx_ring_info(s, dev, "R1:TxDone(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2613+ dump_dma_rx_ring_info(s, dev, "R2:SPL(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2614+ dump_dma_rx_ring_info(s, dev, "R3:TxDone(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2615+ dump_dma_rx_ring_info(s, dev, "R4:TXS(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2616+
2617+ seq_printf(s, "MCU_DMA1 Ring Configuration\n");
2618+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2619+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2620+ dump_dma_tx_ring_info(s, dev, "T0:Event(WM2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR);
2621+ dump_dma_tx_ring_info(s, dev, "T1:Event0(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR);
2622+ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR);
2623+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR);
2624+ dump_dma_rx_ring_info(s, dev, "R1:Cmd(H2WM)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR);
2625+ dump_dma_rx_ring_info(s, dev, "R2:TXD0(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR);
2626+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR);
2627+ dump_dma_rx_ring_info(s, dev, "R4:Cmd(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR);
2628+
2629+ seq_printf(s, "MCU_DMA1 PCIe 1 Ring Configuration\n");
2630+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2631+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2632+ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR);
2633+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR);
2634+}
2635+
2636+static void
2637+mt7986_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2638+{
2639+ u32 sys_ctrl[5] = {};
2640+
2641+ /* HOST DMA */
2642+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
2643+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
2644+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
2645+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
2646+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
2647+
2648+ seq_printf(s, "HOST_DMA Configuration\n");
2649+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2650+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2651+ seq_printf(s, "%10s %10x %10x\n",
2652+ "Merge", sys_ctrl[0], sys_ctrl[1]);
2653+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2654+ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[4],
2655+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK, sys_ctrl[4]),
2656+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK, sys_ctrl[4]),
2657+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK, sys_ctrl[4]),
2658+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK, sys_ctrl[4]));
2659+
2660+
2661+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2662+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2663+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2664+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
2665+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
developer79a21a22023-01-09 13:57:39 +08002666+
2667+ if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed)) {
2668+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(0));
2669+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(1));
2670+ } else {
2671+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
2672+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
2673+ }
2674+
developer3fa816c2022-04-19 10:21:20 +08002675+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
2676+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2677+ dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
developer79a21a22023-01-09 13:57:39 +08002678+ if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed))
2679+ dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_WFDMA_WED_RX_CTRL(1));
2680+ else
2681+ dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
developer3fa816c2022-04-19 10:21:20 +08002682+ dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(3));
2683+ dump_dma_rx_ring_info(s, dev, "R4:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2684+ dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
2685+}
2686+
2687+static void
2688+mt7986_show_mcu_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2689+{
2690+ u32 sys_ctrl[3] = {};
2691+
2692+ /* MCU DMA information */
2693+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2694+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2695+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2696+
2697+ seq_printf(s, "MCU_DMA Configuration\n");
2698+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2699+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2700+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2701+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2702+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2703+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2704+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2705+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2706+
2707+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2708+ seq_printf(s, "%22s %10s %10s %10s %10s %10s\n",
2709+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2710+ dump_dma_tx_ring_info(s, dev, "T0:Event (WM2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2711+ dump_dma_tx_ring_info(s, dev, "T1:Event (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2712+ dump_dma_tx_ring_info(s, dev, "T2:TxDone (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2713+ dump_dma_tx_ring_info(s, dev, "T3:TxDone1 (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR);
2714+ dump_dma_tx_ring_info(s, dev, "T4:TXD (WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR);
2715+ dump_dma_tx_ring_info(s, dev, "T5:TXCMD (WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR);
2716+ dump_dma_tx_ring_info(s, dev, "T6:TXD (WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR);
2717+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2718+ dump_dma_rx_ring_info(s, dev, "R1:Cmd (H2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2719+ dump_dma_rx_ring_info(s, dev, "R2:TXD (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2720+ dump_dma_rx_ring_info(s, dev, "R3:TXD1 (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2721+ dump_dma_rx_ring_info(s, dev, "R4:Cmd (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2722+ dump_dma_rx_ring_info(s, dev, "R5:Data (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR);
2723+ dump_dma_rx_ring_info(s, dev, "R6:TxDone/STS (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR);
2724+ dump_dma_rx_ring_info(s, dev, "R7:RPT (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR);
2725+ dump_dma_rx_ring_info(s, dev, "R8:TxDone/STS (MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR);
2726+ dump_dma_rx_ring_info(s, dev, "R9:Data1 (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR);
2727+
2728+}
2729+
2730+static void
2731+mt7915_show_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2732+{
2733+ u32 sys_ctrl[10] = {};
2734+
2735+ if(is_mt7915(&dev->mt76)) {
2736+ mt7915_show_host_dma_info(s, dev);
2737+ mt7915_show_mcu_dma_info(s, dev);
2738+ } else {
2739+ mt7986_show_host_dma_info(s, dev);
2740+ mt7986_show_mcu_dma_info(s, dev);
2741+ }
2742+
2743+ /* MEM DMA information */
2744+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR);
2745+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR);
2746+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR);
2747+
2748+ seq_printf(s, "MEM_DMA Configuration\n");
2749+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2750+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2751+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2752+ "MEM", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2753+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2754+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2755+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2756+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2757+
2758+ seq_printf(s, "MEM_DMA Ring Configuration\n");
2759+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2760+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2761+ dump_dma_tx_ring_info(s, dev, "T0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR);
2762+ dump_dma_tx_ring_info(s, dev, "T1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR);
2763+ dump_dma_rx_ring_info(s, dev, "R0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR);
2764+ dump_dma_rx_ring_info(s, dev, "R1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR);
2765+}
2766+
2767+static int mt7915_trinfo_read(struct seq_file *s, void *data)
2768+{
2769+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2770+ const struct hif_pci_tx_ring_desc *tx_ring_layout;
2771+ const struct hif_pci_rx_ring_desc *rx_ring_layout;
developer79a21a22023-01-09 13:57:39 +08002772+ struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
developer3fa816c2022-04-19 10:21:20 +08002773+ u32 tx_ring_num, rx_ring_num;
2774+ u32 tbase[5], tcnt[5];
2775+ u32 tcidx[5], tdidx[5];
2776+ u32 rbase[6], rcnt[6];
2777+ u32 rcidx[6], rdidx[6];
2778+ int idx;
developer79a21a22023-01-09 13:57:39 +08002779+ bool flags = false;
developer3fa816c2022-04-19 10:21:20 +08002780+
2781+ if(is_mt7915(&dev->mt76)) {
2782+ tx_ring_layout = &mt7915_tx_ring_layout[0];
2783+ rx_ring_layout = &mt7915_rx_ring_layout[0];
2784+ tx_ring_num = ARRAY_SIZE(mt7915_tx_ring_layout);
2785+ rx_ring_num = ARRAY_SIZE(mt7915_rx_ring_layout);
2786+ } else {
2787+ tx_ring_layout = &mt7986_tx_ring_layout[0];
2788+ rx_ring_layout = &mt7986_rx_ring_layout[0];
2789+ tx_ring_num = ARRAY_SIZE(mt7986_tx_ring_layout);
2790+ rx_ring_num = ARRAY_SIZE(mt7986_rx_ring_layout);
2791+ }
2792+
2793+ for (idx = 0; idx < tx_ring_num; idx++) {
developer79a21a22023-01-09 13:57:39 +08002794+ if (mtk_wed_device_active(wed) &&
2795+ (tx_ring_layout[idx].ring_attr == HIF_TX_DATA)) {
2796+ struct mt76_phy *phy = dev->mt76.phys[MT_BAND0];
2797+ struct mt76_phy *ext_phy = dev->mt76.phys[MT_BAND1];
2798+ struct mt76_queue *q;
2799+
2800+ tbase[idx] = tcnt[idx] = tcidx[idx] = tdidx[idx] = 0;
2801+
2802+ if (!phy)
2803+ continue;
2804+
2805+ if (flags && !ext_phy)
2806+ continue;
2807+
2808+ if (flags && ext_phy)
2809+ phy = ext_phy;
2810+
2811+ q = phy->q_tx[0];
2812+
2813+ if (q->wed_regs) {
2814+ tbase[idx] = mtk_wed_device_reg_read(wed, q->wed_regs);
2815+ tcnt[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x04);
2816+ tcidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x08);
2817+ tdidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x0c);
2818+ }
2819+
2820+ flags = true;
2821+ } else {
2822+ tbase[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx));
2823+ tcnt[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x04);
2824+ tcidx[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x08);
2825+ tdidx[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x0c);}
developer3fa816c2022-04-19 10:21:20 +08002826+ }
2827+
2828+ for (idx = 0; idx < rx_ring_num; idx++) {
developer79a21a22023-01-09 13:57:39 +08002829+ if (rx_ring_layout[idx].ring_attr == HIF_RX_DATA) {
2830+ if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) {
2831+ struct mt76_queue *q = &dev->mt76.q_rx[MT_RXQ_MAIN];
2832+
2833+ rbase[idx] = rcnt[idx] = rcidx[idx] = rdidx[idx] = 0;
2834+
2835+ if (idx == 1)
2836+ q = &dev->mt76.q_rx[MT_RXQ_BAND1];
2837+
2838+ if (q->wed_regs) {
2839+ rbase[idx] = mtk_wed_device_reg_read(wed, q->wed_regs);
2840+ rcnt[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x04);
2841+ rcidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x08);
2842+ rdidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x0c);
2843+ }
2844+ } else {
2845+ rbase[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx));
2846+ rcnt[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x04);
2847+ rcidx[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x08);
2848+ rdidx[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x0c);
2849+ }
developer3fa816c2022-04-19 10:21:20 +08002850+ } else {
developer79a21a22023-01-09 13:57:39 +08002851+ if (mtk_wed_device_active(wed) && rx_ring_layout[idx].flags) {
2852+ struct mt76_queue *q = &dev->mt76.q_rx[MT_RXQ_MAIN_WA];
2853+
2854+ if (is_mt7915(&dev->mt76))
2855+ q = &dev->mt76.q_rx[MT_RXQ_MCU_WA];
2856+
2857+ rbase[idx] = mtk_wed_device_reg_read(wed, q->wed_regs);
2858+ rcnt[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x04);
2859+ rcidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x08);
2860+ rdidx[idx] = mtk_wed_device_reg_read(wed, q->wed_regs + 0x0c);
2861+
2862+ } else {
2863+ rbase[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2));
2864+ rcnt[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x04);
2865+ rcidx[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x08);
2866+ rdidx[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x0c);
2867+ }
developer3fa816c2022-04-19 10:21:20 +08002868+ }
2869+ }
2870+
2871+ seq_printf(s, "=================================================\n");
2872+ seq_printf(s, "TxRing Configuration\n");
2873+ seq_printf(s, "%4s %10s %8s %1s %6s %6s %6s %6s\n",
2874+ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
2875+ "QCnt");
2876+ for (idx = 0; idx < tx_ring_num; idx++) {
2877+ u32 queue_cnt;
2878+
2879+ queue_cnt = (tcidx[idx] >= tdidx[idx]) ?
2880+ (tcidx[idx] - tdidx[idx]) :
2881+ (tcidx[idx] - tdidx[idx] + tcnt[idx]);
2882+ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
2883+ idx, tx_ring_layout[idx].ring_info,
2884+ MT_DBG_TX_RING_CTRL(idx), tbase[idx],
2885+ tcnt[idx], tcidx[idx], tdidx[idx], queue_cnt);
2886+ }
2887+
2888+ seq_printf(s, "RxRing Configuration\n");
2889+ seq_printf(s, "%4s %10s %8s %10s %6s %6s %6s %6s\n",
2890+ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
2891+ "QCnt");
2892+
2893+ for (idx = 0; idx < rx_ring_num; idx++) {
2894+ u32 queue_cnt;
2895+
2896+ queue_cnt = (rdidx[idx] > rcidx[idx]) ?
2897+ (rdidx[idx] - rcidx[idx] - 1) :
2898+ (rdidx[idx] - rcidx[idx] + rcnt[idx] - 1);
2899+ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
2900+ idx, rx_ring_layout[idx].ring_info,
2901+ (idx < 2) ? MT_DBG_RX_DATA_RING_CTRL(idx): MT_DBG_RX_EVENT_RING_CTRL(idx - 2),
2902+ rbase[idx], rcnt[idx], rcidx[idx], rdidx[idx], queue_cnt);
2903+ }
2904+
2905+ mt7915_show_dma_info(s, dev);
2906+ return 0;
2907+}
2908+
2909+static int mt7915_drr_info(struct seq_file *s, void *data)
2910+{
2911+#define DL_AC_START 0x00
2912+#define DL_AC_END 0x0F
2913+#define UL_AC_START 0x10
2914+#define UL_AC_END 0x1F
2915+
2916+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2917+ u32 drr_sta_status[16];
2918+ u32 drr_ctrl_def_val = 0x80220000, drr_ctrl_val = 0;
2919+ bool is_show = false;
2920+ int idx, sta_line = 0, sta_no = 0, max_sta_line = (mt7915_wtbl_size(dev) + 31) / 32;
2921+ seq_printf(s, "DRR Table STA Info:\n");
2922+
2923+ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
2924+ is_show = true;
2925+ drr_ctrl_val = (drr_ctrl_def_val | idx);
2926+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2927+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2928+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2929+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2930+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2931+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2932+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2933+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2934+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2935+
2936+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
2937+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1 << 10);
2938+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2939+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2940+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2941+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2942+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2943+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2944+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2945+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2946+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2947+ }
2948+ if (!is_mt7915(&dev->mt76))
2949+ max_sta_line = 8;
2950+
2951+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
2952+ if (drr_sta_status[sta_line] > 0) {
2953+ for (sta_no = 0; sta_no < 32; sta_no++) {
2954+ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
2955+ if (is_show) {
2956+ seq_printf(s, "\n DL AC%02d Queue Non-Empty STA:\n", idx);
2957+ is_show = false;
2958+ }
2959+ seq_printf(s, "%d ", sta_no + (sta_line * 32));
2960+ }
2961+ }
2962+ }
2963+ }
2964+ }
2965+
2966+ for (idx = UL_AC_START; idx <= UL_AC_END; idx++) {
2967+ is_show = true;
2968+ drr_ctrl_val = (drr_ctrl_def_val | idx);
2969+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2970+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2971+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2972+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2973+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2974+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2975+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2976+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2977+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2978+
2979+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
2980+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1 << 10);
2981+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2982+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2983+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2984+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2985+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2986+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2987+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2988+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2989+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2990+ }
2991+
2992+ if (!is_mt7915(&dev->mt76))
2993+ max_sta_line = 8;
2994+
2995+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
2996+ if (drr_sta_status[sta_line] > 0) {
2997+ for (sta_no = 0; sta_no < 32; sta_no++) {
2998+ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
2999+ if (is_show) {
3000+ seq_printf(s, "\n UL AC%02d Queue Non-Empty STA:\n", idx);
3001+ is_show = false;
3002+ }
3003+ seq_printf(s, "%d ", sta_no + (sta_line * 32));
3004+ }
3005+ }
3006+ }
3007+ }
3008+ }
3009+
3010+ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
3011+ drr_ctrl_def_val = 0x80420000;
3012+ drr_ctrl_val = (drr_ctrl_def_val | idx);
3013+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3014+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3015+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3016+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3017+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3018+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3019+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3020+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3021+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3022+
3023+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
3024+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1<<10);
3025+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
3026+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
3027+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
3028+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
3029+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
3030+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
3031+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
3032+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
3033+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
3034+ }
3035+
3036+ seq_printf(s, "\nBSSGrp[%d]:\n", idx);
3037+ if (!is_mt7915(&dev->mt76))
3038+ max_sta_line = 8;
3039+
3040+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
3041+ seq_printf(s, "0x%08x ", drr_sta_status[sta_line]);
3042+
3043+ if ((sta_line % 4) == 3)
3044+ seq_printf(s, "\n");
3045+ }
3046+ }
3047+
3048+ return 0;
3049+}
3050+
developerf32dabf2022-06-01 10:59:24 +08003051+#define CR_NUM_OF_AC 17
developer3fa816c2022-04-19 10:21:20 +08003052+
3053+typedef enum _ENUM_UMAC_PORT_T {
3054+ ENUM_UMAC_HIF_PORT_0 = 0,
3055+ ENUM_UMAC_CPU_PORT_1 = 1,
3056+ ENUM_UMAC_LMAC_PORT_2 = 2,
3057+ ENUM_PLE_CTRL_PSE_PORT_3 = 3,
3058+ ENUM_UMAC_PSE_PLE_PORT_TOTAL_NUM = 4
3059+} ENUM_UMAC_PORT_T, *P_ENUM_UMAC_PORT_T;
3060+
3061+/* N9 MCU QUEUE LIST */
3062+typedef enum _ENUM_UMAC_CPU_P_QUEUE_T {
3063+ ENUM_UMAC_CTX_Q_0 = 0,
3064+ ENUM_UMAC_CTX_Q_1 = 1,
3065+ ENUM_UMAC_CTX_Q_2 = 2,
3066+ ENUM_UMAC_CTX_Q_3 = 3,
3067+ ENUM_UMAC_CRX = 0,
3068+ ENUM_UMAC_CIF_QUEUE_TOTAL_NUM = 4
3069+} ENUM_UMAC_CPU_P_QUEUE_T, *P_ENUM_UMAC_CPU_P_QUEUE_T;
3070+
3071+/* LMAC PLE TX QUEUE LIST */
3072+typedef enum _ENUM_UMAC_LMAC_PLE_TX_P_QUEUE_T {
3073+ ENUM_UMAC_LMAC_PLE_TX_Q_00 = 0x00,
3074+ ENUM_UMAC_LMAC_PLE_TX_Q_01 = 0x01,
3075+ ENUM_UMAC_LMAC_PLE_TX_Q_02 = 0x02,
3076+ ENUM_UMAC_LMAC_PLE_TX_Q_03 = 0x03,
3077+
3078+ ENUM_UMAC_LMAC_PLE_TX_Q_10 = 0x04,
3079+ ENUM_UMAC_LMAC_PLE_TX_Q_11 = 0x05,
3080+ ENUM_UMAC_LMAC_PLE_TX_Q_12 = 0x06,
3081+ ENUM_UMAC_LMAC_PLE_TX_Q_13 = 0x07,
3082+
3083+ ENUM_UMAC_LMAC_PLE_TX_Q_20 = 0x08,
3084+ ENUM_UMAC_LMAC_PLE_TX_Q_21 = 0x09,
3085+ ENUM_UMAC_LMAC_PLE_TX_Q_22 = 0x0a,
3086+ ENUM_UMAC_LMAC_PLE_TX_Q_23 = 0x0b,
3087+
3088+ ENUM_UMAC_LMAC_PLE_TX_Q_30 = 0x0c,
3089+ ENUM_UMAC_LMAC_PLE_TX_Q_31 = 0x0d,
3090+ ENUM_UMAC_LMAC_PLE_TX_Q_32 = 0x0e,
3091+ ENUM_UMAC_LMAC_PLE_TX_Q_33 = 0x0f,
3092+
3093+ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 = 0x10,
3094+ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0 = 0x11,
3095+ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0 = 0x12,
3096+ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0 = 0x13,
3097+
3098+ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 = 0x14,
3099+ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1 = 0x15,
3100+ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1 = 0x16,
3101+ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1 = 0x17,
3102+ ENUM_UMAC_LMAC_PLE_TX_Q_NAF = 0x18,
3103+ ENUM_UMAC_LMAC_PLE_TX_Q_NBCN = 0x19,
3104+ ENUM_UMAC_LMAC_PLE_TX_Q_RELEASE = 0x1f, /* DE suggests not to use 0x1f, it's only for hw free queue */
3105+ ENUM_UMAC_LMAC_QUEUE_TOTAL_NUM = 24,
3106+
3107+} ENUM_UMAC_LMAC_TX_P_QUEUE_T, *P_ENUM_UMAC_LMAC_TX_P_QUEUE_T;
3108+
3109+typedef struct _EMPTY_QUEUE_INFO_T {
3110+ char *QueueName;
3111+ u32 Portid;
3112+ u32 Queueid;
3113+} EMPTY_QUEUE_INFO_T, *P_EMPTY_QUEUE_INFO_T;
3114+
3115+static EMPTY_QUEUE_INFO_T ple_queue_empty_info[] = {
3116+ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
3117+ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
3118+ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
3119+ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
3120+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
3121+ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0}, /* Q16 */
3122+ {"BMC Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0},
3123+ {"BCN Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0},
3124+ {"PSMP Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0},
3125+ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1},
3126+ {"BMC Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1},
3127+ {"BCN Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1},
3128+ {"PSMP Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1},
3129+ {"NAF Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NAF},
3130+ {"NBCN Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NBCN},
3131+ {NULL, 0, 0}, {NULL, 0, 0}, /* 18, 19 not defined */
3132+ {"FIXFID Q", ENUM_UMAC_LMAC_PORT_2, 0x1a},
3133+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
3134+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 21~29 not defined */
3135+ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7e},
3136+ {"RLS2 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7f}
3137+};
3138+
3139+static EMPTY_QUEUE_INFO_T ple_txcmd_queue_empty_info[] = {
3140+ {"AC00Q", ENUM_UMAC_LMAC_PORT_2, 0x40},
3141+ {"AC01Q", ENUM_UMAC_LMAC_PORT_2, 0x41},
3142+ {"AC02Q", ENUM_UMAC_LMAC_PORT_2, 0x42},
3143+ {"AC03Q", ENUM_UMAC_LMAC_PORT_2, 0x43},
3144+ {"AC10Q", ENUM_UMAC_LMAC_PORT_2, 0x44},
3145+ {"AC11Q", ENUM_UMAC_LMAC_PORT_2, 0x45},
3146+ {"AC12Q", ENUM_UMAC_LMAC_PORT_2, 0x46},
3147+ {"AC13Q", ENUM_UMAC_LMAC_PORT_2, 0x47},
3148+ {"AC20Q", ENUM_UMAC_LMAC_PORT_2, 0x48},
3149+ {"AC21Q", ENUM_UMAC_LMAC_PORT_2, 0x49},
3150+ {"AC22Q", ENUM_UMAC_LMAC_PORT_2, 0x4a},
3151+ {"AC23Q", ENUM_UMAC_LMAC_PORT_2, 0x4b},
3152+ {"AC30Q", ENUM_UMAC_LMAC_PORT_2, 0x4c},
3153+ {"AC31Q", ENUM_UMAC_LMAC_PORT_2, 0x4d},
3154+ {"AC32Q", ENUM_UMAC_LMAC_PORT_2, 0x4e},
3155+ {"AC33Q", ENUM_UMAC_LMAC_PORT_2, 0x4f},
3156+ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, 0x50},
3157+ {"TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x51},
3158+ {"TWT TSF-TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x52},
3159+ {"TWT DL Q0", ENUM_UMAC_LMAC_PORT_2, 0x53},
3160+ {"TWT UL Q0", ENUM_UMAC_LMAC_PORT_2, 0x54},
3161+ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, 0x55},
3162+ {"TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x56},
3163+ {"TWT TSF-TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x57},
3164+ {"TWT DL Q1", ENUM_UMAC_LMAC_PORT_2, 0x58},
3165+ {"TWT UL Q1", ENUM_UMAC_LMAC_PORT_2, 0x59},
3166+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
3167+};
3168+
3169+
3170+
3171+static char* sta_ctrl_reg[] = {"ENABLE", "DISABLE", "PAUSE"};
3172+static u32 chip_show_sta_acq_info(struct seq_file *s, struct mt7915_dev *dev, u32 *ple_stat,
3173+ u32 *sta_pause, u32 *dis_sta_map,
3174+ u32 dumptxd)
3175+{
3176+ int i, j;
3177+ u32 total_nonempty_cnt = 0;
3178+ u32 ac_num = 9, all_ac_num;
3179+
3180+ /* TDO: ac_num = 16 for mt7986 */
developerf32dabf2022-06-01 10:59:24 +08003181+ if (!is_mt7915(&dev->mt76))
3182+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003183+
3184+ all_ac_num = ac_num * 4;
3185+
3186+ for (j = 0; j < all_ac_num; j++) { /* show AC Q info */
3187+ for (i = 0; i < 32; i++) {
3188+ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
developerf32dabf2022-06-01 10:59:24 +08003189+ u32 hfid, tfid, pktcnt, ac_n = j / ac_num, ctrl = 0;
developer3fa816c2022-04-19 10:21:20 +08003190+ u32 sta_num = i + (j % ac_num) * 32, fl_que_ctrl[3] = {0};
3191+ //struct wifi_dev *wdev = wdev_search_by_wcid(pAd, sta_num);
3192+ u32 wmmidx = 0;
3193+ struct mt7915_sta *msta;
3194+ struct mt76_wcid *wcid;
3195+ struct ieee80211_sta *sta = NULL;
3196+
3197+ wcid = rcu_dereference(dev->mt76.wcid[sta_num]);
3198+ sta = wcid_to_sta(wcid);
3199+ if (!sta) {
3200+ printk("ERROR!! no found STA wcid=%d\n", sta_num);
developerf32dabf2022-06-01 10:59:24 +08003201+ continue;
developer3fa816c2022-04-19 10:21:20 +08003202+ }
3203+ msta = container_of(wcid, struct mt7915_sta, wcid);
3204+ wmmidx = msta->vif->mt76.wmm_idx;
3205+
developerf32dabf2022-06-01 10:59:24 +08003206+ seq_printf(s, "\tSTA%d AC%d: ", sta_num, ac_n);
developer3fa816c2022-04-19 10:21:20 +08003207+
3208+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3209+ fl_que_ctrl[0] |= (ENUM_UMAC_LMAC_PORT_2 << MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
developerf32dabf2022-06-01 10:59:24 +08003210+ fl_que_ctrl[0] |= (ac_n << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
developer3fa816c2022-04-19 10:21:20 +08003211+ fl_que_ctrl[0] |= sta_num;
3212+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3213+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3214+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3215+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3216+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3217+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3218+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x",
3219+ tfid, hfid, pktcnt);
3220+
3221+ if (((sta_pause[j % 6] & 0x1 << i) >> i) == 1)
3222+ ctrl = 2;
3223+
3224+ if (((dis_sta_map[j % 6] & 0x1 << i) >> i) == 1)
3225+ ctrl = 1;
3226+
3227+ seq_printf(s, " ctrl = %s", sta_ctrl_reg[ctrl]);
3228+ seq_printf(s, " (wmmidx=%d)\n", wmmidx);
3229+
3230+ total_nonempty_cnt++;
3231+
3232+ // TODO
3233+ //if (pktcnt > 0 && dumptxd > 0)
3234+ // ShowTXDInfo(pAd, hfid);
3235+ }
3236+ }
3237+ }
3238+
3239+ return total_nonempty_cnt;
3240+}
3241+
3242+static void chip_show_txcmdq_info(struct seq_file *s, struct mt7915_dev *dev, u32 ple_txcmd_stat)
3243+{
3244+ int i;
3245+
3246+ seq_printf(s, "Nonempty TXCMD Q info:\n");
developerf32dabf2022-06-01 10:59:24 +08003247+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003248+ if (((ple_txcmd_stat & (0x1 << i)) >> i) == 0) {
3249+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3250+
3251+ if (ple_txcmd_queue_empty_info[i].QueueName != NULL) {
3252+ seq_printf(s, "\t%s: ", ple_txcmd_queue_empty_info[i].QueueName);
3253+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3254+ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Portid <<
3255+ MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
3256+ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Queueid <<
3257+ MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
3258+ } else
3259+ continue;
3260+
3261+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3262+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3263+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3264+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3265+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3266+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3267+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3268+ tfid, hfid, pktcnt);
3269+ }
3270+ }
3271+}
3272+
3273+static void chip_get_ple_acq_stat(struct mt7915_dev *dev, u32 *ple_stat)
3274+{
3275+ int i;
3276+ int cr_num = 9, all_cr_num;
3277+ u32 ac , index;
3278+
3279+ /* TDO: cr_num = 16 for mt7986 */
developer3fa816c2022-04-19 10:21:20 +08003280+ if(!is_mt7915(&dev->mt76))
developerf32dabf2022-06-01 10:59:24 +08003281+ cr_num = 17;
3282+
developer3fa816c2022-04-19 10:21:20 +08003283+ all_cr_num = cr_num * 4;
3284+
3285+ ple_stat[0] = mt76_rr(dev, MT_DBG_PLE_QUEUE_EMPTY);
3286+
3287+ for(i = 0; i < all_cr_num; i++) {
3288+ ac = i / cr_num;
3289+ index = i % cr_num;
3290+ ple_stat[i + 1] =
3291+ mt76_rr(dev, MT_DBG_PLE_AC_QEMPTY(ac, index));
3292+
3293+ }
3294+}
3295+
3296+static void chip_get_dis_sta_map(struct mt7915_dev *dev, u32 *dis_sta_map)
3297+{
3298+ int i;
developerf32dabf2022-06-01 10:59:24 +08003299+ u32 ac_num = 9;
3300+
3301+ /* TDO: ac_num = 16 for mt7986 */
3302+ if (!is_mt7915(&dev->mt76))
3303+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003304+
developerf32dabf2022-06-01 10:59:24 +08003305+ for(i = 0; i < ac_num; i++) {
developer3fa816c2022-04-19 10:21:20 +08003306+ dis_sta_map[i] = mt76_rr(dev, MT_DBG_PLE_DIS_STA_MAP(i));
3307+ }
3308+}
3309+
3310+static void chip_get_sta_pause(struct mt7915_dev *dev, u32 *sta_pause)
3311+{
3312+ int i;
developerf32dabf2022-06-01 10:59:24 +08003313+ u32 ac_num = 9;
developer3fa816c2022-04-19 10:21:20 +08003314+
developerf32dabf2022-06-01 10:59:24 +08003315+ /* TDO: ac_num = 16 for mt7986 */
3316+ if (!is_mt7915(&dev->mt76))
3317+ ac_num = 17;
3318+
3319+ for(i = 0; i < ac_num; i++) {
developer3fa816c2022-04-19 10:21:20 +08003320+ sta_pause[i] = mt76_rr(dev, MT_DBG_PLE_STATION_PAUSE(i));
3321+ }
3322+}
3323+
3324+static int mt7915_pleinfo_read(struct seq_file *s, void *data)
3325+{
3326+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3327+ u32 ple_buf_ctrl, pg_sz, pg_num;
developerf32dabf2022-06-01 10:59:24 +08003328+ u32 ple_stat[70] = {0}, pg_flow_ctrl[8] = {0};
developer3fa816c2022-04-19 10:21:20 +08003329+ u32 ple_native_txcmd_stat;
3330+ u32 ple_txcmd_stat;
3331+ u32 sta_pause[CR_NUM_OF_AC] = {0}, dis_sta_map[CR_NUM_OF_AC] = {0};
3332+ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail, hif_max_q, hif_min_q;
3333+ u32 rpg_hif, upg_hif, cpu_max_q, cpu_min_q, rpg_cpu, upg_cpu;
3334+ int i, j;
3335+ u32 ac_num = 9, all_ac_num;
3336+
3337+ /* TDO: ac_num = 16 for mt7986 */
developerf32dabf2022-06-01 10:59:24 +08003338+ if (!is_mt7915(&dev->mt76))
3339+ ac_num = 17;
developer3fa816c2022-04-19 10:21:20 +08003340+
3341+ all_ac_num = ac_num * 4;
3342+
3343+ ple_buf_ctrl = mt76_rr(dev, MT_DBG_PLE_PBUF_CTRL_ADDR);
3344+ chip_get_ple_acq_stat(dev, ple_stat);
3345+ ple_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_TXCMD_Q_EMPTY);
3346+ ple_native_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY);
3347+ pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PLE_FREEPG_CNT);
3348+ pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FREEPG_HEAD_TAIL);
3349+ pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_GROUP);
3350+ pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PLE_HIF_PG_INFO);
3351+ pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PLE_PG_CPU_GROUP);
3352+ pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PLE_CPU_PG_INFO);
3353+ pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_TXCMD_GROUP);
3354+ pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PLE_HIF_TXCMD_PG_INFO);
3355+ chip_get_dis_sta_map(dev, dis_sta_map);
3356+ chip_get_sta_pause(dev, sta_pause);
3357+
3358+ seq_printf(s, "PLE Configuration Info:\n");
3359+ seq_printf(s, "\tPacket Buffer Control(0x%x): 0x%08x\n",
3360+ MT_DBG_PLE_PBUF_CTRL_ADDR, ple_buf_ctrl);
3361+
3362+ pg_sz = FIELD_GET(MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK, ple_buf_ctrl);
3363+ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n",
3364+ pg_sz, (pg_sz == 1 ? 128 : 64));
3365+ seq_printf(s, "\t\tPage Offset=%ld(in unit of 2KB)\n",
3366+ FIELD_GET(MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK, ple_buf_ctrl));
3367+
3368+ pg_num = FIELD_GET(MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK, ple_buf_ctrl);
3369+ seq_printf(s, "\t\tTotal Page=%d pages\n", pg_num);
3370+
3371+ /* Page Flow Control */
3372+ seq_printf(s, "PLE Page Flow Control:\n");
3373+ seq_printf(s, "\tFree page counter(0x%x): 0x%08x\n",
3374+ MT_DBG_PLE_FREEPG_CNT, pg_flow_ctrl[0]);
3375+ fpg_cnt = FIELD_GET(MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK, pg_flow_ctrl[0]);
3376+
3377+ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3378+ ffa_cnt = FIELD_GET(MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK, pg_flow_ctrl[0]);
3379+
3380+ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3381+ seq_printf(s, "\tFree page head and tail(0x%x): 0x%08x\n",
3382+ MT_DBG_PLE_FREEPG_HEAD_TAIL, pg_flow_ctrl[1]);
3383+
3384+ fpg_head = FIELD_GET(MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK, pg_flow_ctrl[1]);
3385+ fpg_tail = FIELD_GET(MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK, pg_flow_ctrl[1]);
3386+ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3387+ seq_printf(s, "\tReserved page counter of HIF group(0x%x): 0x%08x\n",
3388+ MT_DBG_PLE_PG_HIF_GROUP, pg_flow_ctrl[2]);
3389+ seq_printf(s, "\tHIF group page status(0x%x): 0x%08x\n",
3390+ MT_DBG_PLE_HIF_PG_INFO, pg_flow_ctrl[3]);
3391+
3392+ hif_min_q = FIELD_GET(MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK, pg_flow_ctrl[2]);
3393+ hif_max_q = FIELD_GET(MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK, pg_flow_ctrl[2]);
3394+ seq_printf(s, "\t\tThe max/min quota pages of HIF group=0x%03x/0x%03x\n", hif_max_q, hif_min_q);
3395+
3396+ rpg_hif = FIELD_GET(MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK, pg_flow_ctrl[3]);
3397+ upg_hif = FIELD_GET(MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK, pg_flow_ctrl[3]);
3398+ seq_printf(s, "\t\tThe used/reserved pages of HIF group=0x%03x/0x%03x\n", upg_hif, rpg_hif);
3399+
3400+ seq_printf(s, "\tReserved page counter of HIF_TXCMD group(0x%x): 0x%08x\n",
3401+ MT_DBG_PLE_PG_HIF_TXCMD_GROUP, pg_flow_ctrl[6]);
3402+ seq_printf(s, "\tHIF_TXCMD group page status(0x%x): 0x%08x\n",
3403+ MT_DBG_PLE_HIF_TXCMD_PG_INFO, pg_flow_ctrl[7]);
3404+ cpu_min_q = FIELD_GET(MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
developerf32dabf2022-06-01 10:59:24 +08003405+ cpu_max_q = FIELD_GET(MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK, pg_flow_ctrl[6]);
developer3fa816c2022-04-19 10:21:20 +08003406+ seq_printf(s, "\t\tThe max/min quota pages of HIF_TXCMD group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
3407+
3408+ rpg_cpu = FIELD_GET(MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK, pg_flow_ctrl[7]);
3409+ upg_cpu = FIELD_GET(MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK, pg_flow_ctrl[7]);
3410+ seq_printf(s, "\t\tThe used/reserved pages of HIF_TXCMD group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
3411+
developerf32dabf2022-06-01 10:59:24 +08003412+ seq_printf(s, "\tReserved page counter of CPU group(0x%x): 0x%08x\n",
3413+ MT_DBG_PLE_PG_CPU_GROUP, pg_flow_ctrl[4]);
3414+ seq_printf(s, "\tCPU group page status(0x%x): 0x%08x\n",
3415+ MT_DBG_PLE_CPU_PG_INFO, pg_flow_ctrl[5]);
developer3fa816c2022-04-19 10:21:20 +08003416+ cpu_min_q = FIELD_GET(MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK, pg_flow_ctrl[4]);
3417+ cpu_max_q = FIELD_GET(MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK, pg_flow_ctrl[4]);
3418+ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
3419+
3420+ rpg_cpu = FIELD_GET(MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK, pg_flow_ctrl[5]);
3421+ upg_cpu = FIELD_GET(MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK, pg_flow_ctrl[5]);
3422+ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
3423+
3424+ if ((ple_stat[0] & MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK) == 0) {
3425+ for (j = 0; j < all_ac_num; j++) {
3426+ if (j % ac_num == 0) {
3427+ seq_printf(s, "\n\tNonempty AC%d Q of STA#: ", j / ac_num);
3428+ }
3429+
developerf32dabf2022-06-01 10:59:24 +08003430+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003431+ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
3432+ seq_printf(s, "%d ", i + (j % ac_num) * 32);
3433+ }
3434+ }
3435+ }
3436+
3437+ seq_printf(s, "\n");
3438+ }
3439+
3440+ seq_printf(s, "non-native/native txcmd queue empty = %d/%d\n", ple_txcmd_stat, ple_native_txcmd_stat);
3441+
3442+ seq_printf(s, "Nonempty Q info:\n");
3443+
developerf32dabf2022-06-01 10:59:24 +08003444+ for (i = 0; i < 32; i++) {
developer3fa816c2022-04-19 10:21:20 +08003445+ if (((ple_stat[0] & (0x1 << i)) >> i) == 0) {
3446+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3447+
3448+ if (ple_queue_empty_info[i].QueueName != NULL) {
3449+ seq_printf(s, "\t%s: ", ple_queue_empty_info[i].QueueName);
3450+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3451+ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Portid << MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
3452+ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Queueid << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
3453+ } else
3454+ continue;
3455+
3456+ if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 &&
3457+ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0)
3458+ /* band0 set TGID 0, bit31 = 0 */
3459+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x0);
3460+ else if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 &&
3461+ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1)
3462+ /* band1 set TGID 1, bit31 = 1 */
3463+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x80000000);
3464+
3465+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3466+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3467+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3468+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3469+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3470+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3471+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3472+ tfid, hfid, pktcnt);
3473+
3474+ /* TODO */
3475+ //if (pktcnt > 0 && dumptxd > 0)
3476+ // ShowTXDInfo(pAd, hfid);
3477+ }
3478+ }
3479+
3480+ chip_show_sta_acq_info(s, dev, ple_stat, sta_pause, dis_sta_map, 0/*dumptxd*/);
3481+ chip_show_txcmdq_info(s, dev, ple_native_txcmd_stat);
3482+
3483+ return 0;
3484+}
3485+
3486+typedef enum _ENUM_UMAC_PLE_CTRL_P3_QUEUE_T {
3487+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1E = 0x1e,
3488+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1F = 0x1f,
3489+ ENUM_UMAC_PLE_CTRL_P3_TOTAL_NUM = 2
3490+} ENUM_UMAC_PLE_CTRL_P3_QUEUE_T, *P_ENUM_UMAC_PLE_CTRL_P3_QUEUE_T;
3491+
3492+static EMPTY_QUEUE_INFO_T pse_queue_empty_info[] = {
3493+ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
3494+ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
3495+ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
3496+ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
3497+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
3498+ {"HIF Q0", ENUM_UMAC_HIF_PORT_0, 0}, /* Q8 */
3499+ {"HIF Q1", ENUM_UMAC_HIF_PORT_0, 1},
3500+ {"HIF Q2", ENUM_UMAC_HIF_PORT_0, 2},
3501+ {"HIF Q3", ENUM_UMAC_HIF_PORT_0, 3},
3502+ {"HIF Q4", ENUM_UMAC_HIF_PORT_0, 4},
3503+ {"HIF Q5", ENUM_UMAC_HIF_PORT_0, 5},
3504+ {NULL, 0, 0}, {NULL, 0, 0}, /* 14~15 not defined */
3505+ {"LMAC Q", ENUM_UMAC_LMAC_PORT_2, 0},
3506+ {"MDP TX Q", ENUM_UMAC_LMAC_PORT_2, 1},
3507+ {"MDP RX Q", ENUM_UMAC_LMAC_PORT_2, 2},
3508+ {"SEC TX Q", ENUM_UMAC_LMAC_PORT_2, 3},
3509+ {"SEC RX Q", ENUM_UMAC_LMAC_PORT_2, 4},
3510+ {"SFD_PARK Q", ENUM_UMAC_LMAC_PORT_2, 5},
3511+ {"MDP_TXIOC Q", ENUM_UMAC_LMAC_PORT_2, 6},
3512+ {"MDP_RXIOC Q", ENUM_UMAC_LMAC_PORT_2, 7},
3513+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 24~30 not defined */
3514+ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, ENUM_UMAC_PLE_CTRL_P3_Q_0X1F}
3515+};
3516+
3517+static int mt7915_pseinfo_read(struct seq_file *s, void *data)
3518+{
3519+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3520+ u32 pse_buf_ctrl, pg_sz, pg_num;
3521+ u32 pse_stat, pg_flow_ctrl[22] = {0};
3522+ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail;
3523+ u32 max_q, min_q, rsv_pg, used_pg;
3524+ int i;
3525+
3526+ pse_buf_ctrl = mt76_rr(dev, MT_DBG_PSE_PBUF_CTRL);
3527+ pse_stat = mt76_rr(dev, MT_DBG_PSE_QUEUE_EMPTY);
3528+ pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PSE_FREEPG_CNT);
3529+ pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PSE_FREEPG_HEAD_TAIL);
3530+ pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PSE_PG_HIF0_GROUP);
3531+ pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PSE_HIF0_PG_INFO);
3532+ pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PSE_PG_HIF1_GROUP);
3533+ pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PSE_HIF1_PG_INFO);
3534+ pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PSE_PG_CPU_GROUP);
3535+ pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PSE_CPU_PG_INFO);
3536+ pg_flow_ctrl[8] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC0_GROUP);
3537+ pg_flow_ctrl[9] = mt76_rr(dev, MT_DBG_PSE_LMAC0_PG_INFO);
3538+ pg_flow_ctrl[10] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC1_GROUP);
3539+ pg_flow_ctrl[11] = mt76_rr(dev, MT_DBG_PSE_LMAC1_PG_INFO);
3540+ pg_flow_ctrl[12] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC2_GROUP);
3541+ pg_flow_ctrl[13] = mt76_rr(dev, MT_DBG_PSE_LMAC2_PG_INFO);
3542+ pg_flow_ctrl[14] = mt76_rr(dev, MT_DBG_PSE_PG_PLE_GROUP);
3543+ pg_flow_ctrl[15] = mt76_rr(dev, MT_DBG_PSE_PLE_PG_INFO);
3544+ pg_flow_ctrl[16] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC3_GROUP);
3545+ pg_flow_ctrl[17] = mt76_rr(dev, MT_DBG_PSE_LMAC3_PG_INFO);
3546+ pg_flow_ctrl[18] = mt76_rr(dev, MT_DBG_PSE_PG_MDP_GROUP);
3547+ pg_flow_ctrl[19] = mt76_rr(dev, MT_DBG_PSE_MDP_PG_INFO);
3548+ pg_flow_ctrl[20] = mt76_rr(dev, MT_DBG_PSE_PG_PLE1_GROUP);
3549+ pg_flow_ctrl[21] = mt76_rr(dev,MT_DBG_PSE_PLE1_PG_INFO);
3550+
3551+ /* Configuration Info */
3552+ seq_printf(s, "PSE Configuration Info:\n");
3553+ seq_printf(s, "\tPacket Buffer Control(0x82068014): 0x%08x\n", pse_buf_ctrl);
3554+ pg_sz = FIELD_GET(MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK, pse_buf_ctrl);
3555+
3556+ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n", pg_sz, (pg_sz == 1 ? 256 : 128));
3557+ seq_printf(s, "\t\tPage Offset=%ld(in unit of 64KB)\n",
3558+ FIELD_GET(MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK, pse_buf_ctrl));
3559+ pg_num = FIELD_GET(MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK, pse_buf_ctrl);
3560+
3561+ seq_printf(s, "\t\tTotal page numbers=%d pages\n", pg_num);
3562+
3563+ /* Page Flow Control */
3564+ seq_printf(s, "PSE Page Flow Control:\n");
3565+ seq_printf(s, "\tFree page counter(0x82068100): 0x%08x\n", pg_flow_ctrl[0]);
3566+ fpg_cnt = FIELD_GET(MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK, pg_flow_ctrl[0]);
3567+ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3568+
3569+ ffa_cnt = FIELD_GET(MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK, pg_flow_ctrl[0]);
3570+ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3571+
3572+ seq_printf(s, "\tFree page head and tail(0x82068104): 0x%08x\n", pg_flow_ctrl[1]);
3573+ fpg_head = FIELD_GET(MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK, pg_flow_ctrl[1]);
3574+
3575+ fpg_tail = FIELD_GET(MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK, pg_flow_ctrl[1]);
3576+ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3577+ seq_printf(s, "\tReserved page counter of HIF0 group(0x82068110): 0x%08x\n", pg_flow_ctrl[2]);
3578+ seq_printf(s, "\tHIF0 group page status(0x82068114): 0x%08x\n", pg_flow_ctrl[3]);
3579+ min_q = FIELD_GET(MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK, pg_flow_ctrl[2]);
3580+ max_q = FIELD_GET(MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK, pg_flow_ctrl[2]);
3581+ seq_printf(s, "\t\tThe max/min quota pages of HIF0 group=0x%03x/0x%03x\n", max_q, min_q);
3582+ rsv_pg = FIELD_GET(MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK, pg_flow_ctrl[3]);;
3583+ used_pg = FIELD_GET(MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK, pg_flow_ctrl[3]);
3584+ seq_printf(s, "\t\tThe used/reserved pages of HIF0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3585+ seq_printf(s, "\tReserved page counter of HIF1 group(0x82068118): 0x%08x\n", pg_flow_ctrl[4]);
3586+ seq_printf(s, "\tHIF1 group page status(0x8206811c): 0x%08x\n", pg_flow_ctrl[5]);
3587+ min_q = FIELD_GET(MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK, pg_flow_ctrl[4]);
3588+ max_q = FIELD_GET(MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK, pg_flow_ctrl[4]);
3589+ seq_printf(s, "\t\tThe max/min quota pages of HIF1 group=0x%03x/0x%03x\n", max_q, min_q);
3590+ rsv_pg = FIELD_GET(MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK, pg_flow_ctrl[5]);
3591+ used_pg = FIELD_GET(MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK, pg_flow_ctrl[5]);
3592+
3593+ seq_printf(s, "\t\tThe used/reserved pages of HIF1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3594+ seq_printf(s, "\tReserved page counter of CPU group(0x82068150): 0x%08x\n", pg_flow_ctrl[6]);
3595+ seq_printf(s, "\tCPU group page status(0x82068154): 0x%08x\n", pg_flow_ctrl[7]);
3596+ min_q = FIELD_GET(MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
3597+ max_q = FIELD_GET(MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK, pg_flow_ctrl[6]);
3598+ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", max_q, min_q);
3599+ rsv_pg = FIELD_GET(MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK, pg_flow_ctrl[7]);
3600+ used_pg = FIELD_GET(MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK, pg_flow_ctrl[7]);
3601+ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3602+ seq_printf(s, "\tReserved page counter of LMAC0 group(0x82068170): 0x%08x\n", pg_flow_ctrl[8]);
3603+ seq_printf(s, "\tLMAC0 group page status(0x82068174): 0x%08x\n", pg_flow_ctrl[9]);
3604+ min_q = FIELD_GET(MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK, pg_flow_ctrl[8]);
3605+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK, pg_flow_ctrl[8]);
3606+ seq_printf(s, "\t\tThe max/min quota pages of LMAC0 group=0x%03x/0x%03x\n", max_q, min_q);
3607+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK, pg_flow_ctrl[9]);
3608+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK, pg_flow_ctrl[9]);
3609+ seq_printf(s, "\t\tThe used/reserved pages of LMAC0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3610+ seq_printf(s, "\tReserved page counter of LMAC1 group(0x82068178): 0x%08x\n", pg_flow_ctrl[10]);
3611+ seq_printf(s, "\tLMAC1 group page status(0x8206817c): 0x%08x\n", pg_flow_ctrl[11]);
3612+ min_q = FIELD_GET(MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK, pg_flow_ctrl[10]);
3613+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK, pg_flow_ctrl[10]);
3614+ seq_printf(s, "\t\tThe max/min quota pages of LMAC1 group=0x%03x/0x%03x\n", max_q, min_q);
3615+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK, pg_flow_ctrl[11]);
3616+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK, pg_flow_ctrl[11]);
3617+ seq_printf(s, "\t\tThe used/reserved pages of LMAC1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3618+ seq_printf(s, "\tReserved page counter of LMAC2 group(0x82068180): 0x%08x\n", pg_flow_ctrl[11]);
3619+ seq_printf(s, "\tLMAC2 group page status(0x82068184): 0x%08x\n", pg_flow_ctrl[12]);
3620+ min_q = FIELD_GET(MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK, pg_flow_ctrl[12]);
3621+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK, pg_flow_ctrl[12]);
3622+ seq_printf(s, "\t\tThe max/min quota pages of LMAC2 group=0x%03x/0x%03x\n", max_q, min_q);
3623+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK, pg_flow_ctrl[13]);
3624+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK, pg_flow_ctrl[13]);
3625+ seq_printf(s, "\t\tThe used/reserved pages of LMAC2 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3626+
3627+ seq_printf(s, "\tReserved page counter of LMAC3 group(0x82068188): 0x%08x\n", pg_flow_ctrl[16]);
3628+ seq_printf(s, "\tLMAC3 group page status(0x8206818c): 0x%08x\n", pg_flow_ctrl[17]);
3629+ min_q = FIELD_GET(MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK, pg_flow_ctrl[16]);
3630+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK, pg_flow_ctrl[16]);
3631+ seq_printf(s, "\t\tThe max/min quota pages of LMAC3 group=0x%03x/0x%03x\n", max_q, min_q);
3632+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK, pg_flow_ctrl[17]);
3633+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK, pg_flow_ctrl[17]);
3634+ seq_printf(s, "\t\tThe used/reserved pages of LMAC3 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3635+
3636+ seq_printf(s, "\tReserved page counter of PLE group(0x82068160): 0x%08x\n", pg_flow_ctrl[14]);
3637+ seq_printf(s, "\tPLE group page status(0x82068164): 0x%08x\n", pg_flow_ctrl[15]);
3638+ min_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK, pg_flow_ctrl[14]);
3639+ max_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK, pg_flow_ctrl[14]);
3640+ seq_printf(s, "\t\tThe max/min quota pages of PLE group=0x%03x/0x%03x\n", max_q, min_q);
3641+ rsv_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK, pg_flow_ctrl[15]);
3642+ used_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK, pg_flow_ctrl[15]);
3643+ seq_printf(s, "\t\tThe used/reserved pages of PLE group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3644+
3645+ seq_printf(s, "\tReserved page counter of PLE1 group(0x82068168): 0x%08x\n", pg_flow_ctrl[14]);
3646+ seq_printf(s, "\tPLE1 group page status(0x8206816c): 0x%08x\n", pg_flow_ctrl[15]);
3647+ min_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK, pg_flow_ctrl[20]);
3648+ max_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK, pg_flow_ctrl[20]);
3649+ seq_printf(s, "\t\tThe max/min quota pages of PLE1 group=0x%03x/0x%03x\n", max_q, min_q);
3650+ rsv_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK, pg_flow_ctrl[21]);
3651+ used_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK, pg_flow_ctrl[21]);
3652+ seq_printf(s, "\t\tThe used/reserved pages of PLE1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3653+
3654+ seq_printf(s, "\tReserved page counter of MDP group(0x82068198): 0x%08x\n", pg_flow_ctrl[18]);
3655+ seq_printf(s, "\tMDP group page status(0x8206819c): 0x%08x\n", pg_flow_ctrl[19]);
3656+ min_q = FIELD_GET(MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK, pg_flow_ctrl[18]);
3657+ max_q = FIELD_GET(MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK, pg_flow_ctrl[18]);
3658+ seq_printf(s, "\t\tThe max/min quota pages of MDP group=0x%03x/0x%03x\n", max_q, min_q);
3659+ rsv_pg = FIELD_GET(MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK, pg_flow_ctrl[19]);
3660+ used_pg = FIELD_GET(MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK, pg_flow_ctrl[19]);
3661+ seq_printf(s, "\t\tThe used/reserved pages of MDP group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3662+
3663+ /* Queue Empty Status */
3664+ seq_printf(s, "PSE Queue Empty Status:\n");
3665+ seq_printf(s, "\tQUEUE_EMPTY(0x820680b0): 0x%08x\n", pse_stat);
3666+ seq_printf(s, "\t\tCPU Q0/1/2/3 empty=%ld/%ld/%ld/%ld\n",
3667+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK, pse_stat),
3668+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK, pse_stat),
3669+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK, pse_stat),
3670+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK, pse_stat));
3671+
3672+ seq_printf(s, "\t\tHIF Q0/1/2/3/4/5 empty=%ld/%ld/%ld/%ld/%ld/%ld\n",
3673+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK, pse_stat),
3674+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK, pse_stat),
3675+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK, pse_stat),
3676+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK, pse_stat),
3677+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK, pse_stat),
3678+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK, pse_stat));
3679+
3680+ seq_printf(s, "\t\tLMAC TX Q empty=%ld\n",
3681+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK, pse_stat));
3682+ seq_printf(s, "\t\tMDP TX Q/RX Q empty=%ld/%ld\n",
3683+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK, pse_stat),
3684+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK, pse_stat));
3685+ seq_printf(s, "\t\tSEC TX Q/RX Q empty=%ld/%ld\n",
3686+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK, pse_stat),
3687+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT, pse_stat));
3688+ seq_printf(s, "\t\tSFD PARK Q empty=%ld\n",
3689+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK, pse_stat));
3690+ seq_printf(s, "\t\tMDP TXIOC Q/RXIOC Q empty=%ld/%ld\n",
3691+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK, pse_stat),
3692+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK, pse_stat));
3693+ seq_printf(s, "\t\tRLS Q empty=%ld\n",
3694+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK, pse_stat));
3695+ seq_printf(s, "Nonempty Q info:\n");
3696+
3697+ for (i = 0; i < 31; i++) {
3698+ if (((pse_stat & (0x1 << i)) >> i) == 0) {
3699+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3700+
3701+ if (pse_queue_empty_info[i].QueueName != NULL) {
3702+ seq_printf(s, "\t%s: ", pse_queue_empty_info[i].QueueName);
3703+ fl_que_ctrl[0] |= MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK;
3704+ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Portid << MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT);
3705+ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Queueid << MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT);
3706+ } else
3707+ continue;
3708+
3709+ fl_que_ctrl[0] |= (0x1 << 31);
3710+
3711+ mt76_wr(dev, MT_DBG_PSE_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]);
3712+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PSE_FL_QUE_CTRL_2_ADDR);
3713+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PSE_FL_QUE_CTRL_3_ADDR);
3714+
3715+ hfid = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK, fl_que_ctrl[1]);
3716+ tfid = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK, fl_que_ctrl[1]);
3717+ pktcnt = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK, fl_que_ctrl[2]);
3718+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3719+ tfid, hfid, pktcnt);
3720+ }
3721+ }
3722+
3723+ return 0;
3724+}
3725+
3726+static int mt7915_mibinfo_read_per_band(struct seq_file *s, int band_idx)
3727+{
3728+#define BSS_NUM 4
3729+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3730+ u32 mac_val0, mac_val, mac_val1, idx, band_offset = 0;
3731+ u32 msdr6, msdr7, msdr8, msdr9, msdr10, msdr16, msdr17, msdr18, msdr19, msdr20, msdr21;
3732+ u32 mbxsdr[BSS_NUM][7];
3733+ u32 mbtcr[16], mbtbcr[16], mbrcr[16], mbrbcr[16];
3734+ u32 btcr[BSS_NUM], btbcr[BSS_NUM], brcr[BSS_NUM], brbcr[BSS_NUM], btdcr[BSS_NUM], brdcr[BSS_NUM];
3735+ u32 mu_cnt[5];
3736+ u32 ampdu_cnt[3];
3737+ unsigned long per;
3738+
3739+ seq_printf(s, "Band %d MIB Status\n", band_idx);
3740+ seq_printf(s, "===============================\n");
3741+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SCR0(band_idx));
3742+ seq_printf(s, "MIB Status Control=0x%x\n", mac_val);
3743+ if (is_mt7915(&dev->mt76)) {
3744+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0PBSCR(band_idx));
3745+ seq_printf(s, "MIB Per-BSS Status Control=0x%x\n", mac_val);
3746+ }
3747+
3748+ msdr6 = mt76_rr(dev, MT_DBG_MIB_M0SDR6(band_idx));
3749+ msdr7 = mt76_rr(dev, MT_DBG_MIB_M0SDR7(band_idx));
3750+ msdr8 = mt76_rr(dev, MT_DBG_MIB_M0SDR8(band_idx));
3751+ msdr9 = mt76_rr(dev, MT_DBG_MIB_M0SDR9(band_idx));
3752+ msdr10 = mt76_rr(dev, MT_DBG_MIB_M0SDR10(band_idx));
3753+ msdr16 = mt76_rr(dev, MT_DBG_MIB_M0SDR16(band_idx));
3754+ msdr17 = mt76_rr(dev, MT_DBG_MIB_M0SDR17(band_idx));
3755+ msdr18 = mt76_rr(dev, MT_DBG_MIB_M0SDR18(band_idx));
3756+ msdr19 = mt76_rr(dev, MT_DBG_MIB_M0SDR19(band_idx));
3757+ msdr20 = mt76_rr(dev, MT_DBG_MIB_M0SDR20(band_idx));
3758+ msdr21 = mt76_rr(dev, MT_DBG_MIB_M0SDR21(band_idx));
3759+ ampdu_cnt[0] = mt76_rr(dev, MT_DBG_MIB_M0SDR12(band_idx));
3760+ ampdu_cnt[1] = mt76_rr(dev, MT_DBG_MIB_M0SDR14(band_idx));
3761+ ampdu_cnt[2] = mt76_rr(dev, MT_DBG_MIB_M0SDR15(band_idx));
3762+ ampdu_cnt[1] &= MT_DBG_MIB_M0SDR14_AMPDU_MASK;
3763+ ampdu_cnt[2] &= MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK;
3764+
3765+ seq_printf(s, "===Phy/Timing Related Counters===\n");
3766+ seq_printf(s, "\tChannelIdleCnt=0x%x\n", msdr6 & BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK);
3767+ seq_printf(s, "\tCCA_NAV_Tx_Time=0x%x\n", msdr9 & BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK);
3768+ seq_printf(s, "\tRx_MDRDY_CNT=0x%lx\n", msdr10 & MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK);
3769+ seq_printf(s, "\tCCK_MDRDY_TIME=0x%x, OFDM_MDRDY_TIME=0x%x, OFDM_GREEN_MDRDY_TIME=0x%x\n",
3770+ msdr19 & BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK,
3771+ msdr20 & BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK,
3772+ msdr21 & BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK);
3773+ seq_printf(s, "\tPrim CCA Time=0x%x\n", msdr16 & BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK);
3774+ seq_printf(s, "\tSec CCA Time=0x%x\n", msdr17 & BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK);
3775+ seq_printf(s, "\tPrim ED Time=0x%x\n", msdr18 & BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK);
3776+
3777+ seq_printf(s, "===Tx Related Counters(Generic)===\n");
3778+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR0(band_idx));
3779+ dev->dbg.bcn_total_cnt[band_idx] += (mac_val & BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK);
3780+ seq_printf(s, "\tBeaconTxCnt=0x%x\n",dev->dbg.bcn_total_cnt[band_idx]);
3781+ dev->dbg.bcn_total_cnt[band_idx] = 0;
3782+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR0(band_idx));
3783+ seq_printf(s, "\tTx 20MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK);
3784+ seq_printf(s, "\tTx 40MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT);
3785+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR1(band_idx));
3786+ seq_printf(s, "\tTx 80MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK);
3787+ seq_printf(s, "\tTx 160MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT);
3788+ seq_printf(s, "\tAMPDU Cnt=0x%x\n", ampdu_cnt[0]);
3789+ seq_printf(s, "\tAMPDU MPDU Cnt=0x%x\n", ampdu_cnt[1]);
3790+ seq_printf(s, "\tAMPDU MPDU Ack Cnt=0x%x\n", ampdu_cnt[2]);
3791+ per = (ampdu_cnt[2] == 0 ? 0 : 1000 * (ampdu_cnt[1] - ampdu_cnt[2]) / ampdu_cnt[1]);
3792+ seq_printf(s, "\tAMPDU MPDU PER=%ld.%1ld%%\n", per / 10, per % 10);
3793+
3794+ seq_printf(s, "===MU Related Counters===\n");
3795+ mu_cnt[0] = mt76_rr(dev, MT_DBG_MIB_MUBF(band_idx));
3796+ mu_cnt[1] = mt76_rr(dev, MT_DBG_MIB_M0DR8(band_idx));
3797+ mu_cnt[2] = mt76_rr(dev, MT_DBG_MIB_M0DR9(band_idx));
3798+ mu_cnt[3] = mt76_rr(dev, MT_DBG_MIB_M0DR10(band_idx));
3799+ mu_cnt[4] = mt76_rr(dev, MT_DBG_MIB_M0DR11(band_idx));
3800+ seq_printf(s, "\tMUBF_TX_COUNT=0x%x\n", mu_cnt[0] & BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK);
3801+ seq_printf(s, "\tMU_TX_MPDU_COUNT(Ok+Fail)=0x%x\n", mu_cnt[1]);
3802+ seq_printf(s, "\tMU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[2]);
3803+ seq_printf(s, "\tMU_TO_SU_PPDU_COUNT=0x%x\n", mu_cnt[3] & BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK);
3804+ seq_printf(s, "\tSU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[4]);
3805+
3806+ seq_printf(s, "===Rx Related Counters(Generic)===\n");
3807+ seq_printf(s, "\tVector Mismacth Cnt=0x%x\n", msdr7 & BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK);
3808+ seq_printf(s, "\tDelimiter Fail Cnt=0x%x\n", msdr8 & BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK);
3809+
3810+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR3(band_idx));
3811+ seq_printf(s, "\tRxFCSErrCnt=0x%lx\n", __DBG_FIELD_GET(DBG_MIB_RX_FCS_ERROR_COUNT, mac_val));
3812+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR4(band_idx));
3813+ seq_printf(s, "\tRxFifoFullCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK));
3814+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR11(band_idx));
3815+ seq_printf(s, "\tRxLenMismatch=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK));
3816+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR5(band_idx));
3817+ seq_printf(s, "\tRxMPDUCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK));
3818+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR22(band_idx));
3819+ seq_printf(s, "\tRx AMPDU Cnt=0x%x\n", mac_val);
3820+ /* TODO: shiang-MT7615, is MIB_M0SDR23 used for Rx total byte count for all or just AMPDU only??? */
3821+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR23(band_idx));
3822+ seq_printf(s, "\tRx Total ByteCnt=0x%x\n", mac_val);
3823+
3824+ if (is_mt7915(&dev->mt76)) {
3825+ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;//check
3826+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3827+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
3828+
3829+ for (idx = 0; idx < BSS_NUM; idx++) {
3830+ btcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTCRn_ADDR + band_offset + idx * 4);
3831+ btbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTBCRn_ADDR + band_offset + idx * 4);
3832+ brcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRCRn_ADDR + band_offset + idx * 4);
3833+ brbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRBCRn_ADDR + band_offset + idx * 4);
3834+ btdcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTDCRn_ADDR + band_offset + idx * 4);
3835+ brdcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRDCRn_ADDR + band_offset + idx * 4);
3836+ }
3837+
3838+ for (idx = 0; idx < BSS_NUM; idx++) {
3839+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3840+ idx, btcr[idx], btdcr[idx], btbcr[idx],
3841+ brcr[idx], brdcr[idx], brbcr[idx]);
3842+ }
3843+
3844+ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
3845+ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
3846+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3847+
3848+ for (idx = 0; idx < BSS_NUM; idx++) {
3849+ mbxsdr[idx][0] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR0_ADDR + band_offset + idx * 0x10);
3850+ mbxsdr[idx][1] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR1_ADDR + band_offset + idx * 0x10);
3851+ mbxsdr[idx][2] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR2_ADDR + band_offset + idx * 0x10);
3852+ mbxsdr[idx][3] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR3_ADDR + band_offset + idx * 0x10);
3853+ }
3854+
3855+ for (idx = 0; idx < BSS_NUM; idx++) {
3856+ seq_printf(s, "%d:\t0x%08x/0x%08x 0x%08x \t 0x%08x \t 0x%08x/0x%08x/0x%08x\n",
3857+ idx, (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK),
3858+ (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT,
3859+ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK),
3860+ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT,
3861+ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK),
3862+ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT,
3863+ (mbxsdr[idx][3] & BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK));
3864+ }
3865+
3866+ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;
3867+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3868+ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
3869+
3870+ for (idx = 0; idx < 16; idx++) {
3871+ mbtcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBTCRn_ADDR + band_offset + idx * 4);
3872+ mbtbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBTBCRn_ADDR + band_offset + idx * 4);
3873+ mbrcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBRCRn_ADDR + band_offset + idx * 4);
3874+ mbrbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBRBCRn_ADDR + band_offset + idx * 4);
3875+ }
3876+
3877+ for (idx = 0; idx < 16; idx++) {
3878+ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
3879+ idx, mbtcr[idx], mbtbcr[idx], mbrcr[idx], mbrbcr[idx]);
3880+ }
3881+ return 0;
3882+ } else {
3883+ u32 btocr[BSS_NUM], mbtocr[16],mbrocr[16], brocr[BSS_NUM];
3884+ u8 bss_nums = BSS_NUM;
3885+
3886+ band_offset = (BN1_WF_MIB_TOP_BTOCR_ADDR - BN0_WF_MIB_TOP_BTOCR_ADDR) * band_idx;
3887+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3888+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
3889+
3890+ for (idx = 0; idx < BSS_NUM; idx++) {
3891+ btocr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (idx >> 1) * 4));
3892+ btdcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTDCR_ADDR + band_offset + (idx >> 1) * 4));
3893+ btbcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (idx * 4)));
3894+ brocr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BROCR_ADDR + band_offset + (idx >> 1) * 4));
3895+ brdcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BRDCR_ADDR + band_offset + (idx >> 1) * 4));
3896+ brbcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BRBCR_ADDR + band_offset + (idx * 4)));
3897+
3898+ if ((idx % 2) == 0) {
3899+ btocr[idx] = ((btocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT);
3900+ btdcr[idx] = ((btdcr[idx] & BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT);
3901+ brocr[idx] = ((brocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT);
3902+ brdcr[idx] = ((brdcr[idx] & BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT);
3903+ } else {
3904+ btocr[idx] = ((btocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT);
3905+ btdcr[idx] = ((btdcr[idx] & BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT);
3906+ brocr[idx] = ((brocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT);
3907+ brdcr[idx] = ((brdcr[idx] & BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT);
3908+ }
3909+ }
3910+
3911+ for (idx = 0; idx < BSS_NUM; idx++) {
3912+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3913+ idx, btocr[idx], btdcr[idx], btbcr[idx], brocr[idx], brdcr[idx], brbcr[idx]);
3914+ }
3915+
3916+ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
3917+ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
3918+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3919+
3920+ for (idx = 0; idx < BSS_NUM; idx++) {
3921+ mbxsdr[idx][0] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR0_ADDR + band_offset + ((idx >> 1) * 4));
3922+ mbxsdr[idx][1] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR1_ADDR + band_offset + ((idx >> 1) * 4));
3923+ mbxsdr[idx][2] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR2_ADDR + band_offset + ((idx >> 1) * 4));
3924+ mbxsdr[idx][3] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR3_ADDR + band_offset + ((idx >> 1) * 4));
3925+ mbxsdr[idx][4] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR4_ADDR + band_offset + ((idx >> 1) * 4));
3926+ mbxsdr[idx][5] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR5_ADDR + band_offset + ((idx >> 1) * 4));
3927+ mbxsdr[idx][6] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR6_ADDR + band_offset + ((idx >> 1) * 4));
3928+
3929+ if ((idx % 2) == 0) {
3930+ mbxsdr[idx][0] = ((mbxsdr[idx][0] & BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT);
3931+ mbxsdr[idx][1] = ((mbxsdr[idx][1] & BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT);
3932+ mbxsdr[idx][2] = ((mbxsdr[idx][2] & BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT);
3933+ mbxsdr[idx][3] = ((mbxsdr[idx][3] & BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT);
3934+ mbxsdr[idx][4] = ((mbxsdr[idx][4] & BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT);
3935+ mbxsdr[idx][5] = ((mbxsdr[idx][5] & BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT);
3936+ mbxsdr[idx][6] = ((mbxsdr[idx][6] & BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT);
3937+ } else {
3938+ mbxsdr[idx][0] = ((mbxsdr[idx][0] & BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT);
3939+ mbxsdr[idx][1] = ((mbxsdr[idx][1] & BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT);
3940+ mbxsdr[idx][2] = ((mbxsdr[idx][2] & BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT);
3941+ mbxsdr[idx][3] = ((mbxsdr[idx][3] & BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT);
3942+ mbxsdr[idx][4] = ((mbxsdr[idx][4] & BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT);
3943+ mbxsdr[idx][5] = ((mbxsdr[idx][5] & BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT);
3944+ mbxsdr[idx][6] = ((mbxsdr[idx][6] & BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT);
3945+ }
3946+ }
3947+
3948+ for (idx = 0; idx < BSS_NUM; idx++) {
3949+ seq_printf(s, "%d:\t0x%x/0x%x 0x%x \t 0x%x \t 0x%x/0x%x/0x%x\n",
3950+ idx,
3951+ mbxsdr[idx][0], mbxsdr[idx][1], mbxsdr[idx][2], mbxsdr[idx][3],
3952+ mbxsdr[idx][4], mbxsdr[idx][5], mbxsdr[idx][6]);
3953+ }
3954+
3955+ band_offset = (BN1_WF_MIB_TOP_BTOCR_ADDR - BN0_WF_MIB_TOP_BTOCR_ADDR) * band_idx;
3956+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3957+ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
3958+
3959+ for (idx = 0; idx < 16; idx++) {
3960+ mbtocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + ((idx >> 1) * 4)));
3961+ mbtbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + (idx * 4)));
3962+ mbrocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BROCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + ((idx >> 1) * 4)));
3963+ mbrbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BRBCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + (idx * 4)));
3964+
3965+ if ((idx % 2) == 0) {
3966+ mbtocr[idx] = ((mbtocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT);
3967+ mbrocr[idx] = ((mbrocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT);
3968+ } else {
3969+ mbtocr[idx] = ((mbtocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT);
3970+ mbrocr[idx] = ((mbrocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT);
3971+ }
3972+ }
3973+
3974+ for (idx = 0; idx < 16; idx++) {
3975+ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
3976+ idx, mbtocr[idx], mbtbcr[idx], mbrocr[idx], mbrbcr[idx]);
3977+ }
3978+ }
3979+
3980+ seq_printf(s, "===Dummy delimiter insertion result===\n");
3981+ mac_val0 = mt76_rr(dev, MT_DBG_MIB_M0DR11(band_idx));
3982+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR6(band_idx));
3983+ mac_val1 = mt76_rr(dev, MT_DBG_MIB_M0DR7(band_idx));
3984+ seq_printf(s, "Range0 = %d\t Range1 = %d\t Range2 = %d\t Range3 = %d\t Range4 = %d\n",
3985+ (mac_val0 & BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK),
3986+ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK),
3987+ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT,
3988+ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK),
3989+ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT);
3990+
3991+ return 0;
3992+}
3993+
3994+static int mt7915_mibinfo_band0(struct seq_file *s, void *data)
3995+{
3996+ mt7915_mibinfo_read_per_band(s, 0);
3997+ return 0;
3998+}
3999+
4000+static int mt7915_mibinfo_band1(struct seq_file *s, void *data)
4001+{
4002+ mt7915_mibinfo_read_per_band(s, 1);
4003+ return 0;
4004+}
4005+
4006+static int mt7915_token_read(struct seq_file *s, void *data)
4007+{
4008+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4009+ int id, count = 0;
4010+ struct mt76_txwi_cache *txwi;
4011+
4012+ seq_printf(s, "Cut through token:\n");
4013+ spin_lock_bh(&dev->mt76.token_lock);
4014+ idr_for_each_entry(&dev->mt76.token, txwi, id) {
4015+ seq_printf(s, "%4d ", id);
4016+ count++;
4017+ if (count % 8 == 0)
4018+ seq_printf(s, "\n");
4019+ }
4020+ spin_unlock_bh(&dev->mt76.token_lock);
4021+ seq_printf(s, "\n");
4022+
4023+ return 0;
4024+}
4025+
4026+struct txd_l {
4027+ u32 txd_0;
4028+ u32 txd_1;
4029+ u32 txd_2;
4030+ u32 txd_3;
4031+ u32 txd_4;
4032+ u32 txd_5;
4033+ u32 txd_6;
4034+ u32 txd_7;
4035+} __packed;
4036+
4037+char *pkt_ft_str[] = {"cut_through", "store_forward", "cmd", "PDA_FW_Download"};
4038+char *hdr_fmt_str[] = {
4039+ "Non-80211-Frame",
4040+ "Command-Frame",
4041+ "Normal-80211-Frame",
4042+ "enhanced-80211-Frame",
4043+};
4044+/* TMAC_TXD_1.hdr_format */
4045+#define TMI_HDR_FT_NON_80211 0x0
4046+#define TMI_HDR_FT_CMD 0x1
4047+#define TMI_HDR_FT_NOR_80211 0x2
4048+#define TMI_HDR_FT_ENH_80211 0x3
4049+
4050+void mt7915_dump_tmac_info(u8 *tmac_info)
4051+{
4052+ struct txd_l *txd = (struct txd_l *)tmac_info;
4053+
4054+ printk("txd raw data: size=%d\n", MT_TXD_SIZE);
4055+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, tmac_info, MT_TXD_SIZE, false);
4056+
4057+ printk("TMAC_TXD Fields:\n");
4058+ printk("\tTMAC_TXD_0:\n");
4059+
4060+ /* DW0 */
4061+ /* TX Byte Count [15:0] */
4062+ printk("\t\tTxByteCnt = %ld\n", FIELD_GET(MT_TXD0_TX_BYTES, txd->txd_0));
4063+
4064+ /* PKT_FT: Packet Format [24:23] */
4065+ printk("\t\tpkt_ft = %ld(%s)\n",
4066+ FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0),
4067+ pkt_ft_str[FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0)]);
4068+
4069+ /* Q_IDX [31:25] */
4070+ printk("\t\tQueID =0x%lx\n", FIELD_GET(MT_TXD0_Q_IDX, txd->txd_0));
4071+
4072+ printk("\tTMAC_TXD_1:\n");
4073+
4074+ /* DW1 */
4075+ /* WLAN Indec [9:0] */
4076+ printk("\t\tWlan Index = %ld\n", FIELD_GET(MT_TXD1_WLAN_IDX, txd->txd_1));
4077+
4078+ /* VTA [10] */
4079+ printk("\t\tVTA = %d\n", ((txd->txd_1 & MT_TXD1_VTA) ? 1 : 0));
4080+
4081+ /* HF: Header Format [17:16] */
4082+ printk("\t\tHdrFmt = %ld(%s)\n",
4083+ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1),
4084+ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1) < 4 ?
4085+ hdr_fmt_str[FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)] : "N/A");
4086+
4087+ switch (FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)) {
4088+ case TMI_HDR_FT_NON_80211:
4089+ /* MRD [11], EOSP [12], RMVL [13], VLAN [14], ETYPE [15] */
4090+ printk("\t\t\tMRD = %d, EOSP = %d,\
4091+ RMVL = %d, VLAN = %d, ETYP = %d\n",
4092+ (txd->txd_1 & MT_TXD1_MRD) ? 1 : 0,
4093+ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
4094+ (txd->txd_1 & MT_TXD1_RMVL) ? 1 : 0,
4095+ (txd->txd_1 & MT_TXD1_VLAN) ? 1 : 0,
4096+ (txd->txd_1 & MT_TXD1_ETYP) ? 1 : 0);
4097+ break;
4098+ case TMI_HDR_FT_NOR_80211:
4099+ /* HEADER_LENGTH [15:11] */
4100+ printk("\t\t\tHeader Len = %ld(WORD)\n", FIELD_GET(MT_TXD1_HDR_INFO, txd->txd_1));
4101+ break;
4102+
4103+ case TMI_HDR_FT_ENH_80211:
4104+ /* EOSP [12], AMS [13] */
4105+ printk("\t\t\tEOSP = %d, AMS = %d\n",
4106+ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
4107+ (txd->txd_1 & MT_TXD1_AMS) ? 1 : 0);
4108+ break;
4109+ }
4110+
4111+ /* Header Padding [19:18] */
4112+ printk("\t\tHdrPad = %ld\n", FIELD_GET(MT_TXD1_HDR_PAD, txd->txd_1));
4113+
4114+ /* TID [22:20] */
4115+ printk("\t\tTID = %ld\n", FIELD_GET(MT_TXD1_TID, txd->txd_1));
4116+
4117+
4118+ /* UtxB/AMSDU_C/AMSDU [23] */
4119+ printk("\t\tamsdu = %d\n", ((txd->txd_1 & MT_TXD1_AMSDU) ? 1 : 0));
4120+
4121+ /* OM [29:24] */
4122+ printk("\t\town_mac = %ld\n", FIELD_GET(MT_TXD1_OWN_MAC, txd->txd_1));
4123+
4124+
4125+ /* TGID [30] */
4126+ printk("\t\tTGID = %d\n", ((txd->txd_1 & MT_TXD1_TGID) ? 1 : 0));
4127+
4128+
4129+ /* FT [31] */
4130+ printk("\t\tTxDFormatType = %d\n", (txd->txd_1 & MT_TXD1_LONG_FORMAT) ? 1 : 0);
4131+
4132+ printk("\tTMAC_TXD_2:\n");
4133+ /* DW2 */
4134+ /* Subtype [3:0] */
4135+ printk("\t\tsub_type = %ld\n", FIELD_GET(MT_TXD2_SUB_TYPE, txd->txd_2));
4136+
4137+ /* Type[5:4] */
4138+ printk("\t\tfrm_type = %ld\n", FIELD_GET(MT_TXD2_FRAME_TYPE, txd->txd_2));
4139+
4140+ /* NDP [6] */
4141+ printk("\t\tNDP = %d\n", ((txd->txd_2 & MT_TXD2_NDP) ? 1 : 0));
4142+
4143+ /* NDPA [7] */
4144+ printk("\t\tNDPA = %d\n", ((txd->txd_2 & MT_TXD2_NDPA) ? 1 : 0));
4145+
4146+ /* SD [8] */
4147+ printk("\t\tSounding = %d\n", ((txd->txd_2 & MT_TXD2_SOUNDING) ? 1 : 0));
4148+
4149+ /* RTS [9] */
4150+ printk("\t\tRTS = %d\n", ((txd->txd_2 & MT_TXD2_RTS) ? 1 : 0));
4151+
4152+ /* BM [10] */
4153+ printk("\t\tbc_mc_pkt = %d\n", ((txd->txd_2 & MT_TXD2_MULTICAST) ? 1 : 0));
4154+
4155+ /* B [11] */
4156+ printk("\t\tBIP = %d\n", ((txd->txd_2 & MT_TXD2_BIP) ? 1 : 0));
4157+
4158+ /* DU [12] */
4159+ printk("\t\tDuration = %d\n", ((txd->txd_2 & MT_TXD2_DURATION) ? 1 : 0));
4160+
4161+ /* HE [13] */
4162+ printk("\t\tHE(HTC Exist) = %d\n", ((txd->txd_2 & MT_TXD2_HTC_VLD) ? 1 : 0));
4163+
4164+ /* FRAG [15:14] */
4165+ printk("\t\tFRAG = %ld\n", FIELD_GET(MT_TXD2_FRAG, txd->txd_2));
4166+
4167+
4168+ /* Remaining Life Time [23:16]*/
4169+ printk("\t\tReamingLife/MaxTx time = %ld (unit: 64TU)\n",
4170+ FIELD_GET(MT_TXD2_MAX_TX_TIME, txd->txd_2));
4171+
4172+ /* Power Offset [29:24] */
4173+ printk("\t\tpwr_offset = %ld\n", FIELD_GET(MT_TXD2_POWER_OFFSET, txd->txd_2));
4174+
4175+ /* FRM [30] */
4176+ printk("\t\tfix rate mode = %d\n", (txd->txd_2 & MT_TXD2_FIXED_RATE) ? 1 : 0);
4177+
4178+ /* FR[31] */
4179+ printk("\t\tfix rate = %d\n", (txd->txd_2 & MT_TXD2_FIX_RATE) ? 1 : 0);
4180+
4181+
4182+ printk("\tTMAC_TXD_3:\n");
4183+
4184+ /* DW3 */
4185+ /* NA [0] */
4186+ printk("\t\tNoAck = %d\n", (txd->txd_3 & MT_TXD3_NO_ACK) ? 1 : 0);
4187+
4188+ /* PF [1] */
4189+ printk("\t\tPF = %d\n", (txd->txd_3 & MT_TXD3_PROTECT_FRAME) ? 1 : 0);
4190+
4191+ /* EMRD [2] */
4192+ printk("\t\tEMRD = %d\n", (txd->txd_3 & MT_TXD3_EMRD) ? 1 : 0);
4193+
4194+ /* EEOSP [3] */
4195+ printk("\t\tEEOSP = %d\n", (txd->txd_3 & MT_TXD3_EEOSP) ? 1 : 0);
4196+
4197+ /* DAS [4] */
4198+ printk("\t\tda_select = %d\n", (txd->txd_3 & MT_TXD3_DAS) ? 1 : 0);
4199+
4200+ /* TM [5] */
4201+ printk("\t\ttm = %d\n", (txd->txd_3 & MT_TXD3_TIMING_MEASURE) ? 1 : 0);
4202+
4203+ /* TX Count [10:6] */
4204+ printk("\t\ttx_cnt = %ld\n", FIELD_GET(MT_TXD3_TX_COUNT, txd->txd_3));
4205+
4206+ /* Remaining TX Count [15:11] */
4207+ printk("\t\tremain_tx_cnt = %ld\n", FIELD_GET(MT_TXD3_REM_TX_COUNT, txd->txd_3));
4208+
4209+ /* SN [27:16] */
4210+ printk("\t\tsn = %ld\n", FIELD_GET(MT_TXD3_SEQ, txd->txd_3));
4211+
4212+ /* BA_DIS [28] */
4213+ printk("\t\tba dis = %d\n", (txd->txd_3 & MT_TXD3_BA_DISABLE) ? 1 : 0);
4214+
4215+ /* Power Management [29] */
4216+ printk("\t\tpwr_mgmt = 0x%x\n", (txd->txd_3 & MT_TXD3_SW_POWER_MGMT) ? 1 : 0);
4217+
4218+ /* PN_VLD [30] */
4219+ printk("\t\tpn_vld = %d\n", (txd->txd_3 & MT_TXD3_PN_VALID) ? 1 : 0);
4220+
4221+ /* SN_VLD [31] */
4222+ printk("\t\tsn_vld = %d\n", (txd->txd_3 & MT_TXD3_SN_VALID) ? 1 : 0);
4223+
4224+
4225+ /* DW4 */
4226+ printk("\tTMAC_TXD_4:\n");
4227+
4228+ /* PN_LOW [31:0] */
4229+ printk("\t\tpn_low = 0x%lx\n", FIELD_GET(MT_TXD4_PN_LOW, txd->txd_4));
4230+
4231+
4232+ /* DW5 */
4233+ printk("\tTMAC_TXD_5:\n");
4234+
4235+ /* PID [7:0] */
4236+ printk("\t\tpid = %ld\n", FIELD_GET(MT_TXD5_PID, txd->txd_5));
4237+
4238+ /* TXSFM [8] */
4239+ printk("\t\ttx_status_fmt = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_FMT) ? 1 : 0);
4240+
4241+ /* TXS2M [9] */
4242+ printk("\t\ttx_status_2_mcu = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_MCU) ? 1 : 0);
4243+
4244+ /* TXS2H [10] */
4245+ printk("\t\ttx_status_2_host = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_HOST) ? 1 : 0);
4246+
4247+ /* ADD_BA [14] */
4248+ printk("\t\tADD_BA = %d\n", (txd->txd_5 & MT_TXD5_ADD_BA) ? 1 : 0);
4249+
4250+ /* MD [15] */
4251+ printk("\t\tMD = %d\n", (txd->txd_5 & MT_TXD5_MD) ? 1 : 0);
4252+
4253+ /* PN_HIGH [31:16] */
4254+ printk("\t\tpn_high = 0x%lx\n", FIELD_GET(MT_TXD5_PN_HIGH, txd->txd_5));
4255+
4256+ /* DW6 */
4257+ printk("\tTMAC_TXD_6:\n");
4258+
4259+ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4260+ /* Fixed BandWidth mode [2:0] */
developer2aa1e642022-12-19 11:33:22 +08004261+ printk("\t\tbw = %ld\n",
4262+ FIELD_GET(MT_TXD6_BW, txd->txd_6) | (txd->txd_6 & MT_TXD6_FIXED_BW));
developer3fa816c2022-04-19 10:21:20 +08004263+
4264+ /* DYN_BW [3] */
4265+ printk("\t\tdyn_bw = %d\n", (txd->txd_6 & MT_TXD6_DYN_BW) ? 1 : 0);
4266+
4267+ /* ANT_ID [7:4] */
4268+ printk("\t\tant_id = %ld\n", FIELD_GET(MT_TXD6_ANT_ID, txd->txd_6));
4269+
4270+ /* SPE_IDX_SEL [10] */
4271+ printk("\t\tspe_idx_sel = %d\n", (txd->txd_6 & MT_TXD6_SPE_ID_IDX) ? 1 : 0);
4272+
4273+ /* LDPC [11] */
4274+ printk("\t\tldpc = %d\n", (txd->txd_6 & MT_TXD6_LDPC) ? 1 : 0);
4275+
4276+ /* HELTF Type[13:12] */
4277+ printk("\t\tHELTF Type = %ld\n", FIELD_GET(MT_TXD6_HELTF, txd->txd_6));
4278+
4279+ /* GI Type [15:14] */
4280+ printk("\t\tGI = %ld\n", FIELD_GET(MT_TXD6_SGI, txd->txd_6));
4281+
4282+ /* Rate to be Fixed [29:16] */
4283+ printk("\t\ttx_rate = 0x%lx\n", FIELD_GET(MT_TXD6_TX_RATE, txd->txd_6));
4284+ }
4285+
4286+ /* TXEBF [30] */
4287+ printk("\t\ttxebf = %d\n", (txd->txd_6 & MT_TXD6_TX_EBF) ? 1 : 0);
4288+
4289+ /* TXIBF [31] */
4290+ printk("\t\ttxibf = %d\n", (txd->txd_6 & MT_TXD6_TX_IBF) ? 1 : 0);
4291+
4292+ /* DW7 */
4293+ printk("\tTMAC_TXD_7:\n");
4294+
4295+ if ((txd->txd_1 & MT_TXD1_VTA) == 0) {
4296+ /* SW Tx Time [9:0] */
4297+ printk("\t\tsw_tx_time = %ld\n", FIELD_GET(MT_TXD7_TX_TIME, txd->txd_7));
4298+ } else {
4299+ /* TXD Arrival Time [9:0] */
4300+ printk("\t\tat = %ld\n", FIELD_GET(MT_TXD7_TAT, txd->txd_7));
4301+ }
4302+
4303+ /* HW_AMSDU_CAP [10] */
4304+ printk("\t\thw amsdu cap = %d\n",(txd->txd_7 & MT_TXD7_HW_AMSDU) ? 1 : 0);
4305+
4306+ /* SPE_IDX [15:11] */
4307+ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4308+ printk("\t\tspe_idx = 0x%lx\n", FIELD_GET(MT_TXD7_SPE_IDX, txd->txd_7));
4309+ }
4310+
4311+ /* PSE_FID [27:16] */
4312+ printk("\t\tpse_fid = 0x%lx\n", FIELD_GET(MT_TXD7_PSE_FID, txd->txd_7));
4313+
4314+ /* Subtype [19:16] */
4315+ printk("\t\tpp_sub_type=%ld\n", FIELD_GET(MT_TXD7_SUB_TYPE, txd->txd_7));
4316+
4317+ /* Type [21:20] */
4318+ printk("\t\tpp_type=%ld\n", FIELD_GET(MT_TXD7_TYPE, txd->txd_7));
4319+
4320+ /* CTXD_CNT [25:23] */
4321+ printk("\t\tctxd cnt=0x%lx\n", FIELD_GET(MT_TXD7_CTXD_CNT, txd->txd_7));
4322+
4323+ /* CTXD [26] */
4324+ printk("\t\tctxd = %d\n", (txd->txd_7 & MT_TXD7_CTXD) ? 1 : 0);
4325+
4326+ /* I [28] */
4327+ printk("\t\ti = %d\n", (txd->txd_7 & MT_TXD7_IP_SUM) ? 1 : 0);
4328+
4329+ /* UT [29] */
4330+ printk("\t\tUT = %d\n", (txd->txd_7 & MT_TXD7_UDP_TCP_SUM) ? 1 : 0);
4331+
4332+ /* TXDLEN [31:30] */
4333+ printk("\t\t txd len= %ld\n", FIELD_GET(MT_TXD7_TXD_LEN, txd->txd_7));
4334+}
4335+
4336+
4337+static int mt7915_token_txd_read(struct seq_file *s, void *data)
4338+{
4339+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4340+ struct mt76_txwi_cache *t;
4341+ u8* txwi;
4342+
4343+ seq_printf(s, "\n");
4344+ spin_lock_bh(&dev->mt76.token_lock);
4345+
4346+ t = idr_find(&dev->mt76.token, dev->dbg.token_idx);
4347+
4348+ spin_unlock_bh(&dev->mt76.token_lock);
4349+ if (t != NULL) {
4350+ struct mt76_dev *mdev = &dev->mt76;
4351+ txwi = ((u8*)(t)) - (mdev->drv->txwi_size);
4352+ mt7915_dump_tmac_info((u8*) txwi);
4353+ seq_printf(s, "\n");
4354+ printk("[SKB]\n");
4355+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)t->skb->data, t->skb->len, false);
4356+ seq_printf(s, "\n");
4357+ }
4358+ return 0;
4359+}
4360+
4361+static int mt7915_amsduinfo_read(struct seq_file *s, void *data)
4362+{
4363+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4364+ u32 ple_stat[8] = {0}, total_amsdu = 0;
4365+ u8 i;
4366+
4367+ for (i = 0; i < 8; i++)
4368+ ple_stat[i] = mt76_rr(dev, MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(i));
4369+
4370+ seq_printf(s, "TXD counter status of MSDU:\n");
4371+
4372+ for (i = 0; i < 8; i++)
4373+ total_amsdu += ple_stat[i];
4374+
4375+ for (i = 0; i < 8; i++) {
4376+ seq_printf(s, "AMSDU pack count of %d MSDU in TXD: 0x%x ", i + 1, ple_stat[i]);
4377+ if (total_amsdu != 0)
4378+ seq_printf(s, "(%d%%)\n", ple_stat[i] * 100 / total_amsdu);
4379+ else
4380+ seq_printf(s, "\n");
4381+ }
4382+
4383+ return 0;
4384+
4385+}
4386+
4387+static int mt7915_agginfo_read_per_band(struct seq_file *s, int band_idx)
4388+{
4389+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4390+ u32 value, idx, agg_rang_sel[15], ampdu_cnt[11], total_ampdu = 0;
4391+
4392+ seq_printf(s, "Band %d AGG Status\n", band_idx);
4393+ seq_printf(s, "===============================\n");
4394+ value = mt76_rr(dev, MT_DBG_AGG_AALCR0(band_idx));
4395+ seq_printf(s, "AC00 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4396+ seq_printf(s, "AC01 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4397+ seq_printf(s, "AC02 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4398+ seq_printf(s, "AC03 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4399+
4400+ value = mt76_rr(dev, MT_DBG_AGG_AALCR1(band_idx));
4401+ seq_printf(s, "AC10 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4402+ seq_printf(s, "AC11 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4403+ seq_printf(s, "AC12 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4404+ seq_printf(s, "AC13 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4405+
4406+ value = mt76_rr(dev, MT_DBG_AGG_AALCR2(band_idx));
4407+ seq_printf(s, "AC20 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4408+ seq_printf(s, "AC21 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4409+ seq_printf(s, "AC22 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4410+ seq_printf(s, "AC23 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4411+
4412+ value = mt76_rr(dev, MT_DBG_AGG_AALCR3(band_idx));
4413+ seq_printf(s, "AC30 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4414+ seq_printf(s, "AC31 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4415+ seq_printf(s, "AC32 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4416+ seq_printf(s, "AC33 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4417+
4418+ value = mt76_rr(dev, MT_DBG_AGG_AALCR4(band_idx));
4419+ seq_printf(s, "ALTX Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK, value));
4420+
4421+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 0));
4422+ seq_printf(s, "Winsize0 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE0_MASK, value));
4423+ seq_printf(s, "Winsize1 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE1_MASK, value));
4424+ seq_printf(s, "Winsize2 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE2_MASK, value));
4425+ seq_printf(s, "Winsize3 limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE3_MASK, value));
4426+
4427+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 1));
4428+ seq_printf(s, "Winsize4 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE4_MASK, value));
4429+ seq_printf(s, "Winsize5 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE5_MASK, value));
4430+ seq_printf(s, "Winsize6 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE6_MASK, value));
4431+ seq_printf(s, "Winsize7 limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE7_MASK, value));
4432+
4433+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 2));
4434+ seq_printf(s, "Winsize8 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZE8_MASK, value));
4435+ seq_printf(s, "Winsize9 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZE9_MASK, value));
4436+ seq_printf(s, "WinsizeA limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZEA_MASK, value));
4437+ seq_printf(s, "WinsizeB limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZEB_MASK, value));
4438+
4439+
4440+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 3));
4441+ seq_printf(s, "WinsizeC limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZEC_MASK, value));
4442+ seq_printf(s, "WinsizeD limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZED_MASK, value));
4443+ seq_printf(s, "WinsizeE limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZEE_MASK, value));
4444+
4445+ seq_printf(s, "===AMPDU Related Counters===\n");
4446+
4447+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 0));
4448+ agg_rang_sel[0] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK, value);
4449+ agg_rang_sel[1] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK, value);
4450+ agg_rang_sel[2] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK, value);
4451+ agg_rang_sel[3] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK, value);
4452+
4453+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 1));
4454+ agg_rang_sel[4] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK, value);
4455+ agg_rang_sel[5] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK, value);
4456+ agg_rang_sel[6] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK, value);
4457+ agg_rang_sel[7] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK, value);
4458+
4459+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 2));
4460+ agg_rang_sel[8] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK, value);
4461+ agg_rang_sel[9] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK, value);
4462+ agg_rang_sel[10] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK, value);
4463+ agg_rang_sel[11] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK, value);
4464+
4465+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 3));
4466+ agg_rang_sel[12] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK, value);
4467+ agg_rang_sel[13] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK, value);
4468+ agg_rang_sel[14] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK, value);
4469+
4470+ /* Need to add 1 after read from AGG_RANG_SEL CR */
4471+ for (idx = 0; idx < 15; idx++)
4472+ agg_rang_sel[idx]++;
4473+
4474+ ampdu_cnt[3] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 0));
4475+ ampdu_cnt[4] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 1));
4476+ ampdu_cnt[5] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 2));
4477+ ampdu_cnt[6] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 3));
4478+ ampdu_cnt[7] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 0));
4479+ ampdu_cnt[8] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 1));
4480+ ampdu_cnt[9] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 2));
4481+ ampdu_cnt[10] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 3));
4482+
4483+ seq_printf(s, "\tTx Agg Range: \t%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d\n",
4484+ agg_rang_sel[0],
4485+ agg_rang_sel[0] + 1, agg_rang_sel[1],
4486+ agg_rang_sel[1] + 1, agg_rang_sel[2],
4487+ agg_rang_sel[2] + 1, agg_rang_sel[3],
4488+ agg_rang_sel[3] + 1, agg_rang_sel[4],
4489+ agg_rang_sel[4] + 1, agg_rang_sel[5],
4490+ agg_rang_sel[5] + 1, agg_rang_sel[6],
4491+ agg_rang_sel[6] + 1, agg_rang_sel[7]);
4492+
4493+#define BIT_0_to_15_MASK 0x0000FFFF
4494+#define BIT_15_to_31_MASK 0xFFFF0000
4495+#define SHFIT_16_BIT 16
4496+
4497+ for (idx = 3; idx < 11; idx++)
4498+ total_ampdu = total_ampdu + (ampdu_cnt[idx] & BIT_0_to_15_MASK) + ((ampdu_cnt[idx] & BIT_15_to_31_MASK) >> SHFIT_16_BIT);
4499+
4500+ seq_printf(s, "\t\t\t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx\n",
4501+ (ampdu_cnt[3]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK,
4502+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[3]),
4503+ (ampdu_cnt[4]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK,
4504+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[4]),
4505+ (ampdu_cnt[5]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK,
4506+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[5]),
4507+ (ampdu_cnt[6]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK,
4508+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[6]));
4509+
4510+ if (total_ampdu != 0) {
4511+ seq_printf(s, "\t\t\t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%)\n",
4512+ ((ampdu_cnt[3]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK) * 100 / total_ampdu,
4513+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[3]) * 100 / total_ampdu,
4514+ ((ampdu_cnt[4]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK) * 100 / total_ampdu,
4515+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[4]) * 100 / total_ampdu,
4516+ ((ampdu_cnt[5]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK) * 100 / total_ampdu,
4517+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[5]) * 100 / total_ampdu,
4518+ ((ampdu_cnt[6]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK) * 100 / total_ampdu,
4519+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[6]) * 100 / total_ampdu);
4520+ }
4521+
4522+ seq_printf(s, "\t\t\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~256\n",
4523+ agg_rang_sel[7] + 1, agg_rang_sel[8],
4524+ agg_rang_sel[8] + 1, agg_rang_sel[9],
4525+ agg_rang_sel[9] + 1, agg_rang_sel[10],
4526+ agg_rang_sel[10] + 1, agg_rang_sel[11],
4527+ agg_rang_sel[11] + 1, agg_rang_sel[12],
4528+ agg_rang_sel[12] + 1, agg_rang_sel[13],
4529+ agg_rang_sel[13] + 1, agg_rang_sel[14],
4530+ agg_rang_sel[14] + 1);
4531+
4532+ seq_printf(s, "\t\t\t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx\n",
4533+ (ampdu_cnt[7]) & MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK,
4534+ FIELD_GET(MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK, ampdu_cnt[7]),
4535+ (ampdu_cnt[8]) & MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK,
4536+ FIELD_GET(MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK, ampdu_cnt[8]),
4537+ (ampdu_cnt[9]) & MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK,
4538+ FIELD_GET(MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK, ampdu_cnt[9]),
4539+ (ampdu_cnt[10]) & MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK,
4540+ FIELD_GET(MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK, ampdu_cnt[10]));
4541+
4542+ if (total_ampdu != 0) {
4543+ seq_printf(s, "\t\t\t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%)\n",
4544+ ((ampdu_cnt[7]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK) * 100 / total_ampdu,
4545+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[7]) * 100 / total_ampdu,
4546+ ((ampdu_cnt[8]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK) * 100 / total_ampdu,
4547+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[8]) * 100 / total_ampdu,
4548+ ((ampdu_cnt[9]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK) * 100 / total_ampdu,
4549+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[9]) * 100 / total_ampdu,
4550+ ((ampdu_cnt[10]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK) * 100 / total_ampdu,
4551+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[10]) * 100 / total_ampdu);
4552+ }
4553+
4554+ return 0;
4555+}
4556+
4557+static int mt7915_agginfo_read_band0(struct seq_file *s, void *data)
4558+{
4559+ mt7915_agginfo_read_per_band(s, 0);
4560+ return 0;
4561+}
4562+
4563+static int mt7915_agginfo_read_band1(struct seq_file *s, void *data)
4564+{
4565+ mt7915_agginfo_read_per_band(s, 1);
4566+ return 0;
4567+}
4568+
4569+/*usage: <en> <num> <len>
4570+ en: BIT(16) 0: sw amsdu 1: hw amsdu
4571+ num: GENMASK(15, 8) range 1-8
4572+ len: GENMASK(7, 0) unit: 256 bytes */
4573+static int mt7915_sta_tx_amsdu_set(void *data, u64 tx_amsdu)
4574+{
4575+/* UWTBL DW 6 */
4576+#define WTBL_AMSDU_LEN_MASK GENMASK(5, 0)
4577+#define WTBL_AMSDU_NUM_MASK GENMASK(8, 6)
4578+#define WTBL_AMSDU_EN_MASK BIT(9)
4579+#define UWTBL_HW_AMSDU_DW 6
4580+
4581+ struct mt7915_dev *dev = data;
4582+ u32 len = FIELD_GET(GENMASK(7, 0), tx_amsdu);
4583+ u32 num = FIELD_GET(GENMASK(15, 8), tx_amsdu);
4584+ u32 uwtbl;
4585+
developer9e5bcc52022-09-27 10:30:15 +08004586+ mt7915_mcu_set_amsdu_algo(dev, dev->wlan_idx, 0);
4587+
developer3fa816c2022-04-19 10:21:20 +08004588+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC,
4589+ UWTBL_HW_AMSDU_DW, 1, &uwtbl);
4590+
4591+ if (len) {
4592+ uwtbl &= ~WTBL_AMSDU_LEN_MASK;
4593+ uwtbl |= FIELD_PREP(WTBL_AMSDU_LEN_MASK, len);
4594+ }
4595+
4596+ uwtbl &= ~WTBL_AMSDU_NUM_MASK;
4597+ uwtbl |= FIELD_PREP(WTBL_AMSDU_NUM_MASK, num);
4598+
4599+ if (tx_amsdu & BIT(16))
4600+ uwtbl |= WTBL_AMSDU_EN_MASK;
4601+
4602+ mt7915_wtbl_write_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC,
4603+ UWTBL_HW_AMSDU_DW, uwtbl);
4604+
4605+ return 0;
4606+}
4607+
4608+DEFINE_DEBUGFS_ATTRIBUTE(fops_tx_amsdu, NULL,
4609+ mt7915_sta_tx_amsdu_set, "%llx\n");
4610+
4611+static int mt7915_red_enable_set(void *data, u64 en)
4612+{
4613+ struct mt7915_dev *dev = data;
4614+
4615+ return mt7915_mcu_set_red(dev, en);
4616+}
4617+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_en, NULL,
4618+ mt7915_red_enable_set, "%llx\n");
4619+
4620+static int mt7915_red_show_sta_set(void *data, u64 wlan_idx)
4621+{
4622+ struct mt7915_dev *dev = data;
4623+
4624+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
4625+ MCU_WA_PARAM_RED_SHOW_STA,
4626+ wlan_idx, 0, true);
4627+
4628+ return 0;
4629+}
4630+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_show_sta, NULL,
4631+ mt7915_red_show_sta_set, "%llx\n");
4632+
4633+static int mt7915_red_target_dly_set(void *data, u64 delay)
4634+{
4635+ struct mt7915_dev *dev = data;
4636+
4637+ if (delay > 0 && delay <= 32767)
4638+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
4639+ MCU_WA_PARAM_RED_TARGET_DELAY,
4640+ delay, 0, true);
4641+
4642+ return 0;
4643+}
4644+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_target_dly, NULL,
4645+ mt7915_red_target_dly_set, "%llx\n");
4646+
4647+static int
4648+mt7915_txpower_level_set(void *data, u64 val)
4649+{
4650+ struct mt7915_dev *dev = data;
4651+ struct mt7915_phy *ext_phy = mt7915_ext_phy(dev);
4652+ mt7915_mcu_set_txpower_level(&dev->phy, val);
4653+ if (ext_phy)
4654+ mt7915_mcu_set_txpower_level(ext_phy, val);
4655+
4656+ return 0;
4657+}
4658+
4659+DEFINE_DEBUGFS_ATTRIBUTE(fops_txpower_level, NULL,
4660+ mt7915_txpower_level_set, "%lld\n");
4661+
4662+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_set */
4663+static int
4664+mt7915_wa_set(void *data, u64 val)
4665+{
4666+ struct mt7915_dev *dev = data;
4667+ u32 arg1, arg2, arg3;
4668+
4669+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
4670+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
4671+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
4672+
4673+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), arg1, arg2, arg3, false);
4674+
4675+ return 0;
4676+}
4677+
4678+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_set, NULL, mt7915_wa_set,
4679+ "0x%llx\n");
4680+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_query */
4681+static int
4682+mt7915_wa_query(void *data, u64 val)
4683+{
4684+ struct mt7915_dev *dev = data;
4685+ u32 arg1, arg2, arg3;
4686+
4687+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
4688+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
4689+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
4690+
4691+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY), arg1, arg2, arg3, false);
4692+
4693+ return 0;
4694+}
4695+
4696+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_query, NULL, mt7915_wa_query,
4697+ "0x%llx\n");
4698+/* set wa debug level
4699+ usage:
4700+ echo 0x[arg] > fw_wa_debug
4701+ bit0 : DEBUG_WIFI_TX
4702+ bit1 : DEBUG_CMD_EVENT
4703+ bit2 : DEBUG_RED
4704+ bit3 : DEBUG_WARN
4705+ bit4 : DEBUG_WIFI_RX
4706+ bit5 : DEBUG_TIME_STAMP
4707+ bit6 : DEBUG_TX_FREE_DONE_EVENT
4708+ bit12 : DEBUG_WIFI_TXD */
4709+static int
4710+mt7915_wa_debug(void *data, u64 val)
4711+{
4712+ struct mt7915_dev *dev = data;
4713+ u32 arg;
4714+
4715+ arg = FIELD_GET(GENMASK_ULL(15, 0), val);
4716+
4717+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(DEBUG), arg, 0, 0, false);
4718+
4719+ return 0;
4720+}
4721+
4722+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_debug, NULL, mt7915_wa_debug,
4723+ "0x%llx\n");
4724+
4725+int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir)
4726+{
4727+ struct mt7915_dev *dev = phy->dev;
4728+ u32 device_id = (dev->mt76.rev) >> 16;
4729+ int i = 0;
4730+
4731+ for (i = 0; i < ARRAY_SIZE(dbg_reg_s); i++) {
4732+ if (device_id == dbg_reg_s[i].id) {
4733+ dev->dbg_reg = &dbg_reg_s[i];
4734+ break;
4735+ }
4736+ }
4737+
4738+ mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 0);
4739+
4740+ debugfs_create_file("fw_debug_module", 0600, dir, dev,
4741+ &fops_fw_debug_module);
4742+ debugfs_create_file("fw_debug_level", 0600, dir, dev,
4743+ &fops_fw_debug_level);
4744+
developerf32dabf2022-06-01 10:59:24 +08004745+ debugfs_create_devm_seqfile(dev->mt76.dev, "sta_info", dir,
4746+ mt7915_sta_info);
developer3fa816c2022-04-19 10:21:20 +08004747+ debugfs_create_devm_seqfile(dev->mt76.dev, "wtbl_info", dir,
4748+ mt7915_wtbl_read);
4749+ debugfs_create_devm_seqfile(dev->mt76.dev, "uwtbl_info", dir,
4750+ mt7915_uwtbl_read);
4751+
4752+ debugfs_create_devm_seqfile(dev->mt76.dev, "tr_info", dir,
4753+ mt7915_trinfo_read);
4754+
4755+ debugfs_create_devm_seqfile(dev->mt76.dev, "drr_info", dir,
4756+ mt7915_drr_info);
4757+
4758+ debugfs_create_devm_seqfile(dev->mt76.dev, "ple_info", dir,
4759+ mt7915_pleinfo_read);
4760+
4761+ debugfs_create_devm_seqfile(dev->mt76.dev, "pse_info", dir,
4762+ mt7915_pseinfo_read);
4763+
4764+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info0", dir,
4765+ mt7915_mibinfo_band0);
4766+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info1", dir,
4767+ mt7915_mibinfo_band1);
4768+
4769+ debugfs_create_u32("token_idx", 0600, dir, &dev->dbg.token_idx);
4770+ debugfs_create_devm_seqfile(dev->mt76.dev, "token", dir,
4771+ mt7915_token_read);
4772+ debugfs_create_devm_seqfile(dev->mt76.dev, "token_txd", dir,
4773+ mt7915_token_txd_read);
4774+
4775+ debugfs_create_devm_seqfile(dev->mt76.dev, "amsdu_info", dir,
4776+ mt7915_amsduinfo_read);
4777+
4778+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info0", dir,
4779+ mt7915_agginfo_read_band0);
4780+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info1", dir,
4781+ mt7915_agginfo_read_band1);
4782+
4783+ debugfs_create_file("tx_amsdu", 0600, dir, dev, &fops_tx_amsdu);
4784+
4785+ debugfs_create_file("fw_wa_query", 0600, dir, dev, &fops_wa_query);
4786+ debugfs_create_file("fw_wa_set", 0600, dir, dev, &fops_wa_set);
4787+ debugfs_create_file("fw_wa_debug", 0600, dir, dev, &fops_wa_debug);
4788+
4789+ debugfs_create_file("red_en", 0600, dir, dev,
4790+ &fops_red_en);
4791+ debugfs_create_file("red_show_sta", 0600, dir, dev,
4792+ &fops_red_show_sta);
4793+ debugfs_create_file("red_target_dly", 0600, dir, dev,
4794+ &fops_red_target_dly);
4795+
4796+ debugfs_create_file("txpower_level", 0400, dir, dev,
4797+ &fops_txpower_level);
4798+
developeraace7f52022-06-24 13:40:42 +08004799+ debugfs_create_u8("sku_disable", 0600, dir, &dev->dbg.sku_disable);
4800+
developer3fa816c2022-04-19 10:21:20 +08004801+ return 0;
4802+}
4803+#endif
4804diff --git a/mt7915/mtk_mcu.c b/mt7915/mtk_mcu.c
4805new file mode 100644
developerf3f5d9b2023-02-07 15:24:34 +08004806index 00000000..143dae26
developer3fa816c2022-04-19 10:21:20 +08004807--- /dev/null
4808+++ b/mt7915/mtk_mcu.c
4809@@ -0,0 +1,51 @@
4810+#include <linux/firmware.h>
4811+#include <linux/fs.h>
4812+#include<linux/inet.h>
4813+#include "mt7915.h"
4814+#include "mcu.h"
4815+#include "mac.h"
4816+
4817+int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level)
4818+{
4819+ struct mt7915_dev *dev = phy->dev;
4820+ struct mt7915_sku_val {
4821+ u8 format_id;
4822+ u8 val;
4823+ u8 band;
4824+ u8 _rsv;
4825+ } __packed req = {
4826+ .format_id = 1,
developer2458e702022-12-13 15:52:04 +08004827+ .band = phy->mt76->band_idx,
developer3fa816c2022-04-19 10:21:20 +08004828+ .val = !!drop_level,
4829+ };
4830+ int ret;
4831+
4832+ ret = mt76_mcu_send_msg(&dev->mt76,
4833+ MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
4834+ sizeof(req), true);
4835+ if (ret)
4836+ return ret;
4837+
4838+ req.format_id = 2;
4839+ if ((drop_level > 90 && drop_level < 100) || !drop_level)
4840+ req.val = 0;
4841+ else if (drop_level > 60 && drop_level <= 90)
4842+ /* reduce Pwr for 1 dB. */
4843+ req.val = 2;
4844+ else if (drop_level > 30 && drop_level <= 60)
4845+ /* reduce Pwr for 3 dB. */
4846+ req.val = 6;
4847+ else if (drop_level > 15 && drop_level <= 30)
4848+ /* reduce Pwr for 6 dB. */
4849+ req.val = 12;
4850+ else if (drop_level > 9 && drop_level <= 15)
4851+ /* reduce Pwr for 9 dB. */
4852+ req.val = 18;
4853+ else if (drop_level > 0 && drop_level <= 9)
4854+ /* reduce Pwr for 12 dB. */
4855+ req.val = 24;
4856+
4857+ return mt76_mcu_send_msg(&dev->mt76,
4858+ MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
4859+ sizeof(req), true);
4860+}
4861diff --git a/tools/fwlog.c b/tools/fwlog.c
developerf3f5d9b2023-02-07 15:24:34 +08004862index e5d4a105..3d51d9ec 100644
developer3fa816c2022-04-19 10:21:20 +08004863--- a/tools/fwlog.c
4864+++ b/tools/fwlog.c
4865@@ -26,7 +26,7 @@ static const char *debugfs_path(const char *phyname, const char *file)
4866 return path;
4867 }
4868
4869-static int mt76_set_fwlog_en(const char *phyname, bool en)
4870+static int mt76_set_fwlog_en(const char *phyname, bool en, char *val)
4871 {
4872 FILE *f = fopen(debugfs_path(phyname, "fw_debug_bin"), "w");
4873
4874@@ -35,7 +35,13 @@ static int mt76_set_fwlog_en(const char *phyname, bool en)
4875 return 1;
4876 }
4877
4878- fprintf(f, "7");
4879+ if (en && val)
4880+ fprintf(f, "%s", val);
4881+ else if (en)
4882+ fprintf(f, "7");
4883+ else
4884+ fprintf(f, "0");
4885+
4886 fclose(f);
4887
4888 return 0;
4889@@ -76,6 +82,7 @@ static void handle_signal(int sig)
4890
4891 int mt76_fwlog(const char *phyname, int argc, char **argv)
4892 {
4893+#define BUF_SIZE 1504
4894 struct sockaddr_in local = {
4895 .sin_family = AF_INET,
4896 .sin_addr.s_addr = INADDR_ANY,
developerf32dabf2022-06-01 10:59:24 +08004897@@ -84,9 +91,10 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
developer3fa816c2022-04-19 10:21:20 +08004898 .sin_family = AF_INET,
4899 .sin_port = htons(55688),
4900 };
4901- char buf[1504];
4902+ char *buf = calloc(BUF_SIZE, sizeof(char));
developerf32dabf2022-06-01 10:59:24 +08004903+ FILE *logfile = NULL;
developer3fa816c2022-04-19 10:21:20 +08004904 int ret = 0;
4905- int yes = 1;
4906+ /* int yes = 1; */
4907 int s, fd;
4908
4909 if (argc < 1) {
developerf32dabf2022-06-01 10:59:24 +08004910@@ -99,19 +107,28 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4911 return 1;
4912 }
4913
4914+ if (argc == 3) {
4915+ fprintf(stdout, "start logging to file %s\n", argv[2]);
4916+ logfile = fopen(argv[2], "wb");
4917+ if (!logfile) {
4918+ perror("fopen");
4919+ return 1;
4920+ }
4921+ }
4922+
4923 s = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP);
4924 if (s < 0) {
4925 perror("socket");
developer3fa816c2022-04-19 10:21:20 +08004926 return 1;
4927 }
4928
4929- setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes));
4930+ /* setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes)); */
4931 if (bind(s, (struct sockaddr *)&local, sizeof(local)) < 0) {
4932 perror("bind");
4933 return 1;
4934 }
4935
4936- if (mt76_set_fwlog_en(phyname, true))
4937+ if (mt76_set_fwlog_en(phyname, true, argv[1]))
4938 return 1;
4939
4940 fd = open(debugfs_path(phyname, "fwlog_data"), O_RDONLY);
developerf32dabf2022-06-01 10:59:24 +08004941@@ -145,8 +162,8 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
developer3fa816c2022-04-19 10:21:20 +08004942 if (!r)
4943 continue;
4944
4945- if (len > sizeof(buf)) {
4946- fprintf(stderr, "Length error: %d > %d\n", len, (int)sizeof(buf));
4947+ if (len > BUF_SIZE) {
4948+ fprintf(stderr, "Length error: %d > %d\n", len, BUF_SIZE);
4949 ret = 1;
4950 break;
4951 }
developerf32dabf2022-06-01 10:59:24 +08004952@@ -164,14 +181,19 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4953 break;
4954 }
4955
4956- /* send buf */
4957- sendto(s, buf, len, 0, (struct sockaddr *)&remote, sizeof(remote));
4958+ if (logfile)
4959+ fwrite(buf, 1, len, logfile);
4960+ else
4961+ /* send buf */
4962+ sendto(s, buf, len, 0, (struct sockaddr *)&remote, sizeof(remote));
4963 }
4964
developer3fa816c2022-04-19 10:21:20 +08004965 close(fd);
4966
4967 out:
4968- mt76_set_fwlog_en(phyname, false);
4969+ mt76_set_fwlog_en(phyname, false, NULL);
4970+ free(buf);
developerf32dabf2022-06-01 10:59:24 +08004971+ fclose(logfile);
developer3fa816c2022-04-19 10:21:20 +08004972
4973 return ret;
4974 }
4975--
developer79a21a22023-01-09 13:57:39 +080049762.18.0
developer3fa816c2022-04-19 10:21:20 +08004977