Gitiles
Code Review Sign In
git01.mediatek.com / filogic / rdk-b / meta-filogic / 3fa816cb0d792089b65b2502d223c7b307004462 / . / recipes-kernel / linux-mt76 / files / patches / 1001-mt76-mt7915-add-mtk-internal-debug-tools-for-mt76.patch
blob: e615e9cbaa5f8f1b7e5d0b641b6ee1d1cb121ef4 [file] [log] [blame]
developer3fa816c2022-04-19 10:21:20 +0800[diff] [blame^]1From 3dd7344c6aa1124982d81d98defea6263899673b Mon Sep 17 00:00:00 2001
2From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Thu, 17 Feb 2022 00:17:39 +0800
4Subject: [PATCH] mt76: mt7915: add mtk internal debug tools for mt76
5
6---
7 .../wireless/mediatek/mt76/mt76_connac_mcu.h | 6 +
8 .../wireless/mediatek/mt76/mt7915/Makefile | 2 +-
9 .../wireless/mediatek/mt76/mt7915/debugfs.c | 72 +-
10 .../net/wireless/mediatek/mt76/mt7915/mac.c | 14 +
11 .../net/wireless/mediatek/mt76/mt7915/mcu.c | 41 +
12 .../net/wireless/mediatek/mt76/mt7915/mcu.h | 4 +
13 .../wireless/mediatek/mt76/mt7915/mt7915.h | 41 +
14 .../mediatek/mt76/mt7915/mt7915_debug.h | 1350 ++++++++
15 .../mediatek/mt76/mt7915/mtk_debugfs.c | 2893 +++++++++++++++++
16 .../wireless/mediatek/mt76/mt7915/mtk_mcu.c | 51 +
17 .../net/wireless/mediatek/mt76/tools/fwlog.c | 26 +-
18 11 files changed, 4489 insertions(+), 11 deletions(-)
19 create mode 100644 drivers/net/wireless/mediatek/mt76/mt7915/mt7915_debug.h
20 create mode 100644 drivers/net/wireless/mediatek/mt76/mt7915/mtk_debugfs.c
21 create mode 100644 drivers/net/wireless/mediatek/mt76/mt7915/mtk_mcu.c
22
23diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
24index 54419864..494c5c71 100644
25--- a/mt76_connac_mcu.h
26+++ b/mt76_connac_mcu.h
27@@ -968,6 +968,12 @@ enum {
28 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
29 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
30 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
31+#ifdef MTK_DEBUG
32+ MCU_EXT_CMD_RED_ENABLE = 0x68,
33+ MCU_EXT_CMD_RED_SHOW_STA = 0x69,
34+ MCU_EXT_CMD_RED_TARGET_DELAY = 0x6A,
35+ MCU_EXT_CMD_RED_TX_RPT = 0x6B,
36+#endif
37 MCU_EXT_CMD_TXDPD_CAL = 0x60,
38 MCU_EXT_CMD_CAL_CACHE = 0x67,
39 MCU_EXT_CMD_SET_RADAR_TH = 0x7c,
40diff --git a/mt7915/Makefile b/mt7915/Makefile
41index b794ceb7..a3474e2f 100644
42--- a/mt7915/Makefile
43+++ b/mt7915/Makefile
44@@ -3,7 +3,7 @@
45 obj-$(CONFIG_MT7915E) += mt7915e.o
46
47 mt7915e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
48- debugfs.o mmio.o
49+ debugfs.o mmio.o mtk_debugfs.o mtk_mcu.o
50
51 mt7915e-$(CONFIG_NL80211_TESTMODE) += testmode.o
52 mt7915e-$(CONFIG_MT7986_WMAC) += soc.o
53\ No newline at end of file
54diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c
55index 4e1ecaec..6df148c5 100644
56--- a/mt7915/debugfs.c
57+++ b/mt7915/debugfs.c
58@@ -8,6 +8,9 @@
59 #include "mac.h"
60
61 #define FW_BIN_LOG_MAGIC 0x44e98caf
62+#ifdef MTK_DEBUG
63+#define FW_BIN_LOG_MAGIC_V2 0x44d9c99a
64+#endif
65
66 /** global debugfs **/
67
68@@ -370,6 +373,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
69 int ret;
70
71 dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
72+#ifdef MTK_DEBUG
73+ dev->fw_debug_wm = val;
74+#endif
75
76 if (dev->fw_debug_bin)
77 val = 16;
78@@ -394,6 +400,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
79 if (ret)
80 return ret;
81 }
82+#ifdef MTK_DEBUG
83+ mt7915_mcu_fw_dbg_ctrl(dev, 68, !!val);
84+#endif
85
86 /* WM CPU info record control */
87 mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0));
88@@ -401,6 +410,12 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
89 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5));
90 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5));
91
92+#ifdef MTK_DEBUG
93+ if (dev->fw_debug_bin & BIT(3))
94+ /* use bit 7 to indicate v2 magic number */
95+ dev->fw_debug_wm |= BIT(7);
96+#endif
97+
98 return 0;
99 }
100
101@@ -409,7 +424,11 @@ mt7915_fw_debug_wm_get(void *data, u64 *val)
102 {
103 struct mt7915_dev *dev = data;
104
105- *val = dev->fw_debug_wm;
106+#ifdef MTK_DEBUG
107+ *val = dev->fw_debug_wm & ~BIT(7);
108+#else
109+ val = dev->fw_debug_wm;
110+#endif
111
112 return 0;
113 }
114@@ -489,6 +508,16 @@ mt7915_fw_debug_bin_set(void *data, u64 val)
115
116 relay_reset(dev->relay_fwlog);
117
118+#ifdef MTK_DEBUG
119+ dev->dbg.dump_mcu_pkt = val & BIT(4) ? true : false;
120+ dev->dbg.dump_txd = val & BIT(5) ? true : false;
121+ dev->dbg.dump_tx_pkt = val & BIT(6) ? true : false;
122+ dev->dbg.dump_rx_pkt = val & BIT(7) ? true : false;
123+ dev->dbg.dump_rx_raw = val & BIT(8) ? true : false;
124+ if (!(val & GENMASK(3, 0)))
125+ return 0;
126+#endif
127+
128 return mt7915_fw_debug_wm_set(dev, dev->fw_debug_wm);
129 }
130
131@@ -910,6 +939,11 @@ int mt7915_init_debugfs(struct mt7915_phy *phy)
132 if (!ext_phy)
133 dev->debugfs_dir = dir;
134
135+#ifdef MTK_DEBUG
136+ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
137+ mt7915_mtk_init_debugfs(phy, dir);
138+#endif
139+
140 return 0;
141 }
142
143@@ -950,17 +984,53 @@ void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int
144 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),
145 };
146
147+#ifdef MTK_DEBUG
148+ struct {
149+ __le32 magic;
150+ u8 version;
151+ u8 _rsv;
152+ __le16 serial_id;
153+ __le32 timestamp;
154+ __le16 msg_type;
155+ __le16 len;
156+ } hdr2 = {
157+ .version = 0x1,
158+ .magic = cpu_to_le32(FW_BIN_LOG_MAGIC_V2),
159+ .msg_type = PKT_TYPE_RX_FW_MONITOR,
160+ };
161+#endif
162+
163 if (!dev->relay_fwlog)
164 return;
165
166+#ifdef MTK_DEBUG
167+ /* old magic num */
168+ if (!(dev->fw_debug_wm & BIT(7))) {
169+ hdr.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
170+ hdr.len = *(__le16 *)data;
171+ mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
172+ } else {
173+ hdr2.serial_id = dev->dbg.fwlog_seq++;
174+ hdr2.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
175+ hdr2.len = *(__le16 *)data;
176+ mt7915_debugfs_write_fwlog(dev, &hdr2, sizeof(hdr2), data, len);
177+ }
178+#else
179 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
180 hdr.len = *(__le16 *)data;
181 mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
182+#endif
183 }
184
185 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len)
186 {
187+#ifdef MTK_DEBUG
188+ if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC &&
189+ get_unaligned_le32(data) != FW_BIN_LOG_MAGIC_V2 &&
190+ get_unaligned_le32(data) != PKT_BIN_DEBUG_MAGIC)
191+#else
192 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC)
193+#endif
194 return false;
195
196 if (dev->relay_fwlog)
197diff --git a/mt7915/mac.c b/mt7915/mac.c
198index 887292da..6f4cc947 100644
199--- a/mt7915/mac.c
200+++ b/mt7915/mac.c
201@@ -595,6 +595,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
202 __le16 fc = 0;
203 int idx;
204
205+#ifdef MTK_DEBUG
206+ if (dev->dbg.dump_rx_raw)
207+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX_RAW, 0);
208+#endif
209 memset(status, 0, sizeof(*status));
210
211 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->band_idx) {
212@@ -778,6 +782,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
213 }
214
215 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
216+#ifdef MTK_DEBUG
217+ if (dev->dbg.dump_rx_pkt)
218+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX, hdr_gap);
219+#endif
220 if (hdr_trans && ieee80211_has_morefrags(fc)) {
221 if (mt7915_reverse_frag0_hdr_trans(skb, hdr_gap))
222 return -EINVAL;
223@@ -1343,6 +1351,12 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
224 tx_info->buf[1].skip_unmap = true;
225 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
226
227+#ifdef MTK_DEBUG
228+ if (dev->dbg.dump_txd)
229+ mt7915_packet_log_to_host(dev, txwi, MT_TXD_SIZE, PKT_BIN_DEBUG_TXD, 0);
230+ if (dev->dbg.dump_tx_pkt)
231+ mt7915_packet_log_to_host(dev, t->skb->data, t->skb->len, PKT_BIN_DEBUG_TX, 0);
232+#endif
233 return 0;
234 }
235
236diff --git a/mt7915/mcu.c b/mt7915/mcu.c
237index 549281a4..15a6fe5a 100644
238--- a/mt7915/mcu.c
239+++ b/mt7915/mcu.c
240@@ -298,6 +298,10 @@ mt7915_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
241 mcu_txd->s2d_index = MCU_S2D_H2N;
242
243 exit:
244+#ifdef MTK_DEBUG
245+ if (dev->dbg.dump_mcu_pkt)
246+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_MCU, 0);
247+#endif
248 if (wait_seq)
249 *wait_seq = seq;
250
251@@ -3613,3 +3617,40 @@ int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev,
252 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TWT_AGRT_UPDATE),
253 &req, sizeof(req), true);
254 }
255+
256+#ifdef MTK_DEBUG
257+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp)
258+{
259+ struct {
260+ __le32 args[3];
261+ } req = {
262+ .args = {
263+ cpu_to_le32(a1),
264+ cpu_to_le32(a2),
265+ cpu_to_le32(a3),
266+ },
267+ };
268+
269+ return mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), wait_resp);
270+}
271+
272+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled)
273+{
274+#define RED_DISABLE 0
275+#define RED_BY_HOST_ENABLE 1
276+#define RED_BY_WA_ENABLE 2
277+ int ret;
278+ u32 red_type = enabled > 0 ? RED_BY_WA_ENABLE : RED_DISABLE;
279+ __le32 req = cpu_to_le32(red_type);
280+
281+ ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RED_ENABLE), &req,
282+ sizeof(req), false);
283+ if (ret < 0)
284+ return ret;
285+
286+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
287+ MCU_WA_PARAM_RED, enabled, 0, true);
288+
289+ return 0;
290+}
291+#endif
292diff --git a/mt7915/mcu.h b/mt7915/mcu.h
293index 52368dc3..94e0a81b 100644
294--- a/mt7915/mcu.h
295+++ b/mt7915/mcu.h
296@@ -296,6 +296,10 @@ enum {
297 MCU_WA_PARAM_PDMA_RX = 0x04,
298 MCU_WA_PARAM_CPU_UTIL = 0x0b,
299 MCU_WA_PARAM_RED = 0x0e,
300+#ifdef MTK_DEBUG
301+ MCU_WA_PARAM_RED_SHOW_STA = 0xf,
302+ MCU_WA_PARAM_RED_TARGET_DELAY = 0x10,
303+#endif
304 };
305
306 enum mcu_mmps_mode {
307diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
308index 6efa0a2e..8bcd861f 100644
309--- a/mt7915/mt7915.h
310+++ b/mt7915/mt7915.h
311@@ -9,6 +9,7 @@
312 #include "../mt76_connac.h"
313 #include "regs.h"
314
315+#define MTK_DEBUG 1
316 #define MT7915_MAX_INTERFACES 19
317 #define MT7915_MAX_WMM_SETS 4
318 #define MT7915_WTBL_SIZE 288
319@@ -326,6 +327,27 @@ struct mt7915_dev {
320 struct reset_control *rstc;
321 void __iomem *dcm;
322 void __iomem *sku;
323+
324+#ifdef MTK_DEBUG
325+ u16 wlan_idx;
326+ struct {
327+ u32 fixed_rate;
328+ u32 l1debugfs_reg;
329+ u32 l2debugfs_reg;
330+ u32 mac_reg;
331+ u32 fw_dbg_module;
332+ u8 fw_dbg_lv;
333+ u32 bcn_total_cnt[2];
334+ u16 fwlog_seq;
335+ bool dump_mcu_pkt;
336+ bool dump_txd;
337+ bool dump_tx_pkt;
338+ bool dump_rx_pkt;
339+ bool dump_rx_raw;
340+ u32 token_idx;
341+ } dbg;
342+ const struct mt7915_dbg_reg_desc *dbg_reg;
343+#endif
344 };
345
346 enum {
347@@ -593,4 +615,23 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
348 struct ieee80211_sta *sta, struct dentry *dir);
349 #endif
350
351+#ifdef MTK_DEBUG
352+int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir);
353+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp);
354+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled);
355+void mt7915_dump_tmac_info(u8 *tmac_info);
356+int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level);
357+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len);
358+
359+#define PKT_BIN_DEBUG_MAGIC 0xc8763123
360+enum {
361+ PKT_BIN_DEBUG_MCU,
362+ PKT_BIN_DEBUG_TXD,
363+ PKT_BIN_DEBUG_TX,
364+ PKT_BIN_DEBUG_RX,
365+ PKT_BIN_DEBUG_RX_RAW,
366+};
367+
368+#endif
369+
370 #endif
371diff --git a/mt7915/mt7915_debug.h b/mt7915/mt7915_debug.h
372new file mode 100644
373index 00000000..59c057e0
374--- /dev/null
375+++ b/mt7915/mt7915_debug.h
376@@ -0,0 +1,1350 @@
377+#ifndef __MT7915_DEBUG_H
378+#define __MT7915_DEBUG_H
379+
380+#ifdef MTK_DEBUG
381+
382+#define DBG_INVALID_BASE 0xffffffff
383+#define DBG_INVALID_OFFSET 0x0
384+
385+struct __dbg_map {
386+ u32 phys;
387+ u32 maps;
388+ u32 size;
389+};
390+
391+struct __dbg_reg {
392+ u32 base;
393+ u32 offs;
394+};
395+
396+struct __dbg_mask {
397+ u32 end;
398+ u32 start;
399+};
400+
401+enum dbg_base_rev {
402+ MT_DBG_WFDMA0_BASE,
403+ MT_DBG_WFDMA1_BASE,
404+ MT_DBG_WFDMA0_PCIE1_BASE,
405+ MT_DBG_WFDMA1_PCIE1_BASE,
406+ MT_DBG_WFDMA_EXT_CSR_BASE,
407+ MT_DBG_SWDEF_BASE,
408+ __MT_DBG_BASE_REV_MAX,
409+};
410+
411+enum dbg_reg_rev {
412+ DBG_INT_SOURCE_CSR,
413+ DBG_INT_MASK_CSR,
414+ DBG_INT1_SOURCE_CSR,
415+ DBG_INT1_MASK_CSR,
416+ DBG_TX_RING_BASE,
417+ DBG_RX_EVENT_RING_BASE,
418+ DBG_RX_STS_RING_BASE,
419+ DBG_RX_DATA_RING_BASE,
420+ DBG_DMA_ICSC_FR0,
421+ DBG_DMA_ICSC_FR1,
422+ DBG_TMAC_ICSCR0,
423+ DBG_RMAC_RXICSRPT,
424+ DBG_MIB_M0SDR0,
425+ DBG_MIB_M0SDR3,
426+ DBG_MIB_M0SDR4,
427+ DBG_MIB_M0SDR5,
428+ DBG_MIB_M0SDR7,
429+ DBG_MIB_M0SDR8,
430+ DBG_MIB_M0SDR9,
431+ DBG_MIB_M0SDR10,
432+ DBG_MIB_M0SDR11,
433+ DBG_MIB_M0SDR12,
434+ DBG_MIB_M0SDR14,
435+ DBG_MIB_M0SDR15,
436+ DBG_MIB_M0SDR16,
437+ DBG_MIB_M0SDR17,
438+ DBG_MIB_M0SDR18,
439+ DBG_MIB_M0SDR19,
440+ DBG_MIB_M0SDR20,
441+ DBG_MIB_M0SDR21,
442+ DBG_MIB_M0SDR22,
443+ DBG_MIB_M0SDR23,
444+ DBG_MIB_M0DR0,
445+ DBG_MIB_M0DR1,
446+ DBG_MIB_MUBF,
447+ DBG_MIB_M0DR6,
448+ DBG_MIB_M0DR7,
449+ DBG_MIB_M0DR8,
450+ DBG_MIB_M0DR9,
451+ DBG_MIB_M0DR10,
452+ DBG_MIB_M0DR11,
453+ DBG_MIB_M0DR12,
454+ DBG_WTBLON_WDUCR,
455+ DBG_UWTBL_WDUCR,
456+ DBG_PLE_DRR_TABLE_CTRL,
457+ DBG_PLE_DRR_TABLE_RDATA,
458+ DBG_PLE_PBUF_CTRL,
459+ DBG_PLE_QUEUE_EMPTY,
460+ DBG_PLE_FREEPG_CNT,
461+ DBG_PLE_FREEPG_HEAD_TAIL,
462+ DBG_PLE_PG_HIF_GROUP,
463+ DBG_PLE_HIF_PG_INFO,
464+ DBG_PLE_PG_HIF_TXCMD_GROUP,
465+ DBG_PLE_HIF_TXCMD_PG_INFO,
466+ DBG_PLE_PG_CPU_GROUP,
467+ DBG_PLE_CPU_PG_INFO,
468+ DBG_PLE_FL_QUE_CTRL,
469+ DBG_PLE_NATIVE_TXCMD_Q_EMPTY,
470+ DBG_PLE_TXCMD_Q_EMPTY,
471+ DBG_PLE_AC_QEMPTY,
472+ DBG_PLE_AC_OFFSET,
473+ DBG_PLE_STATION_PAUSE,
474+ DBG_PLE_DIS_STA_MAP,
475+ DBG_PSE_PBUF_CTRL,
476+ DBG_PSE_FREEPG_CNT,
477+ DBG_PSE_FREEPG_HEAD_TAIL,
478+ DBG_PSE_HIF0_PG_INFO,
479+ DBG_PSE_PG_HIF1_GROUP,
480+ DBG_PSE_HIF1_PG_INFO,
481+ DBG_PSE_PG_CPU_GROUP,
482+ DBG_PSE_CPU_PG_INFO,
483+ DBG_PSE_PG_PLE_GROUP,
484+ DBG_PSE_PLE_PG_INFO,
485+ DBG_PSE_PG_LMAC0_GROUP,
486+ DBG_PSE_LMAC0_PG_INFO,
487+ DBG_PSE_PG_LMAC1_GROUP,
488+ DBG_PSE_LMAC1_PG_INFO,
489+ DBG_PSE_PG_LMAC2_GROUP,
490+ DBG_PSE_LMAC2_PG_INFO,
491+ DBG_PSE_PG_LMAC3_GROUP,
492+ DBG_PSE_LMAC3_PG_INFO,
493+ DBG_PSE_PG_MDP_GROUP,
494+ DBG_PSE_MDP_PG_INFO,
495+ DBG_PSE_PG_PLE1_GROUP,
496+ DBG_PSE_PLE1_PG_INFO,
497+ DBG_AGG_AALCR0,
498+ DBG_AGG_AALCR1,
499+ DBG_AGG_AALCR2,
500+ DBG_AGG_AALCR3,
501+ DBG_AGG_AALCR4,
502+ DBG_AGG_B0BRR0,
503+ DBG_AGG_B1BRR0,
504+ DBG_AGG_B2BRR0,
505+ DBG_AGG_B3BRR0,
506+ DBG_AGG_AWSCR0,
507+ DBG_AGG_PCR0,
508+ DBG_AGG_TTCR0,
509+ DBG_MIB_M0ARNG0,
510+ DBG_MIB_M0DR2,
511+ DBG_MIB_M0DR13,
512+ __MT_DBG_REG_REV_MAX,
513+};
514+
515+enum dbg_mask_rev {
516+ DBG_MIB_M0SDR10_RX_MDRDY_COUNT,
517+ DBG_MIB_M0SDR14_AMPDU,
518+ DBG_MIB_M0SDR15_AMPDU_ACKED,
519+ DBG_MIB_RX_FCS_ERROR_COUNT,
520+ __MT_DBG_MASK_REV_MAX,
521+};
522+
523+enum dbg_bit_rev {
524+ __MT_DBG_BIT_REV_MAX,
525+};
526+
527+static const u32 mt7915_dbg_base[] = {
528+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
529+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
530+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
531+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
532+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
533+ [MT_DBG_SWDEF_BASE] = 0x41f200,
534+};
535+
536+static const u32 mt7916_dbg_base[] = {
537+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
538+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
539+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
540+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
541+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
542+ [MT_DBG_SWDEF_BASE] = 0x411400,
543+};
544+
545+static const u32 mt7986_dbg_base[] = {
546+ [MT_DBG_WFDMA0_BASE] = 0x24000,
547+ [MT_DBG_WFDMA1_BASE] = 0x25000,
548+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0x28000,
549+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0x29000,
550+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0x27000,
551+ [MT_DBG_SWDEF_BASE] = 0x411400,
552+};
553+
554+/* mt7915 regs with different base and offset */
555+static const struct __dbg_reg mt7915_dbg_reg[] = {
556+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x10 },
557+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x14 },
558+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x88 },
559+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x8c },
560+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x400 },
561+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x500 },
562+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x510 },
563+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
564+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x0f0 },
565+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x0f4 },
566+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x200 },
567+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0x618},
568+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x010},
569+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x014},
570+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x018},
571+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x01c},
572+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x024},
573+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x028},
574+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x02C},
575+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x030},
576+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x034},
577+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x038},
578+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x040},
579+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x044},
580+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x048},
581+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x04c},
582+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x050},
583+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x054},
584+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x058},
585+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x05c},
586+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x060},
587+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x064},
588+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x0a0},
589+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x0a4},
590+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x090},
591+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x0b8},
592+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x0bc},
593+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x0c0},
594+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x0c4},
595+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x0c8},
596+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x0cc},
597+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x160},
598+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x0},
599+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x0},
600+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x388},
601+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x350},
602+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
603+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x0b0},
604+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
605+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
606+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x110},
607+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x114},
608+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x120},
609+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x124},
610+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
611+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
612+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x1b0},
613+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x22c},
614+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x230},
615+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x500},
616+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x040},
617+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x400},
618+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x440},
619+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
620+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
621+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
622+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x114},
623+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x118},
624+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x11c},
625+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
626+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
627+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x160},
628+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x164},
629+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x170},
630+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x174},
631+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x178},
632+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
633+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x180},
634+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x184},
635+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x188},
636+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x18c},
637+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x198},
638+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x19c},
639+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x168},
640+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
641+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x048},
642+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x04c},
643+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x050},
644+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x054},
645+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x058},
646+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x100},
647+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x104},
648+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x108},
649+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x10c},
650+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x030},
651+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x040},
652+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x04c},
653+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x4b8},
654+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x0a8},
655+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x164},
656+};
657+
658+/* mt7986/mt7916 regs with different base and offset */
659+static const struct __dbg_reg mt7916_dbg_reg[] = {
660+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA0_BASE, 0x200 },
661+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA0_BASE, 0x204 },
662+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x200 },
663+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x204 },
664+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x400 },
665+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
666+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x520 },
667+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x540 },
668+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x05c },
669+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x060 },
670+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x120 },
671+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0xd0 },
672+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x7d8},
673+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x698},
674+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x788},
675+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x780},
676+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x5a8},
677+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x78c},
678+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x024},
679+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x76c},
680+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x790},
681+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x558},
682+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x564},
683+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x564},
684+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x7fc},
685+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x800},
686+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x030},
687+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x5ac},
688+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x5b0},
689+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x5b4},
690+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x770},
691+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x774},
692+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x594},
693+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x598},
694+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x7ac},
695+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x658},
696+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x65c},
697+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x56c},
698+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x570},
699+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x578},
700+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x574},
701+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x654},
702+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x200},
703+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x094},
704+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x490},
705+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x470},
706+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
707+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x360},
708+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
709+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
710+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x00c},
711+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x388},
712+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x014},
713+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x390},
714+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x018},
715+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x394},
716+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x3e0},
717+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x370},
718+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x374},
719+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x600},
720+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x080},
721+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x100},
722+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x180},
723+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
724+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
725+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
726+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x150},
727+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x154},
728+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
729+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x118},
730+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x158},
731+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x11c},
732+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x15c},
733+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x124},
734+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x164},
735+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x128},
736+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x168},
737+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x12c},
738+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
739+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x130},
740+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
741+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x134},
742+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x174},
743+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x120},
744+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
745+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x028},
746+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x144},
747+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x14c},
748+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x154},
749+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x02c},
750+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x08c},
751+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x148},
752+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x150},
753+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x158},
754+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x05c},
755+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x06c},
756+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x07c},
757+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x0b0},
758+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x7dc},
759+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x7ec},
760+};
761+
762+static const struct __dbg_mask mt7915_dbg_mask[] = {
763+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {25, 0},
764+ [DBG_MIB_M0SDR14_AMPDU] = {23, 0},
765+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {23, 0},
766+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {15, 0},
767+};
768+
769+static const struct __dbg_mask mt7916_dbg_mask[] = {
770+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {31, 0},
771+ [DBG_MIB_M0SDR14_AMPDU] = {31, 0},
772+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {31, 0},
773+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {31, 16},
774+};
775+
776+/* used to differentiate between generations */
777+struct mt7915_dbg_reg_desc {
778+ const u32 id;
779+ const u32 *base_rev;
780+ const struct __dbg_reg *reg_rev;
781+ const struct __dbg_mask *mask_rev;
782+};
783+
784+static const struct mt7915_dbg_reg_desc dbg_reg_s[] = {
785+ { 0x7915,
786+ mt7915_dbg_base,
787+ mt7915_dbg_reg,
788+ mt7915_dbg_mask
789+ },
790+ { 0x7906,
791+ mt7916_dbg_base,
792+ mt7916_dbg_reg,
793+ mt7916_dbg_mask
794+ },
795+ { 0x7986,
796+ mt7986_dbg_base,
797+ mt7916_dbg_reg,
798+ mt7916_dbg_mask
799+ },
800+};
801+
802+struct bin_debug_hdr {
803+ __le32 magic_num;
804+ __le16 serial_id;
805+ __le16 msg_type;
806+ __le16 len;
807+ __le16 des_len; /* descriptor len for rxd */
808+} __packed;
809+
810+#define __DBG_REG_MAP(_dev, id, ofs) ((_dev)->dbg_reg->base_rev[(id)] + (ofs))
811+#define __DBG_REG_BASE(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].base)
812+#define __DBG_REG_OFFS(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].offs)
813+
814+#define __DBG_MASK(_dev, id) GENMASK((_dev)->dbg_reg->mask_rev[(id)].end, \
815+ (_dev)->dbg_reg->mask_rev[(id)].start)
816+#define __DBG_REG(_dev, id) __DBG_REG_MAP((_dev), __DBG_REG_BASE((_dev), (id)), \
817+ __DBG_REG_OFFS((_dev), (id)))
818+
819+#define __DBG_FIELD_GET(id, _reg) (((_reg) & __DBG_MASK(dev, (id))) >> \
820+ dev->dbg_reg->mask_rev[(id)].start)
821+#define __DBG_FIELD_PREP(id, _reg) (((_reg) << dev->dbg_reg->mask_rev[(id)].start) & \
822+ __DBG_MASK(dev, (id)))
823+
824+
825+#define MT_DBG_TX_RING_BASE __DBG_REG(dev, DBG_TX_RING_BASE)
826+#define MT_DBG_RX_EVENT_RING_BASE __DBG_REG(dev, DBG_RX_EVENT_RING_BASE)
827+#define MT_DBG_RX_STS_RING_BASE __DBG_REG(dev, DBG_RX_STS_RING_BASE)
828+#define MT_DBG_RX_DATA_RING_BASE __DBG_REG(dev, DBG_RX_DATA_RING_BASE)
829+
830+#define MT_DBG_TX_RING_CTRL(n) (MT_DBG_TX_RING_BASE + (0x10 * (n)))
831+#define MT_DBG_RX_DATA_RING_CTRL(n) (MT_DBG_RX_DATA_RING_BASE + (0x10 * (n)))
832+#define MT_DBG_RX_EVENT_RING_CTRL(n) (MT_DBG_RX_EVENT_RING_BASE + (0x10 * (n)))
833+
834+/* WFDMA COMMON */
835+#define MT_DBG_INT_SOURCE_CSR __DBG_REG(dev, DBG_INT_SOURCE_CSR)
836+#define MT_DBG_INT_MASK_CSR __DBG_REG(dev, DBG_INT_MASK_CSR)
837+#define MT_DBG_INT1_SOURCE_CSR __DBG_REG(dev, DBG_INT1_SOURCE_CSR)
838+#define MT_DBG_INT1_MASK_CSR __DBG_REG(dev, DBG_INT1_MASK_CSR)
839+
840+/* WFDMA0 */
841+#define MT_DBG_WFDMA0(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_BASE, (_ofs))
842+
843+#define MT_DBG_WFDMA0_INT_SOURCE_CSR MT_DBG_WFDMA0(0x200)
844+#define MT_DBG_WFDMA0_INT_MASK_CSR MT_DBG_WFDMA0(0x204)
845+
846+#define MT_DBG_WFDMA0_GLO_CFG MT_DBG_WFDMA0(0x208)
847+#define MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
848+#define MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
849+#define MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK BIT(1)
850+#define MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK BIT(3)
851+
852+
853+/* WFDMA1 */
854+#define MT_DBG_WFDMA1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_BASE, (_ofs))
855+#define MT_DBG_WFDMA1_INT_SOURCE_CSR MT_DBG_WFDMA1(0x200)
856+#define MT_DBG_WFDMA1_INT_MASK_CSR MT_DBG_WFDMA1(0x204)
857+
858+#define MT_DBG_WFDMA1_GLO_CFG MT_DBG_WFDMA1(0x208)
859+
860+#define MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
861+#define MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
862+#define MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK BIT(1)
863+#define MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK BIT(3)
864+
865+/* WFDMA0 PCIE1 */
866+#define MT_DBG_WFDMA0_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_PCIE1_BASE, (_ofs))
867+
868+#define MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA0_PCIE1(0x200)
869+#define MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR MT_DBG_WFDMA0_PCIE1(0x204)
870+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG MT_DBG_WFDMA0_PCIE1(0x208)
871+#define MT_DBG_WFDMA0_PCIE1_RX1_CTRL0 MT_DBG_WFDMA1_PCIE1(0x510)
872+
873+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
874+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
875+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
876+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
877+
878+/* WFDMA1 PCIE1 */
879+#define MT_DBG_WFDMA1_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_PCIE1_BASE, (_ofs))
880+#define MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA1_PCIE1(0x200)
881+#define MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR MT_DBG_WFDMA1_PCIE1(0x204)
882+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG MT_DBG_WFDMA1_PCIE1(0x208)
883+#define MT_DBG_WFDMA1_PCIE1_TX19_CTRL0 MT_DBG_WFDMA1_PCIE1(0x330)
884+#define MT_DBG_WFDMA1_PCIE1_RX2_CTRL0 MT_DBG_WFDMA1_PCIE1(0x520)
885+
886+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
887+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
888+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
889+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
890+
891+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK BIT(2)
892+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK BIT(0)
893+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK BIT(3)
894+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK BIT(1)
895+
896+
897+/* WF DMA TOP: band 0(0x820E7000),band 1(0x820F7000) */
898+#define MT_DBG_WF_DMA_BASE(_band) ((_band) ? 0x820F7000 : 0x820E7000)
899+#define MT_DBG_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
900+
901+#define MT_DBG_DMA_DCR0(_band) MT_DBG_WF_DMA((_band), 0x000)
902+#define MT_DBG_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
903+#define MT_DBG_DMA_DCR0_RXD_G5_EN BIT(23)
904+
905+#define MT_DBG_DMA_ICSC_FR0(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR0))
906+#define MT_DBG_DMA_ICSC_FR0_RXBF_EN BIT(25)
907+#define MT_DBG_DMA_ICSC_FR0_EN BIT(24)
908+#define MT_DBG_DMA_ICSC_FR0_TOUT_MASK GENMASK(23, 16)
909+#define MT_DBG_DMA_ICSC_FR0_PID_MASK GENMASK(9, 8)
910+#define MT_DBG_DMA_ICSC_FR0_QID_MASK GENMASK(6, 0)
911+
912+#define MT_DBG_DMA_ICSC_FR1(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR1))
913+#define MT_DBG_DMA_ICSC_FR1_AGG_SIZE_MASK GENMASK(26, 16)
914+#define MT_DBG_DMA_ICSC_FR1_MAX_FRAME_SIZE_MASK GENMASK(10, 0)
915+
916+/* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
917+#define MT_DBG_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
918+#define MT_DBG_WF_TMAC(_band, ofs) (MT_DBG_WF_TMAC_BASE(_band) + (ofs))
919+
920+#define MT_DBG_TMAC_ICSCR0(_band) MT_DBG_WF_TMAC((_band), __DBG_REG_OFFS(dev, DBG_TMAC_ICSCR0))
921+#define MT_DBG_TMAC_ICSCR0_ICSRPT_EN BIT(0)
922+
923+/* RMAC: band 0(0x820E5000), band 1(0x820f5000) */
924+#define MT_DBG_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820E5000)
925+#define MT_DBG_WF_RMAC(_band, ofs) (MT_DBG_WF_RMAC_BASE(_band) + (ofs))
926+
927+#define MT_DBG_RMAC_RXICSRPT(_band) MT_DBG_WF_RMAC((_band), __DBG_REG_OFFS(dev, DBG_RMAC_RXICSRPT))
928+#define MT_DBG_RMAC_RXICSRPT_ICSRPT_EN BIT(0)
929+
930+/* MIB: band 0(0x820ed000), band 1(0x820fd000) */
931+#define MT_DBG_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
932+#define MT_DBG_MIB(_band, ofs) (MT_DBG_MIB_BASE(_band) + (ofs))
933+
934+
935+#define MT_DBG_MIB_M0SCR0(_band) MT_DBG_MIB((_band), 0x00)
936+#define MT_DBG_MIB_M0PBSCR(_band) MT_DBG_MIB((_band), 0x04)
937+
938+#define MT_DBG_MIB_M0SDR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR0))
939+#define MT_DBG_MIB_M0SDR3(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR3))
940+#define MT_DBG_MIB_RX_FCS_ERROR_COUNT_MASK __DBG_MASK(dev, DBG_MIB_RX_FCS_ERROR_COUNT)
941+#define MT_DBG_MIB_M0SDR4(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR4))
942+#define MT_DBG_MIB_M0SDR5(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR5))
943+#define MT_DBG_MIB_M0SDR6(_band) MT_DBG_MIB((_band), 0x20)
944+#define MT_DBG_MIB_M0SDR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR7))
945+#define MT_DBG_MIB_M0SDR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR8))
946+#define MT_DBG_MIB_M0SDR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR9))
947+#define MT_DBG_MIB_M0SDR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR10))
948+#define MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK __DBG_MASK(dev, DBG_MIB_M0SDR10_RX_MDRDY_COUNT)
949+#define MT_DBG_MIB_M0SDR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR11))
950+
951+#define MT_DBG_MIB_M0SDR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR12))
952+
953+#define MT_DBG_MIB_M0SDR14(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR14))
954+#define MT_DBG_MIB_M0SDR14_AMPDU_MASK __DBG_MASK(dev, DBG_MIB_M0SDR14_AMPDU)
955+#define MT_DBG_MIB_M0SDR15(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR15))
956+#define MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK __DBG_MASK(dev, DBG_MIB_M0SDR15_AMPDU_ACKED)
957+#define MT_DBG_MIB_M0SDR16(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR16))
958+#define MT_DBG_MIB_M0SDR17(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR17))
959+#define MT_DBG_MIB_M0SDR18(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR18))
960+#define MT_DBG_MIB_M0SDR19(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR19))
961+#define MT_DBG_MIB_M0SDR20(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR20))
962+#define MT_DBG_MIB_M0SDR21(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR21))
963+#define MT_DBG_MIB_M0SDR22(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR22))
964+#define MT_DBG_MIB_M0SDR23(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR23))
965+#define MT_DBG_MIB_M0DR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR0))
966+#define MT_DBG_MIB_M0DR1(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR1))
967+
968+#define MT_DBG_MIB_MUBF(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_MUBF))
969+#define MT_DBG_MIB_M0DR6(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR6))
970+#define MT_DBG_MIB_M0DR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR7))
971+#define MT_DBG_MIB_M0DR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR8))
972+#define MT_DBG_MIB_M0DR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR9))
973+#define MT_DBG_MIB_M0DR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR10))
974+#define MT_DBG_MIB_M0DR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR11))
975+ #define MT_DBG_MIB_M0DR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR12))
976+
977+/* WTBLON TOP: 0x820D4000/pcie(0x34000) rbus(0x434000) */
978+#define MT_DBG_WTBLON_TOP_BASE 0x820D4000
979+#define MT_DBG_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
980+#define MT_DBG_WTBLON_TOP_WDUCR MT_DBG_WTBLON_TOP(__DBG_REG_OFFS(dev, DBG_WTBLON_WDUCR))
981+#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
982+
983+#define WF_WTBLON_TOP_B0BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1000) // 5000
984+#define WF_WTBLON_TOP_B0BTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1010) // 5010
985+#define WF_WTBLON_TOP_B0BRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1020) // 5020
986+#define WF_WTBLON_TOP_B0BRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1030) // 5030
987+#define WF_WTBLON_TOP_B0BTDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1040) // 5040
988+#define WF_WTBLON_TOP_B0BRDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1050) // 5050
989+#define WF_WTBLON_TOP_B0MBTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1100) // 5100
990+#define WF_WTBLON_TOP_B0MBTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1140) // 5140
991+#define WF_WTBLON_TOP_B0MBRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1180) // 5180
992+#define WF_WTBLON_TOP_B0MBRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x11C0) // 51C0
993+
994+#define WF_WTBLON_TOP_B1BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1800) // 5800
995+
996+/* WTBLON TOP: 0x820C4000/pcie(0xa8000) rbus(0x4a8000) */
997+#define MT_DBG_UWTBL_TOP_BASE 0x820C4000
998+#define MT_DBG_UWTBL_TOP(ofs) (MT_DBG_UWTBL_TOP_BASE + (ofs))
999+
1000+#define MT_DBG_UWTBL_TOP_WDUCR MT_DBG_WTBLON_TOP(__DBG_REG_OFFS(dev, DBG_UWTBL_WDUCR))
1001+
1002+#define MT_UWTBL_TOP_WDUCR_TARGET BIT(31)
1003+#define MT_UWTBL_TOP_WDUCR_GROUP GENMASK(3, 0)
1004+
1005+
1006+/* WTBL : 0x820D8000/pcie(0x38000) rbus(0x438000) */
1007+#define MT_DBG_WTBL_BASE 0x820D8000
1008+
1009+/* PLE related CRs. */
1010+#define MT_DBG_PLE_BASE 0x820C0000
1011+#define MT_DBG_PLE(ofs) (MT_DBG_PLE_BASE + (ofs))
1012+
1013+#define MT_DBG_PLE_DRR_TAB_CTRL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_CTRL))
1014+#define MT_DBG_PLE_DRR_TAB_RD_OFS __DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_RDATA)
1015+
1016+#define MT_DBG_PLE_DRR_TABLE_RDATA0 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x0)
1017+#define MT_DBG_PLE_DRR_TABLE_RDATA1 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x4)
1018+#define MT_DBG_PLE_DRR_TABLE_RDATA2 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x8)
1019+#define MT_DBG_PLE_DRR_TABLE_RDATA3 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0xc)
1020+#define MT_DBG_PLE_DRR_TABLE_RDATA4 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x10)
1021+#define MT_DBG_PLE_DRR_TABLE_RDATA5 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x14)
1022+#define MT_DBG_PLE_DRR_TABLE_RDATA6 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x18)
1023+#define MT_DBG_PLE_DRR_TABLE_RDATA7 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS+ 0x1c)
1024+
1025+#define MT_DBG_PLE_PBUF_CTRL_ADDR MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PBUF_CTRL))
1026+#define MT_DBG_PLE_QUEUE_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_QUEUE_EMPTY))
1027+#define MT_DBG_PLE_FREEPG_CNT MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_CNT))
1028+#define MT_DBG_PLE_FREEPG_HEAD_TAIL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_HEAD_TAIL))
1029+#define MT_DBG_PLE_PG_HIF_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_GROUP))
1030+#define MT_DBG_PLE_HIF_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_PG_INFO))
1031+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_TXCMD_GROUP))
1032+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_TXCMD_PG_INFO))
1033+#define MT_DBG_PLE_PG_CPU_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_CPU_GROUP))
1034+#define MT_DBG_PLE_CPU_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_CPU_PG_INFO))
1035+#define PLE_FL_QUE_CTRL_OFFSET __DBG_REG_OFFS(dev, DBG_PLE_FL_QUE_CTRL)
1036+#define MT_DBG_PLE_FL_QUE_CTRL0 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x0)
1037+#define MT_DBG_PLE_FL_QUE_CTRL1 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x4)
1038+#define MT_DBG_PLE_FL_QUE_CTRL2 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x8)
1039+#define MT_DBG_PLE_FL_QUE_CTRL3 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0xc)
1040+#define MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_NATIVE_TXCMD_Q_EMPTY))
1041+#define MT_DBG_PLE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_TXCMD_Q_EMPTY))
1042+
1043+#define MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK BIT(31)
1044+#define MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK GENMASK(25, 17)
1045+#define MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1046+
1047+#define MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1048+#define MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1049+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1050+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1051+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK GENMASK(27, 16)
1052+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK GENMASK(11, 0)
1053+
1054+#define MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK GENMASK(27, 16)
1055+#define MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK GENMASK(11, 0)
1056+
1057+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK GENMASK(27, 16)
1058+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK GENMASK(11, 0)
1059+
1060+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
1061+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
1062+
1063+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
1064+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
1065+
1066+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1067+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1068+
1069+#define MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1070+#define MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1071+
1072+#define MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK BIT(24)
1073+#define MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK BIT(31)
1074+#define MT_DBG_PLE_FL_QUE_CTRL0_Q_BUF_QID_MASK GENMASK(30, 24)
1075+
1076+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT 24
1077+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT 10
1078+
1079+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK GENMASK(27, 16)
1080+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK GENMASK(11, 0)
1081+#define MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK GENMASK(11, 0)
1082+
1083+#define MT_DBG_PLE_STATION_PAUSE(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_STATION_PAUSE) + ((n) << 2))
1084+#define MT_DBG_PLE_DIS_STA_MAP(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DIS_STA_MAP) + ((n) << 2))
1085+#define MT_DBG_PLE_AC_QEMPTY(ac, n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_AC_QEMPTY) + \
1086+ __DBG_REG_OFFS(dev, DBG_PLE_AC_OFFSET) * (ac) + ((n) << 2))
1087+
1088+#define MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(n) MT_DBG_PLE(0x10e0 + ((n) << 2))
1089+
1090+/* pseinfo related CRs. */
1091+#define MT_DBG_PSE_BASE 0x820C8000
1092+#define MT_DBG_PSE(ofs) (MT_DBG_PSE_BASE + (ofs))
1093+
1094+#define MT_DBG_PSE_PBUF_CTRL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PBUF_CTRL))
1095+#define MT_DBG_PSE_QUEUE_EMPTY MT_DBG_PLE(0x0b0)
1096+#define MT_DBG_PSE_FREEPG_CNT MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_CNT))
1097+#define MT_DBG_PSE_FREEPG_HEAD_TAIL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_HEAD_TAIL))
1098+#define MT_DBG_PSE_PG_HIF0_GROUP MT_DBG_PLE(0x110)
1099+#define MT_DBG_PSE_HIF0_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_HIF0_PG_INFO))
1100+#define MT_DBG_PSE_PG_HIF1_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_HIF1_GROUP))
1101+#define MT_DBG_PSE_HIF1_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_HIF1_PG_INFO))
1102+#define MT_DBG_PSE_PG_CPU_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_CPU_GROUP))
1103+#define MT_DBG_PSE_CPU_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_CPU_PG_INFO))
1104+#define MT_DBG_PSE_PG_LMAC0_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC0_GROUP))
1105+#define MT_DBG_PSE_LMAC0_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC0_PG_INFO))
1106+#define MT_DBG_PSE_PG_LMAC1_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC1_GROUP))
1107+#define MT_DBG_PSE_LMAC1_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC1_PG_INFO))
1108+#define MT_DBG_PSE_PG_LMAC2_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC2_GROUP))
1109+#define MT_DBG_PSE_LMAC2_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC2_PG_INFO))
1110+#define MT_DBG_PSE_PG_PLE_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE_GROUP))
1111+#define MT_DBG_PSE_PLE_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PLE_PG_INFO))
1112+#define MT_DBG_PSE_PG_LMAC3_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC3_GROUP))
1113+#define MT_DBG_PSE_LMAC3_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC3_PG_INFO))
1114+#define MT_DBG_PSE_PG_MDP_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_MDP_GROUP))
1115+#define MT_DBG_PSE_MDP_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_MDP_PG_INFO))
1116+#define MT_DBG_PSE_PG_PLE1_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE1_GROUP))
1117+#define MT_DBG_PSE_PLE1_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PSE_PLE1_PG_INFO))
1118+
1119+#define MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK BIT(31)
1120+#define MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK GENMASK(25, 17)
1121+#define MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
1122+#define MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK BIT(31)
1123+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK BIT(23)
1124+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK BIT(22)
1125+#define MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK BIT(21)
1126+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT BIT(20)
1127+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK BIT(19)
1128+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK BIT(18)
1129+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK BIT(17)
1130+#define MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK BIT(16)
1131+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK BIT(13)
1132+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK BIT(12)
1133+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK BIT(11)
1134+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK BIT(10)
1135+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK BIT(9)
1136+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK BIT(8)
1137+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK BIT(3)
1138+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK BIT(2)
1139+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK BIT(1)
1140+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK BIT(0)
1141+#define MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
1142+#define MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
1143+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
1144+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
1145+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1146+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1147+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
1148+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
1149+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK GENMASK(27, 16)
1150+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK GENMASK(11, 0)
1151+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK GENMASK(27, 16)
1152+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK GENMASK(11, 0)
1153+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK GENMASK(27, 16)
1154+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK GENMASK(11, 0)
1155+#define MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
1156+#define MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
1157+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK GENMASK(27, 16)
1158+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK GENMASK(11, 0)
1159+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
1160+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
1161+#define MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK GENMASK(27, 16)
1162+#define MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK GENMASK(11, 0)
1163+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK GENMASK(27, 16)
1164+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK GENMASK(11, 0)
1165+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK GENMASK(27, 16)
1166+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK GENMASK(11, 0)
1167+#define MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK GENMASK(27, 16)
1168+#define MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK GENMASK(11, 0)
1169+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK GENMASK(27, 16)
1170+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK GENMASK(11, 0)
1171+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK GENMASK(27, 16)
1172+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK GENMASK(11, 0)
1173+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK GENMASK(27, 16)
1174+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK GENMASK(11, 0)
1175+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1176+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1177+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK GENMASK(27, 16)
1178+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK GENMASK(11, 0)
1179+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
1180+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
1181+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK GENMASK(27, 16)
1182+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK GENMASK(11, 0)
1183+#define MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK GENMASK(27, 16)
1184+#define MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK GENMASK(11, 0)
1185+
1186+#define MT_DBG_PSE_FL_QUE_CTRL_0_ADDR MT_DBG_PLE(0x1b0)
1187+#define MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK BIT(31)
1188+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24
1189+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT 10
1190+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK GENMASK(9, 0)
1191+
1192+#define MT_DBG_PSE_FL_QUE_CTRL_2_ADDR MT_DBG_PLE(0x1b8)
1193+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK GENMASK(27, 16)
1194+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK GENMASK(11, 0)
1195+
1196+#define MT_DBG_PSE_FL_QUE_CTRL_3_ADDR MT_DBG_PLE(0x1bc)
1197+#define MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK GENMASK(11, 0)
1198+
1199+
1200+/* AGG */
1201+#define MT_DBG_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
1202+#define MT_DBG_AGG(_band, ofs) (MT_DBG_AGG_BASE(_band) + (ofs))
1203+
1204+#define MT_DBG_AGG_AALCR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR0))
1205+#define MT_DBG_AGG_AALCR1(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR1))
1206+#define MT_DBG_AGG_AALCR2(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR2))
1207+#define MT_DBG_AGG_AALCR3(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR3))
1208+#define MT_DBG_AGG_AALCR4(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR4))
1209+#define MT_DBG_AGG_B0BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B0BRR0))
1210+#define MT_DBG_AGG_B1BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B1BRR0))
1211+#define MT_DBG_AGG_B2BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B2BRR0))
1212+#define MT_DBG_AGG_B3BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B3BRR0))
1213+#define MT_DBG_AGG_AWSCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AWSCR0) + ((n) << 2))
1214+#define MT_DBG_AGG_PCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_PCR0) + ((n) << 2))
1215+#define MT_DBG_AGG_TTCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_TTCR0) + ((n) << 2))
1216+#define MT_DBG_MIB_M0ARNG(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0ARNG0) + ((n) << 2))
1217+#define MT_DBG_MIB_M0DR2(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR2) + ((n) << 2))
1218+#define MT_DBG_MIB_M0DR13(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR13) + ((n) << 2))
1219+
1220+#define MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK GENMASK(31, 24)
1221+#define MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK GENMASK(23, 16)
1222+#define MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK GENMASK(15, 8)
1223+#define MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK GENMASK(7, 0)
1224+#define MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK GENMASK(7, 0)
1225+
1226+#define MT_DBG_AGG_AWSCR0_WINSIZE3_MASK GENMASK(31, 24)
1227+#define MT_DBG_AGG_AWSCR0_WINSIZE2_MASK GENMASK(23, 16)
1228+#define MT_DBG_AGG_AWSCR0_WINSIZE1_MASK GENMASK(15, 8)
1229+#define MT_DBG_AGG_AWSCR0_WINSIZE0_MASK GENMASK(7, 0)
1230+
1231+#define MT_DBG_AGG_AWSCR1_WINSIZE7_MASK GENMASK(31, 24)
1232+#define MT_DBG_AGG_AWSCR1_WINSIZE6_MASK GENMASK(23, 16)
1233+#define MT_DBG_AGG_AWSCR1_WINSIZE5_MASK GENMASK(15, 8)
1234+#define MT_DBG_AGG_AWSCR1_WINSIZE4_MASK GENMASK(7, 0)
1235+
1236+#define MT_DBG_AGG_AWSCR2_WINSIZEB_MASK GENMASK(31, 24)
1237+#define MT_DBG_AGG_AWSCR2_WINSIZEA_MASK GENMASK(23, 16)
1238+#define MT_DBG_AGG_AWSCR2_WINSIZE9_MASK GENMASK(15, 8)
1239+#define MT_DBG_AGG_AWSCR2_WINSIZE8_MASK GENMASK(7, 0)
1240+
1241+#define MT_DBG_AGG_AWSCR3_WINSIZEE_MASK GENMASK(23, 16)
1242+#define MT_DBG_AGG_AWSCR3_WINSIZED_MASK GENMASK(15, 8)
1243+#define MT_DBG_AGG_AWSCR3_WINSIZEC_MASK GENMASK(7, 0)
1244+
1245+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK GENMASK(31, 24)
1246+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK GENMASK(23, 16)
1247+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK GENMASK(15, 8)
1248+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK GENMASK(7, 0)
1249+
1250+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK GENMASK(31, 24)
1251+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK GENMASK(23, 16)
1252+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK GENMASK(15, 8)
1253+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK GENMASK(7, 0)
1254+
1255+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK GENMASK(31, 24)
1256+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK GENMASK(23, 16)
1257+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK GENMASK(15, 8)
1258+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK GENMASK(7, 0)
1259+
1260+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK GENMASK(23, 16)
1261+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK GENMASK(15, 8)
1262+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK GENMASK(7, 0)
1263+
1264+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK GENMASK(31, 16)
1265+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK GENMASK(15, 0)
1266+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK GENMASK(31, 16)
1267+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK GENMASK(15, 0)
1268+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK GENMASK(31, 16)
1269+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK GENMASK(15, 0)
1270+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK GENMASK(31, 16)
1271+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK GENMASK(15, 0)
1272+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK GENMASK(31, 16)
1273+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK GENMASK(15, 0)
1274+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK GENMASK(31, 16)
1275+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK GENMASK(15, 0)
1276+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK GENMASK(31, 16)
1277+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK GENMASK(15, 0)
1278+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK GENMASK(31, 16)
1279+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK GENMASK(15, 0)
1280+
1281+/* mt7915 host DMA*/
1282+#define MT_DBG_INT_DMA1_R0_DONE BIT(0)
1283+#define MT_DBG_INT_DMA1_R1_DONE BIT(1)
1284+#define MT_DBG_INT_DMA1_R2_DONE BIT(2)
1285+
1286+#define MT_DBG_INT_DMA1_T16_DONE BIT(26)
1287+#define MT_DBG_INT_DMA1_T17_DONE BIT(27)
1288+#define MT_DBG_INT_DMA1_T18_DONE BIT(30)
1289+#define MT_DBG_INT_DMA1_T19_DONE BIT(31)
1290+#define MT_DBG_INT_DMA1_T20_DONE BIT(15)
1291+
1292+#define MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE BIT(16)
1293+#define MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE BIT(17)
1294+
1295+/* mt7986 host DMA */
1296+#define MT_DBG_INT_DMA0_R0_DONE BIT(0)
1297+#define MT_DBG_INT_DMA0_R1_DONE BIT(1)
1298+#define MT_DBG_INT_DMA0_R2_DONE BIT(2)
1299+#define MT_DBG_INT_DMA0_R3_DONE BIT(3)
1300+#define MT_DBG_INT_DMA0_R4_DONE BIT(22)
1301+#define MT_DBG_INT_DMA0_R5_DONE BIT(23)
1302+
1303+#define MT_DBG_INT_DMA0_T16_DONE BIT(26)
1304+#define MT_DBG_INT_DMA0_T17_DONE BIT(27)
1305+#define MT_DBG_INT_DMA0_T18_DONE BIT(30)
1306+#define MT_DBG_INT_DMA0_T19_DONE BIT(31)
1307+#define MT_DBG_INT_DMA0_T20_DONE BIT(25)
1308+
1309+/* MCU DMA */
1310+#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
1311+#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
1312+#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
1313+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
1314+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1315+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1316+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1317+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1318+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1319+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1320+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1321+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1322+
1323+#define WF_WFDMA_MCU_DMA1_BASE 0x55000000
1324+#define WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x200) // 0200
1325+#define WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0X204) // 0204
1326+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x208) // 0208
1327+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1328+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1329+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1330+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1331+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1332+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1333+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1334+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1335+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x300) // 0300
1336+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x310) // 0310
1337+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x320) // 0320
1338+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x500) // 0500
1339+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x510) // 0510
1340+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x520) // 0520
1341+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x530) // 0530
1342+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x540) // 0540
1343+
1344+#define WF_WFDMA_MCU_DMA1_PCIE1_BASE 0x59000000
1345+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x200) // 0200
1346+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0X204) // 0204
1347+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x208) // 0208
1348+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1349+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1350+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1351+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1352+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1353+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1354+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1355+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1356+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x320) // 0320
1357+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x530) // 0530
1358+
1359+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
1360+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
1361+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
1362+/* mt7986 add */
1363+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330
1364+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340
1365+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350
1366+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360
1367+
1368+
1369+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
1370+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
1371+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
1372+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
1373+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
1374+
1375+/* mt7986 add */
1376+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550
1377+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560
1378+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570
1379+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580
1380+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590
1381+
1382+/* MEM DMA */
1383+#define WF_WFDMA_MEM_DMA_BASE 0x58000000
1384+#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
1385+#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
1386+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
1387+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
1388+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
1389+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
1390+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
1391+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
1392+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
1393+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
1394+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
1395+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
1396+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
1397+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
1398+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
1399+
1400+enum resource_attr {
1401+ HIF_TX_DATA,
1402+ HIF_TX_CMD,
1403+ HIF_TX_CMD_WM, /* direct path to WMCPU, only exist for WFDMA arch with 2 CPU */
1404+ HIF_TX_FWDL,
1405+ HIF_RX_DATA,
1406+ HIF_RX_EVENT,
1407+ RING_ATTR_NUM
1408+};
1409+
1410+struct hif_pci_tx_ring_desc {
1411+ u32 hw_int_mask;
1412+ u16 ring_size;
1413+ enum resource_attr ring_attr;
1414+ u8 band_idx;
1415+ char *const ring_info;
1416+};
1417+
1418+struct hif_pci_rx_ring_desc {
1419+ u32 hw_desc_base;
1420+ u32 hw_int_mask;
1421+ u16 ring_size;
1422+ enum resource_attr ring_attr;
1423+ u16 max_rx_process_cnt;
1424+ u16 max_sw_read_idx_inc;
1425+ char *const ring_info;
1426+};
1427+
1428+const struct hif_pci_tx_ring_desc mt7915_tx_ring_layout[] = {
1429+ {
1430+ .hw_int_mask = MT_DBG_INT_DMA1_T16_DONE,
1431+ .ring_size = 128,
1432+ .ring_attr = HIF_TX_FWDL,
1433+ .ring_info = "FWDL"
1434+ },
1435+ {
1436+ .hw_int_mask = MT_DBG_INT_DMA1_T17_DONE,
1437+ .ring_size = 256,
1438+ .ring_attr = HIF_TX_CMD_WM,
1439+ .ring_info = "cmd to WM"
1440+ },
1441+ {
1442+ .hw_int_mask = MT_DBG_INT_DMA1_T18_DONE,
1443+ .ring_size = 2048,
1444+ .ring_attr = HIF_TX_DATA,
1445+ .ring_info = "band0 TXD"
1446+ },
1447+ {
1448+ .hw_int_mask = MT_DBG_INT_DMA1_T19_DONE,
1449+ .ring_size = 2048,
1450+ .ring_attr = HIF_TX_DATA,
1451+ .ring_info = "band1 TXD"
1452+ },
1453+ {
1454+ .hw_int_mask = MT_DBG_INT_DMA1_T20_DONE,
1455+ .ring_size = 256,
1456+ .ring_attr = HIF_TX_CMD,
1457+ .ring_info = "cmd to WA"
1458+ }
1459+};
1460+
1461+const struct hif_pci_rx_ring_desc mt7915_rx_ring_layout[] = {
1462+ {
1463+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE,
1464+ .ring_size = 1536,
1465+ .ring_attr = HIF_RX_DATA,
1466+ .ring_info = "band0 RX data"
1467+ },
1468+ {
1469+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE,
1470+ .ring_size = 1536,
1471+ .ring_attr = HIF_RX_DATA,
1472+ .ring_info = "band1 RX data"
1473+ },
1474+ {
1475+ .hw_int_mask = MT_DBG_INT_DMA1_R0_DONE,
1476+ .ring_size = 512,
1477+ .ring_attr = HIF_RX_EVENT,
1478+ .ring_info = "event from WM"
1479+ },
1480+ {
1481+ .hw_int_mask = MT_DBG_INT_DMA1_R1_DONE,
1482+ .ring_size = 1024,
1483+ .ring_attr = HIF_RX_EVENT,
1484+ .ring_info = "event from WA band0"
1485+ },
1486+ {
1487+ .hw_int_mask = MT_DBG_INT_DMA1_R2_DONE,
1488+ .ring_size = 512,
1489+ .ring_attr = HIF_RX_EVENT,
1490+ .ring_info = "event from WA band1"
1491+ }
1492+};
1493+
1494+const struct hif_pci_tx_ring_desc mt7986_tx_ring_layout[] = {
1495+ {
1496+ .hw_int_mask = MT_DBG_INT_DMA0_T16_DONE,
1497+ .ring_size = 128,
1498+ .ring_attr = HIF_TX_FWDL,
1499+ .ring_info = "FWDL"
1500+ },
1501+ {
1502+ .hw_int_mask = MT_DBG_INT_DMA0_T17_DONE,
1503+ .ring_size = 256,
1504+ .ring_attr = HIF_TX_CMD_WM,
1505+ .ring_info = "cmd to WM"
1506+ },
1507+ {
1508+ .hw_int_mask = MT_DBG_INT_DMA0_T18_DONE,
1509+ .ring_size = 2048,
1510+ .ring_attr = HIF_TX_DATA,
1511+ .ring_info = "band0 TXD"
1512+ },
1513+ {
1514+ .hw_int_mask = MT_DBG_INT_DMA0_T19_DONE,
1515+ .ring_size = 2048,
1516+ .ring_attr = HIF_TX_DATA,
1517+ .ring_info = "band1 TXD"
1518+ },
1519+ {
1520+ .hw_int_mask = MT_DBG_INT_DMA0_T20_DONE,
1521+ .ring_size = 256,
1522+ .ring_attr = HIF_TX_CMD,
1523+ .ring_info = "cmd to WA"
1524+ }
1525+};
1526+
1527+const struct hif_pci_rx_ring_desc mt7986_rx_ring_layout[] = {
1528+ {
1529+ .hw_int_mask = MT_DBG_INT_DMA0_R4_DONE,
1530+ .ring_size = 1536,
1531+ .ring_attr = HIF_RX_DATA,
1532+ .ring_info = "band0 RX data"
1533+ },
1534+ {
1535+ .hw_int_mask = MT_DBG_INT_DMA0_R5_DONE,
1536+ .ring_size = 1536,
1537+ .ring_attr = HIF_RX_DATA,
1538+ .ring_info = "band1 RX data"
1539+ },
1540+ {
1541+ .hw_int_mask = MT_DBG_INT_DMA0_R0_DONE,
1542+ .ring_size = 512,
1543+ .ring_attr = HIF_RX_EVENT,
1544+ .ring_info = "event from WM"
1545+ },
1546+ {
1547+ .hw_int_mask = MT_DBG_INT_DMA0_R1_DONE,
1548+ .ring_size = 512,
1549+ .ring_attr = HIF_RX_EVENT,
1550+ .ring_info = "event from WA"
1551+ },
1552+ {
1553+ .hw_int_mask = MT_DBG_INT_DMA0_R2_DONE,
1554+ .ring_size = 1024,
1555+ .ring_attr = HIF_RX_EVENT,
1556+ .ring_info = "STS WA band0"
1557+ },
1558+ {
1559+ .hw_int_mask = MT_DBG_INT_DMA0_R3_DONE,
1560+ .ring_size = 512,
1561+ .ring_attr = HIF_RX_EVENT,
1562+ .ring_info = "STS WA band1"
1563+ },
1564+};
1565+
1566+/* mibinfo related CRs. */
1567+#define BN0_WF_MIB_TOP_BASE 0x820ed000
1568+#define BN1_WF_MIB_TOP_BASE 0x820fd000
1569+
1570+#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400
1571+#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x428) // D428
1572+#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x4F0) // D4F0
1573+
1574+#define BN0_WF_MIB_TOP_BSDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x688) // D688
1575+#define BN0_WF_MIB_TOP_BSDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x690) // D690
1576+
1577+#define BN0_WF_MIB_TOP_BSDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x518) // D518
1578+#define BN0_WF_MIB_TOP_BSDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x520) // D520
1579+#define BN0_WF_MIB_TOP_BSDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x528) // D528
1580+#define BN0_WF_MIB_TOP_BSDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x530) // D530
1581+#define BN0_WF_MIB_TOP_BSDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x538) // D538
1582+
1583+#define BN0_WF_MIB_TOP_BROCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5B8) // D5B8
1584+#define BN0_WF_MIB_TOP_BRBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0
1585+#define BN0_WF_MIB_TOP_BRDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x630) // D630
1586+
1587+#define BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK 0x0000FFFF // BEACONTXCOUNT[15..0]
1588+
1589+#define BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK 0x0000FFFF // RX_FIFO_FULL_COUNT[15..0]
1590+
1591+#define BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
1592+
1593+#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
1594+
1595+#define BN1_WF_MIB_TOP_BTOCR_ADDR (BN1_WF_MIB_TOP_BASE + 0x400) // D400
1596+
1597+#define BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK 0x0000FFFF // VEC_MISS_COUNT[15..0]
1598+#define BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK 0x0000FFFF // DELIMITER_FAIL_COUNT[15..0]
1599+#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
1600+
1601+#define BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK 0x0000FFFF // RX_LEN_MISMATCH[15..0]
1602+
1603+#define BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK 0x00FFFFFF // P_CCA_TIME[23..0]
1604+#define BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK 0x00FFFFFF // S_CCA_TIME[23..0]
1605+#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
1606+#define BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK 0x00FFFFFF // CCK_MDRDY_TIME[23..0]
1607+#define BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[23..0]
1608+#define BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_GREEN_MDRDY_TIME[23..0]
1609+
1610+#define BN0_WF_MIB_TOP_M0SDR22_ADDR (BN0_WF_MIB_TOP_BASE + 0x60) // D060
1611+#define BN0_WF_MIB_TOP_M0SDR23_ADDR (BN0_WF_MIB_TOP_BASE + 0x64) // D064
1612+
1613+#define BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK 0x0000FFFF // MUBF_TX_COUNT[15..0]
1614+
1615+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK 0xFFFF0000 // TX_40MHZ_CNT[31..16]
1616+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT 16
1617+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK 0x0000FFFF // TX_20MHZ_CNT[15..0]
1618+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_SHFT 0
1619+
1620+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK 0xFFFF0000 // TX_160MHZ_CNT[31..16]
1621+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT 16
1622+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK 0x0000FFFF // TX_80MHZ_CNT[15..0]
1623+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_SHFT 0
1624+
1625+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG2_CNT[31..16]
1626+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT 16
1627+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG1_CNT[15..0]
1628+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_SHFT 0
1629+
1630+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG4_CNT[31..16]
1631+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT 16
1632+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG3_CNT[15..0]
1633+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_SHFT 0
1634+
1635+#define BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK 0x0000FFFF // MU_FAIL_PPDU_CNT[15..0]
1636+
1637+#define BN0_WF_MIB_TOP_M0B0SDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x100) // D100
1638+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK 0xFFFF0000 // RTSRETRYCOUNT[31..16]
1639+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT 16
1640+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK 0x0000FFFF // RTSTXCOUNT[15..0]
1641+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_SHFT 0
1642+#define BN0_WF_MIB_TOP_M0B0SDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x104) // D104
1643+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK 0xFFFF0000 // ACKFAILCOUNT[31..16]
1644+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT 16
1645+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK 0x0000FFFF // BAMISSCOUNT[15..0]
1646+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_SHFT 0
1647+#define BN0_WF_MIB_TOP_M0B0SDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x108) // D108
1648+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK 0xFFFF0000 // FRAMERETRY2COUNT[31..16]
1649+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT 16
1650+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK 0x0000FFFF // FRAMERETRYCOUNT[15..0]
1651+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_SHFT 0
1652+#define BN0_WF_MIB_TOP_M0B0SDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x10C) // D10C
1653+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK 0x0000FFFF // FRAMERETRY3COUNT[15..0]
1654+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_SHFT 0
1655+#define BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG0_CNT[15..0]
1656+
1657+
1658+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK 0xFFFF0000 // TX_OK_COUNT2np1[31..16]
1659+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT 16
1660+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK 0x0000FFFF // TX_OK_COUNT2n[15..0]
1661+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT 0
1662+
1663+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK 0xFFFF0000 // TX_DATA_COUNT2np1[31..16]
1664+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT 16
1665+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK 0x0000FFFF // TX_DATA_COUNT2n[15..0]
1666+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT 0
1667+
1668+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK 0xFFFF0000 // RX_OK_COUNT2np1[31..16]
1669+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT 16
1670+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK 0x0000FFFF // RX_OK_COUNT2n[15..0]
1671+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT 0
1672+
1673+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK 0xFFFF0000 // RX_DATA_COUNT2np1[31..16]
1674+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT 16
1675+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK 0x0000FFFF // RX_DATA_COUNT2n[15..0]
1676+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT 0
1677+
1678+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK 0xFFFF0000 // RTSTXCOUNT2np1[31..16]
1679+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT 16
1680+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK 0x0000FFFF // RTSTXCOUNT2n[15..0]
1681+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT 0
1682+
1683+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK 0xFFFF0000 // RTSRETRYCOUNT2np1[31..16]
1684+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT 16
1685+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK 0x0000FFFF // RTSRETRYCOUNT2n[15..0]
1686+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT 0
1687+
1688+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK 0xFFFF0000 // BAMISSCOUNT2np1[31..16]
1689+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT 16
1690+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK 0x0000FFFF // BAMISSCOUNT2n[15..0]
1691+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT 0
1692+
1693+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK 0xFFFF0000 // ACKFAILCOUNT2np1[31..16]
1694+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT 16
1695+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK 0x0000FFFF // ACKFAILCOUNT2n[15..0]
1696+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT 0
1697+
1698+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK 0xFFFF0000 // FRAMERETRYCOUNT2np1[31..16]
1699+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT 16
1700+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK 0x0000FFFF // FRAMERETRYCOUNT2n[15..0]
1701+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT 0
1702+
1703+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY2COUNT2np1[31..16]
1704+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT 16
1705+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK 0x0000FFFF // FRAMERETRY2COUNT2n[15..0]
1706+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT 0
1707+
1708+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY3COUNT2np1[31..16]
1709+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT 16
1710+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK 0x0000FFFF // FRAMERETRY3COUNT2n[15..0]
1711+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT 0
1712+/* TXD */
1713+
1714+#define MT_TXD1_ETYP BIT(15)
1715+#define MT_TXD1_VLAN BIT(14)
1716+#define MT_TXD1_RMVL BIT(13)
1717+#define MT_TXD1_AMS BIT(13)
1718+#define MT_TXD1_EOSP BIT(12)
1719+#define MT_TXD1_MRD BIT(11)
1720+
1721+#define MT_TXD7_CTXD BIT(26)
1722+#define MT_TXD7_CTXD_CNT GENMASK(25, 23)
1723+#define MT_TXD7_TAT GENMASK(9, 0)
1724+
1725+#endif
1726+#endif
1727diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c
1728new file mode 100644
1729index 00000000..246eb129
1730--- /dev/null
1731+++ b/mt7915/mtk_debugfs.c
1732@@ -0,0 +1,2893 @@
1733+#include<linux/inet.h>
1734+#include "mt7915.h"
1735+#include "mt7915_debug.h"
1736+#include "mac.h"
1737+#include "mcu.h"
1738+
1739+#ifdef MTK_DEBUG
1740+#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
1741+#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
1742+#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \
1743+ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
1744+ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
1745+
1746+#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
1747+#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
1748+#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1749+ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
1750+ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
1751+
1752+#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
1753+#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
1754+#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1755+ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
1756+ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
1757+
1758+enum mt7915_wtbl_type {
1759+ WTBL_TYPE_LMAC, /* WTBL in LMAC */
1760+ WTBL_TYPE_UMAC, /* WTBL in UMAC */
1761+ WTBL_TYPE_KEY, /* Key Table */
1762+ MAX_NUM_WTBL_TYPE
1763+};
1764+
1765+static int mt7915_wtbl_read_raw(struct mt7915_dev *dev, u16 idx,
1766+ enum mt7915_wtbl_type type, u16 start_dw,
1767+ u16 len, void *buf)
1768+{
1769+ u32 *dest_cpy = (u32 *)buf;
1770+ u32 size_dw = len;
1771+ u32 src = 0;
1772+
1773+ if (!buf)
1774+ return 0xFF;
1775+
1776+ if (type == WTBL_TYPE_LMAC) {
1777+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1778+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1779+ src = LWTBL_IDX2BASE(idx, start_dw);
1780+ } else if (type == WTBL_TYPE_UMAC) {
1781+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1782+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1783+ src = UWTBL_IDX2BASE(idx, start_dw);
1784+ } else if (type == WTBL_TYPE_KEY) {
1785+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1786+ MT_UWTBL_TOP_WDUCR_TARGET |
1787+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1788+ src = KEYTBL_IDX2BASE(idx, start_dw);
1789+ }
1790+
1791+ while (size_dw--) {
1792+ *dest_cpy++ = mt76_rr(dev, src);
1793+ src += 4;
1794+ };
1795+
1796+ return 0;
1797+}
1798+
1799+static int mt7915_wtbl_write_raw(struct mt7915_dev *dev, u16 idx,
1800+ enum mt7915_wtbl_type type, u16 start_dw,
1801+ u32 val)
1802+{
1803+ u32 addr = 0;
1804+
1805+ if (type == WTBL_TYPE_LMAC) {
1806+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
1807+ FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
1808+ addr = LWTBL_IDX2BASE(idx, start_dw);
1809+ } else if (type == WTBL_TYPE_UMAC) {
1810+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1811+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1812+ addr = UWTBL_IDX2BASE(idx, start_dw);
1813+ } else if (type == WTBL_TYPE_KEY) {
1814+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
1815+ MT_UWTBL_TOP_WDUCR_TARGET |
1816+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
1817+ addr = KEYTBL_IDX2BASE(idx, start_dw);
1818+ }
1819+
1820+ mt76_wr(dev, addr, val);
1821+
1822+ return 0;
1823+}
1824+
1825+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len)
1826+{
1827+ struct bin_debug_hdr *hdr;
1828+ char *buf;
1829+
1830+ if (len > 1500 - sizeof(*hdr))
1831+ len = 1500 - sizeof(*hdr);
1832+
1833+ buf = kzalloc(sizeof(*hdr) + len, GFP_KERNEL);
1834+ if (!buf)
1835+ return;
1836+
1837+ hdr = (struct bin_debug_hdr *)buf;
1838+ hdr->magic_num = cpu_to_le32(PKT_BIN_DEBUG_MAGIC);
1839+ hdr->serial_id = cpu_to_le16(dev->dbg.fwlog_seq++);
1840+ hdr->msg_type = cpu_to_le16(type);
1841+ hdr->len = cpu_to_le16(len);
1842+ hdr->des_len = cpu_to_le16(des_len);
1843+
1844+ memcpy(buf + sizeof(*hdr), data, len);
1845+
1846+ mt7915_debugfs_rx_log(dev, buf, sizeof(*hdr) + len);
1847+}
1848+
1849+static int
1850+mt7915_fw_debug_module_set(void *data, u64 module)
1851+{
1852+ struct mt7915_dev *dev = data;
1853+
1854+ dev->dbg.fw_dbg_module = module;
1855+ return 0;
1856+}
1857+
1858+static int
1859+mt7915_fw_debug_module_get(void *data, u64 *module)
1860+{
1861+ struct mt7915_dev *dev = data;
1862+
1863+ *module = dev->dbg.fw_dbg_module;
1864+ return 0;
1865+}
1866+
1867+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, mt7915_fw_debug_module_get,
1868+ mt7915_fw_debug_module_set, "%lld\n");
1869+
1870+static int
1871+mt7915_fw_debug_level_set(void *data, u64 level)
1872+{
1873+ struct mt7915_dev *dev = data;
1874+
1875+ dev->dbg.fw_dbg_lv = level;
1876+ mt7915_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv);
1877+ return 0;
1878+}
1879+
1880+static int
1881+mt7915_fw_debug_level_get(void *data, u64 *level)
1882+{
1883+ struct mt7915_dev *dev = data;
1884+
1885+ *level = dev->dbg.fw_dbg_lv;
1886+ return 0;
1887+}
1888+
1889+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, mt7915_fw_debug_level_get,
1890+ mt7915_fw_debug_level_set, "%lld\n");
1891+
1892+#define MAX_TX_MODE 12
1893+static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT",
1894+ "N/A", "N/A", "N/A", "HE_SU", "HE_EXT_SU",
1895+ "HE_TRIG", "HE_MU", "N/A"};
1896+static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong",
1897+ "N/A", "2Mshort", "5.5Mshort", "11Mshort",
1898+ "N/A"};
1899+static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M",
1900+ "48M", "54M", "N/A"};
1901+static char *fcap_str[] = {"20MHz", "20/40MHz", "20/40/80MHz",
1902+ "20/40/80/160/80+80MHz"};
1903+
1904+static char *hw_rate_ofdm_str(u16 ofdm_idx)
1905+{
1906+ switch (ofdm_idx) {
1907+ case 11: /* 6M */
1908+ return HW_TX_RATE_OFDM_STR[0];
1909+
1910+ case 15: /* 9M */
1911+ return HW_TX_RATE_OFDM_STR[1];
1912+
1913+ case 10: /* 12M */
1914+ return HW_TX_RATE_OFDM_STR[2];
1915+
1916+ case 14: /* 18M */
1917+ return HW_TX_RATE_OFDM_STR[3];
1918+
1919+ case 9: /* 24M */
1920+ return HW_TX_RATE_OFDM_STR[4];
1921+
1922+ case 13: /* 36M */
1923+ return HW_TX_RATE_OFDM_STR[5];
1924+
1925+ case 8: /* 48M */
1926+ return HW_TX_RATE_OFDM_STR[6];
1927+
1928+ case 12: /* 54M */
1929+ return HW_TX_RATE_OFDM_STR[7];
1930+
1931+ default:
1932+ return HW_TX_RATE_OFDM_STR[8];
1933+ }
1934+}
1935+
1936+static char *hw_rate_str(u8 mode, u16 rate_idx)
1937+{
1938+ if (mode == 0)
1939+ return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8];
1940+ else if (mode == 1)
1941+ return hw_rate_ofdm_str(rate_idx);
1942+ else
1943+ return "MCS";
1944+}
1945+
1946+static void parse_rate(struct seq_file *s, u16 rate_idx, u16 txrate)
1947+{
1948+ u16 txmode, mcs, nss, stbc;
1949+
1950+ txmode = FIELD_GET(GENMASK(9, 6), txrate);
1951+ mcs = FIELD_GET(GENMASK(5, 0), txrate);
1952+ nss = FIELD_GET(GENMASK(12, 10), txrate);
1953+ stbc = FIELD_GET(BIT(13), txrate);
1954+
1955+ seq_printf(s, "\tRate%d(0x%x):TxMode=%d(%s), TxRate=%d(%s), Nsts=%d, STBC=%d\n",
1956+ rate_idx + 1, txrate,
1957+ txmode, (txmode < MAX_TX_MODE ? HW_TX_MODE_STR[txmode] : HW_TX_MODE_STR[MAX_TX_MODE]),
1958+ mcs, hw_rate_str(txmode, mcs), nss, stbc);
1959+}
1960+
1961+#define LWTBL_LEN_IN_DW 32
1962+#define UWTBL_LEN_IN_DW 8
1963+#define ONE_KEY_ENTRY_LEN_IN_DW 8
1964+static int mt7915_wtbl_read(struct seq_file *s, void *data)
1965+{
1966+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
1967+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
1968+ int x;
1969+ u32 *addr = 0;
1970+ u32 dw_value = 0;
1971+
1972+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_LMAC, 0,
1973+ LWTBL_LEN_IN_DW, lwtbl);
1974+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
1975+ seq_printf(s, "LMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
1976+ MT_DBG_WTBLON_TOP_WDUCR,
1977+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
1978+ LWTBL_IDX2BASE(dev->wlan_idx, 0));
1979+ for (x = 0; x < LWTBL_LEN_IN_DW; x++) {
1980+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
1981+ x,
1982+ lwtbl[x * 4 + 3],
1983+ lwtbl[x * 4 + 2],
1984+ lwtbl[x * 4 + 1],
1985+ lwtbl[x * 4]);
1986+ }
1987+
1988+ seq_printf(s, "\n\tAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
1989+ lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
1990+
1991+ // DW0, DW1
1992+ seq_printf(s, "LWTBL DW 0/1\n\t");
1993+ addr = (u32 *)&(lwtbl[0]);
1994+ dw_value = *addr;
1995+ seq_printf(s, "MUAR_IDX:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
1996+ seq_printf(s, "RCA1:%ld/ ", FIELD_GET(BIT(22), dw_value));
1997+ seq_printf(s, "KID:%lu/ ", FIELD_GET(GENMASK(24, 23), dw_value));
1998+ seq_printf(s, "RCID:%ld/ ", FIELD_GET(BIT(25), dw_value));
1999+ seq_printf(s, "FROM_DS:%ld\n\t", FIELD_GET(BIT(26), dw_value));
2000+ seq_printf(s, "TO_DS:%ld/ ", FIELD_GET(BIT(27), dw_value));
2001+ seq_printf(s, "RV:%ld/ ", FIELD_GET(BIT(28), dw_value));
2002+ seq_printf(s, "RCA2:%ld/ ", FIELD_GET(BIT(29), dw_value));
2003+ seq_printf(s, "WPI_FLAG:%ld\n", FIELD_GET(BIT(30), dw_value));
2004+
2005+ // DW2
2006+ seq_printf(s, "LWTBL DW 2\n\t");
2007+ addr = (u32 *)&(lwtbl[2*4]);
2008+ dw_value = *addr;
2009+ seq_printf(s, "AID12:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
2010+ seq_printf(s, "SU:%ld/ ", FIELD_GET(BIT(12), dw_value));
2011+ seq_printf(s, "SPP_EN:%ld/ ", FIELD_GET(BIT(13), dw_value));
2012+ seq_printf(s, "WPI_EVEN:%ld\n\t",FIELD_GET(BIT(14), dw_value));
2013+ seq_printf(s, "CIPHER:%lu/ ", FIELD_GET(GENMASK(20, 16), dw_value));
2014+ seq_printf(s, "CIPHER_IGTK:%lu/ ",FIELD_GET(GENMASK(22, 21), dw_value));
2015+ seq_printf(s, "AAD_OM:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2016+ seq_printf(s, "SW:%ld/ ", FIELD_GET(BIT(24), dw_value));
2017+ seq_printf(s, "UL:%ld/ ", FIELD_GET(BIT(25), dw_value));
2018+ seq_printf(s, "TX_POWER_SAVE:%ld\n\t", FIELD_GET(BIT(26), dw_value));
2019+ seq_printf(s, "QOS:%ld/ ", FIELD_GET(BIT(27), dw_value));
2020+ seq_printf(s, "HT:%ld/ ", FIELD_GET(BIT(28), dw_value));
2021+ seq_printf(s, "VHT:%ld/ ", FIELD_GET(BIT(29), dw_value));
2022+ seq_printf(s, "HE:%ld/ ", FIELD_GET(BIT(30), dw_value));
2023+ seq_printf(s, "MESH:%ld\n", FIELD_GET(BIT(31), dw_value));
2024+
2025+ // DW3
2026+ seq_printf(s, "LWTBL DW 3\n\t");
2027+ addr = (u32 *)&(lwtbl[3*4]);
2028+ dw_value = *addr;
2029+ seq_printf(s, "WMM_Q:%lu/ ", FIELD_GET(GENMASK(1, 0), dw_value));
2030+ seq_printf(s, "RXD_DUP_MODE:%lu\n\t", FIELD_GET(GENMASK(3, 2), dw_value));
2031+ seq_printf(s, "VLAN2ETH:%ld/ ", FIELD_GET(BIT(4), dw_value));
2032+ seq_printf(s, "BEAM_CHG:%ld/ ", FIELD_GET(BIT(5), dw_value));
2033+ seq_printf(s, "DIS_BA256:%ld\n\t", FIELD_GET(BIT(6), dw_value));
2034+ seq_printf(s, "PFMU_IDX:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2035+ seq_printf(s, "ULPF_IDX:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
2036+ seq_printf(s, "RIBF:%ld/ ", FIELD_GET(BIT(24), dw_value));
2037+ seq_printf(s, "ULPF:%ld\n\t", FIELD_GET(BIT(25), dw_value));
2038+ seq_printf(s, "IGN_FBK:%ld/ ", FIELD_GET(BIT(26), dw_value));
2039+ seq_printf(s, "TBF:%ld/ ", FIELD_GET(BIT(29), dw_value));
2040+ seq_printf(s, "TBF_VHT:%ld/ ", FIELD_GET(BIT(30), dw_value));
2041+ seq_printf(s, "TBF_HE:%ld\n", FIELD_GET(BIT(31), dw_value));
2042+
2043+ // DW4
2044+ seq_printf(s, "LWTBL DW 4\n\t");
2045+ addr = (u32 *)&(lwtbl[4*4]);
2046+ dw_value = *addr;
2047+ seq_printf(s, "ANT_ID_STS0:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2048+ seq_printf(s, "STS1:%lu/ ", FIELD_GET(GENMASK(5, 3), dw_value));
2049+ seq_printf(s, "STS2:%lu/ ", FIELD_GET(GENMASK(8, 6), dw_value));
2050+ seq_printf(s, "STS3:%lu\n\t", FIELD_GET(GENMASK(11, 9), dw_value));
2051+ seq_printf(s, "ANT_ID_STS4:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
2052+ seq_printf(s, "STS5:%lu/ ", FIELD_GET(GENMASK(17, 15), dw_value));
2053+ seq_printf(s, "STS6:%ld/ ", FIELD_GET(GENMASK(20, 18), dw_value));
2054+ seq_printf(s, "STS7:%lu\n\t", FIELD_GET(GENMASK(23, 21), dw_value));
2055+ seq_printf(s, "CASCAD:%ld/ ", FIELD_GET(BIT(24), dw_value));
2056+ seq_printf(s, "LDPC_HT:%ld/ ", FIELD_GET(BIT(25), dw_value));
2057+ seq_printf(s, "LDPC_VHT:%ld/ ", FIELD_GET(BIT(26), dw_value));
2058+ seq_printf(s, "LDPC_HE:%ld\n\t", FIELD_GET(BIT(27), dw_value));
2059+ seq_printf(s, "DIS_RHTR:%ld/ ", FIELD_GET(BIT(28), dw_value));
2060+ seq_printf(s, "ALL_ACK:%ld/ ", FIELD_GET(BIT(29), dw_value));
2061+ seq_printf(s, "DROP:%ld/ ", FIELD_GET(BIT(30), dw_value));
2062+ seq_printf(s, "ACK_EN:%ld\n", FIELD_GET(BIT(31), dw_value));
2063+
2064+ // DW5
2065+ seq_printf(s, "LWTBL DW 5\n\t");
2066+ addr = (u32 *)&(lwtbl[5*4]);
2067+ dw_value = *addr;
2068+ seq_printf(s, "AF:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2069+ seq_printf(s, "AF_HE:%lu/ ", FIELD_GET(GENMASK(4, 3), dw_value));
2070+ seq_printf(s, "RTS:%ld/ ", FIELD_GET(BIT(5), dw_value));
2071+ seq_printf(s, "SMPS:%ld/ ", FIELD_GET(BIT(6), dw_value));
2072+ seq_printf(s, "DYN_BW:%ld\n\t", FIELD_GET(BIT(7), dw_value));
2073+ seq_printf(s, "MMSS:%lu/ ", FIELD_GET(GENMASK(10, 8), dw_value));
2074+ seq_printf(s, "USR:%ld/ ", FIELD_GET(BIT(11), dw_value));
2075+ seq_printf(s, "SR_RATE:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
2076+ seq_printf(s, "SR_ABORT:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2077+ seq_printf(s, "TX_POWER_OFFSET:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
2078+ seq_printf(s, "WTBL_MPDU_SIZE:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
2079+ seq_printf(s, "PE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
2080+ seq_printf(s, "DOPPL:%ld/ ", FIELD_GET(BIT(26), dw_value));
2081+ seq_printf(s, "TXOP_PS_CAP:%ld/ ", FIELD_GET(BIT(27), dw_value));
2082+ seq_printf(s, "DONOT_UPDATE_I_PSM:%ld\n\t", FIELD_GET(BIT(28), dw_value));
2083+ seq_printf(s, "I_PSM:%ld/ ", FIELD_GET(BIT(29), dw_value));
2084+ seq_printf(s, "PSM:%ld/ ", FIELD_GET(BIT(30), dw_value));
2085+ seq_printf(s, "SKIP_TX:%ld\n", FIELD_GET(BIT(31), dw_value));
2086+
2087+ // DW6
2088+ seq_printf(s, "LWTBL DW 6\n\t");
2089+ seq_printf(s, "TID 0/1/2/3/4/5/6/7 BA_WIN_SIZE:");
2090+ addr = (u32 *)&(lwtbl[6*4]);
2091+ dw_value = *addr;
2092+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(3, 0), dw_value));
2093+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(7, 4), dw_value));
2094+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(11, 8), dw_value));
2095+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(15, 12), dw_value));
2096+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(19, 16), dw_value));
2097+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(23, 20), dw_value));
2098+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(27, 24), dw_value));
2099+ seq_printf(s, "%lu\n", FIELD_GET(GENMASK(31, 28), dw_value));
2100+
2101+ // DW7
2102+ seq_printf(s, "LWTBL DW 7\n\t");
2103+ addr = (u32 *)&(lwtbl[7*4]);
2104+ dw_value = *addr;
2105+ seq_printf(s, "CBRN:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
2106+ seq_printf(s, "DBNSS_EN:%ld/ ", FIELD_GET(BIT(3), dw_value));
2107+ seq_printf(s, "BAF_EN:%ld/ ", FIELD_GET(BIT(4), dw_value));
2108+ seq_printf(s, "RDGBA:%ld\n\t", FIELD_GET(BIT(5), dw_value));
2109+ seq_printf(s, "RDG:%ld/ ", FIELD_GET(BIT(6), dw_value));
2110+ seq_printf(s, "SPE_IDX:%lu/ ", FIELD_GET(GENMASK(11, 7), dw_value));
2111+ seq_printf(s, "G2:%ld/ ", FIELD_GET(BIT(12), dw_value));
2112+ seq_printf(s, "G4:%ld/ ", FIELD_GET(BIT(13), dw_value));
2113+ seq_printf(s, "G8:%ld/ ", FIELD_GET(BIT(14), dw_value));
2114+ seq_printf(s, "G16:%ld\n\t", FIELD_GET(BIT(15), dw_value));
2115+ seq_printf(s, "G2_LTF:%lu/ ", FIELD_GET(GENMASK(17, 16), dw_value));
2116+ seq_printf(s, "G4_LTF:%lu/ ", FIELD_GET(GENMASK(19, 18), dw_value));
2117+ seq_printf(s, "G8_LTF:%lu/ ", FIELD_GET(GENMASK(21, 20), dw_value));
2118+ seq_printf(s, "G16_LTF:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
2119+ seq_printf(s, "G2_HE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
2120+ seq_printf(s, "G4_HE:%lu/ ", FIELD_GET(GENMASK(27, 27), dw_value));
2121+ seq_printf(s, "G8_HE:%lu/ ", FIELD_GET(GENMASK(29, 28), dw_value));
2122+ seq_printf(s, "G16_HE:%lu\n", FIELD_GET(GENMASK(31, 30), dw_value));
2123+
2124+ // DW8
2125+ seq_printf(s, "LWTBL DW 8\n\t");
2126+ addr = (u32 *)&(lwtbl[8*4]);
2127+ dw_value = *addr;
2128+ seq_printf(s, "FAIL_CNT_AC0:%lu/ ", FIELD_GET(GENMASK(4, 0), dw_value));
2129+ seq_printf(s, "AC1:%lu/ ", FIELD_GET(GENMASK(9, 5), dw_value));
2130+ seq_printf(s, "AC2:%lu/ ", FIELD_GET(GENMASK(14, 10), dw_value));
2131+ seq_printf(s, "AC3:%lu\n\t", FIELD_GET(GENMASK(19, 15), dw_value));
2132+ seq_printf(s, "PARTIAL_AID:%lu/ ", FIELD_GET(GENMASK(28, 20), dw_value));
2133+ seq_printf(s, "CHK_PER:%lu\n", FIELD_GET(BIT(31), dw_value));
2134+
2135+ // DW9
2136+ seq_printf(s, "LWTBL DW 9\n\t");
2137+ addr = (u32 *)&(lwtbl[9*4]);
2138+ dw_value = *addr;
2139+ seq_printf(s, "RX_AVG_MPDU:%lu/ ", FIELD_GET(GENMASK(13, 0), dw_value));
2140+ seq_printf(s, "PRITX_SW_MODE:%ld/ ", FIELD_GET(BIT(16), dw_value));
2141+ seq_printf(s, "PRITX_PLR:%ld\n\t", FIELD_GET(BIT(17), dw_value));
2142+ seq_printf(s, "PRITX_DCM:%ld/ ", FIELD_GET(BIT(18), dw_value));
2143+ seq_printf(s, "PRITX_ER160:%ld/ ", FIELD_GET(BIT(19), dw_value));
2144+ seq_printf(s, "PRITX_ERSU:%lu\n\t", FIELD_GET(BIT(20), dw_value));
2145+ seq_printf(s, "MPDU_FAIL_CNT:%lu/ ", FIELD_GET(GENMASK(25, 23), dw_value));
2146+ seq_printf(s, "MPDU_OK_CNT:%lu/ ", FIELD_GET(GENMASK(28, 26), dw_value));
2147+ seq_printf(s, "RATE_IDX:%lu\n\t", FIELD_GET(GENMASK(31, 29), dw_value));
2148+ seq_printf(s, "FCAP:%s\n", fcap_str[FIELD_GET(GENMASK(22, 21), dw_value)]);
2149+
2150+ // DW10
2151+ seq_printf(s, "LWTBL DW 10\n");
2152+ addr = (u32 *)&(lwtbl[10*4]);
2153+ dw_value = *addr;
2154+ parse_rate(s, 0, FIELD_GET(GENMASK(13, 0), dw_value));
2155+ parse_rate(s, 1, FIELD_GET(GENMASK(29, 16), dw_value));
2156+ // DW11
2157+ seq_printf(s, "LWTBL DW 11\n");
2158+ addr = (u32 *)&(lwtbl[11*4]);
2159+ dw_value = *addr;
2160+ parse_rate(s, 2, FIELD_GET(GENMASK(13, 0), dw_value));
2161+ parse_rate(s, 3, FIELD_GET(GENMASK(29, 16), dw_value));
2162+ // DW12
2163+ seq_printf(s, "LWTBL DW 12\n");
2164+ addr = (u32 *)&(lwtbl[12*4]);
2165+ dw_value = *addr;
2166+ parse_rate(s, 4, FIELD_GET(GENMASK(13, 0), dw_value));
2167+ parse_rate(s, 5, FIELD_GET(GENMASK(29, 16), dw_value));
2168+ // DW13
2169+ seq_printf(s, "LWTBL DW 13\n");
2170+ addr = (u32 *)&(lwtbl[13*4]);
2171+ dw_value = *addr;
2172+ parse_rate(s, 6, FIELD_GET(GENMASK(13, 0), dw_value));
2173+ parse_rate(s, 7, FIELD_GET(GENMASK(29, 16), dw_value));
2174+
2175+ //DW28
2176+ seq_printf(s, "LWTBL DW 28\n\t");
2177+ addr = (u32 *)&(lwtbl[28*4]);
2178+ dw_value = *addr;
2179+ seq_printf(s, "OM_INFO:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
2180+ seq_printf(s, "OM_RXD_DUP_MODE:%u\n\t", !!(dw_value & BIT(12)) );
2181+
2182+ //DW29
2183+ seq_printf(s, "LWTBL DW 29\n");
2184+ addr = (u32 *)&(lwtbl[29*4]);
2185+ dw_value = *addr;
2186+ seq_printf(s, "USER_RSSI:%lu/ ", FIELD_GET(GENMASK(8, 0), dw_value));
2187+ seq_printf(s, "USER_SNR:%lu/ ", FIELD_GET(GENMASK(14, 9), dw_value));
2188+ seq_printf(s, "RAPID_REACTION_RATE:%lu/ ", FIELD_GET(GENMASK(26, 16), dw_value));
2189+ seq_printf(s, "HT_AMSDU(Read Only):%u/ ", !!(dw_value & BIT(30)) );
2190+ seq_printf(s, "AMSDU_CROSS_LG(Read Only):%u\n\t ", !!(dw_value & BIT(31)));
2191+
2192+ //DW30
2193+ seq_printf(s, "LWTBL DW 30\n\t");
2194+ addr = (u32 *)&(lwtbl[30*4]);
2195+ dw_value = *addr;
2196+ seq_printf(s, "RCPI 0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2197+ seq_printf(s, "RCPI 1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2198+ seq_printf(s, "RCPI 2:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
2199+ seq_printf(s, "RCPI 3:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
2200+
2201+ //DW31
2202+ seq_printf(s, "LWTBL DW 31\n\t");
2203+ addr = (u32 *)&(lwtbl[31*4]);
2204+ dw_value = *addr;
2205+ seq_printf(s, "RCPI 4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2206+ seq_printf(s, "RCPI 5:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2207+ seq_printf(s, "RCPI 6:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
2208+ seq_printf(s, "RCPI 7:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
2209+
2210+ return 0;
2211+}
2212+
2213+static int mt7915_uwtbl_read(struct seq_file *s, void *data)
2214+{
2215+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2216+ u8 uwtbl[UWTBL_LEN_IN_DW * 4] = {0};
2217+ u8 keytbl[ONE_KEY_ENTRY_LEN_IN_DW*4] = {0};
2218+ int x;
2219+ u32 *addr = 0;
2220+ u32 dw_value = 0;
2221+ u32 amsdu_len = 0;
2222+ u32 u2SN = 0;
2223+ u16 keyloc0, keyloc1;
2224+
2225+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC, 0,
2226+ UWTBL_LEN_IN_DW, uwtbl);
2227+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
2228+ seq_printf(s, "UMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2229+ MT_DBG_WTBLON_TOP_WDUCR,
2230+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2231+ UWTBL_IDX2BASE(dev->wlan_idx, 0));
2232+ for (x = 0; x < UWTBL_LEN_IN_DW; x++) {
2233+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2234+ x,
2235+ uwtbl[x * 4 + 3],
2236+ uwtbl[x * 4 + 2],
2237+ uwtbl[x * 4 + 1],
2238+ uwtbl[x * 4]);
2239+ }
2240+
2241+ /* UMAC WTBL DW 0 */
2242+ seq_printf(s, "\nUWTBL PN\n\t");
2243+ addr = (u32 *)&(uwtbl[0]);
2244+ dw_value = *addr;
2245+ seq_printf(s, "PN0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2246+ seq_printf(s, "PN1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
2247+ seq_printf(s, "PN2:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
2248+ seq_printf(s, "PN3:%lu/ ", FIELD_GET(GENMASK(31, 24), dw_value));
2249+
2250+ addr = (u32 *)&(uwtbl[1 * 4]);
2251+ dw_value = *addr;
2252+ seq_printf(s, "PN4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
2253+ seq_printf(s, "PN5:%lu\n", FIELD_GET(GENMASK(15, 8), dw_value));
2254+
2255+ /* UMAC WTBL DW SN part */
2256+ seq_printf(s, "\nUWTBL SN\n");
2257+ addr = (u32 *)&(uwtbl[2 * 4]);
2258+ dw_value = *addr;
2259+ seq_printf(s, "TID0_AC0_SN:%lu\n", FIELD_GET(GENMASK(11, 0), dw_value));
2260+ seq_printf(s, "TID1_AC1_SN:%lu\n", FIELD_GET(GENMASK(23, 12), dw_value));
2261+
2262+ u2SN = FIELD_GET(GENMASK(31, 24), dw_value);
2263+ addr = (u32 *)&(uwtbl[3 * 4]);
2264+ dw_value = *addr;
2265+ u2SN |= FIELD_GET(GENMASK(3, 0), dw_value);
2266+ seq_printf(s, "TID2_AC2_SN:%u\n", u2SN);
2267+ seq_printf(s, "TID3_AC3_SN:%lu\n", FIELD_GET(GENMASK(15, 4), dw_value));
2268+ seq_printf(s, "TID4_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
2269+
2270+ u2SN = FIELD_GET(GENMASK(31, 28), dw_value);
2271+ addr = (u32 *)&(uwtbl[4 * 4]);
2272+ dw_value = *addr;
2273+ u2SN |= FIELD_GET(GENMASK(7, 0), dw_value);
2274+ seq_printf(s, "TID5_SN:%u\n", u2SN);
2275+ seq_printf(s, "TID6_SN:%lu\n", FIELD_GET(GENMASK(19, 8), dw_value));
2276+ seq_printf(s, "TID7_SN:%lu\n", FIELD_GET(GENMASK(31, 20), dw_value));
2277+
2278+ addr = (u32 *)&(uwtbl[1 * 4]);
2279+ dw_value = *addr;
2280+ seq_printf(s, "COM_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
2281+
2282+ /* UMAC WTBL DW 0 */
2283+ seq_printf(s, "\nUWTBL others\n");
2284+
2285+ addr = (u32 *)&(uwtbl[5 * 4]);
2286+ dw_value = *addr;
2287+ keyloc0 = FIELD_GET(GENMASK(10, 0), dw_value);
2288+ keyloc1 = FIELD_GET(GENMASK(26, 16), dw_value);
2289+ seq_printf(s, "\tKey Loc 1/2:%lu/%lu\n",
2290+ FIELD_GET(GENMASK(10, 0), dw_value),
2291+ FIELD_GET(GENMASK(26, 16), dw_value));
2292+ seq_printf(s, "\tUWTBL_QOS:%lu\n", FIELD_GET(BIT(27), dw_value));
2293+ seq_printf(s, "\tUWTBL_HT_VHT_HE:%lu\n", FIELD_GET(BIT(28), dw_value));
2294+
2295+ addr = (u32 *)&(uwtbl[6*4]);
2296+ dw_value = *addr;
2297+ seq_printf(s, "\tHW AMSDU Enable:%lu\n", FIELD_GET(BIT(9), dw_value));
2298+
2299+ amsdu_len = FIELD_GET(GENMASK(5, 0), dw_value);
2300+ if (amsdu_len == 0)
2301+ seq_printf(s, "\tHW AMSDU Len:invalid (WTBL value=0x%x)\n", amsdu_len);
2302+ else if (amsdu_len == 1)
2303+ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
2304+ 1,
2305+ 255,
2306+ amsdu_len);
2307+ else
2308+ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
2309+ 256 * (amsdu_len - 1),
2310+ 256 * (amsdu_len - 1) + 255,
2311+ amsdu_len
2312+ );
2313+ seq_printf(s, "\tHW AMSDU Num:%lu (WTBL value=0x%lx)\n",
2314+ FIELD_GET(GENMASK(8, 6), dw_value) + 1,
2315+ FIELD_GET(GENMASK(8, 6), dw_value));
2316+
2317+ /* Parse KEY link */
2318+ seq_printf(s, "\n\tkeyloc0:%d\n", keyloc0);
2319+ if(keyloc0 != GENMASK(10, 0)) {
2320+ mt7915_wtbl_read_raw(dev, keyloc0, WTBL_TYPE_KEY,
2321+ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
2322+ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2323+ MT_DBG_WTBLON_TOP_WDUCR,
2324+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2325+ KEYTBL_IDX2BASE(keyloc0, 0));
2326+
2327+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
2328+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2329+ x,
2330+ keytbl[x * 4 + 3],
2331+ keytbl[x * 4 + 2],
2332+ keytbl[x * 4 + 1],
2333+ keytbl[x * 4]);
2334+ }
2335+ }
2336+
2337+ seq_printf(s, "\n\tkeyloc1:%d\n", keyloc1);
2338+ if(keyloc1 != GENMASK(26, 16)) {
2339+ mt7915_wtbl_read_raw(dev, keyloc1, WTBL_TYPE_KEY,
2340+ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
2341+ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
2342+ MT_DBG_WTBLON_TOP_WDUCR,
2343+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
2344+ KEYTBL_IDX2BASE(keyloc1, 0));
2345+
2346+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
2347+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
2348+ x,
2349+ keytbl[x * 4 + 3],
2350+ keytbl[x * 4 + 2],
2351+ keytbl[x * 4 + 1],
2352+ keytbl[x * 4]);
2353+ }
2354+ }
2355+ return 0;
2356+}
2357+
2358+static void
2359+dump_dma_tx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
2360+{
2361+ u32 base, cnt, cidx, didx, queue_cnt;
2362+
2363+ base= mt76_rr(dev, ring_base);
2364+ cnt = mt76_rr(dev, ring_base + 4);
2365+ cidx = mt76_rr(dev, ring_base + 8);
2366+ didx = mt76_rr(dev, ring_base + 12);
2367+ queue_cnt = (cidx >= didx) ? (cidx - didx) : (cidx - didx + cnt);
2368+
2369+ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
2370+}
2371+
2372+static void
2373+dump_dma_rx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
2374+{
2375+ u32 base, cnt, cidx, didx, queue_cnt;
2376+
2377+ base= mt76_rr(dev, ring_base);
2378+ cnt = mt76_rr(dev, ring_base + 4);
2379+ cidx = mt76_rr(dev, ring_base + 8);
2380+ didx = mt76_rr(dev, ring_base + 12);
2381+ queue_cnt = (didx > cidx) ? (didx - cidx - 1) : (didx - cidx + cnt - 1);
2382+
2383+ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
2384+}
2385+
2386+static void
2387+mt7915_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2388+{
2389+ u32 sys_ctrl[10] = {};
2390+
2391+ /* HOST DMA */
2392+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
2393+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
2394+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
2395+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
2396+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_INT_SOURCE_CSR);
2397+ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_INT_MASK_CSR);
2398+ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
2399+ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_GLO_CFG);
2400+ seq_printf(s, "HOST_DMA Configuration\n");
2401+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2402+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2403+ seq_printf(s, "%10s %10x %10x\n",
2404+ "Merge", sys_ctrl[0], sys_ctrl[1]);
2405+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2406+ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
2407+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
2408+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
2409+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
2410+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
2411+
2412+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2413+ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
2414+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
2415+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
2416+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[7]),
2417+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[7]));
2418+
2419+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT1_SOURCE_CSR);
2420+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT1_MASK_CSR);
2421+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR);
2422+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR);
2423+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR);
2424+ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR);
2425+ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_PCIE1_GLO_CFG);
2426+ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_PCIE1_GLO_CFG);
2427+ seq_printf(s, "%10s %10x %10x\n",
2428+ "MergeP1", sys_ctrl[0], sys_ctrl[1]);
2429+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2430+ "DMA0P1", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
2431+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
2432+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
2433+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
2434+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
2435+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2436+ "DMA1P1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
2437+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
2438+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
2439+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK, sys_ctrl[7]),
2440+ FIELD_GET(MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK, sys_ctrl[7]));
2441+
2442+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2443+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2444+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2445+ dump_dma_rx_ring_info(s, dev, "R0:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2446+ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
2447+
2448+ seq_printf(s, "HOST_DMA0 PCIe 1 Ring Configuration\n");
2449+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2450+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2451+ dump_dma_rx_ring_info(s, dev, "R1:Data1(MAC2H)", MT_DBG_WFDMA0_PCIE1_RX1_CTRL0);
2452+
2453+ seq_printf(s, "HOST_DMA1 Ring Configuration\n");
2454+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2455+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2456+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
2457+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
2458+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
2459+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
2460+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
2461+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_EVENT_RING_CTRL(0));
2462+ dump_dma_rx_ring_info(s, dev, "R1:Event0(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
2463+ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
2464+
2465+ seq_printf(s, "HOST_DMA1 PCIe 1 Ring Configuration\n");
2466+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2467+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2468+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA1_PCIE1_TX19_CTRL0);
2469+ dump_dma_rx_ring_info(s, dev, "R2:Event1(WA2H)", MT_DBG_WFDMA1_PCIE1_RX2_CTRL0);
2470+}
2471+
2472+static void
2473+mt7915_show_mcu_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2474+{
2475+ u32 sys_ctrl[9] = {};
2476+
2477+ /* MCU DMA information */
2478+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2479+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2480+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2481+
2482+ sys_ctrl[3] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR);
2483+ sys_ctrl[4] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR);
2484+ sys_ctrl[5] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR);
2485+ sys_ctrl[6] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR);
2486+ sys_ctrl[7] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR);
2487+ sys_ctrl[8] = mt76_rr(dev, WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR);
2488+
2489+ seq_printf(s, "MCU_DMA Configuration\n");
2490+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2491+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2492+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2493+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2494+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2495+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2496+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2497+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2498+
2499+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2500+ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[3],
2501+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2502+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2503+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2504+ (sys_ctrl[3] & WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2505+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2506+ "DMA1P1", sys_ctrl[7], sys_ctrl[8], sys_ctrl[6],
2507+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2508+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2509+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2510+ (sys_ctrl[6] & WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2511+
2512+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2513+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2514+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2515+ dump_dma_tx_ring_info(s, dev, "T0:TXD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2516+ dump_dma_tx_ring_info(s, dev, "T1:TXCMD(WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2517+ dump_dma_tx_ring_info(s, dev, "T2:TXD(WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2518+ dump_dma_rx_ring_info(s, dev, "R0:Data(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2519+ dump_dma_rx_ring_info(s, dev, "R1:TxDone(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2520+ dump_dma_rx_ring_info(s, dev, "R2:SPL(MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2521+ dump_dma_rx_ring_info(s, dev, "R3:TxDone(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2522+ dump_dma_rx_ring_info(s, dev, "R4:TXS(MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2523+
2524+ seq_printf(s, "MCU_DMA1 Ring Configuration\n");
2525+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2526+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2527+ dump_dma_tx_ring_info(s, dev, "T0:Event(WM2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR);
2528+ dump_dma_tx_ring_info(s, dev, "T1:Event0(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR);
2529+ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR);
2530+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR);
2531+ dump_dma_rx_ring_info(s, dev, "R1:Cmd(H2WM)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR);
2532+ dump_dma_rx_ring_info(s, dev, "R2:TXD0(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR);
2533+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR);
2534+ dump_dma_rx_ring_info(s, dev, "R4:Cmd(H2WA)", WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR);
2535+
2536+ seq_printf(s, "MCU_DMA1 PCIe 1 Ring Configuration\n");
2537+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2538+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2539+ dump_dma_tx_ring_info(s, dev, "T2:Event1(WA2H)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR);
2540+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR);
2541+}
2542+
2543+static void
2544+mt7986_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2545+{
2546+ u32 sys_ctrl[5] = {};
2547+
2548+ /* HOST DMA */
2549+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
2550+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
2551+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
2552+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
2553+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
2554+
2555+ seq_printf(s, "HOST_DMA Configuration\n");
2556+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2557+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2558+ seq_printf(s, "%10s %10x %10x\n",
2559+ "Merge", sys_ctrl[0], sys_ctrl[1]);
2560+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
2561+ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[4],
2562+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK, sys_ctrl[4]),
2563+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK, sys_ctrl[4]),
2564+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK, sys_ctrl[4]),
2565+ FIELD_GET(MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK, sys_ctrl[4]));
2566+
2567+
2568+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2569+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2570+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2571+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0));
2572+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1));
2573+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_TX_RING_CTRL(2));
2574+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_TX_RING_CTRL(3));
2575+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4));
2576+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2577+ dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1));
2578+ dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2));
2579+ dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(3));
2580+ dump_dma_rx_ring_info(s, dev, "R4:Data0(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(0));
2581+ dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", MT_DBG_RX_DATA_RING_CTRL(1));
2582+}
2583+
2584+static void
2585+mt7986_show_mcu_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2586+{
2587+ u32 sys_ctrl[3] = {};
2588+
2589+ /* MCU DMA information */
2590+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2591+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2592+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2593+
2594+ seq_printf(s, "MCU_DMA Configuration\n");
2595+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2596+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2597+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2598+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2599+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2600+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2601+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2602+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2603+
2604+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2605+ seq_printf(s, "%22s %10s %10s %10s %10s %10s\n",
2606+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2607+ dump_dma_tx_ring_info(s, dev, "T0:Event (WM2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2608+ dump_dma_tx_ring_info(s, dev, "T1:Event (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2609+ dump_dma_tx_ring_info(s, dev, "T2:TxDone (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2610+ dump_dma_tx_ring_info(s, dev, "T3:TxDone1 (WA2H)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR);
2611+ dump_dma_tx_ring_info(s, dev, "T4:TXD (WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR);
2612+ dump_dma_tx_ring_info(s, dev, "T5:TXCMD (WM2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR);
2613+ dump_dma_tx_ring_info(s, dev, "T6:TXD (WA2MAC)", WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR);
2614+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2615+ dump_dma_rx_ring_info(s, dev, "R1:Cmd (H2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2616+ dump_dma_rx_ring_info(s, dev, "R2:TXD (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2617+ dump_dma_rx_ring_info(s, dev, "R3:TXD1 (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2618+ dump_dma_rx_ring_info(s, dev, "R4:Cmd (H2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2619+ dump_dma_rx_ring_info(s, dev, "R5:Data (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR);
2620+ dump_dma_rx_ring_info(s, dev, "R6:TxDone/STS (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR);
2621+ dump_dma_rx_ring_info(s, dev, "R7:RPT (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR);
2622+ dump_dma_rx_ring_info(s, dev, "R8:TxDone/STS (MAC2WA)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR);
2623+ dump_dma_rx_ring_info(s, dev, "R9:Data1 (MAC2WM)", WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR);
2624+
2625+}
2626+
2627+static void
2628+mt7915_show_dma_info(struct seq_file *s, struct mt7915_dev *dev)
2629+{
2630+ u32 sys_ctrl[10] = {};
2631+
2632+ if(is_mt7915(&dev->mt76)) {
2633+ mt7915_show_host_dma_info(s, dev);
2634+ mt7915_show_mcu_dma_info(s, dev);
2635+ } else {
2636+ mt7986_show_host_dma_info(s, dev);
2637+ mt7986_show_mcu_dma_info(s, dev);
2638+ }
2639+
2640+ /* MEM DMA information */
2641+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR);
2642+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR);
2643+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR);
2644+
2645+ seq_printf(s, "MEM_DMA Configuration\n");
2646+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2647+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2648+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2649+ "MEM", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2650+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2651+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2652+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2653+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2654+
2655+ seq_printf(s, "MEM_DMA Ring Configuration\n");
2656+ seq_printf(s, "%20s %10s %10s %10s %10s %10s\n",
2657+ "Name", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2658+ dump_dma_tx_ring_info(s, dev, "T0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR);
2659+ dump_dma_tx_ring_info(s, dev, "T1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR);
2660+ dump_dma_rx_ring_info(s, dev, "R0:CmdEvent(WM2WA)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR);
2661+ dump_dma_rx_ring_info(s, dev, "R1:CmdEvent(WA2WM)", WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR);
2662+}
2663+
2664+static int mt7915_trinfo_read(struct seq_file *s, void *data)
2665+{
2666+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2667+ const struct hif_pci_tx_ring_desc *tx_ring_layout;
2668+ const struct hif_pci_rx_ring_desc *rx_ring_layout;
2669+ u32 tx_ring_num, rx_ring_num;
2670+ u32 tbase[5], tcnt[5];
2671+ u32 tcidx[5], tdidx[5];
2672+ u32 rbase[6], rcnt[6];
2673+ u32 rcidx[6], rdidx[6];
2674+ int idx;
2675+
2676+ if(is_mt7915(&dev->mt76)) {
2677+ tx_ring_layout = &mt7915_tx_ring_layout[0];
2678+ rx_ring_layout = &mt7915_rx_ring_layout[0];
2679+ tx_ring_num = ARRAY_SIZE(mt7915_tx_ring_layout);
2680+ rx_ring_num = ARRAY_SIZE(mt7915_rx_ring_layout);
2681+ } else {
2682+ tx_ring_layout = &mt7986_tx_ring_layout[0];
2683+ rx_ring_layout = &mt7986_rx_ring_layout[0];
2684+ tx_ring_num = ARRAY_SIZE(mt7986_tx_ring_layout);
2685+ rx_ring_num = ARRAY_SIZE(mt7986_rx_ring_layout);
2686+ }
2687+
2688+ for (idx = 0; idx < tx_ring_num; idx++) {
2689+ tbase[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx));
2690+ tcnt[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x04);
2691+ tcidx[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x08);
2692+ tdidx[idx] = mt76_rr(dev, MT_DBG_TX_RING_CTRL(idx) + 0x0c);
2693+ }
2694+
2695+ for (idx = 0; idx < rx_ring_num; idx++) {
2696+ if (idx < 2) {
2697+ rbase[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx));
2698+ rcnt[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x04);
2699+ rcidx[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x08);
2700+ rdidx[idx] = mt76_rr(dev, MT_DBG_RX_DATA_RING_CTRL(idx) + 0x0c);
2701+ } else {
2702+ rbase[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2));
2703+ rcnt[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x04);
2704+ rcidx[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x08);
2705+ rdidx[idx] = mt76_rr(dev, MT_DBG_RX_EVENT_RING_CTRL(idx - 2) + 0x0c);
2706+ }
2707+ }
2708+
2709+ seq_printf(s, "=================================================\n");
2710+ seq_printf(s, "TxRing Configuration\n");
2711+ seq_printf(s, "%4s %10s %8s %1s %6s %6s %6s %6s\n",
2712+ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
2713+ "QCnt");
2714+ for (idx = 0; idx < tx_ring_num; idx++) {
2715+ u32 queue_cnt;
2716+
2717+ queue_cnt = (tcidx[idx] >= tdidx[idx]) ?
2718+ (tcidx[idx] - tdidx[idx]) :
2719+ (tcidx[idx] - tdidx[idx] + tcnt[idx]);
2720+ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
2721+ idx, tx_ring_layout[idx].ring_info,
2722+ MT_DBG_TX_RING_CTRL(idx), tbase[idx],
2723+ tcnt[idx], tcidx[idx], tdidx[idx], queue_cnt);
2724+ }
2725+
2726+ seq_printf(s, "RxRing Configuration\n");
2727+ seq_printf(s, "%4s %10s %8s %10s %6s %6s %6s %6s\n",
2728+ "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX",
2729+ "QCnt");
2730+
2731+ for (idx = 0; idx < rx_ring_num; idx++) {
2732+ u32 queue_cnt;
2733+
2734+ queue_cnt = (rdidx[idx] > rcidx[idx]) ?
2735+ (rdidx[idx] - rcidx[idx] - 1) :
2736+ (rdidx[idx] - rcidx[idx] + rcnt[idx] - 1);
2737+ seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n",
2738+ idx, rx_ring_layout[idx].ring_info,
2739+ (idx < 2) ? MT_DBG_RX_DATA_RING_CTRL(idx): MT_DBG_RX_EVENT_RING_CTRL(idx - 2),
2740+ rbase[idx], rcnt[idx], rcidx[idx], rdidx[idx], queue_cnt);
2741+ }
2742+
2743+ mt7915_show_dma_info(s, dev);
2744+ return 0;
2745+}
2746+
2747+static int mt7915_drr_info(struct seq_file *s, void *data)
2748+{
2749+#define DL_AC_START 0x00
2750+#define DL_AC_END 0x0F
2751+#define UL_AC_START 0x10
2752+#define UL_AC_END 0x1F
2753+
2754+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
2755+ u32 drr_sta_status[16];
2756+ u32 drr_ctrl_def_val = 0x80220000, drr_ctrl_val = 0;
2757+ bool is_show = false;
2758+ int idx, sta_line = 0, sta_no = 0, max_sta_line = (mt7915_wtbl_size(dev) + 31) / 32;
2759+ seq_printf(s, "DRR Table STA Info:\n");
2760+
2761+ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
2762+ is_show = true;
2763+ drr_ctrl_val = (drr_ctrl_def_val | idx);
2764+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2765+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2766+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2767+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2768+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2769+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2770+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2771+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2772+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2773+
2774+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
2775+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1 << 10);
2776+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2777+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2778+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2779+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2780+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2781+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2782+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2783+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2784+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2785+ }
2786+ if (!is_mt7915(&dev->mt76))
2787+ max_sta_line = 8;
2788+
2789+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
2790+ if (drr_sta_status[sta_line] > 0) {
2791+ for (sta_no = 0; sta_no < 32; sta_no++) {
2792+ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
2793+ if (is_show) {
2794+ seq_printf(s, "\n DL AC%02d Queue Non-Empty STA:\n", idx);
2795+ is_show = false;
2796+ }
2797+ seq_printf(s, "%d ", sta_no + (sta_line * 32));
2798+ }
2799+ }
2800+ }
2801+ }
2802+ }
2803+
2804+ for (idx = UL_AC_START; idx <= UL_AC_END; idx++) {
2805+ is_show = true;
2806+ drr_ctrl_val = (drr_ctrl_def_val | idx);
2807+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2808+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2809+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2810+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2811+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2812+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2813+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2814+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2815+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2816+
2817+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
2818+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1 << 10);
2819+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2820+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2821+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2822+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2823+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2824+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2825+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2826+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2827+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2828+ }
2829+
2830+ if (!is_mt7915(&dev->mt76))
2831+ max_sta_line = 8;
2832+
2833+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
2834+ if (drr_sta_status[sta_line] > 0) {
2835+ for (sta_no = 0; sta_no < 32; sta_no++) {
2836+ if (((drr_sta_status[sta_line] & (0x1 << sta_no)) >> sta_no)) {
2837+ if (is_show) {
2838+ seq_printf(s, "\n UL AC%02d Queue Non-Empty STA:\n", idx);
2839+ is_show = false;
2840+ }
2841+ seq_printf(s, "%d ", sta_no + (sta_line * 32));
2842+ }
2843+ }
2844+ }
2845+ }
2846+ }
2847+
2848+ for (idx = DL_AC_START; idx <= DL_AC_END; idx++) {
2849+ drr_ctrl_def_val = 0x80420000;
2850+ drr_ctrl_val = (drr_ctrl_def_val | idx);
2851+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2852+ drr_sta_status[0] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2853+ drr_sta_status[1] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2854+ drr_sta_status[2] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2855+ drr_sta_status[3] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2856+ drr_sta_status[4] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2857+ drr_sta_status[5] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2858+ drr_sta_status[6] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2859+ drr_sta_status[7] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2860+
2861+ if (is_mt7915(&dev->mt76) && max_sta_line > 8) {
2862+ drr_ctrl_val = (drr_ctrl_def_val | idx | 1<<10);
2863+ mt76_wr(dev, MT_DBG_PLE_DRR_TAB_CTRL, drr_ctrl_val);
2864+ drr_sta_status[8] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA0);
2865+ drr_sta_status[9] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA1);
2866+ drr_sta_status[10] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA2);
2867+ drr_sta_status[11] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA3);
2868+ drr_sta_status[12] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA4);
2869+ drr_sta_status[13] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA5);
2870+ drr_sta_status[14] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA6);
2871+ drr_sta_status[15] = mt76_rr(dev, MT_DBG_PLE_DRR_TABLE_RDATA7);
2872+ }
2873+
2874+ seq_printf(s, "\nBSSGrp[%d]:\n", idx);
2875+ if (!is_mt7915(&dev->mt76))
2876+ max_sta_line = 8;
2877+
2878+ for (sta_line = 0; sta_line < max_sta_line; sta_line++) {
2879+ seq_printf(s, "0x%08x ", drr_sta_status[sta_line]);
2880+
2881+ if ((sta_line % 4) == 3)
2882+ seq_printf(s, "\n");
2883+ }
2884+ }
2885+
2886+ return 0;
2887+}
2888+
2889+#define CR_NUM_OF_AC 9
2890+
2891+typedef enum _ENUM_UMAC_PORT_T {
2892+ ENUM_UMAC_HIF_PORT_0 = 0,
2893+ ENUM_UMAC_CPU_PORT_1 = 1,
2894+ ENUM_UMAC_LMAC_PORT_2 = 2,
2895+ ENUM_PLE_CTRL_PSE_PORT_3 = 3,
2896+ ENUM_UMAC_PSE_PLE_PORT_TOTAL_NUM = 4
2897+} ENUM_UMAC_PORT_T, *P_ENUM_UMAC_PORT_T;
2898+
2899+/* N9 MCU QUEUE LIST */
2900+typedef enum _ENUM_UMAC_CPU_P_QUEUE_T {
2901+ ENUM_UMAC_CTX_Q_0 = 0,
2902+ ENUM_UMAC_CTX_Q_1 = 1,
2903+ ENUM_UMAC_CTX_Q_2 = 2,
2904+ ENUM_UMAC_CTX_Q_3 = 3,
2905+ ENUM_UMAC_CRX = 0,
2906+ ENUM_UMAC_CIF_QUEUE_TOTAL_NUM = 4
2907+} ENUM_UMAC_CPU_P_QUEUE_T, *P_ENUM_UMAC_CPU_P_QUEUE_T;
2908+
2909+/* LMAC PLE TX QUEUE LIST */
2910+typedef enum _ENUM_UMAC_LMAC_PLE_TX_P_QUEUE_T {
2911+ ENUM_UMAC_LMAC_PLE_TX_Q_00 = 0x00,
2912+ ENUM_UMAC_LMAC_PLE_TX_Q_01 = 0x01,
2913+ ENUM_UMAC_LMAC_PLE_TX_Q_02 = 0x02,
2914+ ENUM_UMAC_LMAC_PLE_TX_Q_03 = 0x03,
2915+
2916+ ENUM_UMAC_LMAC_PLE_TX_Q_10 = 0x04,
2917+ ENUM_UMAC_LMAC_PLE_TX_Q_11 = 0x05,
2918+ ENUM_UMAC_LMAC_PLE_TX_Q_12 = 0x06,
2919+ ENUM_UMAC_LMAC_PLE_TX_Q_13 = 0x07,
2920+
2921+ ENUM_UMAC_LMAC_PLE_TX_Q_20 = 0x08,
2922+ ENUM_UMAC_LMAC_PLE_TX_Q_21 = 0x09,
2923+ ENUM_UMAC_LMAC_PLE_TX_Q_22 = 0x0a,
2924+ ENUM_UMAC_LMAC_PLE_TX_Q_23 = 0x0b,
2925+
2926+ ENUM_UMAC_LMAC_PLE_TX_Q_30 = 0x0c,
2927+ ENUM_UMAC_LMAC_PLE_TX_Q_31 = 0x0d,
2928+ ENUM_UMAC_LMAC_PLE_TX_Q_32 = 0x0e,
2929+ ENUM_UMAC_LMAC_PLE_TX_Q_33 = 0x0f,
2930+
2931+ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 = 0x10,
2932+ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0 = 0x11,
2933+ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0 = 0x12,
2934+ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0 = 0x13,
2935+
2936+ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 = 0x14,
2937+ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1 = 0x15,
2938+ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1 = 0x16,
2939+ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1 = 0x17,
2940+ ENUM_UMAC_LMAC_PLE_TX_Q_NAF = 0x18,
2941+ ENUM_UMAC_LMAC_PLE_TX_Q_NBCN = 0x19,
2942+ ENUM_UMAC_LMAC_PLE_TX_Q_RELEASE = 0x1f, /* DE suggests not to use 0x1f, it's only for hw free queue */
2943+ ENUM_UMAC_LMAC_QUEUE_TOTAL_NUM = 24,
2944+
2945+} ENUM_UMAC_LMAC_TX_P_QUEUE_T, *P_ENUM_UMAC_LMAC_TX_P_QUEUE_T;
2946+
2947+typedef struct _EMPTY_QUEUE_INFO_T {
2948+ char *QueueName;
2949+ u32 Portid;
2950+ u32 Queueid;
2951+} EMPTY_QUEUE_INFO_T, *P_EMPTY_QUEUE_INFO_T;
2952+
2953+static EMPTY_QUEUE_INFO_T ple_queue_empty_info[] = {
2954+ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
2955+ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
2956+ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
2957+ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
2958+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
2959+ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0}, /* Q16 */
2960+ {"BMC Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0},
2961+ {"BCN Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0},
2962+ {"PSMP Q0", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0},
2963+ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1},
2964+ {"BMC Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1},
2965+ {"BCN Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1},
2966+ {"PSMP Q1", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1},
2967+ {"NAF Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NAF},
2968+ {"NBCN Q", ENUM_UMAC_LMAC_PORT_2, ENUM_UMAC_LMAC_PLE_TX_Q_NBCN},
2969+ {NULL, 0, 0}, {NULL, 0, 0}, /* 18, 19 not defined */
2970+ {"FIXFID Q", ENUM_UMAC_LMAC_PORT_2, 0x1a},
2971+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
2972+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 21~29 not defined */
2973+ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7e},
2974+ {"RLS2 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7f}
2975+};
2976+
2977+static EMPTY_QUEUE_INFO_T ple_txcmd_queue_empty_info[] = {
2978+ {"AC00Q", ENUM_UMAC_LMAC_PORT_2, 0x40},
2979+ {"AC01Q", ENUM_UMAC_LMAC_PORT_2, 0x41},
2980+ {"AC02Q", ENUM_UMAC_LMAC_PORT_2, 0x42},
2981+ {"AC03Q", ENUM_UMAC_LMAC_PORT_2, 0x43},
2982+ {"AC10Q", ENUM_UMAC_LMAC_PORT_2, 0x44},
2983+ {"AC11Q", ENUM_UMAC_LMAC_PORT_2, 0x45},
2984+ {"AC12Q", ENUM_UMAC_LMAC_PORT_2, 0x46},
2985+ {"AC13Q", ENUM_UMAC_LMAC_PORT_2, 0x47},
2986+ {"AC20Q", ENUM_UMAC_LMAC_PORT_2, 0x48},
2987+ {"AC21Q", ENUM_UMAC_LMAC_PORT_2, 0x49},
2988+ {"AC22Q", ENUM_UMAC_LMAC_PORT_2, 0x4a},
2989+ {"AC23Q", ENUM_UMAC_LMAC_PORT_2, 0x4b},
2990+ {"AC30Q", ENUM_UMAC_LMAC_PORT_2, 0x4c},
2991+ {"AC31Q", ENUM_UMAC_LMAC_PORT_2, 0x4d},
2992+ {"AC32Q", ENUM_UMAC_LMAC_PORT_2, 0x4e},
2993+ {"AC33Q", ENUM_UMAC_LMAC_PORT_2, 0x4f},
2994+ {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, 0x50},
2995+ {"TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x51},
2996+ {"TWT TSF-TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x52},
2997+ {"TWT DL Q0", ENUM_UMAC_LMAC_PORT_2, 0x53},
2998+ {"TWT UL Q0", ENUM_UMAC_LMAC_PORT_2, 0x54},
2999+ {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, 0x55},
3000+ {"TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x56},
3001+ {"TWT TSF-TF Q1", ENUM_UMAC_LMAC_PORT_2, 0x57},
3002+ {"TWT DL Q1", ENUM_UMAC_LMAC_PORT_2, 0x58},
3003+ {"TWT UL Q1", ENUM_UMAC_LMAC_PORT_2, 0x59},
3004+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
3005+};
3006+
3007+
3008+
3009+static char* sta_ctrl_reg[] = {"ENABLE", "DISABLE", "PAUSE"};
3010+static u32 chip_show_sta_acq_info(struct seq_file *s, struct mt7915_dev *dev, u32 *ple_stat,
3011+ u32 *sta_pause, u32 *dis_sta_map,
3012+ u32 dumptxd)
3013+{
3014+ int i, j;
3015+ u32 total_nonempty_cnt = 0;
3016+ u32 ac_num = 9, all_ac_num;
3017+
3018+ /* TDO: ac_num = 16 for mt7986 */
3019+ /* if (!is_mt7915(&dev->mt76))
3020+ ac_num = 16;
3021+ */
3022+
3023+ all_ac_num = ac_num * 4;
3024+
3025+ for (j = 0; j < all_ac_num; j++) { /* show AC Q info */
3026+ for (i = 0; i < 32; i++) {
3027+ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
3028+ u32 hfid, tfid, pktcnt, ac_num = j / ac_num, ctrl = 0;
3029+ u32 sta_num = i + (j % ac_num) * 32, fl_que_ctrl[3] = {0};
3030+ //struct wifi_dev *wdev = wdev_search_by_wcid(pAd, sta_num);
3031+ u32 wmmidx = 0;
3032+ struct mt7915_sta *msta;
3033+ struct mt76_wcid *wcid;
3034+ struct ieee80211_sta *sta = NULL;
3035+
3036+ wcid = rcu_dereference(dev->mt76.wcid[sta_num]);
3037+ sta = wcid_to_sta(wcid);
3038+ if (!sta) {
3039+ printk("ERROR!! no found STA wcid=%d\n", sta_num);
3040+ return 0;
3041+ }
3042+ msta = container_of(wcid, struct mt7915_sta, wcid);
3043+ wmmidx = msta->vif->mt76.wmm_idx;
3044+
3045+ seq_printf(s, "\tSTA%d AC%d: ", sta_num, ac_num);
3046+
3047+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3048+ fl_que_ctrl[0] |= (ENUM_UMAC_LMAC_PORT_2 << MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
3049+ fl_que_ctrl[0] |= (ac_num << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
3050+ fl_que_ctrl[0] |= sta_num;
3051+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3052+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3053+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3054+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3055+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3056+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3057+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x",
3058+ tfid, hfid, pktcnt);
3059+
3060+ if (((sta_pause[j % 6] & 0x1 << i) >> i) == 1)
3061+ ctrl = 2;
3062+
3063+ if (((dis_sta_map[j % 6] & 0x1 << i) >> i) == 1)
3064+ ctrl = 1;
3065+
3066+ seq_printf(s, " ctrl = %s", sta_ctrl_reg[ctrl]);
3067+ seq_printf(s, " (wmmidx=%d)\n", wmmidx);
3068+
3069+ total_nonempty_cnt++;
3070+
3071+ // TODO
3072+ //if (pktcnt > 0 && dumptxd > 0)
3073+ // ShowTXDInfo(pAd, hfid);
3074+ }
3075+ }
3076+ }
3077+
3078+ return total_nonempty_cnt;
3079+}
3080+
3081+static void chip_show_txcmdq_info(struct seq_file *s, struct mt7915_dev *dev, u32 ple_txcmd_stat)
3082+{
3083+ int i;
3084+
3085+ seq_printf(s, "Nonempty TXCMD Q info:\n");
3086+ for (i = 0; i < 31; i++) {
3087+ if (((ple_txcmd_stat & (0x1 << i)) >> i) == 0) {
3088+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3089+
3090+ if (ple_txcmd_queue_empty_info[i].QueueName != NULL) {
3091+ seq_printf(s, "\t%s: ", ple_txcmd_queue_empty_info[i].QueueName);
3092+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3093+ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Portid <<
3094+ MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
3095+ fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Queueid <<
3096+ MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
3097+ } else
3098+ continue;
3099+
3100+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3101+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3102+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3103+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3104+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3105+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3106+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3107+ tfid, hfid, pktcnt);
3108+ }
3109+ }
3110+}
3111+
3112+static void chip_get_ple_acq_stat(struct mt7915_dev *dev, u32 *ple_stat)
3113+{
3114+ int i;
3115+ int cr_num = 9, all_cr_num;
3116+ u32 ac , index;
3117+
3118+ /* TDO: cr_num = 16 for mt7986 */
3119+ /*
3120+ if(!is_mt7915(&dev->mt76))
3121+ cr_num = 16;
3122+ */
3123+ all_cr_num = cr_num * 4;
3124+
3125+ ple_stat[0] = mt76_rr(dev, MT_DBG_PLE_QUEUE_EMPTY);
3126+
3127+ for(i = 0; i < all_cr_num; i++) {
3128+ ac = i / cr_num;
3129+ index = i % cr_num;
3130+ ple_stat[i + 1] =
3131+ mt76_rr(dev, MT_DBG_PLE_AC_QEMPTY(ac, index));
3132+
3133+ }
3134+}
3135+
3136+static void chip_get_dis_sta_map(struct mt7915_dev *dev, u32 *dis_sta_map)
3137+{
3138+ int i;
3139+
3140+ for(i = 0; i < CR_NUM_OF_AC; i++) {
3141+ dis_sta_map[i] = mt76_rr(dev, MT_DBG_PLE_DIS_STA_MAP(i));
3142+ }
3143+}
3144+
3145+static void chip_get_sta_pause(struct mt7915_dev *dev, u32 *sta_pause)
3146+{
3147+ int i;
3148+
3149+ for(i = 0; i < CR_NUM_OF_AC; i++) {
3150+ sta_pause[i] = mt76_rr(dev, MT_DBG_PLE_STATION_PAUSE(i));
3151+ }
3152+}
3153+
3154+static int mt7915_pleinfo_read(struct seq_file *s, void *data)
3155+{
3156+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3157+ u32 ple_buf_ctrl, pg_sz, pg_num;
3158+ u32 ple_stat[65] = {0}, pg_flow_ctrl[8] = {0};
3159+ u32 ple_native_txcmd_stat;
3160+ u32 ple_txcmd_stat;
3161+ u32 sta_pause[CR_NUM_OF_AC] = {0}, dis_sta_map[CR_NUM_OF_AC] = {0};
3162+ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail, hif_max_q, hif_min_q;
3163+ u32 rpg_hif, upg_hif, cpu_max_q, cpu_min_q, rpg_cpu, upg_cpu;
3164+ int i, j;
3165+ u32 ac_num = 9, all_ac_num;
3166+
3167+ /* TDO: ac_num = 16 for mt7986 */
3168+ /* if (!is_mt7915(&dev->mt76))
3169+ ac_num = 16;
3170+ */
3171+
3172+ all_ac_num = ac_num * 4;
3173+
3174+ ple_buf_ctrl = mt76_rr(dev, MT_DBG_PLE_PBUF_CTRL_ADDR);
3175+ chip_get_ple_acq_stat(dev, ple_stat);
3176+ ple_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_TXCMD_Q_EMPTY);
3177+ ple_native_txcmd_stat = mt76_rr(dev, MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY);
3178+ pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PLE_FREEPG_CNT);
3179+ pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FREEPG_HEAD_TAIL);
3180+ pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_GROUP);
3181+ pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PLE_HIF_PG_INFO);
3182+ pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PLE_PG_CPU_GROUP);
3183+ pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PLE_CPU_PG_INFO);
3184+ pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PLE_PG_HIF_TXCMD_GROUP);
3185+ pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PLE_HIF_TXCMD_PG_INFO);
3186+ chip_get_dis_sta_map(dev, dis_sta_map);
3187+ chip_get_sta_pause(dev, sta_pause);
3188+
3189+ seq_printf(s, "PLE Configuration Info:\n");
3190+ seq_printf(s, "\tPacket Buffer Control(0x%x): 0x%08x\n",
3191+ MT_DBG_PLE_PBUF_CTRL_ADDR, ple_buf_ctrl);
3192+
3193+ pg_sz = FIELD_GET(MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK, ple_buf_ctrl);
3194+ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n",
3195+ pg_sz, (pg_sz == 1 ? 128 : 64));
3196+ seq_printf(s, "\t\tPage Offset=%ld(in unit of 2KB)\n",
3197+ FIELD_GET(MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK, ple_buf_ctrl));
3198+
3199+ pg_num = FIELD_GET(MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK, ple_buf_ctrl);
3200+ seq_printf(s, "\t\tTotal Page=%d pages\n", pg_num);
3201+
3202+ /* Page Flow Control */
3203+ seq_printf(s, "PLE Page Flow Control:\n");
3204+ seq_printf(s, "\tFree page counter(0x%x): 0x%08x\n",
3205+ MT_DBG_PLE_FREEPG_CNT, pg_flow_ctrl[0]);
3206+ fpg_cnt = FIELD_GET(MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK, pg_flow_ctrl[0]);
3207+
3208+ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3209+ ffa_cnt = FIELD_GET(MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK, pg_flow_ctrl[0]);
3210+
3211+ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3212+ seq_printf(s, "\tFree page head and tail(0x%x): 0x%08x\n",
3213+ MT_DBG_PLE_FREEPG_HEAD_TAIL, pg_flow_ctrl[1]);
3214+
3215+ fpg_head = FIELD_GET(MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK, pg_flow_ctrl[1]);
3216+ fpg_tail = FIELD_GET(MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK, pg_flow_ctrl[1]);
3217+ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3218+ seq_printf(s, "\tReserved page counter of HIF group(0x%x): 0x%08x\n",
3219+ MT_DBG_PLE_PG_HIF_GROUP, pg_flow_ctrl[2]);
3220+ seq_printf(s, "\tHIF group page status(0x%x): 0x%08x\n",
3221+ MT_DBG_PLE_HIF_PG_INFO, pg_flow_ctrl[3]);
3222+
3223+ hif_min_q = FIELD_GET(MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK, pg_flow_ctrl[2]);
3224+ hif_max_q = FIELD_GET(MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK, pg_flow_ctrl[2]);
3225+ seq_printf(s, "\t\tThe max/min quota pages of HIF group=0x%03x/0x%03x\n", hif_max_q, hif_min_q);
3226+
3227+ rpg_hif = FIELD_GET(MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK, pg_flow_ctrl[3]);
3228+ upg_hif = FIELD_GET(MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK, pg_flow_ctrl[3]);
3229+ seq_printf(s, "\t\tThe used/reserved pages of HIF group=0x%03x/0x%03x\n", upg_hif, rpg_hif);
3230+
3231+ seq_printf(s, "\tReserved page counter of HIF_TXCMD group(0x%x): 0x%08x\n",
3232+ MT_DBG_PLE_PG_HIF_TXCMD_GROUP, pg_flow_ctrl[6]);
3233+ seq_printf(s, "\tHIF_TXCMD group page status(0x%x): 0x%08x\n",
3234+ MT_DBG_PLE_HIF_TXCMD_PG_INFO, pg_flow_ctrl[7]);
3235+ cpu_min_q = FIELD_GET(MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
3236+ cpu_max_q = FIELD_GET(MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
3237+ seq_printf(s, "\t\tThe max/min quota pages of HIF_TXCMD group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
3238+
3239+ rpg_cpu = FIELD_GET(MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK, pg_flow_ctrl[7]);
3240+ upg_cpu = FIELD_GET(MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK, pg_flow_ctrl[7]);
3241+ seq_printf(s, "\t\tThe used/reserved pages of HIF_TXCMD group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
3242+
3243+ seq_printf(s, "\tReserved page counter of CPU group(0x820c0150): 0x%08x\n", pg_flow_ctrl[4]);
3244+ seq_printf(s, "\tCPU group page status(0x820c0154): 0x%08x\n", pg_flow_ctrl[5]);
3245+ cpu_min_q = FIELD_GET(MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK, pg_flow_ctrl[4]);
3246+ cpu_max_q = FIELD_GET(MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK, pg_flow_ctrl[4]);
3247+ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q);
3248+
3249+ rpg_cpu = FIELD_GET(MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK, pg_flow_ctrl[5]);
3250+ upg_cpu = FIELD_GET(MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK, pg_flow_ctrl[5]);
3251+ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu);
3252+
3253+ if ((ple_stat[0] & MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK) == 0) {
3254+ for (j = 0; j < all_ac_num; j++) {
3255+ if (j % ac_num == 0) {
3256+ seq_printf(s, "\n\tNonempty AC%d Q of STA#: ", j / ac_num);
3257+ }
3258+
3259+ for (i = 0; i < all_ac_num; i++) {
3260+ if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) {
3261+ seq_printf(s, "%d ", i + (j % ac_num) * 32);
3262+ }
3263+ }
3264+ }
3265+
3266+ seq_printf(s, "\n");
3267+ }
3268+
3269+ seq_printf(s, "non-native/native txcmd queue empty = %d/%d\n", ple_txcmd_stat, ple_native_txcmd_stat);
3270+
3271+ seq_printf(s, "Nonempty Q info:\n");
3272+
3273+ for (i = 0; i < all_ac_num; i++) {
3274+ if (((ple_stat[0] & (0x1 << i)) >> i) == 0) {
3275+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3276+
3277+ if (ple_queue_empty_info[i].QueueName != NULL) {
3278+ seq_printf(s, "\t%s: ", ple_queue_empty_info[i].QueueName);
3279+ fl_que_ctrl[0] |= MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK;
3280+ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Portid << MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT);
3281+ fl_que_ctrl[0] |= (ple_queue_empty_info[i].Queueid << MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT);
3282+ } else
3283+ continue;
3284+
3285+ if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 &&
3286+ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0)
3287+ /* band0 set TGID 0, bit31 = 0 */
3288+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x0);
3289+ else if (ple_queue_empty_info[i].Queueid >= ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 &&
3290+ ple_queue_empty_info[i].Queueid <= ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1)
3291+ /* band1 set TGID 1, bit31 = 1 */
3292+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL1, 0x80000000);
3293+
3294+ mt76_wr(dev, MT_DBG_PLE_FL_QUE_CTRL0, fl_que_ctrl[0]);
3295+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL2);
3296+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PLE_FL_QUE_CTRL3);
3297+ hfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK, fl_que_ctrl[1]);
3298+ tfid = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK, fl_que_ctrl[1]);
3299+ pktcnt = FIELD_GET(MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK, fl_que_ctrl[2]);
3300+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3301+ tfid, hfid, pktcnt);
3302+
3303+ /* TODO */
3304+ //if (pktcnt > 0 && dumptxd > 0)
3305+ // ShowTXDInfo(pAd, hfid);
3306+ }
3307+ }
3308+
3309+ chip_show_sta_acq_info(s, dev, ple_stat, sta_pause, dis_sta_map, 0/*dumptxd*/);
3310+ chip_show_txcmdq_info(s, dev, ple_native_txcmd_stat);
3311+
3312+ return 0;
3313+}
3314+
3315+typedef enum _ENUM_UMAC_PLE_CTRL_P3_QUEUE_T {
3316+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1E = 0x1e,
3317+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1F = 0x1f,
3318+ ENUM_UMAC_PLE_CTRL_P3_TOTAL_NUM = 2
3319+} ENUM_UMAC_PLE_CTRL_P3_QUEUE_T, *P_ENUM_UMAC_PLE_CTRL_P3_QUEUE_T;
3320+
3321+static EMPTY_QUEUE_INFO_T pse_queue_empty_info[] = {
3322+ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
3323+ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
3324+ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
3325+ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
3326+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
3327+ {"HIF Q0", ENUM_UMAC_HIF_PORT_0, 0}, /* Q8 */
3328+ {"HIF Q1", ENUM_UMAC_HIF_PORT_0, 1},
3329+ {"HIF Q2", ENUM_UMAC_HIF_PORT_0, 2},
3330+ {"HIF Q3", ENUM_UMAC_HIF_PORT_0, 3},
3331+ {"HIF Q4", ENUM_UMAC_HIF_PORT_0, 4},
3332+ {"HIF Q5", ENUM_UMAC_HIF_PORT_0, 5},
3333+ {NULL, 0, 0}, {NULL, 0, 0}, /* 14~15 not defined */
3334+ {"LMAC Q", ENUM_UMAC_LMAC_PORT_2, 0},
3335+ {"MDP TX Q", ENUM_UMAC_LMAC_PORT_2, 1},
3336+ {"MDP RX Q", ENUM_UMAC_LMAC_PORT_2, 2},
3337+ {"SEC TX Q", ENUM_UMAC_LMAC_PORT_2, 3},
3338+ {"SEC RX Q", ENUM_UMAC_LMAC_PORT_2, 4},
3339+ {"SFD_PARK Q", ENUM_UMAC_LMAC_PORT_2, 5},
3340+ {"MDP_TXIOC Q", ENUM_UMAC_LMAC_PORT_2, 6},
3341+ {"MDP_RXIOC Q", ENUM_UMAC_LMAC_PORT_2, 7},
3342+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 24~30 not defined */
3343+ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, ENUM_UMAC_PLE_CTRL_P3_Q_0X1F}
3344+};
3345+
3346+static int mt7915_pseinfo_read(struct seq_file *s, void *data)
3347+{
3348+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3349+ u32 pse_buf_ctrl, pg_sz, pg_num;
3350+ u32 pse_stat, pg_flow_ctrl[22] = {0};
3351+ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail;
3352+ u32 max_q, min_q, rsv_pg, used_pg;
3353+ int i;
3354+
3355+ pse_buf_ctrl = mt76_rr(dev, MT_DBG_PSE_PBUF_CTRL);
3356+ pse_stat = mt76_rr(dev, MT_DBG_PSE_QUEUE_EMPTY);
3357+ pg_flow_ctrl[0] = mt76_rr(dev, MT_DBG_PSE_FREEPG_CNT);
3358+ pg_flow_ctrl[1] = mt76_rr(dev, MT_DBG_PSE_FREEPG_HEAD_TAIL);
3359+ pg_flow_ctrl[2] = mt76_rr(dev, MT_DBG_PSE_PG_HIF0_GROUP);
3360+ pg_flow_ctrl[3] = mt76_rr(dev, MT_DBG_PSE_HIF0_PG_INFO);
3361+ pg_flow_ctrl[4] = mt76_rr(dev, MT_DBG_PSE_PG_HIF1_GROUP);
3362+ pg_flow_ctrl[5] = mt76_rr(dev, MT_DBG_PSE_HIF1_PG_INFO);
3363+ pg_flow_ctrl[6] = mt76_rr(dev, MT_DBG_PSE_PG_CPU_GROUP);
3364+ pg_flow_ctrl[7] = mt76_rr(dev, MT_DBG_PSE_CPU_PG_INFO);
3365+ pg_flow_ctrl[8] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC0_GROUP);
3366+ pg_flow_ctrl[9] = mt76_rr(dev, MT_DBG_PSE_LMAC0_PG_INFO);
3367+ pg_flow_ctrl[10] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC1_GROUP);
3368+ pg_flow_ctrl[11] = mt76_rr(dev, MT_DBG_PSE_LMAC1_PG_INFO);
3369+ pg_flow_ctrl[12] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC2_GROUP);
3370+ pg_flow_ctrl[13] = mt76_rr(dev, MT_DBG_PSE_LMAC2_PG_INFO);
3371+ pg_flow_ctrl[14] = mt76_rr(dev, MT_DBG_PSE_PG_PLE_GROUP);
3372+ pg_flow_ctrl[15] = mt76_rr(dev, MT_DBG_PSE_PLE_PG_INFO);
3373+ pg_flow_ctrl[16] = mt76_rr(dev, MT_DBG_PSE_PG_LMAC3_GROUP);
3374+ pg_flow_ctrl[17] = mt76_rr(dev, MT_DBG_PSE_LMAC3_PG_INFO);
3375+ pg_flow_ctrl[18] = mt76_rr(dev, MT_DBG_PSE_PG_MDP_GROUP);
3376+ pg_flow_ctrl[19] = mt76_rr(dev, MT_DBG_PSE_MDP_PG_INFO);
3377+ pg_flow_ctrl[20] = mt76_rr(dev, MT_DBG_PSE_PG_PLE1_GROUP);
3378+ pg_flow_ctrl[21] = mt76_rr(dev,MT_DBG_PSE_PLE1_PG_INFO);
3379+
3380+ /* Configuration Info */
3381+ seq_printf(s, "PSE Configuration Info:\n");
3382+ seq_printf(s, "\tPacket Buffer Control(0x82068014): 0x%08x\n", pse_buf_ctrl);
3383+ pg_sz = FIELD_GET(MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK, pse_buf_ctrl);
3384+
3385+ seq_printf(s, "\t\tPage Size=%d(%d bytes per page)\n", pg_sz, (pg_sz == 1 ? 256 : 128));
3386+ seq_printf(s, "\t\tPage Offset=%ld(in unit of 64KB)\n",
3387+ FIELD_GET(MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK, pse_buf_ctrl));
3388+ pg_num = FIELD_GET(MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK, pse_buf_ctrl);
3389+
3390+ seq_printf(s, "\t\tTotal page numbers=%d pages\n", pg_num);
3391+
3392+ /* Page Flow Control */
3393+ seq_printf(s, "PSE Page Flow Control:\n");
3394+ seq_printf(s, "\tFree page counter(0x82068100): 0x%08x\n", pg_flow_ctrl[0]);
3395+ fpg_cnt = FIELD_GET(MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK, pg_flow_ctrl[0]);
3396+ seq_printf(s, "\t\tThe toal page number of free=0x%03x\n", fpg_cnt);
3397+
3398+ ffa_cnt = FIELD_GET(MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK, pg_flow_ctrl[0]);
3399+ seq_printf(s, "\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt);
3400+
3401+ seq_printf(s, "\tFree page head and tail(0x82068104): 0x%08x\n", pg_flow_ctrl[1]);
3402+ fpg_head = FIELD_GET(MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK, pg_flow_ctrl[1]);
3403+
3404+ fpg_tail = FIELD_GET(MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK, pg_flow_ctrl[1]);
3405+ seq_printf(s, "\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head);
3406+ seq_printf(s, "\tReserved page counter of HIF0 group(0x82068110): 0x%08x\n", pg_flow_ctrl[2]);
3407+ seq_printf(s, "\tHIF0 group page status(0x82068114): 0x%08x\n", pg_flow_ctrl[3]);
3408+ min_q = FIELD_GET(MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK, pg_flow_ctrl[2]);
3409+ max_q = FIELD_GET(MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK, pg_flow_ctrl[2]);
3410+ seq_printf(s, "\t\tThe max/min quota pages of HIF0 group=0x%03x/0x%03x\n", max_q, min_q);
3411+ rsv_pg = FIELD_GET(MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK, pg_flow_ctrl[3]);;
3412+ used_pg = FIELD_GET(MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK, pg_flow_ctrl[3]);
3413+ seq_printf(s, "\t\tThe used/reserved pages of HIF0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3414+ seq_printf(s, "\tReserved page counter of HIF1 group(0x82068118): 0x%08x\n", pg_flow_ctrl[4]);
3415+ seq_printf(s, "\tHIF1 group page status(0x8206811c): 0x%08x\n", pg_flow_ctrl[5]);
3416+ min_q = FIELD_GET(MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK, pg_flow_ctrl[4]);
3417+ max_q = FIELD_GET(MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK, pg_flow_ctrl[4]);
3418+ seq_printf(s, "\t\tThe max/min quota pages of HIF1 group=0x%03x/0x%03x\n", max_q, min_q);
3419+ rsv_pg = FIELD_GET(MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK, pg_flow_ctrl[5]);
3420+ used_pg = FIELD_GET(MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK, pg_flow_ctrl[5]);
3421+
3422+ seq_printf(s, "\t\tThe used/reserved pages of HIF1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3423+ seq_printf(s, "\tReserved page counter of CPU group(0x82068150): 0x%08x\n", pg_flow_ctrl[6]);
3424+ seq_printf(s, "\tCPU group page status(0x82068154): 0x%08x\n", pg_flow_ctrl[7]);
3425+ min_q = FIELD_GET(MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK, pg_flow_ctrl[6]);
3426+ max_q = FIELD_GET(MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK, pg_flow_ctrl[6]);
3427+ seq_printf(s, "\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", max_q, min_q);
3428+ rsv_pg = FIELD_GET(MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK, pg_flow_ctrl[7]);
3429+ used_pg = FIELD_GET(MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK, pg_flow_ctrl[7]);
3430+ seq_printf(s, "\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3431+ seq_printf(s, "\tReserved page counter of LMAC0 group(0x82068170): 0x%08x\n", pg_flow_ctrl[8]);
3432+ seq_printf(s, "\tLMAC0 group page status(0x82068174): 0x%08x\n", pg_flow_ctrl[9]);
3433+ min_q = FIELD_GET(MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK, pg_flow_ctrl[8]);
3434+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK, pg_flow_ctrl[8]);
3435+ seq_printf(s, "\t\tThe max/min quota pages of LMAC0 group=0x%03x/0x%03x\n", max_q, min_q);
3436+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK, pg_flow_ctrl[9]);
3437+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK, pg_flow_ctrl[9]);
3438+ seq_printf(s, "\t\tThe used/reserved pages of LMAC0 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3439+ seq_printf(s, "\tReserved page counter of LMAC1 group(0x82068178): 0x%08x\n", pg_flow_ctrl[10]);
3440+ seq_printf(s, "\tLMAC1 group page status(0x8206817c): 0x%08x\n", pg_flow_ctrl[11]);
3441+ min_q = FIELD_GET(MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK, pg_flow_ctrl[10]);
3442+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK, pg_flow_ctrl[10]);
3443+ seq_printf(s, "\t\tThe max/min quota pages of LMAC1 group=0x%03x/0x%03x\n", max_q, min_q);
3444+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK, pg_flow_ctrl[11]);
3445+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK, pg_flow_ctrl[11]);
3446+ seq_printf(s, "\t\tThe used/reserved pages of LMAC1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3447+ seq_printf(s, "\tReserved page counter of LMAC2 group(0x82068180): 0x%08x\n", pg_flow_ctrl[11]);
3448+ seq_printf(s, "\tLMAC2 group page status(0x82068184): 0x%08x\n", pg_flow_ctrl[12]);
3449+ min_q = FIELD_GET(MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK, pg_flow_ctrl[12]);
3450+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK, pg_flow_ctrl[12]);
3451+ seq_printf(s, "\t\tThe max/min quota pages of LMAC2 group=0x%03x/0x%03x\n", max_q, min_q);
3452+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK, pg_flow_ctrl[13]);
3453+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK, pg_flow_ctrl[13]);
3454+ seq_printf(s, "\t\tThe used/reserved pages of LMAC2 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3455+
3456+ seq_printf(s, "\tReserved page counter of LMAC3 group(0x82068188): 0x%08x\n", pg_flow_ctrl[16]);
3457+ seq_printf(s, "\tLMAC3 group page status(0x8206818c): 0x%08x\n", pg_flow_ctrl[17]);
3458+ min_q = FIELD_GET(MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK, pg_flow_ctrl[16]);
3459+ max_q = FIELD_GET(MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK, pg_flow_ctrl[16]);
3460+ seq_printf(s, "\t\tThe max/min quota pages of LMAC3 group=0x%03x/0x%03x\n", max_q, min_q);
3461+ rsv_pg = FIELD_GET(MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK, pg_flow_ctrl[17]);
3462+ used_pg = FIELD_GET(MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK, pg_flow_ctrl[17]);
3463+ seq_printf(s, "\t\tThe used/reserved pages of LMAC3 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3464+
3465+ seq_printf(s, "\tReserved page counter of PLE group(0x82068160): 0x%08x\n", pg_flow_ctrl[14]);
3466+ seq_printf(s, "\tPLE group page status(0x82068164): 0x%08x\n", pg_flow_ctrl[15]);
3467+ min_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK, pg_flow_ctrl[14]);
3468+ max_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK, pg_flow_ctrl[14]);
3469+ seq_printf(s, "\t\tThe max/min quota pages of PLE group=0x%03x/0x%03x\n", max_q, min_q);
3470+ rsv_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK, pg_flow_ctrl[15]);
3471+ used_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK, pg_flow_ctrl[15]);
3472+ seq_printf(s, "\t\tThe used/reserved pages of PLE group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3473+
3474+ seq_printf(s, "\tReserved page counter of PLE1 group(0x82068168): 0x%08x\n", pg_flow_ctrl[14]);
3475+ seq_printf(s, "\tPLE1 group page status(0x8206816c): 0x%08x\n", pg_flow_ctrl[15]);
3476+ min_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK, pg_flow_ctrl[20]);
3477+ max_q = FIELD_GET(MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK, pg_flow_ctrl[20]);
3478+ seq_printf(s, "\t\tThe max/min quota pages of PLE1 group=0x%03x/0x%03x\n", max_q, min_q);
3479+ rsv_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK, pg_flow_ctrl[21]);
3480+ used_pg = FIELD_GET(MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK, pg_flow_ctrl[21]);
3481+ seq_printf(s, "\t\tThe used/reserved pages of PLE1 group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3482+
3483+ seq_printf(s, "\tReserved page counter of MDP group(0x82068198): 0x%08x\n", pg_flow_ctrl[18]);
3484+ seq_printf(s, "\tMDP group page status(0x8206819c): 0x%08x\n", pg_flow_ctrl[19]);
3485+ min_q = FIELD_GET(MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK, pg_flow_ctrl[18]);
3486+ max_q = FIELD_GET(MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK, pg_flow_ctrl[18]);
3487+ seq_printf(s, "\t\tThe max/min quota pages of MDP group=0x%03x/0x%03x\n", max_q, min_q);
3488+ rsv_pg = FIELD_GET(MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK, pg_flow_ctrl[19]);
3489+ used_pg = FIELD_GET(MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK, pg_flow_ctrl[19]);
3490+ seq_printf(s, "\t\tThe used/reserved pages of MDP group=0x%03x/0x%03x\n", used_pg, rsv_pg);
3491+
3492+ /* Queue Empty Status */
3493+ seq_printf(s, "PSE Queue Empty Status:\n");
3494+ seq_printf(s, "\tQUEUE_EMPTY(0x820680b0): 0x%08x\n", pse_stat);
3495+ seq_printf(s, "\t\tCPU Q0/1/2/3 empty=%ld/%ld/%ld/%ld\n",
3496+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK, pse_stat),
3497+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK, pse_stat),
3498+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK, pse_stat),
3499+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK, pse_stat));
3500+
3501+ seq_printf(s, "\t\tHIF Q0/1/2/3/4/5 empty=%ld/%ld/%ld/%ld/%ld/%ld\n",
3502+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK, pse_stat),
3503+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK, pse_stat),
3504+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK, pse_stat),
3505+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK, pse_stat),
3506+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK, pse_stat),
3507+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK, pse_stat));
3508+
3509+ seq_printf(s, "\t\tLMAC TX Q empty=%ld\n",
3510+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK, pse_stat));
3511+ seq_printf(s, "\t\tMDP TX Q/RX Q empty=%ld/%ld\n",
3512+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK, pse_stat),
3513+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK, pse_stat));
3514+ seq_printf(s, "\t\tSEC TX Q/RX Q empty=%ld/%ld\n",
3515+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK, pse_stat),
3516+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT, pse_stat));
3517+ seq_printf(s, "\t\tSFD PARK Q empty=%ld\n",
3518+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK, pse_stat));
3519+ seq_printf(s, "\t\tMDP TXIOC Q/RXIOC Q empty=%ld/%ld\n",
3520+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK, pse_stat),
3521+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK, pse_stat));
3522+ seq_printf(s, "\t\tRLS Q empty=%ld\n",
3523+ FIELD_GET(MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK, pse_stat));
3524+ seq_printf(s, "Nonempty Q info:\n");
3525+
3526+ for (i = 0; i < 31; i++) {
3527+ if (((pse_stat & (0x1 << i)) >> i) == 0) {
3528+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
3529+
3530+ if (pse_queue_empty_info[i].QueueName != NULL) {
3531+ seq_printf(s, "\t%s: ", pse_queue_empty_info[i].QueueName);
3532+ fl_que_ctrl[0] |= MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK;
3533+ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Portid << MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT);
3534+ fl_que_ctrl[0] |= (pse_queue_empty_info[i].Queueid << MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT);
3535+ } else
3536+ continue;
3537+
3538+ fl_que_ctrl[0] |= (0x1 << 31);
3539+
3540+ mt76_wr(dev, MT_DBG_PSE_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]);
3541+ fl_que_ctrl[1] = mt76_rr(dev, MT_DBG_PSE_FL_QUE_CTRL_2_ADDR);
3542+ fl_que_ctrl[2] = mt76_rr(dev, MT_DBG_PSE_FL_QUE_CTRL_3_ADDR);
3543+
3544+ hfid = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK, fl_que_ctrl[1]);
3545+ tfid = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK, fl_que_ctrl[1]);
3546+ pktcnt = FIELD_GET(MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK, fl_que_ctrl[2]);
3547+ seq_printf(s, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
3548+ tfid, hfid, pktcnt);
3549+ }
3550+ }
3551+
3552+ return 0;
3553+}
3554+
3555+static int mt7915_mibinfo_read_per_band(struct seq_file *s, int band_idx)
3556+{
3557+#define BSS_NUM 4
3558+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3559+ u32 mac_val0, mac_val, mac_val1, idx, band_offset = 0;
3560+ u32 msdr6, msdr7, msdr8, msdr9, msdr10, msdr16, msdr17, msdr18, msdr19, msdr20, msdr21;
3561+ u32 mbxsdr[BSS_NUM][7];
3562+ u32 mbtcr[16], mbtbcr[16], mbrcr[16], mbrbcr[16];
3563+ u32 btcr[BSS_NUM], btbcr[BSS_NUM], brcr[BSS_NUM], brbcr[BSS_NUM], btdcr[BSS_NUM], brdcr[BSS_NUM];
3564+ u32 mu_cnt[5];
3565+ u32 ampdu_cnt[3];
3566+ unsigned long per;
3567+
3568+ seq_printf(s, "Band %d MIB Status\n", band_idx);
3569+ seq_printf(s, "===============================\n");
3570+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SCR0(band_idx));
3571+ seq_printf(s, "MIB Status Control=0x%x\n", mac_val);
3572+ if (is_mt7915(&dev->mt76)) {
3573+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0PBSCR(band_idx));
3574+ seq_printf(s, "MIB Per-BSS Status Control=0x%x\n", mac_val);
3575+ }
3576+
3577+ msdr6 = mt76_rr(dev, MT_DBG_MIB_M0SDR6(band_idx));
3578+ msdr7 = mt76_rr(dev, MT_DBG_MIB_M0SDR7(band_idx));
3579+ msdr8 = mt76_rr(dev, MT_DBG_MIB_M0SDR8(band_idx));
3580+ msdr9 = mt76_rr(dev, MT_DBG_MIB_M0SDR9(band_idx));
3581+ msdr10 = mt76_rr(dev, MT_DBG_MIB_M0SDR10(band_idx));
3582+ msdr16 = mt76_rr(dev, MT_DBG_MIB_M0SDR16(band_idx));
3583+ msdr17 = mt76_rr(dev, MT_DBG_MIB_M0SDR17(band_idx));
3584+ msdr18 = mt76_rr(dev, MT_DBG_MIB_M0SDR18(band_idx));
3585+ msdr19 = mt76_rr(dev, MT_DBG_MIB_M0SDR19(band_idx));
3586+ msdr20 = mt76_rr(dev, MT_DBG_MIB_M0SDR20(band_idx));
3587+ msdr21 = mt76_rr(dev, MT_DBG_MIB_M0SDR21(band_idx));
3588+ ampdu_cnt[0] = mt76_rr(dev, MT_DBG_MIB_M0SDR12(band_idx));
3589+ ampdu_cnt[1] = mt76_rr(dev, MT_DBG_MIB_M0SDR14(band_idx));
3590+ ampdu_cnt[2] = mt76_rr(dev, MT_DBG_MIB_M0SDR15(band_idx));
3591+ ampdu_cnt[1] &= MT_DBG_MIB_M0SDR14_AMPDU_MASK;
3592+ ampdu_cnt[2] &= MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK;
3593+
3594+ seq_printf(s, "===Phy/Timing Related Counters===\n");
3595+ seq_printf(s, "\tChannelIdleCnt=0x%x\n", msdr6 & BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK);
3596+ seq_printf(s, "\tCCA_NAV_Tx_Time=0x%x\n", msdr9 & BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK);
3597+ seq_printf(s, "\tRx_MDRDY_CNT=0x%lx\n", msdr10 & MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK);
3598+ seq_printf(s, "\tCCK_MDRDY_TIME=0x%x, OFDM_MDRDY_TIME=0x%x, OFDM_GREEN_MDRDY_TIME=0x%x\n",
3599+ msdr19 & BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK,
3600+ msdr20 & BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK,
3601+ msdr21 & BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK);
3602+ seq_printf(s, "\tPrim CCA Time=0x%x\n", msdr16 & BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK);
3603+ seq_printf(s, "\tSec CCA Time=0x%x\n", msdr17 & BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK);
3604+ seq_printf(s, "\tPrim ED Time=0x%x\n", msdr18 & BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK);
3605+
3606+ seq_printf(s, "===Tx Related Counters(Generic)===\n");
3607+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR0(band_idx));
3608+ dev->dbg.bcn_total_cnt[band_idx] += (mac_val & BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK);
3609+ seq_printf(s, "\tBeaconTxCnt=0x%x\n",dev->dbg.bcn_total_cnt[band_idx]);
3610+ dev->dbg.bcn_total_cnt[band_idx] = 0;
3611+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR0(band_idx));
3612+ seq_printf(s, "\tTx 20MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK);
3613+ seq_printf(s, "\tTx 40MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT);
3614+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR1(band_idx));
3615+ seq_printf(s, "\tTx 80MHz Cnt=0x%x\n", mac_val & BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK);
3616+ seq_printf(s, "\tTx 160MHz Cnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT);
3617+ seq_printf(s, "\tAMPDU Cnt=0x%x\n", ampdu_cnt[0]);
3618+ seq_printf(s, "\tAMPDU MPDU Cnt=0x%x\n", ampdu_cnt[1]);
3619+ seq_printf(s, "\tAMPDU MPDU Ack Cnt=0x%x\n", ampdu_cnt[2]);
3620+ per = (ampdu_cnt[2] == 0 ? 0 : 1000 * (ampdu_cnt[1] - ampdu_cnt[2]) / ampdu_cnt[1]);
3621+ seq_printf(s, "\tAMPDU MPDU PER=%ld.%1ld%%\n", per / 10, per % 10);
3622+
3623+ seq_printf(s, "===MU Related Counters===\n");
3624+ mu_cnt[0] = mt76_rr(dev, MT_DBG_MIB_MUBF(band_idx));
3625+ mu_cnt[1] = mt76_rr(dev, MT_DBG_MIB_M0DR8(band_idx));
3626+ mu_cnt[2] = mt76_rr(dev, MT_DBG_MIB_M0DR9(band_idx));
3627+ mu_cnt[3] = mt76_rr(dev, MT_DBG_MIB_M0DR10(band_idx));
3628+ mu_cnt[4] = mt76_rr(dev, MT_DBG_MIB_M0DR11(band_idx));
3629+ seq_printf(s, "\tMUBF_TX_COUNT=0x%x\n", mu_cnt[0] & BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK);
3630+ seq_printf(s, "\tMU_TX_MPDU_COUNT(Ok+Fail)=0x%x\n", mu_cnt[1]);
3631+ seq_printf(s, "\tMU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[2]);
3632+ seq_printf(s, "\tMU_TO_SU_PPDU_COUNT=0x%x\n", mu_cnt[3] & BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK);
3633+ seq_printf(s, "\tSU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[4]);
3634+
3635+ seq_printf(s, "===Rx Related Counters(Generic)===\n");
3636+ seq_printf(s, "\tVector Mismacth Cnt=0x%x\n", msdr7 & BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK);
3637+ seq_printf(s, "\tDelimiter Fail Cnt=0x%x\n", msdr8 & BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK);
3638+
3639+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR3(band_idx));
3640+ seq_printf(s, "\tRxFCSErrCnt=0x%lx\n", __DBG_FIELD_GET(DBG_MIB_RX_FCS_ERROR_COUNT, mac_val));
3641+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR4(band_idx));
3642+ seq_printf(s, "\tRxFifoFullCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK));
3643+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR11(band_idx));
3644+ seq_printf(s, "\tRxLenMismatch=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK));
3645+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR5(band_idx));
3646+ seq_printf(s, "\tRxMPDUCnt=0x%x\n", (mac_val & BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK));
3647+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR22(band_idx));
3648+ seq_printf(s, "\tRx AMPDU Cnt=0x%x\n", mac_val);
3649+ /* TODO: shiang-MT7615, is MIB_M0SDR23 used for Rx total byte count for all or just AMPDU only??? */
3650+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0SDR23(band_idx));
3651+ seq_printf(s, "\tRx Total ByteCnt=0x%x\n", mac_val);
3652+
3653+ if (is_mt7915(&dev->mt76)) {
3654+ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;//check
3655+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3656+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
3657+
3658+ for (idx = 0; idx < BSS_NUM; idx++) {
3659+ btcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTCRn_ADDR + band_offset + idx * 4);
3660+ btbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTBCRn_ADDR + band_offset + idx * 4);
3661+ brcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRCRn_ADDR + band_offset + idx * 4);
3662+ brbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRBCRn_ADDR + band_offset + idx * 4);
3663+ btdcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BTDCRn_ADDR + band_offset + idx * 4);
3664+ brdcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0BRDCRn_ADDR + band_offset + idx * 4);
3665+ }
3666+
3667+ for (idx = 0; idx < BSS_NUM; idx++) {
3668+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3669+ idx, btcr[idx], btdcr[idx], btbcr[idx],
3670+ brcr[idx], brdcr[idx], brbcr[idx]);
3671+ }
3672+
3673+ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
3674+ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
3675+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3676+
3677+ for (idx = 0; idx < BSS_NUM; idx++) {
3678+ mbxsdr[idx][0] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR0_ADDR + band_offset + idx * 0x10);
3679+ mbxsdr[idx][1] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR1_ADDR + band_offset + idx * 0x10);
3680+ mbxsdr[idx][2] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR2_ADDR + band_offset + idx * 0x10);
3681+ mbxsdr[idx][3] = mt76_rr(dev, BN0_WF_MIB_TOP_M0B0SDR3_ADDR + band_offset + idx * 0x10);
3682+ }
3683+
3684+ for (idx = 0; idx < BSS_NUM; idx++) {
3685+ seq_printf(s, "%d:\t0x%08x/0x%08x 0x%08x \t 0x%08x \t 0x%08x/0x%08x/0x%08x\n",
3686+ idx, (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK),
3687+ (mbxsdr[idx][0] & BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT,
3688+ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK),
3689+ (mbxsdr[idx][1] & BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT,
3690+ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK),
3691+ (mbxsdr[idx][2] & BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK) >> BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT,
3692+ (mbxsdr[idx][3] & BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK));
3693+ }
3694+
3695+ band_offset = WF_WTBLON_TOP_B1BTCRn_ADDR - WF_WTBLON_TOP_B0BTCRn_ADDR;
3696+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3697+ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
3698+
3699+ for (idx = 0; idx < 16; idx++) {
3700+ mbtcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBTCRn_ADDR + band_offset + idx * 4);
3701+ mbtbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBTBCRn_ADDR + band_offset + idx * 4);
3702+ mbrcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBRCRn_ADDR + band_offset + idx * 4);
3703+ mbrbcr[idx] = mt76_rr(dev, WF_WTBLON_TOP_B0MBRBCRn_ADDR + band_offset + idx * 4);
3704+ }
3705+
3706+ for (idx = 0; idx < 16; idx++) {
3707+ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
3708+ idx, mbtcr[idx], mbtbcr[idx], mbrcr[idx], mbrbcr[idx]);
3709+ }
3710+ return 0;
3711+ } else {
3712+ u32 btocr[BSS_NUM], mbtocr[16],mbrocr[16], brocr[BSS_NUM];
3713+ u8 bss_nums = BSS_NUM;
3714+
3715+ band_offset = (BN1_WF_MIB_TOP_BTOCR_ADDR - BN0_WF_MIB_TOP_BTOCR_ADDR) * band_idx;
3716+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3717+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxCnt/DataCnt RxByteCnt\n");
3718+
3719+ for (idx = 0; idx < BSS_NUM; idx++) {
3720+ btocr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (idx >> 1) * 4));
3721+ btdcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTDCR_ADDR + band_offset + (idx >> 1) * 4));
3722+ btbcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (idx * 4)));
3723+ brocr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BROCR_ADDR + band_offset + (idx >> 1) * 4));
3724+ brdcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BRDCR_ADDR + band_offset + (idx >> 1) * 4));
3725+ brbcr[idx] = mt76_rr(dev, (BN0_WF_MIB_TOP_BRBCR_ADDR + band_offset + (idx * 4)));
3726+
3727+ if ((idx % 2) == 0) {
3728+ btocr[idx] = ((btocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT);
3729+ btdcr[idx] = ((btdcr[idx] & BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT);
3730+ brocr[idx] = ((brocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT);
3731+ brdcr[idx] = ((brdcr[idx] & BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT);
3732+ } else {
3733+ btocr[idx] = ((btocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT);
3734+ btdcr[idx] = ((btdcr[idx] & BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT);
3735+ brocr[idx] = ((brocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT);
3736+ brdcr[idx] = ((brdcr[idx] & BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT);
3737+ }
3738+ }
3739+
3740+ for (idx = 0; idx < BSS_NUM; idx++) {
3741+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3742+ idx, btocr[idx], btdcr[idx], btbcr[idx], brocr[idx], brdcr[idx], brbcr[idx]);
3743+ }
3744+
3745+ band_offset = (BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE) * band_idx;
3746+ seq_printf(s, "===Per-MBSS Related MIB Counters===\n");
3747+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3748+
3749+ for (idx = 0; idx < BSS_NUM; idx++) {
3750+ mbxsdr[idx][0] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR0_ADDR + band_offset + ((idx >> 1) * 4));
3751+ mbxsdr[idx][1] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR1_ADDR + band_offset + ((idx >> 1) * 4));
3752+ mbxsdr[idx][2] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR2_ADDR + band_offset + ((idx >> 1) * 4));
3753+ mbxsdr[idx][3] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR3_ADDR + band_offset + ((idx >> 1) * 4));
3754+ mbxsdr[idx][4] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR4_ADDR + band_offset + ((idx >> 1) * 4));
3755+ mbxsdr[idx][5] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR5_ADDR + band_offset + ((idx >> 1) * 4));
3756+ mbxsdr[idx][6] = mt76_rr(dev, BN0_WF_MIB_TOP_BSDR6_ADDR + band_offset + ((idx >> 1) * 4));
3757+
3758+ if ((idx % 2) == 0) {
3759+ mbxsdr[idx][0] = ((mbxsdr[idx][0] & BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT);
3760+ mbxsdr[idx][1] = ((mbxsdr[idx][1] & BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT);
3761+ mbxsdr[idx][2] = ((mbxsdr[idx][2] & BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT);
3762+ mbxsdr[idx][3] = ((mbxsdr[idx][3] & BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT);
3763+ mbxsdr[idx][4] = ((mbxsdr[idx][4] & BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT);
3764+ mbxsdr[idx][5] = ((mbxsdr[idx][5] & BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT);
3765+ mbxsdr[idx][6] = ((mbxsdr[idx][6] & BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK) >> BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT);
3766+ } else {
3767+ mbxsdr[idx][0] = ((mbxsdr[idx][0] & BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT);
3768+ mbxsdr[idx][1] = ((mbxsdr[idx][1] & BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT);
3769+ mbxsdr[idx][2] = ((mbxsdr[idx][2] & BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT);
3770+ mbxsdr[idx][3] = ((mbxsdr[idx][3] & BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT);
3771+ mbxsdr[idx][4] = ((mbxsdr[idx][4] & BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT);
3772+ mbxsdr[idx][5] = ((mbxsdr[idx][5] & BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT);
3773+ mbxsdr[idx][6] = ((mbxsdr[idx][6] & BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT);
3774+ }
3775+ }
3776+
3777+ for (idx = 0; idx < BSS_NUM; idx++) {
3778+ seq_printf(s, "%d:\t0x%x/0x%x 0x%x \t 0x%x \t 0x%x/0x%x/0x%x\n",
3779+ idx,
3780+ mbxsdr[idx][0], mbxsdr[idx][1], mbxsdr[idx][2], mbxsdr[idx][3],
3781+ mbxsdr[idx][4], mbxsdr[idx][5], mbxsdr[idx][6]);
3782+ }
3783+
3784+ band_offset = (BN1_WF_MIB_TOP_BTOCR_ADDR - BN0_WF_MIB_TOP_BTOCR_ADDR) * band_idx;
3785+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3786+ seq_printf(s, "MBSSIdx TxCnt TxByteCnt RxCnt RxByteCnt\n");
3787+
3788+ for (idx = 0; idx < 16; idx++) {
3789+ mbtocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + ((idx >> 1) * 4)));
3790+ mbtbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + (idx * 4)));
3791+ mbrocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BROCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + ((idx >> 1) * 4)));
3792+ mbrbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BRBCR_ADDR + band_offset + (((bss_nums >> 1) * 4) + (idx * 4)));
3793+
3794+ if ((idx % 2) == 0) {
3795+ mbtocr[idx] = ((mbtocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT);
3796+ mbrocr[idx] = ((mbrocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT);
3797+ } else {
3798+ mbtocr[idx] = ((mbtocr[idx] & BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT);
3799+ mbrocr[idx] = ((mbrocr[idx] & BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK) >> BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT);
3800+ }
3801+ }
3802+
3803+ for (idx = 0; idx < 16; idx++) {
3804+ seq_printf(s, "%d\t 0x%08x\t 0x%08x \t 0x%08x \t 0x%08x\n",
3805+ idx, mbtocr[idx], mbtbcr[idx], mbrocr[idx], mbrbcr[idx]);
3806+ }
3807+ }
3808+
3809+ seq_printf(s, "===Dummy delimiter insertion result===\n");
3810+ mac_val0 = mt76_rr(dev, MT_DBG_MIB_M0DR11(band_idx));
3811+ mac_val = mt76_rr(dev, MT_DBG_MIB_M0DR6(band_idx));
3812+ mac_val1 = mt76_rr(dev, MT_DBG_MIB_M0DR7(band_idx));
3813+ seq_printf(s, "Range0 = %d\t Range1 = %d\t Range2 = %d\t Range3 = %d\t Range4 = %d\n",
3814+ (mac_val0 & BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK),
3815+ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK),
3816+ (mac_val & BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT,
3817+ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK),
3818+ (mac_val1 & BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK) >> BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT);
3819+
3820+ return 0;
3821+}
3822+
3823+static int mt7915_mibinfo_band0(struct seq_file *s, void *data)
3824+{
3825+ mt7915_mibinfo_read_per_band(s, 0);
3826+ return 0;
3827+}
3828+
3829+static int mt7915_mibinfo_band1(struct seq_file *s, void *data)
3830+{
3831+ mt7915_mibinfo_read_per_band(s, 1);
3832+ return 0;
3833+}
3834+
3835+static int mt7915_token_read(struct seq_file *s, void *data)
3836+{
3837+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
3838+ int id, count = 0;
3839+ struct mt76_txwi_cache *txwi;
3840+
3841+ seq_printf(s, "Cut through token:\n");
3842+ spin_lock_bh(&dev->mt76.token_lock);
3843+ idr_for_each_entry(&dev->mt76.token, txwi, id) {
3844+ seq_printf(s, "%4d ", id);
3845+ count++;
3846+ if (count % 8 == 0)
3847+ seq_printf(s, "\n");
3848+ }
3849+ spin_unlock_bh(&dev->mt76.token_lock);
3850+ seq_printf(s, "\n");
3851+
3852+ return 0;
3853+}
3854+
3855+struct txd_l {
3856+ u32 txd_0;
3857+ u32 txd_1;
3858+ u32 txd_2;
3859+ u32 txd_3;
3860+ u32 txd_4;
3861+ u32 txd_5;
3862+ u32 txd_6;
3863+ u32 txd_7;
3864+} __packed;
3865+
3866+char *pkt_ft_str[] = {"cut_through", "store_forward", "cmd", "PDA_FW_Download"};
3867+char *hdr_fmt_str[] = {
3868+ "Non-80211-Frame",
3869+ "Command-Frame",
3870+ "Normal-80211-Frame",
3871+ "enhanced-80211-Frame",
3872+};
3873+/* TMAC_TXD_1.hdr_format */
3874+#define TMI_HDR_FT_NON_80211 0x0
3875+#define TMI_HDR_FT_CMD 0x1
3876+#define TMI_HDR_FT_NOR_80211 0x2
3877+#define TMI_HDR_FT_ENH_80211 0x3
3878+
3879+void mt7915_dump_tmac_info(u8 *tmac_info)
3880+{
3881+ struct txd_l *txd = (struct txd_l *)tmac_info;
3882+
3883+ printk("txd raw data: size=%d\n", MT_TXD_SIZE);
3884+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, tmac_info, MT_TXD_SIZE, false);
3885+
3886+ printk("TMAC_TXD Fields:\n");
3887+ printk("\tTMAC_TXD_0:\n");
3888+
3889+ /* DW0 */
3890+ /* TX Byte Count [15:0] */
3891+ printk("\t\tTxByteCnt = %ld\n", FIELD_GET(MT_TXD0_TX_BYTES, txd->txd_0));
3892+
3893+ /* PKT_FT: Packet Format [24:23] */
3894+ printk("\t\tpkt_ft = %ld(%s)\n",
3895+ FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0),
3896+ pkt_ft_str[FIELD_GET(MT_TXD0_PKT_FMT, txd->txd_0)]);
3897+
3898+ /* Q_IDX [31:25] */
3899+ printk("\t\tQueID =0x%lx\n", FIELD_GET(MT_TXD0_Q_IDX, txd->txd_0));
3900+
3901+ printk("\tTMAC_TXD_1:\n");
3902+
3903+ /* DW1 */
3904+ /* WLAN Indec [9:0] */
3905+ printk("\t\tWlan Index = %ld\n", FIELD_GET(MT_TXD1_WLAN_IDX, txd->txd_1));
3906+
3907+ /* VTA [10] */
3908+ printk("\t\tVTA = %d\n", ((txd->txd_1 & MT_TXD1_VTA) ? 1 : 0));
3909+
3910+ /* HF: Header Format [17:16] */
3911+ printk("\t\tHdrFmt = %ld(%s)\n",
3912+ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1),
3913+ FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1) < 4 ?
3914+ hdr_fmt_str[FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)] : "N/A");
3915+
3916+ switch (FIELD_GET(MT_TXD1_HDR_FORMAT, txd->txd_1)) {
3917+ case TMI_HDR_FT_NON_80211:
3918+ /* MRD [11], EOSP [12], RMVL [13], VLAN [14], ETYPE [15] */
3919+ printk("\t\t\tMRD = %d, EOSP = %d,\
3920+ RMVL = %d, VLAN = %d, ETYP = %d\n",
3921+ (txd->txd_1 & MT_TXD1_MRD) ? 1 : 0,
3922+ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
3923+ (txd->txd_1 & MT_TXD1_RMVL) ? 1 : 0,
3924+ (txd->txd_1 & MT_TXD1_VLAN) ? 1 : 0,
3925+ (txd->txd_1 & MT_TXD1_ETYP) ? 1 : 0);
3926+ break;
3927+ case TMI_HDR_FT_NOR_80211:
3928+ /* HEADER_LENGTH [15:11] */
3929+ printk("\t\t\tHeader Len = %ld(WORD)\n", FIELD_GET(MT_TXD1_HDR_INFO, txd->txd_1));
3930+ break;
3931+
3932+ case TMI_HDR_FT_ENH_80211:
3933+ /* EOSP [12], AMS [13] */
3934+ printk("\t\t\tEOSP = %d, AMS = %d\n",
3935+ (txd->txd_1 & MT_TXD1_EOSP) ? 1 : 0,
3936+ (txd->txd_1 & MT_TXD1_AMS) ? 1 : 0);
3937+ break;
3938+ }
3939+
3940+ /* Header Padding [19:18] */
3941+ printk("\t\tHdrPad = %ld\n", FIELD_GET(MT_TXD1_HDR_PAD, txd->txd_1));
3942+
3943+ /* TID [22:20] */
3944+ printk("\t\tTID = %ld\n", FIELD_GET(MT_TXD1_TID, txd->txd_1));
3945+
3946+
3947+ /* UtxB/AMSDU_C/AMSDU [23] */
3948+ printk("\t\tamsdu = %d\n", ((txd->txd_1 & MT_TXD1_AMSDU) ? 1 : 0));
3949+
3950+ /* OM [29:24] */
3951+ printk("\t\town_mac = %ld\n", FIELD_GET(MT_TXD1_OWN_MAC, txd->txd_1));
3952+
3953+
3954+ /* TGID [30] */
3955+ printk("\t\tTGID = %d\n", ((txd->txd_1 & MT_TXD1_TGID) ? 1 : 0));
3956+
3957+
3958+ /* FT [31] */
3959+ printk("\t\tTxDFormatType = %d\n", (txd->txd_1 & MT_TXD1_LONG_FORMAT) ? 1 : 0);
3960+
3961+ printk("\tTMAC_TXD_2:\n");
3962+ /* DW2 */
3963+ /* Subtype [3:0] */
3964+ printk("\t\tsub_type = %ld\n", FIELD_GET(MT_TXD2_SUB_TYPE, txd->txd_2));
3965+
3966+ /* Type[5:4] */
3967+ printk("\t\tfrm_type = %ld\n", FIELD_GET(MT_TXD2_FRAME_TYPE, txd->txd_2));
3968+
3969+ /* NDP [6] */
3970+ printk("\t\tNDP = %d\n", ((txd->txd_2 & MT_TXD2_NDP) ? 1 : 0));
3971+
3972+ /* NDPA [7] */
3973+ printk("\t\tNDPA = %d\n", ((txd->txd_2 & MT_TXD2_NDPA) ? 1 : 0));
3974+
3975+ /* SD [8] */
3976+ printk("\t\tSounding = %d\n", ((txd->txd_2 & MT_TXD2_SOUNDING) ? 1 : 0));
3977+
3978+ /* RTS [9] */
3979+ printk("\t\tRTS = %d\n", ((txd->txd_2 & MT_TXD2_RTS) ? 1 : 0));
3980+
3981+ /* BM [10] */
3982+ printk("\t\tbc_mc_pkt = %d\n", ((txd->txd_2 & MT_TXD2_MULTICAST) ? 1 : 0));
3983+
3984+ /* B [11] */
3985+ printk("\t\tBIP = %d\n", ((txd->txd_2 & MT_TXD2_BIP) ? 1 : 0));
3986+
3987+ /* DU [12] */
3988+ printk("\t\tDuration = %d\n", ((txd->txd_2 & MT_TXD2_DURATION) ? 1 : 0));
3989+
3990+ /* HE [13] */
3991+ printk("\t\tHE(HTC Exist) = %d\n", ((txd->txd_2 & MT_TXD2_HTC_VLD) ? 1 : 0));
3992+
3993+ /* FRAG [15:14] */
3994+ printk("\t\tFRAG = %ld\n", FIELD_GET(MT_TXD2_FRAG, txd->txd_2));
3995+
3996+
3997+ /* Remaining Life Time [23:16]*/
3998+ printk("\t\tReamingLife/MaxTx time = %ld (unit: 64TU)\n",
3999+ FIELD_GET(MT_TXD2_MAX_TX_TIME, txd->txd_2));
4000+
4001+ /* Power Offset [29:24] */
4002+ printk("\t\tpwr_offset = %ld\n", FIELD_GET(MT_TXD2_POWER_OFFSET, txd->txd_2));
4003+
4004+ /* FRM [30] */
4005+ printk("\t\tfix rate mode = %d\n", (txd->txd_2 & MT_TXD2_FIXED_RATE) ? 1 : 0);
4006+
4007+ /* FR[31] */
4008+ printk("\t\tfix rate = %d\n", (txd->txd_2 & MT_TXD2_FIX_RATE) ? 1 : 0);
4009+
4010+
4011+ printk("\tTMAC_TXD_3:\n");
4012+
4013+ /* DW3 */
4014+ /* NA [0] */
4015+ printk("\t\tNoAck = %d\n", (txd->txd_3 & MT_TXD3_NO_ACK) ? 1 : 0);
4016+
4017+ /* PF [1] */
4018+ printk("\t\tPF = %d\n", (txd->txd_3 & MT_TXD3_PROTECT_FRAME) ? 1 : 0);
4019+
4020+ /* EMRD [2] */
4021+ printk("\t\tEMRD = %d\n", (txd->txd_3 & MT_TXD3_EMRD) ? 1 : 0);
4022+
4023+ /* EEOSP [3] */
4024+ printk("\t\tEEOSP = %d\n", (txd->txd_3 & MT_TXD3_EEOSP) ? 1 : 0);
4025+
4026+ /* DAS [4] */
4027+ printk("\t\tda_select = %d\n", (txd->txd_3 & MT_TXD3_DAS) ? 1 : 0);
4028+
4029+ /* TM [5] */
4030+ printk("\t\ttm = %d\n", (txd->txd_3 & MT_TXD3_TIMING_MEASURE) ? 1 : 0);
4031+
4032+ /* TX Count [10:6] */
4033+ printk("\t\ttx_cnt = %ld\n", FIELD_GET(MT_TXD3_TX_COUNT, txd->txd_3));
4034+
4035+ /* Remaining TX Count [15:11] */
4036+ printk("\t\tremain_tx_cnt = %ld\n", FIELD_GET(MT_TXD3_REM_TX_COUNT, txd->txd_3));
4037+
4038+ /* SN [27:16] */
4039+ printk("\t\tsn = %ld\n", FIELD_GET(MT_TXD3_SEQ, txd->txd_3));
4040+
4041+ /* BA_DIS [28] */
4042+ printk("\t\tba dis = %d\n", (txd->txd_3 & MT_TXD3_BA_DISABLE) ? 1 : 0);
4043+
4044+ /* Power Management [29] */
4045+ printk("\t\tpwr_mgmt = 0x%x\n", (txd->txd_3 & MT_TXD3_SW_POWER_MGMT) ? 1 : 0);
4046+
4047+ /* PN_VLD [30] */
4048+ printk("\t\tpn_vld = %d\n", (txd->txd_3 & MT_TXD3_PN_VALID) ? 1 : 0);
4049+
4050+ /* SN_VLD [31] */
4051+ printk("\t\tsn_vld = %d\n", (txd->txd_3 & MT_TXD3_SN_VALID) ? 1 : 0);
4052+
4053+
4054+ /* DW4 */
4055+ printk("\tTMAC_TXD_4:\n");
4056+
4057+ /* PN_LOW [31:0] */
4058+ printk("\t\tpn_low = 0x%lx\n", FIELD_GET(MT_TXD4_PN_LOW, txd->txd_4));
4059+
4060+
4061+ /* DW5 */
4062+ printk("\tTMAC_TXD_5:\n");
4063+
4064+ /* PID [7:0] */
4065+ printk("\t\tpid = %ld\n", FIELD_GET(MT_TXD5_PID, txd->txd_5));
4066+
4067+ /* TXSFM [8] */
4068+ printk("\t\ttx_status_fmt = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_FMT) ? 1 : 0);
4069+
4070+ /* TXS2M [9] */
4071+ printk("\t\ttx_status_2_mcu = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_MCU) ? 1 : 0);
4072+
4073+ /* TXS2H [10] */
4074+ printk("\t\ttx_status_2_host = %d\n", (txd->txd_5 & MT_TXD5_TX_STATUS_HOST) ? 1 : 0);
4075+
4076+ /* ADD_BA [14] */
4077+ printk("\t\tADD_BA = %d\n", (txd->txd_5 & MT_TXD5_ADD_BA) ? 1 : 0);
4078+
4079+ /* MD [15] */
4080+ printk("\t\tMD = %d\n", (txd->txd_5 & MT_TXD5_MD) ? 1 : 0);
4081+
4082+ /* PN_HIGH [31:16] */
4083+ printk("\t\tpn_high = 0x%lx\n", FIELD_GET(MT_TXD5_PN_HIGH, txd->txd_5));
4084+
4085+ /* DW6 */
4086+ printk("\tTMAC_TXD_6:\n");
4087+
4088+ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4089+ /* Fixed BandWidth mode [2:0] */
4090+ printk("\t\tbw = %ld\n", FIELD_GET(MT_TXD6_BW, txd->txd_6));
4091+
4092+ /* DYN_BW [3] */
4093+ printk("\t\tdyn_bw = %d\n", (txd->txd_6 & MT_TXD6_DYN_BW) ? 1 : 0);
4094+
4095+ /* ANT_ID [7:4] */
4096+ printk("\t\tant_id = %ld\n", FIELD_GET(MT_TXD6_ANT_ID, txd->txd_6));
4097+
4098+ /* SPE_IDX_SEL [10] */
4099+ printk("\t\tspe_idx_sel = %d\n", (txd->txd_6 & MT_TXD6_SPE_ID_IDX) ? 1 : 0);
4100+
4101+ /* LDPC [11] */
4102+ printk("\t\tldpc = %d\n", (txd->txd_6 & MT_TXD6_LDPC) ? 1 : 0);
4103+
4104+ /* HELTF Type[13:12] */
4105+ printk("\t\tHELTF Type = %ld\n", FIELD_GET(MT_TXD6_HELTF, txd->txd_6));
4106+
4107+ /* GI Type [15:14] */
4108+ printk("\t\tGI = %ld\n", FIELD_GET(MT_TXD6_SGI, txd->txd_6));
4109+
4110+ /* Rate to be Fixed [29:16] */
4111+ printk("\t\ttx_rate = 0x%lx\n", FIELD_GET(MT_TXD6_TX_RATE, txd->txd_6));
4112+ }
4113+
4114+ /* TXEBF [30] */
4115+ printk("\t\ttxebf = %d\n", (txd->txd_6 & MT_TXD6_TX_EBF) ? 1 : 0);
4116+
4117+ /* TXIBF [31] */
4118+ printk("\t\ttxibf = %d\n", (txd->txd_6 & MT_TXD6_TX_IBF) ? 1 : 0);
4119+
4120+ /* DW7 */
4121+ printk("\tTMAC_TXD_7:\n");
4122+
4123+ if ((txd->txd_1 & MT_TXD1_VTA) == 0) {
4124+ /* SW Tx Time [9:0] */
4125+ printk("\t\tsw_tx_time = %ld\n", FIELD_GET(MT_TXD7_TX_TIME, txd->txd_7));
4126+ } else {
4127+ /* TXD Arrival Time [9:0] */
4128+ printk("\t\tat = %ld\n", FIELD_GET(MT_TXD7_TAT, txd->txd_7));
4129+ }
4130+
4131+ /* HW_AMSDU_CAP [10] */
4132+ printk("\t\thw amsdu cap = %d\n",(txd->txd_7 & MT_TXD7_HW_AMSDU) ? 1 : 0);
4133+
4134+ /* SPE_IDX [15:11] */
4135+ if (txd->txd_2 & MT_TXD2_FIX_RATE) {
4136+ printk("\t\tspe_idx = 0x%lx\n", FIELD_GET(MT_TXD7_SPE_IDX, txd->txd_7));
4137+ }
4138+
4139+ /* PSE_FID [27:16] */
4140+ printk("\t\tpse_fid = 0x%lx\n", FIELD_GET(MT_TXD7_PSE_FID, txd->txd_7));
4141+
4142+ /* Subtype [19:16] */
4143+ printk("\t\tpp_sub_type=%ld\n", FIELD_GET(MT_TXD7_SUB_TYPE, txd->txd_7));
4144+
4145+ /* Type [21:20] */
4146+ printk("\t\tpp_type=%ld\n", FIELD_GET(MT_TXD7_TYPE, txd->txd_7));
4147+
4148+ /* CTXD_CNT [25:23] */
4149+ printk("\t\tctxd cnt=0x%lx\n", FIELD_GET(MT_TXD7_CTXD_CNT, txd->txd_7));
4150+
4151+ /* CTXD [26] */
4152+ printk("\t\tctxd = %d\n", (txd->txd_7 & MT_TXD7_CTXD) ? 1 : 0);
4153+
4154+ /* I [28] */
4155+ printk("\t\ti = %d\n", (txd->txd_7 & MT_TXD7_IP_SUM) ? 1 : 0);
4156+
4157+ /* UT [29] */
4158+ printk("\t\tUT = %d\n", (txd->txd_7 & MT_TXD7_UDP_TCP_SUM) ? 1 : 0);
4159+
4160+ /* TXDLEN [31:30] */
4161+ printk("\t\t txd len= %ld\n", FIELD_GET(MT_TXD7_TXD_LEN, txd->txd_7));
4162+}
4163+
4164+
4165+static int mt7915_token_txd_read(struct seq_file *s, void *data)
4166+{
4167+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4168+ struct mt76_txwi_cache *t;
4169+ u8* txwi;
4170+
4171+ seq_printf(s, "\n");
4172+ spin_lock_bh(&dev->mt76.token_lock);
4173+
4174+ t = idr_find(&dev->mt76.token, dev->dbg.token_idx);
4175+
4176+ spin_unlock_bh(&dev->mt76.token_lock);
4177+ if (t != NULL) {
4178+ struct mt76_dev *mdev = &dev->mt76;
4179+ txwi = ((u8*)(t)) - (mdev->drv->txwi_size);
4180+ mt7915_dump_tmac_info((u8*) txwi);
4181+ seq_printf(s, "\n");
4182+ printk("[SKB]\n");
4183+ print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)t->skb->data, t->skb->len, false);
4184+ seq_printf(s, "\n");
4185+ }
4186+ return 0;
4187+}
4188+
4189+static int mt7915_amsduinfo_read(struct seq_file *s, void *data)
4190+{
4191+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4192+ u32 ple_stat[8] = {0}, total_amsdu = 0;
4193+ u8 i;
4194+
4195+ for (i = 0; i < 8; i++)
4196+ ple_stat[i] = mt76_rr(dev, MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(i));
4197+
4198+ seq_printf(s, "TXD counter status of MSDU:\n");
4199+
4200+ for (i = 0; i < 8; i++)
4201+ total_amsdu += ple_stat[i];
4202+
4203+ for (i = 0; i < 8; i++) {
4204+ seq_printf(s, "AMSDU pack count of %d MSDU in TXD: 0x%x ", i + 1, ple_stat[i]);
4205+ if (total_amsdu != 0)
4206+ seq_printf(s, "(%d%%)\n", ple_stat[i] * 100 / total_amsdu);
4207+ else
4208+ seq_printf(s, "\n");
4209+ }
4210+
4211+ return 0;
4212+
4213+}
4214+
4215+static int mt7915_agginfo_read_per_band(struct seq_file *s, int band_idx)
4216+{
4217+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
4218+ u32 value, idx, agg_rang_sel[15], ampdu_cnt[11], total_ampdu = 0;
4219+
4220+ seq_printf(s, "Band %d AGG Status\n", band_idx);
4221+ seq_printf(s, "===============================\n");
4222+ value = mt76_rr(dev, MT_DBG_AGG_AALCR0(band_idx));
4223+ seq_printf(s, "AC00 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4224+ seq_printf(s, "AC01 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4225+ seq_printf(s, "AC02 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4226+ seq_printf(s, "AC03 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4227+
4228+ value = mt76_rr(dev, MT_DBG_AGG_AALCR1(band_idx));
4229+ seq_printf(s, "AC10 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4230+ seq_printf(s, "AC11 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4231+ seq_printf(s, "AC12 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4232+ seq_printf(s, "AC13 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4233+
4234+ value = mt76_rr(dev, MT_DBG_AGG_AALCR2(band_idx));
4235+ seq_printf(s, "AC20 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4236+ seq_printf(s, "AC21 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4237+ seq_printf(s, "AC22 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4238+ seq_printf(s, "AC23 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4239+
4240+ value = mt76_rr(dev, MT_DBG_AGG_AALCR3(band_idx));
4241+ seq_printf(s, "AC30 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK, value));
4242+ seq_printf(s, "AC31 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK, value));
4243+ seq_printf(s, "AC32 Agg limit = %ld\t", FIELD_GET(MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK, value));
4244+ seq_printf(s, "AC33 Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK, value));
4245+
4246+ value = mt76_rr(dev, MT_DBG_AGG_AALCR4(band_idx));
4247+ seq_printf(s, "ALTX Agg limit = %ld\n", FIELD_GET(MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK, value));
4248+
4249+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 0));
4250+ seq_printf(s, "Winsize0 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE0_MASK, value));
4251+ seq_printf(s, "Winsize1 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE1_MASK, value));
4252+ seq_printf(s, "Winsize2 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE2_MASK, value));
4253+ seq_printf(s, "Winsize3 limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR0_WINSIZE3_MASK, value));
4254+
4255+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 1));
4256+ seq_printf(s, "Winsize4 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE4_MASK, value));
4257+ seq_printf(s, "Winsize5 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE5_MASK, value));
4258+ seq_printf(s, "Winsize6 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE6_MASK, value));
4259+ seq_printf(s, "Winsize7 limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR1_WINSIZE7_MASK, value));
4260+
4261+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 2));
4262+ seq_printf(s, "Winsize8 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZE8_MASK, value));
4263+ seq_printf(s, "Winsize9 limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZE9_MASK, value));
4264+ seq_printf(s, "WinsizeA limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZEA_MASK, value));
4265+ seq_printf(s, "WinsizeB limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR2_WINSIZEB_MASK, value));
4266+
4267+
4268+ value = mt76_rr(dev, MT_DBG_AGG_AWSCR(band_idx, 3));
4269+ seq_printf(s, "WinsizeC limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZEC_MASK, value));
4270+ seq_printf(s, "WinsizeD limit = %ld\t", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZED_MASK, value));
4271+ seq_printf(s, "WinsizeE limit = %ld\n", FIELD_GET(MT_DBG_AGG_AWSCR3_WINSIZEE_MASK, value));
4272+
4273+ seq_printf(s, "===AMPDU Related Counters===\n");
4274+
4275+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 0));
4276+ agg_rang_sel[0] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK, value);
4277+ agg_rang_sel[1] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK, value);
4278+ agg_rang_sel[2] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK, value);
4279+ agg_rang_sel[3] = FIELD_GET(MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK, value);
4280+
4281+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 1));
4282+ agg_rang_sel[4] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK, value);
4283+ agg_rang_sel[5] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK, value);
4284+ agg_rang_sel[6] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK, value);
4285+ agg_rang_sel[7] = FIELD_GET(MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK, value);
4286+
4287+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 2));
4288+ agg_rang_sel[8] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK, value);
4289+ agg_rang_sel[9] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK, value);
4290+ agg_rang_sel[10] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK, value);
4291+ agg_rang_sel[11] = FIELD_GET(MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK, value);
4292+
4293+ value = mt76_rr(dev, MT_DBG_MIB_M0ARNG(band_idx, 3));
4294+ agg_rang_sel[12] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK, value);
4295+ agg_rang_sel[13] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK, value);
4296+ agg_rang_sel[14] = FIELD_GET(MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK, value);
4297+
4298+ /* Need to add 1 after read from AGG_RANG_SEL CR */
4299+ for (idx = 0; idx < 15; idx++)
4300+ agg_rang_sel[idx]++;
4301+
4302+ ampdu_cnt[3] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 0));
4303+ ampdu_cnt[4] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 1));
4304+ ampdu_cnt[5] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 2));
4305+ ampdu_cnt[6] = mt76_rr(dev, MT_DBG_MIB_M0DR2(band_idx, 3));
4306+ ampdu_cnt[7] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 0));
4307+ ampdu_cnt[8] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 1));
4308+ ampdu_cnt[9] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 2));
4309+ ampdu_cnt[10] = mt76_rr(dev, MT_DBG_MIB_M0DR13(band_idx, 3));
4310+
4311+ seq_printf(s, "\tTx Agg Range: \t%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d \t%d~%d\n",
4312+ agg_rang_sel[0],
4313+ agg_rang_sel[0] + 1, agg_rang_sel[1],
4314+ agg_rang_sel[1] + 1, agg_rang_sel[2],
4315+ agg_rang_sel[2] + 1, agg_rang_sel[3],
4316+ agg_rang_sel[3] + 1, agg_rang_sel[4],
4317+ agg_rang_sel[4] + 1, agg_rang_sel[5],
4318+ agg_rang_sel[5] + 1, agg_rang_sel[6],
4319+ agg_rang_sel[6] + 1, agg_rang_sel[7]);
4320+
4321+#define BIT_0_to_15_MASK 0x0000FFFF
4322+#define BIT_15_to_31_MASK 0xFFFF0000
4323+#define SHFIT_16_BIT 16
4324+
4325+ for (idx = 3; idx < 11; idx++)
4326+ total_ampdu = total_ampdu + (ampdu_cnt[idx] & BIT_0_to_15_MASK) + ((ampdu_cnt[idx] & BIT_15_to_31_MASK) >> SHFIT_16_BIT);
4327+
4328+ seq_printf(s, "\t\t\t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx\n",
4329+ (ampdu_cnt[3]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK,
4330+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[3]),
4331+ (ampdu_cnt[4]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK,
4332+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[4]),
4333+ (ampdu_cnt[5]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK,
4334+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[5]),
4335+ (ampdu_cnt[6]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK,
4336+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[6]));
4337+
4338+ if (total_ampdu != 0) {
4339+ seq_printf(s, "\t\t\t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%)\n",
4340+ ((ampdu_cnt[3]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK) * 100 / total_ampdu,
4341+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[3]) * 100 / total_ampdu,
4342+ ((ampdu_cnt[4]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK) * 100 / total_ampdu,
4343+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[4]) * 100 / total_ampdu,
4344+ ((ampdu_cnt[5]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK) * 100 / total_ampdu,
4345+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[5]) * 100 / total_ampdu,
4346+ ((ampdu_cnt[6]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK) * 100 / total_ampdu,
4347+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[6]) * 100 / total_ampdu);
4348+ }
4349+
4350+ seq_printf(s, "\t\t\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~%d\t%d~256\n",
4351+ agg_rang_sel[7] + 1, agg_rang_sel[8],
4352+ agg_rang_sel[8] + 1, agg_rang_sel[9],
4353+ agg_rang_sel[9] + 1, agg_rang_sel[10],
4354+ agg_rang_sel[10] + 1, agg_rang_sel[11],
4355+ agg_rang_sel[11] + 1, agg_rang_sel[12],
4356+ agg_rang_sel[12] + 1, agg_rang_sel[13],
4357+ agg_rang_sel[13] + 1, agg_rang_sel[14],
4358+ agg_rang_sel[14] + 1);
4359+
4360+ seq_printf(s, "\t\t\t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx \t0x%lx\n",
4361+ (ampdu_cnt[7]) & MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK,
4362+ FIELD_GET(MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK, ampdu_cnt[7]),
4363+ (ampdu_cnt[8]) & MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK,
4364+ FIELD_GET(MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK, ampdu_cnt[8]),
4365+ (ampdu_cnt[9]) & MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK,
4366+ FIELD_GET(MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK, ampdu_cnt[9]),
4367+ (ampdu_cnt[10]) & MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK,
4368+ FIELD_GET(MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK, ampdu_cnt[10]));
4369+
4370+ if (total_ampdu != 0) {
4371+ seq_printf(s, "\t\t\t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%) \t(%ld%%)\n",
4372+ ((ampdu_cnt[7]) & MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK) * 100 / total_ampdu,
4373+ FIELD_GET(MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK, ampdu_cnt[7]) * 100 / total_ampdu,
4374+ ((ampdu_cnt[8]) & MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK) * 100 / total_ampdu,
4375+ FIELD_GET(MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK, ampdu_cnt[8]) * 100 / total_ampdu,
4376+ ((ampdu_cnt[9]) & MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK) * 100 / total_ampdu,
4377+ FIELD_GET(MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK, ampdu_cnt[9]) * 100 / total_ampdu,
4378+ ((ampdu_cnt[10]) & MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK) * 100 / total_ampdu,
4379+ FIELD_GET(MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK, ampdu_cnt[10]) * 100 / total_ampdu);
4380+ }
4381+
4382+ return 0;
4383+}
4384+
4385+static int mt7915_agginfo_read_band0(struct seq_file *s, void *data)
4386+{
4387+ mt7915_agginfo_read_per_band(s, 0);
4388+ return 0;
4389+}
4390+
4391+static int mt7915_agginfo_read_band1(struct seq_file *s, void *data)
4392+{
4393+ mt7915_agginfo_read_per_band(s, 1);
4394+ return 0;
4395+}
4396+
4397+/*usage: <en> <num> <len>
4398+ en: BIT(16) 0: sw amsdu 1: hw amsdu
4399+ num: GENMASK(15, 8) range 1-8
4400+ len: GENMASK(7, 0) unit: 256 bytes */
4401+static int mt7915_sta_tx_amsdu_set(void *data, u64 tx_amsdu)
4402+{
4403+/* UWTBL DW 6 */
4404+#define WTBL_AMSDU_LEN_MASK GENMASK(5, 0)
4405+#define WTBL_AMSDU_NUM_MASK GENMASK(8, 6)
4406+#define WTBL_AMSDU_EN_MASK BIT(9)
4407+#define UWTBL_HW_AMSDU_DW 6
4408+
4409+ struct mt7915_dev *dev = data;
4410+ u32 len = FIELD_GET(GENMASK(7, 0), tx_amsdu);
4411+ u32 num = FIELD_GET(GENMASK(15, 8), tx_amsdu);
4412+ u32 uwtbl;
4413+
4414+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC,
4415+ UWTBL_HW_AMSDU_DW, 1, &uwtbl);
4416+
4417+ if (len) {
4418+ uwtbl &= ~WTBL_AMSDU_LEN_MASK;
4419+ uwtbl |= FIELD_PREP(WTBL_AMSDU_LEN_MASK, len);
4420+ }
4421+
4422+ uwtbl &= ~WTBL_AMSDU_NUM_MASK;
4423+ uwtbl |= FIELD_PREP(WTBL_AMSDU_NUM_MASK, num);
4424+
4425+ if (tx_amsdu & BIT(16))
4426+ uwtbl |= WTBL_AMSDU_EN_MASK;
4427+
4428+ mt7915_wtbl_write_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC,
4429+ UWTBL_HW_AMSDU_DW, uwtbl);
4430+
4431+ return 0;
4432+}
4433+
4434+DEFINE_DEBUGFS_ATTRIBUTE(fops_tx_amsdu, NULL,
4435+ mt7915_sta_tx_amsdu_set, "%llx\n");
4436+
4437+static int mt7915_red_enable_set(void *data, u64 en)
4438+{
4439+ struct mt7915_dev *dev = data;
4440+
4441+ return mt7915_mcu_set_red(dev, en);
4442+}
4443+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_en, NULL,
4444+ mt7915_red_enable_set, "%llx\n");
4445+
4446+static int mt7915_red_show_sta_set(void *data, u64 wlan_idx)
4447+{
4448+ struct mt7915_dev *dev = data;
4449+
4450+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
4451+ MCU_WA_PARAM_RED_SHOW_STA,
4452+ wlan_idx, 0, true);
4453+
4454+ return 0;
4455+}
4456+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_show_sta, NULL,
4457+ mt7915_red_show_sta_set, "%llx\n");
4458+
4459+static int mt7915_red_target_dly_set(void *data, u64 delay)
4460+{
4461+ struct mt7915_dev *dev = data;
4462+
4463+ if (delay > 0 && delay <= 32767)
4464+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
4465+ MCU_WA_PARAM_RED_TARGET_DELAY,
4466+ delay, 0, true);
4467+
4468+ return 0;
4469+}
4470+DEFINE_DEBUGFS_ATTRIBUTE(fops_red_target_dly, NULL,
4471+ mt7915_red_target_dly_set, "%llx\n");
4472+
4473+static int
4474+mt7915_txpower_level_set(void *data, u64 val)
4475+{
4476+ struct mt7915_dev *dev = data;
4477+ struct mt7915_phy *ext_phy = mt7915_ext_phy(dev);
4478+ mt7915_mcu_set_txpower_level(&dev->phy, val);
4479+ if (ext_phy)
4480+ mt7915_mcu_set_txpower_level(ext_phy, val);
4481+
4482+ return 0;
4483+}
4484+
4485+DEFINE_DEBUGFS_ATTRIBUTE(fops_txpower_level, NULL,
4486+ mt7915_txpower_level_set, "%lld\n");
4487+
4488+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_set */
4489+static int
4490+mt7915_wa_set(void *data, u64 val)
4491+{
4492+ struct mt7915_dev *dev = data;
4493+ u32 arg1, arg2, arg3;
4494+
4495+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
4496+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
4497+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
4498+
4499+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), arg1, arg2, arg3, false);
4500+
4501+ return 0;
4502+}
4503+
4504+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_set, NULL, mt7915_wa_set,
4505+ "0x%llx\n");
4506+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_query */
4507+static int
4508+mt7915_wa_query(void *data, u64 val)
4509+{
4510+ struct mt7915_dev *dev = data;
4511+ u32 arg1, arg2, arg3;
4512+
4513+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
4514+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
4515+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
4516+
4517+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY), arg1, arg2, arg3, false);
4518+
4519+ return 0;
4520+}
4521+
4522+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_query, NULL, mt7915_wa_query,
4523+ "0x%llx\n");
4524+/* set wa debug level
4525+ usage:
4526+ echo 0x[arg] > fw_wa_debug
4527+ bit0 : DEBUG_WIFI_TX
4528+ bit1 : DEBUG_CMD_EVENT
4529+ bit2 : DEBUG_RED
4530+ bit3 : DEBUG_WARN
4531+ bit4 : DEBUG_WIFI_RX
4532+ bit5 : DEBUG_TIME_STAMP
4533+ bit6 : DEBUG_TX_FREE_DONE_EVENT
4534+ bit12 : DEBUG_WIFI_TXD */
4535+static int
4536+mt7915_wa_debug(void *data, u64 val)
4537+{
4538+ struct mt7915_dev *dev = data;
4539+ u32 arg;
4540+
4541+ arg = FIELD_GET(GENMASK_ULL(15, 0), val);
4542+
4543+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(DEBUG), arg, 0, 0, false);
4544+
4545+ return 0;
4546+}
4547+
4548+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_debug, NULL, mt7915_wa_debug,
4549+ "0x%llx\n");
4550+
4551+int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir)
4552+{
4553+ struct mt7915_dev *dev = phy->dev;
4554+ u32 device_id = (dev->mt76.rev) >> 16;
4555+ int i = 0;
4556+
4557+ for (i = 0; i < ARRAY_SIZE(dbg_reg_s); i++) {
4558+ if (device_id == dbg_reg_s[i].id) {
4559+ dev->dbg_reg = &dbg_reg_s[i];
4560+ break;
4561+ }
4562+ }
4563+
4564+ mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 0);
4565+
4566+ debugfs_create_file("fw_debug_module", 0600, dir, dev,
4567+ &fops_fw_debug_module);
4568+ debugfs_create_file("fw_debug_level", 0600, dir, dev,
4569+ &fops_fw_debug_level);
4570+
4571+ debugfs_create_devm_seqfile(dev->mt76.dev, "wtbl_info", dir,
4572+ mt7915_wtbl_read);
4573+ debugfs_create_devm_seqfile(dev->mt76.dev, "uwtbl_info", dir,
4574+ mt7915_uwtbl_read);
4575+
4576+ debugfs_create_devm_seqfile(dev->mt76.dev, "tr_info", dir,
4577+ mt7915_trinfo_read);
4578+
4579+ debugfs_create_devm_seqfile(dev->mt76.dev, "drr_info", dir,
4580+ mt7915_drr_info);
4581+
4582+ debugfs_create_devm_seqfile(dev->mt76.dev, "ple_info", dir,
4583+ mt7915_pleinfo_read);
4584+
4585+ debugfs_create_devm_seqfile(dev->mt76.dev, "pse_info", dir,
4586+ mt7915_pseinfo_read);
4587+
4588+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info0", dir,
4589+ mt7915_mibinfo_band0);
4590+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info1", dir,
4591+ mt7915_mibinfo_band1);
4592+
4593+ debugfs_create_u32("token_idx", 0600, dir, &dev->dbg.token_idx);
4594+ debugfs_create_devm_seqfile(dev->mt76.dev, "token", dir,
4595+ mt7915_token_read);
4596+ debugfs_create_devm_seqfile(dev->mt76.dev, "token_txd", dir,
4597+ mt7915_token_txd_read);
4598+
4599+ debugfs_create_devm_seqfile(dev->mt76.dev, "amsdu_info", dir,
4600+ mt7915_amsduinfo_read);
4601+
4602+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info0", dir,
4603+ mt7915_agginfo_read_band0);
4604+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info1", dir,
4605+ mt7915_agginfo_read_band1);
4606+
4607+ debugfs_create_file("tx_amsdu", 0600, dir, dev, &fops_tx_amsdu);
4608+
4609+ debugfs_create_file("fw_wa_query", 0600, dir, dev, &fops_wa_query);
4610+ debugfs_create_file("fw_wa_set", 0600, dir, dev, &fops_wa_set);
4611+ debugfs_create_file("fw_wa_debug", 0600, dir, dev, &fops_wa_debug);
4612+
4613+ debugfs_create_file("red_en", 0600, dir, dev,
4614+ &fops_red_en);
4615+ debugfs_create_file("red_show_sta", 0600, dir, dev,
4616+ &fops_red_show_sta);
4617+ debugfs_create_file("red_target_dly", 0600, dir, dev,
4618+ &fops_red_target_dly);
4619+
4620+ debugfs_create_file("txpower_level", 0400, dir, dev,
4621+ &fops_txpower_level);
4622+
4623+ return 0;
4624+}
4625+#endif
4626diff --git a/mt7915/mtk_mcu.c b/mt7915/mtk_mcu.c
4627new file mode 100644
4628index 00000000..145fe785
4629--- /dev/null
4630+++ b/mt7915/mtk_mcu.c
4631@@ -0,0 +1,51 @@
4632+#include <linux/firmware.h>
4633+#include <linux/fs.h>
4634+#include<linux/inet.h>
4635+#include "mt7915.h"
4636+#include "mcu.h"
4637+#include "mac.h"
4638+
4639+int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level)
4640+{
4641+ struct mt7915_dev *dev = phy->dev;
4642+ struct mt7915_sku_val {
4643+ u8 format_id;
4644+ u8 val;
4645+ u8 band;
4646+ u8 _rsv;
4647+ } __packed req = {
4648+ .format_id = 1,
4649+ .band = phy->band_idx,
4650+ .val = !!drop_level,
4651+ };
4652+ int ret;
4653+
4654+ ret = mt76_mcu_send_msg(&dev->mt76,
4655+ MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
4656+ sizeof(req), true);
4657+ if (ret)
4658+ return ret;
4659+
4660+ req.format_id = 2;
4661+ if ((drop_level > 90 && drop_level < 100) || !drop_level)
4662+ req.val = 0;
4663+ else if (drop_level > 60 && drop_level <= 90)
4664+ /* reduce Pwr for 1 dB. */
4665+ req.val = 2;
4666+ else if (drop_level > 30 && drop_level <= 60)
4667+ /* reduce Pwr for 3 dB. */
4668+ req.val = 6;
4669+ else if (drop_level > 15 && drop_level <= 30)
4670+ /* reduce Pwr for 6 dB. */
4671+ req.val = 12;
4672+ else if (drop_level > 9 && drop_level <= 15)
4673+ /* reduce Pwr for 9 dB. */
4674+ req.val = 18;
4675+ else if (drop_level > 0 && drop_level <= 9)
4676+ /* reduce Pwr for 12 dB. */
4677+ req.val = 24;
4678+
4679+ return mt76_mcu_send_msg(&dev->mt76,
4680+ MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), &req,
4681+ sizeof(req), true);
4682+}
4683diff --git a/tools/fwlog.c b/tools/fwlog.c
4684index e5d4a105..58a976a9 100644
4685--- a/tools/fwlog.c
4686+++ b/tools/fwlog.c
4687@@ -26,7 +26,7 @@ static const char *debugfs_path(const char *phyname, const char *file)
4688 return path;
4689 }
4690
4691-static int mt76_set_fwlog_en(const char *phyname, bool en)
4692+static int mt76_set_fwlog_en(const char *phyname, bool en, char *val)
4693 {
4694 FILE *f = fopen(debugfs_path(phyname, "fw_debug_bin"), "w");
4695
4696@@ -35,7 +35,13 @@ static int mt76_set_fwlog_en(const char *phyname, bool en)
4697 return 1;
4698 }
4699
4700- fprintf(f, "7");
4701+ if (en && val)
4702+ fprintf(f, "%s", val);
4703+ else if (en)
4704+ fprintf(f, "7");
4705+ else
4706+ fprintf(f, "0");
4707+
4708 fclose(f);
4709
4710 return 0;
4711@@ -76,6 +82,7 @@ static void handle_signal(int sig)
4712
4713 int mt76_fwlog(const char *phyname, int argc, char **argv)
4714 {
4715+#define BUF_SIZE 1504
4716 struct sockaddr_in local = {
4717 .sin_family = AF_INET,
4718 .sin_addr.s_addr = INADDR_ANY,
4719@@ -84,9 +91,9 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4720 .sin_family = AF_INET,
4721 .sin_port = htons(55688),
4722 };
4723- char buf[1504];
4724+ char *buf = calloc(BUF_SIZE, sizeof(char));
4725 int ret = 0;
4726- int yes = 1;
4727+ /* int yes = 1; */
4728 int s, fd;
4729
4730 if (argc < 1) {
4731@@ -105,13 +112,13 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4732 return 1;
4733 }
4734
4735- setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes));
4736+ /* setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes)); */
4737 if (bind(s, (struct sockaddr *)&local, sizeof(local)) < 0) {
4738 perror("bind");
4739 return 1;
4740 }
4741
4742- if (mt76_set_fwlog_en(phyname, true))
4743+ if (mt76_set_fwlog_en(phyname, true, argv[1]))
4744 return 1;
4745
4746 fd = open(debugfs_path(phyname, "fwlog_data"), O_RDONLY);
4747@@ -145,8 +152,8 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4748 if (!r)
4749 continue;
4750
4751- if (len > sizeof(buf)) {
4752- fprintf(stderr, "Length error: %d > %d\n", len, (int)sizeof(buf));
4753+ if (len > BUF_SIZE) {
4754+ fprintf(stderr, "Length error: %d > %d\n", len, BUF_SIZE);
4755 ret = 1;
4756 break;
4757 }
4758@@ -171,7 +178,8 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4759 close(fd);
4760
4761 out:
4762- mt76_set_fwlog_en(phyname, false);
4763+ mt76_set_fwlog_en(phyname, false, NULL);
4764+ free(buf);
4765
4766 return ret;
4767 }
4768--
47692.25.1
4770