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git01.mediatek.com / filogic / atf / 50cd106077a35f913731523ebae7c7d13dfa3109 / include / lib
  1. c9e2c92 SPMD: Adds partially supported EL2 registers. by Max Shvetsov · Mon Feb 17 16:15:47 2020 +0000
  2. bdf502d SPMD: save/restore EL2 system registers. by Max Shvetsov · Tue Feb 25 13:56:19 2020 +0000
  3. 7029c3a Merge "fconf: Fix misra issues" into integration by Sandrine Bailleux · Fri Feb 28 10:22:05 2020 +0000
  4. 2711cc8 fconf: Fix misra issues by Louis Mayencourt · Mon Feb 24 14:37:25 2020 +0000
  5. e5a6fef Read-only xlat tables for BL31 memory by Petre-Ionut Tudor · Thu Nov 07 15:18:03 2019 +0000
  6. 0fc5403 Merge "Add Matterhorn CPU lib" into integration by joanna.farley · Fri Feb 21 17:51:10 2020 +0000
  7. c9a45ed Merge "Add CPULib for Klein Core" into integration by joanna.farley · Fri Feb 21 17:50:01 2020 +0000
  8. 0a176e3 include: move MHZ_TICKS_PER_SEC to utils_def.h by Varun Wadekar · Thu Feb 13 13:07:12 2020 -0800
  9. 5ee3abc cpus: higher performance non-cacheable load forwarding by Varun Wadekar · Tue Jun 12 16:49:12 2018 -0700
  10. 91d8061 coverity: fix MISRA violations by Zelalem · Wed Feb 12 10:37:03 2020 -0600
  11. d904ac1 Add Matterhorn CPU lib by Jimmy Brisson · Wed Jan 08 13:52:51 2020 -0600
  12. 2463f9d Add CPULib for Klein Core by Jimmy Brisson · Mon Dec 09 14:02:22 2019 -0600
  13. 5b9055f fconf: Add mbedtls shared heap as property by Louis Mayencourt · Tue Oct 01 10:45:14 2019 +0100
  14. 4da9b31 fconf: Add TBBR disable_authentication property by Louis Mayencourt · Mon Sep 30 10:57:24 2019 +0100
  15. 6d2b573 fconf: Add dynamic config DTBs info as property by Louis Mayencourt · Tue Dec 17 13:17:25 2019 +0000
  16. 81bd916 fconf: Populate properties from dtb during bl2 setup by Louis Mayencourt · Thu Oct 17 15:14:25 2019 +0100
  17. 5a15b2d fconf: Load config dtb from bl1 by Louis Mayencourt · Thu Oct 17 14:46:51 2019 +0100
  18. 944ade8 fconf: initial commit by Louis Mayencourt · Thu Aug 08 12:03:26 2019 +0100
  19. ff46037 Merge "Use correct type when reading SCR register" into integration by Alexei Fedorov · Thu Jan 30 16:55:55 2020 +0000
  20. d57f1d2 Merge changes I0fb7cf79,Ia8eb4710 into integration by Soby Mathew · Wed Jan 29 09:51:21 2020 +0000
  21. 1c819c3 Use correct type when reading SCR register by Louis Mayencourt · Fri Jan 24 13:30:28 2020 +0000
  22. 3880a36 Neovers N1: added support to update presence of External LLC by Manish Pandey · Fri Jan 24 11:54:44 2020 +0000
  23. f3a6839 qemu: Implement qemu_system_off via semihosting. by Andrew Walbran · Wed Jan 15 14:18:04 2020 +0000
  24. a265ade lib: utils_def: add CLAMP macro by Lionel Debieve · Thu Jan 02 11:14:16 2020 +0100
  25. 025b1d2 Merge "Unify type of "cpu_idx" across PSCI module." into integration by Mark Dykes · Fri Jan 10 19:39:17 2020 +0000
  26. 4287c0c Unify type of "cpu_idx" across PSCI module. by Deepika Bhavnani · Fri Dec 13 10:23:18 2019 -0600
  27. 71e66b4 Merge "smccc: add get smc function id num macro" into integration by Mark Dykes · Thu Jan 09 20:22:16 2020 +0000
  28. 304b7f9 smccc: add get smc function id num macro by Olivier Deprez · Mon Dec 23 12:04:45 2019 +0100
  29. a091d04 Simplify PMF helper macro definitions across header files by Madhukar Pappireddy · Mon Jan 06 14:42:30 2020 -0600
  30. c74aa31 Merge "Workaround for Hercules erratum 1688305" into integration by Manish Pandey · Mon Dec 30 15:52:32 2019 +0000
  31. 4efede7 Workaround for Hercules erratum 1688305 by Madhukar Pappireddy · Wed Dec 18 15:56:27 2019 -0600
  32. 9ab98aa lib: cpu: Add additional field definition for A72 L2 control by Sheetal Tigadoli · Fri Apr 12 15:28:44 2019 +0530
  33. ce9af96 Merge "debugfs: add SMC channel" into integration by Mark Dykes · Fri Dec 20 20:56:23 2019 +0000
  34. 40b88bd Merge "debugfs: add 9p device interface" into integration by Mark Dykes · Fri Dec 20 18:10:50 2019 +0000
  35. db4e25a spm: Remove SPM Alpha 1 prototype and support files by Paul Beesley · Mon Oct 14 15:27:12 2019 +0000
  36. aa4fd60 Merge changes from topic "bs/pmf32" into integration by György Szing · Fri Dec 20 10:33:43 2019 +0000
  37. 9660dc1 debugfs: add SMC channel by Ambroise Vincent · Fri Jul 12 13:47:03 2019 +0100
  38. f8cee2d Merge "arm: gicv3: Fix compiler dependent behavior" into integration by Soby Mathew · Tue Dec 17 16:43:39 2019 +0000
  39. 78dc10c pmf: Make the runtime instrumentation work on AArch32 by Bence Szépkúti · Thu Nov 07 12:09:24 2019 +0100
  40. cb4c562 debugfs: add 9p device interface by Olivier Deprez · Thu Sep 19 17:46:46 2019 +0200
  41. cf17578 libc: Fix SIZE_MAX on AArch32 by Bence Szépkúti · Mon Dec 16 14:57:40 2019 +0100
  42. 94606d6 Merge "libc: add memrchr" into integration by Alexei Fedorov · Wed Dec 11 10:14:13 2019 +0000
  43. 35248f2 libc: add memrchr by Ambroise Vincent · Wed Jun 19 17:14:09 2019 +0100
  44. 67dd93e arm: gicv3: Fix compiler dependent behavior by Ambroise Vincent · Thu Jul 18 10:56:14 2019 +0100
  45. e5ed19c Merge changes from topic "bs/libc" into integration by Soby Mathew · Fri Dec 06 11:15:58 2019 +0000
  46. 92410c9 libc: Consolidate the size_t and NULL definitions by Bence Szépkúti · Fri Oct 25 18:12:41 2019 +0200
  47. fddf518 libc: Consolidate unified definitions by Bence Szépkúti · Fri Oct 25 17:48:20 2019 +0200
  48. d52c9da libc: Unify intmax_t and uintmax_t on AArch32/64 by Bence Szépkúti · Fri Oct 25 16:52:55 2019 +0200
  49. 20be077 Changes to support updated register usage in SMCCC v1.2 by Madhukar Pappireddy · Sat Nov 09 23:28:08 2019 -0600
  50. b669361 Replace deprecated __ASSEMBLY__ macro with __ASSEMBLER__ by Balint Dobszay · Fri Oct 11 14:01:43 2019 +0200
  51. 2fbce24 Merge "Neoverse N1 Errata Workaround 1542419" into integration by Soby Mathew · Mon Oct 07 12:05:26 2019 +0000
  52. 94accd3 Neoverse N1 Errata Workaround 1542419 by laurenw-arm · Tue Aug 20 15:51:24 2019 -0500
  53. 584410e Introducing support for Cortex-A65AE by Imre Kis · Mon Jul 22 14:36:30 2019 +0200
  54. 05e4d22 Introducing support for Cortex-A65 by Imre Kis · Thu Jul 18 14:30:03 2019 +0200
  55. fea97f7 Cortex_hercules: Add support for Hercules-AE by Artsem Artsemenka · Mon Sep 16 15:11:21 2019 +0100
  56. 33bd514 Adding new optional PSCI hook pwr_domain_on_finish_late by Madhukar Pappireddy · Mon Aug 12 18:31:33 2019 -0500
  57. 7c9a4e6 Merge "Refactor ARMv8.3 Pointer Authentication support code" into integration by Soby Mathew · Fri Sep 13 15:22:23 2019 +0000
  58. f41355c Refactor ARMv8.3 Pointer Authentication support code by Alexei Fedorov · Fri Sep 13 14:11:59 2019 +0100
  59. 09a3b8d Merge changes I08cf22df,I535ee414,Ie84cfc96,I8c35ce4e,If7649764, ... into integration by Soby Mathew · Fri Sep 13 11:51:49 2019 +0000
  60. 9180af2 Merge "libc: fix sparse warning for __assert()" into integration by Soby Mathew · Thu Sep 12 12:34:27 2019 +0000
  61. 77389b2 libc: fix sparse warning for __assert() by Masahiro Yamada · Fri Jul 26 20:21:39 2019 +0900
  62. a21d47e mediatek: mt8183: support CPU hotplug by developer · Thu May 02 19:29:25 2019 +0800
  63. 1c7c13a Enable MTE support in both secure and non-secure worlds by Justin Chadwell · Thu Jul 18 14:25:33 2019 +0100
  64. 503bbf3 AArch64: Disable Secure Cycle Counter by Alexei Fedorov · Tue Aug 13 15:17:53 2019 +0100
  65. 8e0ef0f Switch AARCH32/AARCH64 to __aarch64__ by Julius Werner · Tue Jul 09 14:02:43 2019 -0700
  66. 53456fc Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ by Julius Werner · Tue Jul 09 13:49:11 2019 -0700
  67. db2ec85 Enable AMU for Cortex-Hercules by Balint Dobszay · Mon Jul 15 11:46:20 2019 +0200
  68. 4047728 Merge changes I0d17ba6c,I540741d2,I9e6475ad,Ifd769320,I12c04a85, ... into integration by Soby Mathew · Thu Jul 25 09:04:21 2019 +0000
  69. 2a231e3 Factor out cross-BL API into export headers suitable for 3rd party code by Julius Werner · Tue May 28 21:03:58 2019 -0700
  70. dbba2b3 Introduce lightweight BL platform parameter library by Julius Werner · Fri May 24 20:31:15 2019 -0700
  71. f57f108 Cortex_hercules: Introduce preliminary cpu support by Louis Mayencourt · Tue May 14 11:00:45 2019 +0100
  72. 5ecfb39 Merge "AArch64: Add 128-bit integer types definitions" into integration by Sandrine Bailleux · Fri Jul 12 08:37:24 2019 +0000
  73. abf08e1 AArch64: Add 128-bit integer types definitions by Alexei Fedorov · Wed Jul 10 11:32:52 2019 +0100
  74. cc94264 Rename Cortex-Deimos to Cortex-A77 by Balint Dobszay · Wed Jul 03 13:02:56 2019 +0200
  75. 00396bf Workaround for Neoverse N1 erratum 1262888 by lauwal01 · Mon Jun 24 11:47:30 2019 -0500
  76. 42771af Workaround for Neoverse N1 erratum 1262606 by lauwal01 · Mon Jun 24 11:44:58 2019 -0500
  77. 07c2a23 Workaround for Neoverse N1 erratum 1257314 by lauwal01 · Mon Jun 24 11:42:02 2019 -0500
  78. 197f14c Workaround for Neoverse N1 erratum 1220197 by lauwal01 · Mon Jun 24 11:38:53 2019 -0500
  79. e159044 Workaround for Neoverse N1 erratum 1207823 by lauwal01 · Mon Jun 24 11:35:37 2019 -0500
  80. f2adb13 Workaround for Neoverse N1 erratum 1165347 by lauwal01 · Mon Jun 24 11:32:40 2019 -0500
  81. 363ee3c Workaround for Neoverse N1 erratum 1130799 by lauwal01 · Mon Jun 24 11:28:34 2019 -0500
  82. bd555f4 Workaround for Neoverse N1 erratum 1073348 by lauwal01 · Mon Jun 24 11:23:50 2019 -0500
  83. b934740 Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703 by Andre Przywara · Mon May 20 14:57:06 2019 +0100
  84. db737bb Merge "Cortex-A55: workarounds for errata 1221012" into integration by Paul Beesley · Wed May 29 11:29:12 2019 +0000
  85. b72fe7a Cortex-A55: workarounds for errata 1221012 by Ambroise Vincent · Tue May 28 09:52:48 2019 +0100
  86. 90f2e88 Add support for Branch Target Identification by Alexei Fedorov · Fri May 24 12:17:09 2019 +0100
  87. 1d3ba1c Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112 by Soby Mathew · Wed May 01 09:43:18 2019 +0100
  88. b58142b Neoverse N1: Forces cacheable atomic to near by Louis Mayencourt · Thu Apr 18 14:34:11 2019 +0100
  89. 4498b15 DSU: Implement workaround for errata 798953 by Louis Mayencourt · Tue Apr 09 16:29:01 2019 +0100
  90. 254f6f0 DSU: Small fix and reformat on errata framework by Louis Mayencourt · Tue Apr 09 14:11:06 2019 +0100
  91. 8a06127 Cortex-A35: Implement workaround for errata 855472 by Louis Mayencourt · Fri Apr 05 16:25:25 2019 +0100
  92. 1601a15 Merge "cpus: Fix Cortex-A12 MIDR mask" into integration by Antonio Niño Díaz · Tue Apr 09 10:50:52 2019 +0000
  93. 4800943 Add support for Cortex-A76AE CPU by Alexei Fedorov · Thu Apr 04 16:26:34 2019 +0100
  94. 68a8d2b cpus: Fix Cortex-A12 MIDR mask by Heiko Stuebner · Fri Apr 05 14:44:33 2019 +0200
  95. 987c20a Merge pull request #1894 from jts-arm/e1_midr by Soby Mathew · Mon Mar 18 16:15:12 2019 +0000
  96. a5447ec Fix wrong MIDR_EL1 value for Neoverse E1 by John Tsichritzis · Fri Mar 15 15:40:27 2019 +0000
  97. 6deaf9c Introduce preliminary support for Neoverse Zeus by John Tsichritzis · Mon Oct 08 17:09:43 2018 +0100
  98. 8cf9eef Cortex-A17: Implement workaround for errata 852421 by Ambroise Vincent · Thu Feb 28 16:23:53 2019 +0000
  99. 68b3812 Cortex-A15: Implement workaround for errata 827671 by Ambroise Vincent · Tue Mar 05 09:54:21 2019 +0000
  100. fb6f2fc Merge pull request #1751 from vwadekar/tegra-scatter-file-support by Antonio Niño Díaz · Fri Mar 01 11:23:58 2019 +0000