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git01.mediatek.com / filogic / atf / 42771afa7b2f9d63515b3b0a723fbfc8d5b7b1f7 / include / lib / cpus
  1. 42771af Workaround for Neoverse N1 erratum 1262606 by lauwal01 · Mon Jun 24 11:44:58 2019 -0500
  2. 07c2a23 Workaround for Neoverse N1 erratum 1257314 by lauwal01 · Mon Jun 24 11:42:02 2019 -0500
  3. 197f14c Workaround for Neoverse N1 erratum 1220197 by lauwal01 · Mon Jun 24 11:38:53 2019 -0500
  4. e159044 Workaround for Neoverse N1 erratum 1207823 by lauwal01 · Mon Jun 24 11:35:37 2019 -0500
  5. f2adb13 Workaround for Neoverse N1 erratum 1165347 by lauwal01 · Mon Jun 24 11:32:40 2019 -0500
  6. 363ee3c Workaround for Neoverse N1 erratum 1130799 by lauwal01 · Mon Jun 24 11:28:34 2019 -0500
  7. bd555f4 Workaround for Neoverse N1 erratum 1073348 by lauwal01 · Mon Jun 24 11:23:50 2019 -0500
  8. b934740 Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703 by Andre Przywara · Mon May 20 14:57:06 2019 +0100
  9. b72fe7a Cortex-A55: workarounds for errata 1221012 by Ambroise Vincent · Tue May 28 09:52:48 2019 +0100
  10. 1d3ba1c Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112 by Soby Mathew · Wed May 01 09:43:18 2019 +0100
  11. b58142b Neoverse N1: Forces cacheable atomic to near by Louis Mayencourt · Thu Apr 18 14:34:11 2019 +0100
  12. 4498b15 DSU: Implement workaround for errata 798953 by Louis Mayencourt · Tue Apr 09 16:29:01 2019 +0100
  13. 254f6f0 DSU: Small fix and reformat on errata framework by Louis Mayencourt · Tue Apr 09 14:11:06 2019 +0100
  14. 8a06127 Cortex-A35: Implement workaround for errata 855472 by Louis Mayencourt · Fri Apr 05 16:25:25 2019 +0100
  15. 1601a15 Merge "cpus: Fix Cortex-A12 MIDR mask" into integration by Antonio Niño Díaz · Tue Apr 09 10:50:52 2019 +0000
  16. 4800943 Add support for Cortex-A76AE CPU by Alexei Fedorov · Thu Apr 04 16:26:34 2019 +0100
  17. 68a8d2b cpus: Fix Cortex-A12 MIDR mask by Heiko Stuebner · Fri Apr 05 14:44:33 2019 +0200
  18. 987c20a Merge pull request #1894 from jts-arm/e1_midr by Soby Mathew · Mon Mar 18 16:15:12 2019 +0000
  19. a5447ec Fix wrong MIDR_EL1 value for Neoverse E1 by John Tsichritzis · Fri Mar 15 15:40:27 2019 +0000
  20. 6deaf9c Introduce preliminary support for Neoverse Zeus by John Tsichritzis · Mon Oct 08 17:09:43 2018 +0100
  21. 8cf9eef Cortex-A17: Implement workaround for errata 852421 by Ambroise Vincent · Thu Feb 28 16:23:53 2019 +0000
  22. 68b3812 Cortex-A15: Implement workaround for errata 827671 by Ambroise Vincent · Tue Mar 05 09:54:21 2019 +0000
  23. cd5a55e Merge pull request #1849 from loumay-arm/lm/a73_errata by Antonio Niño Díaz · Fri Mar 01 11:23:48 2019 +0000
  24. f6505a7 Merge pull request #1845 from ambroise-arm/av/errata by Antonio Niño Díaz · Fri Mar 01 09:17:27 2019 +0000
  25. d69722c Cortex-A73: Implement workaround for errata 852427 by Louis Mayencourt · Wed Feb 27 14:24:16 2019 +0000
  26. 1b0db76 Cortex-A57: Implement workaround for erratum 814670 by Ambroise Vincent · Thu Feb 21 16:35:07 2019 +0000
  27. 6a77f05 Cortex-A55: Implement workaround for erratum 798797 by Ambroise Vincent · Thu Feb 21 16:27:34 2019 +0000
  28. 6f31960 Cortex-A55: Implement workaround for erratum 778703 by Ambroise Vincent · Thu Feb 21 16:25:37 2019 +0000
  29. 7927fa0 Cortex-A55: Implement workaround for erratum 768277 by Ambroise Vincent · Thu Feb 21 16:20:43 2019 +0000
  30. 59fa218 Add workaround for errata 1073348 for Cortex-A76 by Louis Mayencourt · Mon Feb 25 15:17:44 2019 +0000
  31. adda9d4 Add workaround for errata 1220197 for Cortex-A76 by Louis Mayencourt · Mon Feb 25 11:37:38 2019 +0000
  32. 4405de6 Add workaround for errata 855423 of Cortex-A73 by Louis Mayencourt · Thu Feb 21 16:38:16 2019 +0000
  33. 947fea0 Merge pull request #1835 from jts-arm/rename by Antonio Niño Díaz · Fri Feb 22 13:05:37 2019 +0000
  34. 16e6d9f Rename Cortex-Helios to Neoverse E1 by John Tsichritzis · Tue Feb 19 14:01:55 2019 +0000
  35. 3d417ac Rename Cortex-Helios filenames to Neoverse E1 by John Tsichritzis · Tue Feb 19 13:54:21 2019 +0000
  36. 56369c1 Rename Cortex-Ares to Neoverse N1 by John Tsichritzis · Tue Feb 19 13:49:06 2019 +0000
  37. 97ff6d0 Rename Cortex-Ares filenames to Neoverse N1 by John Tsichritzis · Tue Feb 19 13:48:44 2019 +0000
  38. a904487 Update macro to check need for CVE-2017-5715 mitigation by Antonio Nino Diaz · Tue Feb 12 11:25:02 2019 +0000
  39. 5e79cfe cpus: Add casts to all definitions in CPU headers by Antonio Nino Diaz · Mon Feb 11 13:34:15 2019 +0000
  40. 96f1631 cpus: Fix some incorrect definitions in CPU headers by Antonio Nino Diaz · Mon Feb 11 13:34:54 2019 +0000
  41. e0f9063 Sanitise includes across codebase by Antonio Nino Diaz · Fri Dec 14 00:18:21 2018 +0000
  42. 5eb8837 Standardise header guards across codebase by Antonio Nino Diaz · Thu Nov 08 10:20:19 2018 +0000
  43. 9fe40fd Fix MISRA defects in workaround and errata framework by Antonio Nino Diaz · Thu Oct 25 17:11:02 2018 +0100
  44. 033b4bb Fix MISRA defects in extension libs by Antonio Nino Diaz · Thu Oct 25 16:52:26 2018 +0100
  45. 0980dce Make errata reporting mandatory for CPU files by Soby Mathew · Mon Sep 17 04:34:35 2018 +0100
  46. b561536 plat/arm: relocate the jump_if_cpu_midr macro. by Deepak Pandey · Thu Oct 11 13:44:43 2018 +0530
  47. dc9fab1 Remove all other deprecated interfaces and files by Antonio Nino Diaz · Tue Sep 25 09:39:51 2018 +0100
  48. cd38e6e cpus: denver: Implement static workaround for CVE-2018-3639 by Varun Wadekar · Tue Aug 28 09:11:30 2018 -0700
  49. 2b91412 cpus: denver: reset power state to 'C1' on boot by Varun Wadekar · Mon Jun 25 11:36:47 2018 -0700
  50. 4daa1de DSU erratum 936184 workaround by John Tsichritzis · Mon Jul 23 09:11:59 2018 +0100
  51. f7f6041 Merge pull request #1450 from MISL-EBU-System-SW/marvell-support-v6 by danh-arm · Thu Jul 19 17:11:32 2018 +0100
  52. 9eb5cf4 lib: cpu: Add L2 cache aux control register definition to CA72 by Konstantin Porotchkin · Thu Jul 05 11:28:02 2018 +0300
  53. a7c4687 Add initial CPU support for Cortex-Helios by Joel Hutton · Wed Jan 10 16:06:07 2018 +0000
  54. 9463cae Add initial CPU support for Cortex-Deimos by Joel Hutton · Fri May 04 15:09:47 2018 +0100
  55. 26b8589 Remove integrity check in declare_cpu_ops_base by Roberto Vargas · Fri May 04 10:54:33 2018 +0100
  56. 67762d9 Remove .struct directive by Roberto Vargas · Tue May 01 09:54:54 2018 +0100
  57. 312e17e Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76 by Dimitris Papastamos · Wed May 16 09:59:54 2018 +0100
  58. 7ca21db Implement Cortex-Ares 1043202 erratum workaround by Dimitris Papastamos · Mon Mar 26 16:46:01 2018 +0100
  59. 89736dd Add AMU support for Cortex-Ares by Dimitris Papastamos · Tue Feb 13 11:28:02 2018 +0000
  60. ea84d6b Add support for Cortex-Ares and Cortex-A76 CPUs by Isla Mitchell · Thu Aug 03 16:04:46 2017 +0100
  61. ba51d9e Add support for dynamic mitigation for CVE-2018-3639 by Dimitris Papastamos · Wed May 16 11:36:14 2018 +0100
  62. 4a284a4 aarch32: Implement static workaround for CVE-2018-3639 by Dimitris Papastamos · Thu May 17 14:41:13 2018 +0100
  63. e6625ec Implement static workaround for CVE-2018-3639 by Dimitris Papastamos · Thu Apr 05 14:38:26 2018 +0100
  64. 570c06a Rename symbols and files relating to CVE-2017-5715 by Dimitris Papastamos · Fri Apr 06 15:29:34 2018 +0100
  65. efb1f33 Check presence of fix for errata 843419 in Cortex-A53 by Jonathan Wright · Wed Mar 28 15:52:03 2018 +0100
  66. 914757c Fixup `SMCCC_ARCH_FEATURES` semantics by Dimitris Papastamos · Mon Mar 12 14:47:09 2018 +0000
  67. 780cc95 Use PFR0 to identify need for mitigation of CVE-2017-5715 by Dimitris Papastamos · Mon Mar 12 13:27:02 2018 +0000
  68. b8d8145 Merge pull request #1282 from robertovargas-arm/misra-changes by davidcunado-arm · Wed Feb 28 18:53:30 2018 +0000
  69. 0571270 Fix MISRA rule 8.4 in common code by Roberto Vargas · Mon Feb 12 12:36:17 2018 +0000
  70. 864364a MISRA fixes for Cortex A75 AMU implementation by Dimitris Papastamos · Tue Feb 27 10:55:39 2018 +0000
  71. 1be747f Refactor AMU support for Cortex A75 by Dimitris Papastamos · Wed Feb 14 10:28:36 2018 +0000
  72. 0b00f8a Factor out CPU AMU helpers by Dimitris Papastamos · Wed Feb 14 10:00:06 2018 +0000
  73. 04285cf Merge pull request #1228 from dp-arm/dp/cve_2017_5715 by davidcunado-arm · Thu Jan 25 00:06:50 2018 +0000
  74. b5d1f8e Merge pull request #1200 from robertovargas-arm/bl2-el3 by davidcunado-arm · Fri Jan 19 13:40:12 2018 +0000
  75. 8ca0af2 Workaround for CVE-2017-5715 for Cortex A9, A15 and A17 by Dimitris Papastamos · Wed Jan 03 10:48:59 2018 +0000
  76. e0e9946 bl2-el3: Add BL2_EL3 image by Roberto Vargas · Mon Oct 30 14:43:43 2017 +0000
  77. d7e2e9e Add hooks to save/restore AMU context for Cortex A75 by Dimitris Papastamos · Mon Dec 11 11:45:35 2017 +0000
  78. fcedb69 Implement support for the Activity Monitor Unit on Cortex A75 by Dimitris Papastamos · Mon Oct 16 11:40:10 2017 +0100
  79. 09d26a6 ARMv7: introduce Cortex-A12 by Etienne Carriere · Sun Nov 05 22:56:50 2017 +0100
  80. 010dd1f ARMv7: introduce Cortex-A17 by Etienne Carriere · Sun Nov 05 22:56:41 2017 +0100
  81. f2f7b91 ARMv7: introduce Cortex-A7 by Etienne Carriere · Sun Nov 05 22:56:34 2017 +0100
  82. 37f8cdc ARMv7: introduce Cortex-A5 by Etienne Carriere · Sun Nov 05 22:56:26 2017 +0100
  83. a1249e0 ARMv7: introduce Cortex-A9 by Etienne Carriere · Sun Nov 05 22:56:19 2017 +0100
  84. 4ece755 ARMv7: introduce Cortex-A15 by Etienne Carriere · Sun Nov 05 22:56:10 2017 +0100
  85. c3b4ca1 Cortex-A72: Implement workaround for erratum 859971 by Eleanor Bonnici · Wed Aug 02 18:33:41 2017 +0100
  86. 0c9bd27 Cortex-A57: Implement workaround for erratum 859972 by Eleanor Bonnici · Wed Aug 02 16:35:04 2017 +0100
  87. 41b61be CPU: Correct names of implementation-defined aux regs by Eleanor Bonnici · Wed Aug 09 16:42:40 2017 +0100
  88. b83e42b CPU: Make shifted constants unsigned by Eleanor Bonnici · Wed Aug 09 10:36:08 2017 +0100
  89. ac838c5 aarch32: Fix L2CTRL definition for Cortex A57 and A72 by Dimitris Papastamos · Tue Jun 13 12:33:39 2017 +0100
  90. 9c47a5a aarch32: Implement errata workarounds for Cortex A53 by Dimitris Papastamos · Mon Jun 05 13:37:25 2017 +0100
  91. c6a11f6 include: add U()/ULL() macros for constants by Varun Wadekar · Thu May 25 18:04:48 2017 -0700
  92. 1384a16 Unique names for defines in the CPU libraries by Varun Wadekar · Mon Jun 05 14:54:46 2017 -0700
  93. 805c2c7 Add support for Cortex-A75 and Cortex-A55 CPUs by David Wang · Wed Nov 09 16:29:02 2016 +0000
  94. 9326b90 Cortex-A53: add some bit definitions by Haojian Zhuang · Wed May 24 08:48:57 2017 +0800
  95. fa3cf0b Use SPDX license identifiers by dp-arm · Wed May 03 09:38:09 2017 +0100
  96. 7d99b6c Merge branch 'integration' into tf_issue_461 by Scott Branden · Sat Apr 29 08:36:12 2017 -0700
  97. bf404c0 Move defines in utils.h to utils_def.h to fix shared header compile issues by Scott Branden · Mon Apr 10 11:45:52 2017 -0700
  98. a9f776c AArch32: Add support for ARM Cortex-A53/57/72 MPCore Processor by Yatharth Kochar · Thu Nov 10 16:17:51 2016 +0000
  99. 00eefd9 Add workaround for ARM Cortex-A53 erratum 855873 by Andre Przywara · Thu Oct 06 16:54:53 2016 +0100
  100. 69ce101 Tegra: enable ECC/Parity protection for Cortex-A57 CPUs by Varun Wadekar · Thu May 12 13:43:33 2016 -0700