blob: 9051b7b7e59a6367b42cc0e79607f88ca57996cc [file] [log] [blame]
Usama Arifbec5afd2020-04-17 16:13:39 +01001/*
Usama Ariffdfd2502021-03-30 16:39:19 +01002 * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
Usama Arifbec5afd2020-04-17 16:13:39 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
9/ {
10 compatible = "arm,tc0";
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 aliases {
16 serial0 = &soc_uart0;
17 };
18
19 chosen {
Anders Dellien1509a272021-06-08 09:27:17 +010020 bootargs = "console=ttyAMA0 debug user_debug=31 earlycon=pl011,0x7ff80000 loglevel=9 androidboot.hardware=total_compute androidboot.boot_devices=1c050000.mmci ip=dhcp androidboot.selinux=permissive allow_mismatched_32bit_el0";
Nikos Nikoleris35800bd2021-01-21 13:50:25 +000021 stdout-path = "serial0:115200n8";
Usama Arifbec5afd2020-04-17 16:13:39 +010022 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu-map {
29 cluster0 {
30 core0 {
31 cpu = <&CPU0>;
32 };
33 core1 {
34 cpu = <&CPU1>;
35 };
36 core2 {
37 cpu = <&CPU2>;
38 };
39 core3 {
40 cpu = <&CPU3>;
41 };
Avinash Mehtaf68a0842020-10-28 16:43:28 +000042 core4 {
43 cpu = <&CPU4>;
44 };
45 core5 {
46 cpu = <&CPU5>;
47 };
48 core6 {
49 cpu = <&CPU6>;
50 };
51 core7 {
52 cpu = <&CPU7>;
53 };
Usama Arifbec5afd2020-04-17 16:13:39 +010054 };
55 };
56
Usama Arif57900782020-08-12 17:14:37 +010057 /*
58 * The timings below are just to demonstrate working cpuidle.
59 * These values may be inaccurate.
60 */
61 idle-states {
62 entry-method = "arm,psci";
63
64 CPU_SLEEP_0: cpu-sleep-0 {
65 compatible = "arm,idle-state";
66 arm,psci-suspend-param = <0x0010000>;
67 local-timer-stop;
68 entry-latency-us = <300>;
69 exit-latency-us = <1200>;
70 min-residency-us = <2000>;
71 };
72 CLUSTER_SLEEP_0: cluster-sleep-0 {
73 compatible = "arm,idle-state";
74 arm,psci-suspend-param = <0x1010000>;
75 local-timer-stop;
76 entry-latency-us = <400>;
77 exit-latency-us = <1200>;
78 min-residency-us = <2500>;
79 };
80 };
81
Usama Arifbec5afd2020-04-17 16:13:39 +010082 CPU0:cpu@0 {
83 device_type = "cpu";
84 compatible = "arm,armv8";
85 reg = <0x0>;
86 enable-method = "psci";
87 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +010088 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +010089 capacity-dmips-mhz = <406>;
Usama Arifbec5afd2020-04-17 16:13:39 +010090 };
91
92 CPU1:cpu@100 {
93 device_type = "cpu";
94 compatible = "arm,armv8";
95 reg = <0x100>;
96 enable-method = "psci";
97 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +010098 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +010099 capacity-dmips-mhz = <406>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100100 };
101
102 CPU2:cpu@200 {
103 device_type = "cpu";
104 compatible = "arm,armv8";
105 reg = <0x200>;
106 enable-method = "psci";
107 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100108 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100109 capacity-dmips-mhz = <406>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100110 };
111
112 CPU3:cpu@300 {
113 device_type = "cpu";
114 compatible = "arm,armv8";
115 reg = <0x300>;
116 enable-method = "psci";
117 clocks = <&scmi_dvfs 0>;
Usama Arif57900782020-08-12 17:14:37 +0100118 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100119 capacity-dmips-mhz = <406>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100120 };
121
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000122 CPU4:cpu@400 {
123 device_type = "cpu";
124 compatible = "arm,armv8";
125 reg = <0x400>;
126 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000127 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000128 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100129 capacity-dmips-mhz = <912>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000130 };
131
132 CPU5:cpu@500 {
133 device_type = "cpu";
134 compatible = "arm,armv8";
135 reg = <0x500>;
136 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000137 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000138 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100139 capacity-dmips-mhz = <912>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000140 };
141
142 CPU6:cpu@600 {
143 device_type = "cpu";
144 compatible = "arm,armv8";
145 reg = <0x600>;
146 enable-method = "psci";
Usama Arif75edb752021-02-03 15:40:46 +0000147 clocks = <&scmi_dvfs 1>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000148 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100149 capacity-dmips-mhz = <912>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000150 };
151
152 CPU7:cpu@700 {
153 device_type = "cpu";
154 compatible = "arm,armv8";
155 reg = <0x700>;
156 enable-method = "psci";
Usama Arif410d50d2021-04-07 11:48:22 +0100157 clocks = <&scmi_dvfs 2>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000158 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Usama Arifecbc8462021-06-14 12:38:37 +0100159 capacity-dmips-mhz = <1024>;
Avinash Mehtaf68a0842020-10-28 16:43:28 +0000160 };
161
Usama Arifbec5afd2020-04-17 16:13:39 +0100162 };
163
164 memory@80000000 {
165 device_type = "memory";
Arunachalam Ganapathy81da5582020-09-22 12:47:33 +0100166 reg = <0x0 0x80000000 0x0 0x7d000000>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100167 };
168
Arunachalam Ganapathy948bb442020-12-14 12:31:32 +0000169 reserved-memory {
170 #address-cells = <2>;
171 #size-cells = <2>;
172 ranges;
173
174 optee@0xfce00000 {
175 reg = <0x00000000 0xfce00000 0 0x00200000>;
176 no-map;
177 };
178 };
179
Usama Arifbec5afd2020-04-17 16:13:39 +0100180 psci {
Usama Arif7a64bfa2021-05-27 20:09:17 +0100181 compatible = "arm,psci-1.0", "arm,psci-0.2";
Usama Arifbec5afd2020-04-17 16:13:39 +0100182 method = "smc";
183 };
184
185 sram: sram@6000000 {
186 compatible = "mmio-sram";
187 reg = <0x0 0x06000000 0x0 0x8000>;
188
189 #address-cells = <1>;
190 #size-cells = <1>;
191 ranges = <0 0x0 0x06000000 0x8000>;
192
193 cpu_scp_scmi_mem: scp-shmem@0 {
194 compatible = "arm,scmi-shmem";
195 reg = <0x0 0x80>;
196 };
197 };
198
199 mbox_db_rx: mhu@45010000 {
Usama Arifb315c702021-05-27 20:01:39 +0100200 compatible = "arm,mhuv2-rx","arm,primecell";
Usama Arifbec5afd2020-04-17 16:13:39 +0100201 reg = <0x0 0x45010000 0x0 0x1000>;
202 clocks = <&soc_refclk100mhz>;
203 clock-names = "apb_pclk";
Usama Arifb315c702021-05-27 20:01:39 +0100204 #mbox-cells = <2>;
Usama Arif884f40d2020-08-18 12:56:44 +0100205 interrupts = <0 317 4>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100206 interrupt-names = "mhu_rx";
207 mhu-protocol = "doorbell";
Usama Arifb315c702021-05-27 20:01:39 +0100208 arm,mhuv2-protocols = <0 1>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100209 };
210
211 mbox_db_tx: mhu@45000000 {
Usama Arifb315c702021-05-27 20:01:39 +0100212 compatible = "arm,mhuv2-tx","arm,primecell";
Usama Arifbec5afd2020-04-17 16:13:39 +0100213 reg = <0x0 0x45000000 0x0 0x1000>;
214 clocks = <&soc_refclk100mhz>;
215 clock-names = "apb_pclk";
Usama Arifb315c702021-05-27 20:01:39 +0100216 #mbox-cells = <2>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100217 interrupt-names = "mhu_tx";
218 mhu-protocol = "doorbell";
Usama Arifb315c702021-05-27 20:01:39 +0100219 arm,mhuv2-protocols = <0 1>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100220 };
221
222 scmi {
223 compatible = "arm,scmi";
Usama Arifbec5afd2020-04-17 16:13:39 +0100224 mbox-names = "tx", "rx";
Usama Arifb315c702021-05-27 20:01:39 +0100225 mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
Usama Arifbec5afd2020-04-17 16:13:39 +0100226 shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
227 #address-cells = <1>;
228 #size-cells = <0>;
229
230 scmi_dvfs: protocol@13 {
231 reg = <0x13>;
232 #clock-cells = <1>;
233 };
234
235 scmi_clk: protocol@14 {
236 reg = <0x14>;
237 #clock-cells = <1>;
238 };
239 };
240
241 gic: interrupt-controller@2c010000 {
242 compatible = "arm,gic-600", "arm,gic-v3";
243 #address-cells = <2>;
244 #interrupt-cells = <3>;
245 #size-cells = <2>;
246 ranges;
247 interrupt-controller;
248 reg = <0x0 0x30000000 0 0x10000>, /* GICD */
Usama Ariffdfd2502021-03-30 16:39:19 +0100249 <0x0 0x30080000 0 0x200000>; /* GICR */
Usama Arifbec5afd2020-04-17 16:13:39 +0100250 interrupts = <0x1 0x9 0x4>;
251 };
252
253 timer {
254 compatible = "arm,armv8-timer";
255 interrupts = <0x1 13 0x8>,
256 <0x1 14 0x8>,
257 <0x1 11 0x8>,
258 <0x1 10 0x8>;
259 };
260
261 soc_refclk100mhz: refclk100mhz {
262 compatible = "fixed-clock";
263 #clock-cells = <0>;
264 clock-frequency = <100000000>;
265 clock-output-names = "apb_pclk";
266 };
267
268 soc_refclk60mhz: refclk60mhz {
269 compatible = "fixed-clock";
270 #clock-cells = <0>;
271 clock-frequency = <60000000>;
272 clock-output-names = "iofpga_clk";
273 };
274
275 soc_uartclk: uartclk {
276 compatible = "fixed-clock";
277 #clock-cells = <0>;
278 clock-frequency = <50000000>;
279 clock-output-names = "uartclk";
280 };
281
282 soc_uart0: uart@7ff80000 {
283 compatible = "arm,pl011", "arm,primecell";
284 reg = <0x0 0x7ff80000 0x0 0x1000>;
285 interrupts = <0x0 116 0x4>;
286 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
287 clock-names = "uartclk", "apb_pclk";
288 status = "okay";
289 };
290
291 vencoder {
292 compatible = "drm,virtual-encoder";
293
294 port {
295 vencoder_in: endpoint {
Avinash Mehtadf71a602020-07-22 16:40:07 +0100296 remote-endpoint = <&dp_pl0_out0>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100297 };
298 };
299
300 display-timings {
301 panel-timing {
302 clock-frequency = <25175000>;
303 hactive = <640>;
304 vactive = <480>;
305 hfront-porch = <16>;
306 hback-porch = <48>;
307 hsync-len = <96>;
308 vfront-porch = <10>;
309 vback-porch = <33>;
310 vsync-len = <2>;
311 };
312 };
313
314 };
315
316 hdlcd: hdlcd@7ff60000 {
317 compatible = "arm,hdlcd";
318 reg = <0x0 0x7ff60000 0x0 0x1000>;
319 interrupts = <0x0 117 0x4>;
320 clocks = <&fake_hdlcd_clk>;
321 clock-names = "pxlclk";
Avinash Mehtadf71a602020-07-22 16:40:07 +0100322 status = "disabled";
Usama Arifbec5afd2020-04-17 16:13:39 +0100323
324 port {
325 hdlcd_out: endpoint {
326 remote-endpoint = <&vencoder_in>;
327 };
328 };
329 };
330
331 fake_hdlcd_clk: fake-hdlcd-clk {
332 compatible = "fixed-clock";
333 #clock-cells = <0>;
334 clock-frequency = <25175000>;
335 clock-output-names = "pxlclk";
336 };
337
338 ethernet@18000000 {
339 compatible = "smsc,lan91c111";
340 reg = <0x0 0x18000000 0x0 0x10000>;
341 interrupts = <0 109 4>;
342 };
343
344 kmi@1c060000 {
345 compatible = "arm,pl050", "arm,primecell";
346 reg = <0x0 0x001c060000 0x0 0x1000>;
347 interrupts = <0 197 4>;
348 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
349 clock-names = "KMIREFCLK", "apb_pclk";
350 };
351
352 kmi@1c070000 {
353 compatible = "arm,pl050", "arm,primecell";
354 reg = <0x0 0x001c070000 0x0 0x1000>;
355 interrupts = <0 103 4>;
356 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
357 clock-names = "KMIREFCLK", "apb_pclk";
358 };
359
360 bp_clock24mhz: clock24mhz {
361 compatible = "fixed-clock";
362 #clock-cells = <0>;
363 clock-frequency = <24000000>;
364 clock-output-names = "bp:clock24mhz";
365 };
366
367 virtio_block@1c130000 {
368 compatible = "virtio,mmio";
369 reg = <0x0 0x1c130000 0x0 0x200>;
370 interrupts = <0 204 4>;
371 };
372
Usama Arif1cd56dc2020-06-10 16:27:53 +0100373 sysreg: sysreg@1c010000 {
374 compatible = "arm,vexpress-sysreg";
375 reg = <0x0 0x001c010000 0x0 0x1000>;
376 gpio-controller;
377 #gpio-cells = <2>;
378 };
379
380 fixed_3v3: v2m-3v3 {
381 compatible = "regulator-fixed";
382 regulator-name = "3V3";
383 regulator-min-microvolt = <3300000>;
384 regulator-max-microvolt = <3300000>;
385 regulator-always-on;
386 };
387
388 mmci@1c050000 {
389 compatible = "arm,pl180", "arm,primecell";
390 reg = <0x0 0x001c050000 0x0 0x1000>;
391 interrupts = <0 107 0x4>,
392 <0 108 0x4>;
393 cd-gpios = <&sysreg 0 0>;
394 wp-gpios = <&sysreg 1 0>;
395 bus-width = <8>;
396 max-frequency = <12000000>;
397 vmmc-supply = <&fixed_3v3>;
398 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
399 clock-names = "mclk", "apb_pclk";
400 };
401
Usama Arifbec5afd2020-04-17 16:13:39 +0100402 dp0: display@2cc00000 {
403 #address-cells = <1>;
404 #size-cells = <0>;
405 compatible = "arm,mali-d71";
406 reg = <0 0x2cc00000 0 0x20000>;
407 interrupts = <0 69 4>;
408 interrupt-names = "DPU";
409 clocks = <&scmi_clk 0>;
410 clock-names = "aclk";
Usama Arifbec5afd2020-04-17 16:13:39 +0100411 pl0: pipeline@0 {
412 reg = <0>;
413 clocks = <&scmi_clk 1>;
414 clock-names = "pxclk";
415 pl_id = <0>;
416 ports {
417 #address-cells = <1>;
418 #size-cells = <0>;
419 port@0 {
420 reg = <0>;
421 dp_pl0_out0: endpoint {
422 remote-endpoint = <&vencoder_in>;
423 };
424 };
425 };
426 };
427
428 pl1: pipeline@1 {
429 reg = <1>;
430 clocks = <&scmi_clk 2>;
431 clock-names = "pxclk";
432 pl_id = <1>;
433 ports {
434 #address-cells = <1>;
435 #size-cells = <0>;
436 port@0 {
437 reg = <0>;
438 };
439 };
440 };
441 };
Arunachalam Ganapathyc44e43d2020-11-17 15:05:01 +0000442
Usama Arifbec5afd2020-04-17 16:13:39 +0100443};