blob: b1205d43529dda27ae6390088ea4bbaa6f62e873 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010032#include <assert.h>
33#include <bl_common.h>
Sandrine Bailleuxe3060e22014-06-13 14:48:18 +010034#include <debug.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010035#include <console.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010036#include <mmio.h>
37#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010038#include <platform_def.h>
Sandrine Bailleux467d0572014-06-24 14:02:34 +010039#include "../../bl1/bl1_private.h"
Dan Handleyed6ff952014-05-14 17:44:19 +010040#include "fvp_def.h"
41#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010042
43/*******************************************************************************
44 * Declarations of linker defined symbols which will help us find the layout
45 * of trusted SRAM
46 ******************************************************************************/
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000047extern unsigned long __COHERENT_RAM_START__;
48extern unsigned long __COHERENT_RAM_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010049
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000050/*
51 * The next 2 constants identify the extents of the coherent memory region.
52 * These addresses are used by the MMU setup code and therefore they must be
53 * page-aligned. It is the responsibility of the linker script to ensure that
54 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
55 * page-aligned addresses.
56 */
57#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
58#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
Achin Gupta4f6ad662013-10-25 09:08:21 +010059
Achin Gupta4f6ad662013-10-25 09:08:21 +010060/* Data structure which holds the extents of the trusted SRAM for BL1*/
Dan Handleye2712bc2014-04-10 15:37:22 +010061static meminfo_t bl1_tzram_layout;
Achin Gupta4f6ad662013-10-25 09:08:21 +010062
Dan Handleye2712bc2014-04-10 15:37:22 +010063meminfo_t *bl1_plat_sec_mem_layout(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +010064{
Sandrine Bailleuxee12f6f2013-11-28 14:55:58 +000065 return &bl1_tzram_layout;
Achin Gupta4f6ad662013-10-25 09:08:21 +010066}
67
68/*******************************************************************************
69 * Perform any BL1 specific platform actions.
70 ******************************************************************************/
71void bl1_early_platform_setup(void)
72{
Sandrine Bailleuxe3060e22014-06-13 14:48:18 +010073 const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
Achin Gupta4f6ad662013-10-25 09:08:21 +010074
Vikram Kanigiri3684abf2014-03-27 14:33:15 +000075 /* Initialize the console to provide early debug support */
Soby Mathew69817f72014-07-14 15:43:21 +010076 console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
Vikram Kanigiri3684abf2014-03-27 14:33:15 +000077
Sandrine Bailleuxe3060e22014-06-13 14:48:18 +010078 /* Allow BL1 to see the whole Trusted RAM */
Juan Castillo0c70c572014-08-12 13:04:43 +010079 bl1_tzram_layout.total_base = FVP_TRUSTED_SRAM_BASE;
80 bl1_tzram_layout.total_size = FVP_TRUSTED_SRAM_SIZE;
Achin Gupta4f6ad662013-10-25 09:08:21 +010081
Sandrine Bailleuxe3060e22014-06-13 14:48:18 +010082 /* Calculate how much RAM BL1 is using and how much remains free */
Juan Castillo0c70c572014-08-12 13:04:43 +010083 bl1_tzram_layout.free_base = FVP_TRUSTED_SRAM_BASE;
84 bl1_tzram_layout.free_size = FVP_TRUSTED_SRAM_SIZE;
Sandrine Bailleuxe3060e22014-06-13 14:48:18 +010085 reserve_mem(&bl1_tzram_layout.free_base,
86 &bl1_tzram_layout.free_size,
87 BL1_RAM_BASE,
88 bl1_size);
89
Harry Liebel30affd52013-10-30 17:41:48 +000090 /* Initialize the platform config for future decision making */
Dan Handleyea451572014-05-15 14:53:30 +010091 fvp_config_setup();
Achin Gupta4f6ad662013-10-25 09:08:21 +010092}
93
94/*******************************************************************************
95 * Function which will evaluate how much of the trusted ram has been gobbled
96 * up by BL1 and return the base and size of whats available for loading BL2.
97 * Its called after coherency and the MMU have been turned on.
98 ******************************************************************************/
99void bl1_platform_setup(void)
100{
James Morrissey9d72b4e2014-02-10 17:04:32 +0000101 /* Initialise the IO layer and register platform IO devices */
Dan Handleyea451572014-05-15 14:53:30 +0100102 fvp_io_setup();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100103}
104
James Morrissey9d72b4e2014-02-10 17:04:32 +0000105
Achin Gupta4f6ad662013-10-25 09:08:21 +0100106/*******************************************************************************
107 * Perform the very early platform specific architecture setup here. At the
Harry Liebel30affd52013-10-30 17:41:48 +0000108 * moment this only does basic initialization. Later architectural setup
109 * (bl1_arch_setup()) does not do anything platform specific.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100110 ******************************************************************************/
111void bl1_plat_arch_setup(void)
112{
Dan Handleybe234f92014-08-04 16:11:15 +0100113 fvp_cci_init();
114 fvp_cci_enable();
Harry Liebel30affd52013-10-30 17:41:48 +0000115
Dan Handleyea451572014-05-15 14:53:30 +0100116 fvp_configure_mmu_el3(bl1_tzram_layout.total_base,
117 bl1_tzram_layout.total_size,
Juan Castillo0c70c572014-08-12 13:04:43 +0100118 BL1_RO_BASE,
119 BL1_RO_LIMIT,
Dan Handleyea451572014-05-15 14:53:30 +0100120 BL1_COHERENT_RAM_BASE,
121 BL1_COHERENT_RAM_LIMIT);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100122}
Vikram Kanigirida567432014-04-15 18:08:08 +0100123
124
125/*******************************************************************************
126 * Before calling this function BL2 is loaded in memory and its entrypoint
127 * is set by load_image. This is a placeholder for the platform to change
128 * the entrypoint of BL2 and set SPSR and security state.
129 * On FVP we are only setting the security state, entrypoint
130 ******************************************************************************/
131void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image,
132 entry_point_info_t *bl2_ep)
133{
134 SET_SECURITY_STATE(bl2_ep->h.attr, SECURE);
135 bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
136}