Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013, ARM Limited. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <string.h> |
| 32 | #include <assert.h> |
| 33 | #include <arch_helpers.h> |
| 34 | #include <platform.h> |
| 35 | #include <bl1.h> |
| 36 | #include <console.h> |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame^] | 37 | #include <cci400.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 38 | |
| 39 | /******************************************************************************* |
| 40 | * Declarations of linker defined symbols which will help us find the layout |
| 41 | * of trusted SRAM |
| 42 | ******************************************************************************/ |
| 43 | #if defined (__GNUC__) |
| 44 | extern unsigned long __FIRMWARE_ROM_START__; |
| 45 | extern unsigned long __FIRMWARE_ROM_SIZE__; |
| 46 | extern unsigned long __FIRMWARE_DATA_START__; |
| 47 | extern unsigned long __FIRMWARE_DATA_SIZE__; |
| 48 | extern unsigned long __FIRMWARE_BSS_START__; |
| 49 | extern unsigned long __FIRMWARE_BSS_SIZE__; |
| 50 | extern unsigned long __DATA_RAM_START__; |
| 51 | extern unsigned long __DATA_RAM_SIZE__; |
| 52 | extern unsigned long __BSS_RAM_START__; |
| 53 | extern unsigned long __BSS_RAM_SIZE__; |
| 54 | extern unsigned long __FIRMWARE_RAM_STACKS_START__; |
| 55 | extern unsigned long __FIRMWARE_RAM_STACKS_SIZE__; |
| 56 | extern unsigned long __FIRMWARE_RAM_PAGETABLES_START__; |
| 57 | extern unsigned long __FIRMWARE_RAM_PAGETABLES_SIZE__; |
| 58 | extern unsigned long __FIRMWARE_RAM_COHERENT_START__; |
| 59 | extern unsigned long __FIRMWARE_RAM_COHERENT_SIZE__; |
| 60 | |
| 61 | #define BL1_COHERENT_MEM_BASE (&__FIRMWARE_RAM_COHERENT_START__) |
| 62 | #define BL1_COHERENT_MEM_LIMIT \ |
| 63 | ((unsigned long long)&__FIRMWARE_RAM_COHERENT_START__ + \ |
| 64 | (unsigned long long)&__FIRMWARE_RAM_COHERENT_SIZE__) |
| 65 | |
| 66 | #define BL1_FIRMWARE_RAM_GLOBALS_ZI_BASE \ |
| 67 | (unsigned long)(&__BSS_RAM_START__) |
| 68 | #define BL1_FIRMWARE_RAM_GLOBALS_ZI_LENGTH \ |
| 69 | (unsigned long)(&__FIRMWARE_BSS_SIZE__) |
| 70 | |
| 71 | #define BL1_FIRMWARE_RAM_COHERENT_ZI_BASE \ |
| 72 | (unsigned long)(&__FIRMWARE_RAM_COHERENT_START__) |
| 73 | #define BL1_FIRMWARE_RAM_COHERENT_ZI_LENGTH\ |
| 74 | (unsigned long)(&__FIRMWARE_RAM_COHERENT_SIZE__) |
| 75 | |
| 76 | #define BL1_NORMAL_RAM_BASE (unsigned long)(&__BSS_RAM_START__) |
| 77 | #define BL1_NORMAL_RAM_LIMIT \ |
| 78 | ((unsigned long)&__FIRMWARE_RAM_COHERENT_START__ + \ |
| 79 | (unsigned long)&__FIRMWARE_RAM_COHERENT_SIZE__) |
| 80 | #else |
| 81 | #error "Unknown compiler." |
| 82 | #endif |
| 83 | |
| 84 | |
| 85 | /* Data structure which holds the extents of the trusted SRAM for BL1*/ |
| 86 | static meminfo bl1_tzram_layout = {0}; |
| 87 | |
| 88 | meminfo bl1_get_sec_mem_layout(void) |
| 89 | { |
| 90 | return bl1_tzram_layout; |
| 91 | } |
| 92 | |
| 93 | /******************************************************************************* |
| 94 | * Perform any BL1 specific platform actions. |
| 95 | ******************************************************************************/ |
| 96 | void bl1_early_platform_setup(void) |
| 97 | { |
| 98 | unsigned long bl1_normal_ram_base; |
| 99 | unsigned long bl1_coherent_ram_limit; |
| 100 | unsigned long tzram_limit = TZRAM_BASE + TZRAM_SIZE; |
| 101 | |
| 102 | /* |
| 103 | * Initialize extents of the bl1 sections as per the platform |
| 104 | * defined values. |
| 105 | */ |
| 106 | bl1_normal_ram_base = BL1_NORMAL_RAM_BASE; |
| 107 | bl1_coherent_ram_limit = BL1_NORMAL_RAM_LIMIT; |
| 108 | |
| 109 | /* |
| 110 | * Calculate how much ram is BL1 using & how much remains free. |
| 111 | * This also includes a rudimentary mechanism to detect whether |
| 112 | * the BL1 data is loaded at the top or bottom of memory. |
| 113 | * TODO: add support for discontigous chunks of free ram if |
| 114 | * needed. Might need dynamic memory allocation support |
| 115 | * et al. |
| 116 | * Also assuming that the section for coherent memory is |
| 117 | * the last and for globals the first in the scatter file. |
| 118 | */ |
| 119 | bl1_tzram_layout.total_base = TZRAM_BASE; |
| 120 | bl1_tzram_layout.total_size = TZRAM_SIZE; |
| 121 | |
| 122 | if (bl1_coherent_ram_limit == tzram_limit) { |
| 123 | bl1_tzram_layout.free_base = TZRAM_BASE; |
| 124 | bl1_tzram_layout.free_size = bl1_normal_ram_base - TZRAM_BASE; |
| 125 | } else { |
| 126 | bl1_tzram_layout.free_base = bl1_coherent_ram_limit; |
| 127 | bl1_tzram_layout.free_size = |
| 128 | tzram_limit - bl1_coherent_ram_limit; |
| 129 | } |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame^] | 130 | |
| 131 | /* Initialize the platform config for future decision making */ |
| 132 | platform_config_setup(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 133 | } |
| 134 | |
| 135 | /******************************************************************************* |
| 136 | * Function which will evaluate how much of the trusted ram has been gobbled |
| 137 | * up by BL1 and return the base and size of whats available for loading BL2. |
| 138 | * Its called after coherency and the MMU have been turned on. |
| 139 | ******************************************************************************/ |
| 140 | void bl1_platform_setup(void) |
| 141 | { |
| 142 | /* |
| 143 | * This should zero out our coherent stacks as well but we don't care |
| 144 | * as they are not being used right now. |
| 145 | */ |
| 146 | memset((void *) BL1_FIRMWARE_RAM_COHERENT_ZI_BASE, 0, |
| 147 | (size_t) BL1_FIRMWARE_RAM_COHERENT_ZI_LENGTH); |
| 148 | |
| 149 | /* Enable and initialize the System level generic timer */ |
| 150 | mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_EN); |
| 151 | |
| 152 | /* Initialize the console */ |
| 153 | console_init(); |
| 154 | |
| 155 | return; |
| 156 | } |
| 157 | |
| 158 | /******************************************************************************* |
| 159 | * Perform the very early platform specific architecture setup here. At the |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame^] | 160 | * moment this only does basic initialization. Later architectural setup |
| 161 | * (bl1_arch_setup()) does not do anything platform specific. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 162 | ******************************************************************************/ |
| 163 | void bl1_plat_arch_setup(void) |
| 164 | { |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame^] | 165 | unsigned long cci_setup; |
| 166 | |
| 167 | /* |
| 168 | * Enable CCI-400 for this cluster. No need |
| 169 | * for locks as no other cpu is active at the |
| 170 | * moment |
| 171 | */ |
| 172 | cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI); |
| 173 | if (cci_setup) { |
| 174 | cci_enable_coherency(read_mpidr()); |
| 175 | } |
| 176 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 177 | configure_mmu(&bl1_tzram_layout, |
| 178 | TZROM_BASE, /* Read_only region start */ |
| 179 | TZROM_BASE + TZROM_SIZE, /* Read_only region size */ |
| 180 | /* Coherent region start */ |
| 181 | BL1_FIRMWARE_RAM_COHERENT_ZI_BASE, |
| 182 | /* Coherent region size */ |
| 183 | BL1_FIRMWARE_RAM_COHERENT_ZI_BASE + |
| 184 | BL1_FIRMWARE_RAM_COHERENT_ZI_LENGTH); |
| 185 | } |