Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / 4f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a56 / . / plat / fvp / bl1_plat_setup.c
blob: 7131f7a484df2cbf1034213727ccb86774d5349e [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame^]1/*
2 * Copyright (c) 2013, ARM Limited. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <string.h>
32#include <assert.h>
33#include <arch_helpers.h>
34#include <platform.h>
35#include <bl1.h>
36#include <console.h>
37
38/*******************************************************************************
39 * Declarations of linker defined symbols which will help us find the layout
40 * of trusted SRAM
41 ******************************************************************************/
42#if defined (__GNUC__)
43extern unsigned long __FIRMWARE_ROM_START__;
44extern unsigned long __FIRMWARE_ROM_SIZE__;
45extern unsigned long __FIRMWARE_DATA_START__;
46extern unsigned long __FIRMWARE_DATA_SIZE__;
47extern unsigned long __FIRMWARE_BSS_START__;
48extern unsigned long __FIRMWARE_BSS_SIZE__;
49extern unsigned long __DATA_RAM_START__;
50extern unsigned long __DATA_RAM_SIZE__;
51extern unsigned long __BSS_RAM_START__;
52extern unsigned long __BSS_RAM_SIZE__;
53extern unsigned long __FIRMWARE_RAM_STACKS_START__;
54extern unsigned long __FIRMWARE_RAM_STACKS_SIZE__;
55extern unsigned long __FIRMWARE_RAM_PAGETABLES_START__;
56extern unsigned long __FIRMWARE_RAM_PAGETABLES_SIZE__;
57extern unsigned long __FIRMWARE_RAM_COHERENT_START__;
58extern unsigned long __FIRMWARE_RAM_COHERENT_SIZE__;
59
60#define BL1_COHERENT_MEM_BASE (&__FIRMWARE_RAM_COHERENT_START__)
61#define BL1_COHERENT_MEM_LIMIT \
62 ((unsigned long long)&__FIRMWARE_RAM_COHERENT_START__ + \
63 (unsigned long long)&__FIRMWARE_RAM_COHERENT_SIZE__)
64
65#define BL1_FIRMWARE_RAM_GLOBALS_ZI_BASE \
66 (unsigned long)(&__BSS_RAM_START__)
67#define BL1_FIRMWARE_RAM_GLOBALS_ZI_LENGTH \
68 (unsigned long)(&__FIRMWARE_BSS_SIZE__)
69
70#define BL1_FIRMWARE_RAM_COHERENT_ZI_BASE \
71 (unsigned long)(&__FIRMWARE_RAM_COHERENT_START__)
72#define BL1_FIRMWARE_RAM_COHERENT_ZI_LENGTH\
73 (unsigned long)(&__FIRMWARE_RAM_COHERENT_SIZE__)
74
75#define BL1_NORMAL_RAM_BASE (unsigned long)(&__BSS_RAM_START__)
76#define BL1_NORMAL_RAM_LIMIT \
77 ((unsigned long)&__FIRMWARE_RAM_COHERENT_START__ + \
78 (unsigned long)&__FIRMWARE_RAM_COHERENT_SIZE__)
79#else
80 #error "Unknown compiler."
81#endif
82
83
84/* Data structure which holds the extents of the trusted SRAM for BL1*/
85static meminfo bl1_tzram_layout = {0};
86
87meminfo bl1_get_sec_mem_layout(void)
88{
89 return bl1_tzram_layout;
90}
91
92/*******************************************************************************
93 * Perform any BL1 specific platform actions.
94 ******************************************************************************/
95void bl1_early_platform_setup(void)
96{
97 unsigned long bl1_normal_ram_base;
98 unsigned long bl1_coherent_ram_limit;
99 unsigned long tzram_limit = TZRAM_BASE + TZRAM_SIZE;
100
101 /*
102 * Initialize extents of the bl1 sections as per the platform
103 * defined values.
104 */
105 bl1_normal_ram_base = BL1_NORMAL_RAM_BASE;
106 bl1_coherent_ram_limit = BL1_NORMAL_RAM_LIMIT;
107
108 /*
109 * Calculate how much ram is BL1 using & how much remains free.
110 * This also includes a rudimentary mechanism to detect whether
111 * the BL1 data is loaded at the top or bottom of memory.
112 * TODO: add support for discontigous chunks of free ram if
113 * needed. Might need dynamic memory allocation support
114 * et al.
115 * Also assuming that the section for coherent memory is
116 * the last and for globals the first in the scatter file.
117 */
118 bl1_tzram_layout.total_base = TZRAM_BASE;
119 bl1_tzram_layout.total_size = TZRAM_SIZE;
120
121 if (bl1_coherent_ram_limit == tzram_limit) {
122 bl1_tzram_layout.free_base = TZRAM_BASE;
123 bl1_tzram_layout.free_size = bl1_normal_ram_base - TZRAM_BASE;
124 } else {
125 bl1_tzram_layout.free_base = bl1_coherent_ram_limit;
126 bl1_tzram_layout.free_size =
127 tzram_limit - bl1_coherent_ram_limit;
128 }
129}
130
131/*******************************************************************************
132 * Function which will evaluate how much of the trusted ram has been gobbled
133 * up by BL1 and return the base and size of whats available for loading BL2.
134 * Its called after coherency and the MMU have been turned on.
135 ******************************************************************************/
136void bl1_platform_setup(void)
137{
138 /*
139 * This should zero out our coherent stacks as well but we don't care
140 * as they are not being used right now.
141 */
142 memset((void *) BL1_FIRMWARE_RAM_COHERENT_ZI_BASE, 0,
143 (size_t) BL1_FIRMWARE_RAM_COHERENT_ZI_LENGTH);
144
145 /* Enable and initialize the System level generic timer */
146 mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_EN);
147
148 /* Initialize the console */
149 console_init();
150
151 return;
152}
153
154/*******************************************************************************
155 * Perform the very early platform specific architecture setup here. At the
156 * moment this is only intializes the mmu in a quick and dirty way. Later arch-
157 * itectural setup (bl1_arch_setup()) does not do anything platform specific.
158 ******************************************************************************/
159void bl1_plat_arch_setup(void)
160{
161 configure_mmu(&bl1_tzram_layout,
162 TZROM_BASE, /* Read_only region start */
163 TZROM_BASE + TZROM_SIZE, /* Read_only region size */
164 /* Coherent region start */
165 BL1_FIRMWARE_RAM_COHERENT_ZI_BASE,
166 /* Coherent region size */
167 BL1_FIRMWARE_RAM_COHERENT_ZI_BASE +
168 BL1_FIRMWARE_RAM_COHERENT_ZI_LENGTH);
169}