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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010032#include <assert.h>
33#include <bl_common.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010034#include <bl1.h>
35#include <console.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010036#include <mmio.h>
37#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010038#include <platform_def.h>
39#include "fvp_def.h"
40#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010041
42/*******************************************************************************
43 * Declarations of linker defined symbols which will help us find the layout
44 * of trusted SRAM
45 ******************************************************************************/
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000046extern unsigned long __COHERENT_RAM_START__;
47extern unsigned long __COHERENT_RAM_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010048
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000049extern unsigned long __BL1_RAM_START__;
50extern unsigned long __BL1_RAM_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010051
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000052/*
53 * The next 2 constants identify the extents of the coherent memory region.
54 * These addresses are used by the MMU setup code and therefore they must be
55 * page-aligned. It is the responsibility of the linker script to ensure that
56 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
57 * page-aligned addresses.
58 */
59#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
60#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000062#define BL1_RAM_BASE (unsigned long)(&__BL1_RAM_START__)
63#define BL1_RAM_LIMIT (unsigned long)(&__BL1_RAM_END__)
Achin Gupta4f6ad662013-10-25 09:08:21 +010064
Achin Gupta4f6ad662013-10-25 09:08:21 +010065
66/* Data structure which holds the extents of the trusted SRAM for BL1*/
Dan Handleye2712bc2014-04-10 15:37:22 +010067static meminfo_t bl1_tzram_layout;
Achin Gupta4f6ad662013-10-25 09:08:21 +010068
Dan Handleye2712bc2014-04-10 15:37:22 +010069meminfo_t *bl1_plat_sec_mem_layout(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +010070{
Sandrine Bailleuxee12f6f2013-11-28 14:55:58 +000071 return &bl1_tzram_layout;
Achin Gupta4f6ad662013-10-25 09:08:21 +010072}
73
74/*******************************************************************************
75 * Perform any BL1 specific platform actions.
76 ******************************************************************************/
77void bl1_early_platform_setup(void)
78{
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000079 const unsigned long bl1_ram_base = BL1_RAM_BASE;
80 const unsigned long bl1_ram_limit = BL1_RAM_LIMIT;
81 const unsigned long tzram_limit = TZRAM_BASE + TZRAM_SIZE;
Achin Gupta4f6ad662013-10-25 09:08:21 +010082
Vikram Kanigiri3684abf2014-03-27 14:33:15 +000083 /* Initialize the console to provide early debug support */
84 console_init(PL011_UART0_BASE);
85
Achin Gupta4f6ad662013-10-25 09:08:21 +010086 /*
87 * Calculate how much ram is BL1 using & how much remains free.
88 * This also includes a rudimentary mechanism to detect whether
89 * the BL1 data is loaded at the top or bottom of memory.
90 * TODO: add support for discontigous chunks of free ram if
91 * needed. Might need dynamic memory allocation support
92 * et al.
Achin Gupta4f6ad662013-10-25 09:08:21 +010093 */
94 bl1_tzram_layout.total_base = TZRAM_BASE;
95 bl1_tzram_layout.total_size = TZRAM_SIZE;
96
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000097 if (bl1_ram_limit == tzram_limit) {
98 /* BL1 has been loaded at the top of memory. */
Achin Gupta4f6ad662013-10-25 09:08:21 +010099 bl1_tzram_layout.free_base = TZRAM_BASE;
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000100 bl1_tzram_layout.free_size = bl1_ram_base - TZRAM_BASE;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100101 } else {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000102 /* BL1 has been loaded at the bottom of memory. */
103 bl1_tzram_layout.free_base = bl1_ram_limit;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100104 bl1_tzram_layout.free_size =
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000105 tzram_limit - bl1_ram_limit;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100106 }
Harry Liebel30affd52013-10-30 17:41:48 +0000107
108 /* Initialize the platform config for future decision making */
109 platform_config_setup();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100110}
111
112/*******************************************************************************
113 * Function which will evaluate how much of the trusted ram has been gobbled
114 * up by BL1 and return the base and size of whats available for loading BL2.
115 * Its called after coherency and the MMU have been turned on.
116 ******************************************************************************/
117void bl1_platform_setup(void)
118{
James Morrissey9d72b4e2014-02-10 17:04:32 +0000119 /* Initialise the IO layer and register platform IO devices */
120 io_setup();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100121}
122
James Morrissey9d72b4e2014-02-10 17:04:32 +0000123
Achin Gupta4f6ad662013-10-25 09:08:21 +0100124/*******************************************************************************
125 * Perform the very early platform specific architecture setup here. At the
Harry Liebel30affd52013-10-30 17:41:48 +0000126 * moment this only does basic initialization. Later architectural setup
127 * (bl1_arch_setup()) does not do anything platform specific.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100128 ******************************************************************************/
129void bl1_plat_arch_setup(void)
130{
Vikram Kanigiri96377452014-04-24 11:02:16 +0100131 fvp_cci_setup();
Harry Liebel30affd52013-10-30 17:41:48 +0000132
Vikram Kanigirid8c9d262014-05-16 18:48:12 +0100133 configure_mmu_el3(bl1_tzram_layout.total_base,
134 bl1_tzram_layout.total_size,
Sandrine Bailleux74a62b32014-05-09 11:35:36 +0100135 TZROM_BASE,
136 TZROM_BASE + TZROM_SIZE,
137 BL1_COHERENT_RAM_BASE,
138 BL1_COHERENT_RAM_LIMIT);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100139}
Vikram Kanigirida567432014-04-15 18:08:08 +0100140
141
142/*******************************************************************************
143 * Before calling this function BL2 is loaded in memory and its entrypoint
144 * is set by load_image. This is a placeholder for the platform to change
145 * the entrypoint of BL2 and set SPSR and security state.
146 * On FVP we are only setting the security state, entrypoint
147 ******************************************************************************/
148void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image,
149 entry_point_info_t *bl2_ep)
150{
151 SET_SECURITY_STATE(bl2_ep->h.attr, SECURE);
152 bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
153}