Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1 | Arm CPU Specific Build Macros |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2 | ============================= |
| 3 | |
| 4 | |
Paul Beesley | ea22512 | 2019-02-11 17:54:45 +0000 | [diff] [blame^] | 5 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 6 | |
| 7 | .. contents:: |
| 8 | |
| 9 | This document describes the various build options present in the CPU specific |
| 10 | operations framework to enable errata workarounds and to enable optimizations |
| 11 | for a specific CPU on a platform. |
| 12 | |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 13 | Security Vulnerability Workarounds |
| 14 | ---------------------------------- |
| 15 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 16 | TF-A exports a series of build flags which control which security |
| 17 | vulnerability workarounds should be applied at runtime. |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 18 | |
| 19 | - ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for |
Dimitris Papastamos | 6d1f499 | 2018-03-28 12:06:40 +0100 | [diff] [blame] | 20 | `CVE-2017-5715`_. This flag can be set to 0 by the platform if none |
| 21 | of the PEs in the system need the workaround. Setting this flag to 0 provides |
| 22 | no performance benefit for non-affected platforms, it just helps to comply |
| 23 | with the recommendation in the spec regarding workaround discovery. |
| 24 | Defaults to 1. |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 25 | |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 26 | - ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for |
| 27 | `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep |
| 28 | the default value of 1 even on platforms that are unaffected by |
| 29 | CVE-2018-3639, in order to comply with the recommendation in the spec |
| 30 | regarding workaround discovery. |
| 31 | |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 32 | - ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for |
| 33 | `CVE-2018-3639`_. This build option should be set to 1 if the target |
| 34 | platform contains at least 1 CPU that requires dynamic mitigation. |
| 35 | Defaults to 0. |
| 36 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 37 | CPU Errata Workarounds |
| 38 | ---------------------- |
| 39 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 40 | TF-A exports a series of build flags which control the errata workarounds that |
| 41 | are applied to each CPU by the reset handler. The errata details can be found |
| 42 | in the CPU specific errata documents published by Arm: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 43 | |
| 44 | - `Cortex-A53 MPCore Software Developers Errata Notice`_ |
| 45 | - `Cortex-A57 MPCore Software Developers Errata Notice`_ |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 46 | - `Cortex-A72 MPCore Software Developers Errata Notice`_ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 47 | |
| 48 | The errata workarounds are implemented for a particular revision or a set of |
| 49 | processor revisions. This is checked by the reset handler at runtime. Each |
| 50 | errata workaround is identified by its ``ID`` as specified in the processor's |
| 51 | errata notice document. The format of the define used to enable/disable the |
| 52 | errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` |
| 53 | is for example ``A57`` for the ``Cortex_A57`` CPU. |
| 54 | |
| 55 | Refer to the section *CPU errata status reporting* in |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 56 | `Firmware Design guide`_ for information on how to write errata workaround |
| 57 | functions. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 58 | |
| 59 | All workarounds are disabled by default. The platform is responsible for |
| 60 | enabling these workarounds according to its requirement by defining the |
| 61 | errata workaround build flags in the platform specific makefile. In case |
| 62 | these workarounds are enabled for the wrong CPU revision then the errata |
| 63 | workaround is not applied. In the DEBUG build, this is indicated by |
| 64 | printing a warning to the crash console. |
| 65 | |
| 66 | In the current implementation, a platform which has more than 1 variant |
| 67 | with different revisions of a processor has no runtime mechanism available |
| 68 | for it to specify which errata workarounds should be enabled or not. |
| 69 | |
John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 70 | The value of the build flags is 0 by default, that is, disabled. A value of 1 |
| 71 | will enable it. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 72 | |
Joel Hutton | 26d1676 | 2019-04-10 12:52:52 +0100 | [diff] [blame] | 73 | For Cortex-A9, the following errata build flags are defined : |
| 74 | |
Louis Mayencourt | e6469d5 | 2019-04-18 12:11:25 +0100 | [diff] [blame] | 75 | - ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 |
Joel Hutton | 26d1676 | 2019-04-10 12:52:52 +0100 | [diff] [blame] | 76 | CPU. This needs to be enabled for all revisions of the CPU. |
| 77 | |
Ambroise Vincent | d4a51eb | 2019-03-04 16:56:26 +0000 | [diff] [blame] | 78 | For Cortex-A15, the following errata build flags are defined : |
| 79 | |
| 80 | - ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 |
| 81 | CPU. This needs to be enabled only for revision >= r3p0 of the CPU. |
| 82 | |
Ambroise Vincent | 68b3812 | 2019-03-05 09:54:21 +0000 | [diff] [blame] | 83 | - ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 |
| 84 | CPU. This needs to be enabled only for revision >= r3p0 of the CPU. |
| 85 | |
Ambroise Vincent | 8cf9eef | 2019-02-28 16:23:53 +0000 | [diff] [blame] | 86 | For Cortex-A17, the following errata build flags are defined : |
| 87 | |
| 88 | - ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 |
| 89 | CPU. This needs to be enabled only for revision <= r1p2 of the CPU. |
| 90 | |
Ambroise Vincent | fa5c951 | 2019-03-04 13:20:56 +0000 | [diff] [blame] | 91 | - ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 |
| 92 | CPU. This needs to be enabled only for revision <= r1p2 of the CPU. |
| 93 | |
Louis Mayencourt | 8a06127 | 2019-04-05 16:25:25 +0100 | [diff] [blame] | 94 | For Cortex-A35, the following errata build flags are defined : |
| 95 | |
| 96 | - ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 |
| 97 | CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. |
| 98 | |
John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 99 | For Cortex-A53, the following errata build flags are defined : |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 100 | |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 101 | - ``ERRATA_A53_819472``: This applies errata 819472 workaround to all |
| 102 | CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. |
| 103 | |
| 104 | - ``ERRATA_A53_824069``: This applies errata 824069 workaround to all |
| 105 | CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. |
| 106 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 107 | - ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 |
| 108 | CPU. This needs to be enabled only for revision <= r0p2 of the CPU. |
| 109 | |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 110 | - ``ERRATA_A53_827319``: This applies errata 827319 workaround to all |
| 111 | CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. |
| 112 | |
Douglas Raillard | b52353a | 2017-07-17 14:14:52 +0100 | [diff] [blame] | 113 | - ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and |
| 114 | link time to Cortex-A53 CPU. This needs to be enabled for some variants of |
| 115 | revision <= r0p4. This workaround can lead the linker to create ``*.stub`` |
| 116 | sections. |
| 117 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 118 | - ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 |
| 119 | CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From |
| 120 | r0p4 and onwards, this errata is enabled by default in hardware. |
| 121 | |
Douglas Raillard | b52353a | 2017-07-17 14:14:52 +0100 | [diff] [blame] | 122 | - ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time |
| 123 | to Cortex-A53 CPU. This needs to be enabled for some variants of revision |
| 124 | <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections |
| 125 | which are 4kB aligned. |
| 126 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 127 | - ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 |
| 128 | CPUs. Though the erratum is present in every revision of the CPU, |
| 129 | this workaround is only applied to CPUs from r0p3 onwards, which feature |
Sandrine Bailleux | 15530dd | 2019-02-08 15:26:36 +0100 | [diff] [blame] | 130 | a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 131 | Earlier revisions of the CPU have other errata which require the same |
| 132 | workaround in software, so they should be covered anyway. |
| 133 | |
Ambroise Vincent | 7927fa0 | 2019-02-21 16:20:43 +0000 | [diff] [blame] | 134 | For Cortex-A55, the following errata build flags are defined : |
| 135 | |
| 136 | - ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 |
| 137 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 138 | |
Ambroise Vincent | 6f31960 | 2019-02-21 16:25:37 +0000 | [diff] [blame] | 139 | - ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 |
| 140 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 141 | |
Ambroise Vincent | 6a77f05 | 2019-02-21 16:27:34 +0000 | [diff] [blame] | 142 | - ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 |
| 143 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 144 | |
Ambroise Vincent | dd961f7 | 2019-02-21 16:29:16 +0000 | [diff] [blame] | 145 | - ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 |
| 146 | CPU. This needs to be enabled only for revision <= r0p1 of the CPU. |
| 147 | |
Ambroise Vincent | a1d6446 | 2019-02-21 16:29:50 +0000 | [diff] [blame] | 148 | - ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 |
| 149 | CPU. This needs to be enabled only for revision <= r0p1 of the CPU. |
| 150 | |
John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 151 | For Cortex-A57, the following errata build flags are defined : |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 152 | |
| 153 | - ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 |
| 154 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 155 | |
| 156 | - ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 |
| 157 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 158 | |
| 159 | - ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 |
| 160 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 161 | |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 162 | - ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 |
| 163 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 164 | |
Ambroise Vincent | aa2c029 | 2019-02-21 16:35:49 +0000 | [diff] [blame] | 165 | - ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 |
| 166 | CPU. This needs to be enabled only for revision <= r0p1 of the CPU. |
| 167 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 168 | - ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 |
| 169 | CPU. This needs to be enabled only for revision <= r1p1 of the CPU. |
| 170 | |
| 171 | - ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 |
| 172 | CPU. This needs to be enabled only for revision <= r1p1 of the CPU. |
| 173 | |
| 174 | - ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 |
| 175 | CPU. This needs to be enabled only for revision <= r1p1 of the CPU. |
| 176 | |
| 177 | - ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 |
| 178 | CPU. This needs to be enabled only for revision <= r1p2 of the CPU. |
| 179 | |
| 180 | - ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 |
| 181 | CPU. This needs to be enabled only for revision <= r1p2 of the CPU. |
| 182 | |
Eleanor Bonnici | 0c9bd27 | 2017-08-02 16:35:04 +0100 | [diff] [blame] | 183 | - ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 |
| 184 | CPU. This needs to be enabled only for revision <= r1p3 of the CPU. |
| 185 | |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 186 | |
John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 187 | For Cortex-A72, the following errata build flags are defined : |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 188 | |
| 189 | - ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 |
| 190 | CPU. This needs to be enabled only for revision <= r0p3 of the CPU. |
| 191 | |
Louis Mayencourt | 4405de6 | 2019-02-21 16:38:16 +0000 | [diff] [blame] | 192 | For Cortex-A73, the following errata build flags are defined : |
| 193 | |
Louis Mayencourt | d69722c | 2019-02-27 14:24:16 +0000 | [diff] [blame] | 194 | - ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 |
| 195 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 196 | |
Louis Mayencourt | 4405de6 | 2019-02-21 16:38:16 +0000 | [diff] [blame] | 197 | - ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 |
| 198 | CPU. This needs to be enabled only for revision <= r0p1 of the CPU. |
| 199 | |
Louis Mayencourt | 78a0aed | 2019-02-20 12:11:41 +0000 | [diff] [blame] | 200 | For Cortex-A75, the following errata build flags are defined : |
| 201 | |
| 202 | - ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 |
| 203 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 204 | |
Louis Mayencourt | 8d86870 | 2019-02-25 14:57:57 +0000 | [diff] [blame] | 205 | - ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 |
| 206 | CPU. This needs to be enabled only for revision r0p0 of the CPU. |
| 207 | |
Louis Mayencourt | 0992447 | 2019-02-21 17:35:07 +0000 | [diff] [blame] | 208 | For Cortex-A76, the following errata build flags are defined : |
| 209 | |
Louis Mayencourt | 59fa218 | 2019-02-25 15:17:44 +0000 | [diff] [blame] | 210 | - ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 |
| 211 | CPU. This needs to be enabled only for revision <= r1p0 of the CPU. |
| 212 | |
Louis Mayencourt | 0992447 | 2019-02-21 17:35:07 +0000 | [diff] [blame] | 213 | - ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 |
| 214 | CPU. This needs to be enabled only for revision <= r2p0 of the CPU. |
| 215 | |
Louis Mayencourt | adda9d4 | 2019-02-25 11:37:38 +0000 | [diff] [blame] | 216 | - ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 |
| 217 | CPU. This needs to be enabled only for revision <= r2p0 of the CPU. |
| 218 | |
Soby Mathew | 1d3ba1c | 2019-05-01 09:43:18 +0100 | [diff] [blame] | 219 | - ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 |
| 220 | CPU. This needs to be enabled only for revision <= r3p0 of the CPU. |
| 221 | |
| 222 | - ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 |
| 223 | CPU. This needs to be enabled only for revision <= r3p0 of the CPU. |
| 224 | |
| 225 | - ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 |
| 226 | CPU. This needs to be enabled only for revision <= r3p0 of the CPU. |
| 227 | |
| 228 | - ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 |
| 229 | CPU. This needs to be enabled only for revision <= r3p0 of the CPU. |
| 230 | |
John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 231 | DSU Errata Workarounds |
| 232 | ---------------------- |
| 233 | |
| 234 | Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ |
| 235 | Shared Unit) errata. The DSU errata details can be found in the respective Arm |
| 236 | documentation: |
| 237 | |
| 238 | - `Arm DSU Software Developers Errata Notice`_. |
| 239 | |
| 240 | Each erratum is identified by an ``ID``, as defined in the DSU errata notice |
| 241 | document. Thus, the build flags which enable/disable the errata workarounds |
| 242 | have the format ``ERRATA_DSU_<ID>``. The implementation and application logic |
| 243 | of DSU errata workarounds are similar to `CPU errata workarounds`_. |
| 244 | |
| 245 | For DSU errata, the following build flags are defined: |
| 246 | |
Louis Mayencourt | 4498b15 | 2019-04-09 16:29:01 +0100 | [diff] [blame] | 247 | - ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the |
| 248 | affected DSU configurations. This errata applies only for those DSUs that |
| 249 | revision is r0p0 (on r0p1 it is fixed). However, please note that this |
| 250 | workaround results in increased DSU power consumption on idle. |
| 251 | |
John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 252 | - ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the |
| 253 | affected DSU configurations. This errata applies only for those DSUs that |
| 254 | contain the ACP interface **and** the DSU revision is older than r2p0 (on |
| 255 | r2p0 it is fixed). However, please note that this workaround results in |
| 256 | increased DSU power consumption on idle. |
| 257 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 258 | CPU Specific optimizations |
| 259 | -------------------------- |
| 260 | |
| 261 | This section describes some of the optimizations allowed by the CPU micro |
| 262 | architecture that can be enabled by the platform as desired. |
| 263 | |
| 264 | - ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the |
| 265 | Cortex-A57 cluster power down sequence by not flushing the Level 1 data |
| 266 | cache. The L1 data cache and the L2 unified cache are inclusive. A flush |
| 267 | of the L2 by set/way flushes any dirty lines from the L1 as well. This |
| 268 | is a known safe deviation from the Cortex-A57 TRM defined power down |
| 269 | sequence. Each Cortex-A57 based platform must make its own decision on |
| 270 | whether to use the optimization. |
| 271 | |
| 272 | - ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal |
| 273 | hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave |
| 274 | in a way most programmers expect, and will most probably result in a |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 275 | significant speed degradation to any code that employs them. The Armv8-A |
| 276 | architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 277 | the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this |
| 278 | flag enforces this behaviour. This needs to be enabled only for revisions |
| 279 | <= r0p3 of the CPU and is enabled by default. |
| 280 | |
| 281 | - ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as |
| 282 | ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be |
| 283 | enabled only for revisions <= r1p2 of the CPU and is enabled by default, |
| 284 | as recommended in section "4.7 Non-Temporal Loads/Stores" of the |
| 285 | `Cortex-A57 Software Optimization Guide`_. |
| 286 | |
| 287 | -------------- |
| 288 | |
Joel Hutton | 26d1676 | 2019-04-10 12:52:52 +0100 | [diff] [blame] | 289 | *Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.* |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 290 | |
John Tsichritzis | 3eeac41 | 2018-09-04 10:56:53 +0100 | [diff] [blame] | 291 | .. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 |
| 292 | .. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 |
Paul Beesley | 2437ddc | 2019-02-08 16:43:05 +0000 | [diff] [blame] | 293 | .. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html |
| 294 | .. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 295 | .. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 296 | .. _Firmware Design guide: firmware-design.rst |
| 297 | .. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf |
Sandrine Bailleux | 15530dd | 2019-02-08 15:26:36 +0100 | [diff] [blame] | 298 | .. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html |