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Dan Handley610e7e12018-03-01 18:44:00 +00001Trusted Firmware-A User Guide
2=============================
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
4
5.. section-numbering::
6 :suffix: .
7
8.. contents::
9
Dan Handley610e7e12018-03-01 18:44:00 +000010This document describes how to build Trusted Firmware-A (TF-A) and run it with a
Douglas Raillardd7c21b72017-06-28 15:23:03 +010011tested set of other software components using defined configurations on the Juno
Dan Handley610e7e12018-03-01 18:44:00 +000012Arm development platform and Arm Fixed Virtual Platform (FVP) models. It is
Douglas Raillardd7c21b72017-06-28 15:23:03 +010013possible to use other software components, configurations and platforms but that
14is outside the scope of this document.
15
16This document assumes that the reader has previous experience running a fully
17bootable Linux software stack on Juno or FVP using the prebuilt binaries and
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010018filesystems provided by `Linaro`_. Further information may be found in the
19`Linaro instructions`_. It also assumes that the user understands the role of
20the different software components required to boot a Linux system:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
22- Specific firmware images required by the platform (e.g. SCP firmware on Juno)
23- Normal world bootloader (e.g. UEFI or U-Boot)
24- Device tree
25- Linux kernel image
26- Root filesystem
27
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010028This document also assumes that the user is familiar with the `FVP models`_ and
Douglas Raillardd7c21b72017-06-28 15:23:03 +010029the different command line options available to launch the model.
30
31This document should be used in conjunction with the `Firmware Design`_.
32
33Host machine requirements
34-------------------------
35
36The minimum recommended machine specification for building the software and
37running the FVP models is a dual-core processor running at 2GHz with 12GB of
38RAM. For best performance, use a machine with a quad-core processor running at
392.6GHz with 16GB of RAM.
40
Joel Huttonfe027712018-03-19 11:59:57 +000041The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for
Douglas Raillardd7c21b72017-06-28 15:23:03 +010042building the software were installed from that distribution unless otherwise
43specified.
44
45The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
David Cunadob2de0992017-06-29 12:01:33 +010046Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010047
48Tools
49-----
50
Dan Handley610e7e12018-03-01 18:44:00 +000051Install the required packages to build TF-A with the following command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010052
53::
54
Sathees Balya2d0aeb02018-07-10 14:46:51 +010055 sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev
Douglas Raillardd7c21b72017-06-28 15:23:03 +010056
David Cunado05845bf2017-12-19 16:33:25 +000057TF-A has been tested with Linaro Release 18.04.
David Cunadob2de0992017-06-29 12:01:33 +010058
Douglas Raillardd7c21b72017-06-28 15:23:03 +010059Download and install the AArch32 or AArch64 little-endian GCC cross compiler.
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010060The `Linaro Release Notes`_ documents which version of the compiler to use for a
61given Linaro Release. Also, these `Linaro instructions`_ provide further
62guidance and a script, which can be used to download Linaro deliverables
63automatically.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010064
Roberto Vargas0489bc02018-04-16 15:43:26 +010065Optionally, TF-A can be built using clang version 4.0 or newer or Arm
66Compiler 6. See instructions below on how to switch the default compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010067
68In addition, the following optional packages and tools may be needed:
69
Sathees Balya017a67e2018-08-17 10:22:01 +010070- ``device-tree-compiler`` (dtc) package if you need to rebuild the Flattened Device
71 Tree (FDT) source files (``.dts`` files) provided with this software. The
72 version of dtc must be 1.4.6 or above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010073
Dan Handley610e7e12018-03-01 18:44:00 +000074- For debugging, Arm `Development Studio 5 (DS-5)`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010075
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010076- To create and modify the diagram files included in the documentation, `Dia`_.
77 This tool can be found in most Linux distributions. Inkscape is needed to
Antonio Nino Diaz80914a82018-08-08 16:28:43 +010078 generate the actual \*.png files.
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010079
Dan Handley610e7e12018-03-01 18:44:00 +000080Getting the TF-A source code
81----------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010082
Dan Handley610e7e12018-03-01 18:44:00 +000083Download the TF-A source code from Github:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010084
85::
86
87 git clone https://github.com/ARM-software/arm-trusted-firmware.git
88
Dan Handley610e7e12018-03-01 18:44:00 +000089Building TF-A
90-------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010091
Dan Handley610e7e12018-03-01 18:44:00 +000092- Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
93 to the Linaro cross compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010094
95 For AArch64:
96
97 ::
98
99 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
100
101 For AArch32:
102
103 ::
104
105 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
106
Roberto Vargas07b1e242018-04-23 08:38:12 +0100107 It is possible to build TF-A using Clang or Arm Compiler 6. To do so
108 ``CC`` needs to point to the clang or armclang binary, which will
109 also select the clang or armclang assembler. Be aware that the
110 GNU linker is used by default. In case of being needed the linker
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000111 can be overridden using the ``LD`` variable. Clang linker version 6 is
Roberto Vargas07b1e242018-04-23 08:38:12 +0100112 known to work with TF-A.
113
114 In both cases ``CROSS_COMPILE`` should be set as described above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100115
Dan Handley610e7e12018-03-01 18:44:00 +0000116 Arm Compiler 6 will be selected when the base name of the path assigned
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100117 to ``CC`` matches the string 'armclang'.
118
Dan Handley610e7e12018-03-01 18:44:00 +0000119 For AArch64 using Arm Compiler 6:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100120
121 ::
122
123 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
124 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
125
126 Clang will be selected when the base name of the path assigned to ``CC``
127 contains the string 'clang'. This is to allow both clang and clang-X.Y
128 to work.
129
130 For AArch64 using clang:
131
132 ::
133
134 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
135 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
136
Dan Handley610e7e12018-03-01 18:44:00 +0000137- Change to the root directory of the TF-A source tree and build.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100138
139 For AArch64:
140
141 ::
142
143 make PLAT=<platform> all
144
145 For AArch32:
146
147 ::
148
149 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
150
151 Notes:
152
153 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
154 `Summary of build options`_ for more information on available build
155 options.
156
157 - (AArch32 only) Currently only ``PLAT=fvp`` is supported.
158
159 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
160 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp\_min, is
Dan Handley610e7e12018-03-01 18:44:00 +0000161 provided by TF-A to demonstrate how PSCI Library can be integrated with
162 an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
163 include other runtime services, for example Trusted OS services. A guide
164 to integrate PSCI library with AArch32 EL3 Runtime Software can be found
165 `here`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100166
167 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
168 image, is not compiled in by default. Refer to the
169 `Building the Test Secure Payload`_ section below.
170
171 - By default this produces a release version of the build. To produce a
172 debug version instead, refer to the "Debugging options" section below.
173
174 - The build process creates products in a ``build`` directory tree, building
175 the objects and binaries for each boot loader stage in separate
176 sub-directories. The following boot loader binary files are created
177 from the corresponding ELF files:
178
179 - ``build/<platform>/<build-type>/bl1.bin``
180 - ``build/<platform>/<build-type>/bl2.bin``
181 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
182 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
183
184 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
185 is either ``debug`` or ``release``. The actual number of images might differ
186 depending on the platform.
187
188- Build products for a specific build variant can be removed using:
189
190 ::
191
192 make DEBUG=<D> PLAT=<platform> clean
193
194 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
195
196 The build tree can be removed completely using:
197
198 ::
199
200 make realclean
201
202Summary of build options
203~~~~~~~~~~~~~~~~~~~~~~~~
204
Dan Handley610e7e12018-03-01 18:44:00 +0000205The TF-A build system supports the following build options. Unless mentioned
206otherwise, these options are expected to be specified at the build command
207line and are not to be modified in any component makefiles. Note that the
208build system doesn't track dependency for build options. Therefore, if any of
209the build options are changed from a previous build, a clean build must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100210performed.
211
212Common build options
213^^^^^^^^^^^^^^^^^^^^
214
Antonio Nino Diaz80914a82018-08-08 16:28:43 +0100215- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
216 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
217 code having a smaller resulting size.
218
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100219- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
220 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
221 directory containing the SP source, relative to the ``bl32/``; the directory
222 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
223
Dan Handley610e7e12018-03-01 18:44:00 +0000224- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
225 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
226 ``aarch64``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100227
Dan Handley610e7e12018-03-01 18:44:00 +0000228- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
229 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
230 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
231 `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100232
Dan Handley610e7e12018-03-01 18:44:00 +0000233- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
234 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
235 *Armv8 Architecture Extensions* in `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100236
Dan Handley610e7e12018-03-01 18:44:00 +0000237- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000238 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
239 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
240 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
241 this flag is 0. Note that this option is not used on FVP platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100242
243- ``BL2``: This is an optional build option which specifies the path to BL2
Dan Handley610e7e12018-03-01 18:44:00 +0000244 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
245 built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100246
247- ``BL2U``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000248 BL2U image. In this case, the BL2U in TF-A will not be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100249
John Tsichritzisee10e792018-06-06 09:38:10 +0100250- ``BL2_AT_EL3``: This is an optional build option that enables the use of
Roberto Vargasb1584272017-11-20 13:36:10 +0000251 BL2 at EL3 execution level.
252
John Tsichritzisee10e792018-06-06 09:38:10 +0100253- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000254 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
255 the RW sections in RAM, while leaving the RO sections in place. This option
256 enable this use-case. For now, this option is only supported when BL2_AT_EL3
257 is set to '1'.
258
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100259- ``BL31``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000260 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
261 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100262
263- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
264 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
265 this file name will be used to save the key.
266
267- ``BL32``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000268 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
269 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100270
John Tsichritzisee10e792018-06-06 09:38:10 +0100271- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
Summer Qin80726782017-04-20 16:28:39 +0100272 Trusted OS Extra1 image for the ``fip`` target.
273
John Tsichritzisee10e792018-06-06 09:38:10 +0100274- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
Summer Qin80726782017-04-20 16:28:39 +0100275 Trusted OS Extra2 image for the ``fip`` target.
276
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100277- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
278 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
279 this file name will be used to save the key.
280
281- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
Dan Handley610e7e12018-03-01 18:44:00 +0000282 ``fip`` target in case TF-A BL2 is used.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100283
284- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
285 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
286 this file name will be used to save the key.
287
288- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
289 compilation of each build. It must be set to a C string (including quotes
290 where applicable). Defaults to a string that contains the time and date of
291 the compilation.
292
Dan Handley610e7e12018-03-01 18:44:00 +0000293- ``BUILD_STRING``: Input string for VERSION\_STRING, which allows the TF-A
294 build to be uniquely identified. Defaults to the current git commit id.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100295
296- ``CFLAGS``: Extra user options appended on the compiler's command line in
297 addition to the options set by the build system.
298
299- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
300 release several CPUs out of reset. It can take either 0 (several CPUs may be
301 brought up) or 1 (only one CPU will ever be brought up during cold reset).
302 Default is 0. If the platform always brings up a single CPU, there is no
303 need to distinguish between primary and secondary CPUs and the boot path can
304 be optimised. The ``plat_is_my_cpu_primary()`` and
305 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
306 to be implemented in this case.
307
308- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
309 register state when an unexpected exception occurs during execution of
310 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
311 this is only enabled for a debug build of the firmware.
312
313- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
314 certificate generation tool to create new keys in case no valid keys are
315 present or specified. Allowed options are '0' or '1'. Default is '1'.
316
317- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
318 the AArch32 system registers to be included when saving and restoring the
319 CPU context. The option must be set to 0 for AArch64-only platforms (that
320 is on hardware that does not implement AArch32, or at least not at EL1 and
321 higher ELs). Default value is 1.
322
323- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
324 registers to be included when saving and restoring the CPU context. Default
325 is 0.
326
327- ``DEBUG``: Chooses between a debug and release build. It can take either 0
328 (release) or 1 (debug) as values. 0 is the default.
329
John Tsichritzisee10e792018-06-06 09:38:10 +0100330- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
331 Board Boot authentication at runtime. This option is meant to be enabled only
Roberto Vargas025946a2018-09-24 17:20:48 +0100332 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
333 flag has to be enabled. 0 is the default.
Soby Mathew9fe88042018-03-26 12:43:37 +0100334
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100335- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
336 the normal boot flow. It must specify the entry point address of the EL3
337 payload. Please refer to the "Booting an EL3 payload" section for more
338 details.
339
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100340- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100341 This is an optional architectural feature available on v8.4 onwards. Some
342 v8.2 implementations also implement an AMU and this option can be used to
343 enable this feature on those systems as well. Default is 0.
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100344
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100345- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
346 are compiled out. For debug builds, this option defaults to 1, and calls to
347 ``assert()`` are left in place. For release builds, this option defaults to 0
348 and calls to ``assert()`` function are compiled out. This option can be set
349 independently of ``DEBUG``. It can also be used to hide any auxiliary code
350 that is only required for the assertion and does not fit in the assertion
351 itself.
352
Douglas Raillard77414632018-08-21 12:54:45 +0100353- ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace
354 dumps or not. It is supported in both AArch64 and AArch32. However, in
355 AArch32 the format of the frame records are not defined in the AAPCS and they
356 are defined by the implementation. This implementation of backtrace only
357 supports the format used by GCC when T32 interworking is disabled. For this
358 reason enabling this option in AArch32 will force the compiler to only
359 generate A32 code. This option is enabled by default only in AArch64 debug
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000360 builds, but this behaviour can be overridden in each platform's Makefile or
361 in the build command line.
Douglas Raillard77414632018-08-21 12:54:45 +0100362
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100363- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
364 feature. MPAM is an optional Armv8.4 extension that enables various memory
365 system components and resources to define partitions; software running at
366 various ELs can assign themselves to desired partition to control their
367 performance aspects.
368
369 When this option is set to ``1``, EL3 allows lower ELs to access their own
370 MPAM registers without trapping into EL3. This option doesn't make use of
371 partitioning in EL3, however. Platform initialisation code should configure
372 and use partitions in EL3 as required. This option defaults to ``0``.
373
Soby Mathew078f1a42018-08-28 11:13:55 +0100374- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
375 support within generic code in TF-A. This option is currently only supported
376 in BL31. Default is 0.
377
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100378- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
379 Measurement Framework(PMF). Default is 0.
380
381- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
382 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
383 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
384 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
385 software.
386
387- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
Dan Handley610e7e12018-03-01 18:44:00 +0000388 instrumentation which injects timestamp collection points into TF-A to
389 allow runtime performance to be measured. Currently, only PSCI is
390 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
391 as well. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100392
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100393- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100394 extensions. This is an optional architectural feature for AArch64.
395 The default is 1 but is automatically disabled when the target architecture
396 is AArch32.
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100397
Sandrine Bailleux604f0a42018-09-20 12:44:39 +0200398- ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM).
399 Refer to the `Secure Partition Manager Design guide`_ for more details about
400 this feature. Default is 0.
401
David Cunadoce88eee2017-10-20 11:30:57 +0100402- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
403 (SVE) for the Non-secure world only. SVE is an optional architectural feature
404 for AArch64. Note that when SVE is enabled for the Non-secure world, access
405 to SIMD and floating-point functionality from the Secure world is disabled.
406 This is to avoid corruption of the Non-secure world data in the Z-registers
407 which are aliased by the SIMD and FP registers. The build option is not
408 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
409 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
410 1. The default is 1 but is automatically disabled when the target
411 architecture is AArch32.
412
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100413- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
414 checks in GCC. Allowed values are "all", "strong" and "0" (default).
415 "strong" is the recommended stack protection level if this feature is
416 desired. 0 disables the stack protection. For all values other than 0, the
417 ``plat_get_stack_protector_canary()`` platform hook needs to be implemented.
418 The value is passed as the last component of the option
419 ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
420
421- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
422 deprecated platform APIs, helper functions or drivers within Trusted
423 Firmware as error. It can take the value 1 (flag the use of deprecated
424 APIs as error) or 0. The default is 0.
425
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100426- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
427 targeted at EL3. When set ``0`` (default), no exceptions are expected or
428 handled at EL3, and a panic will result. This is supported only for AArch64
429 builds.
430
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000431- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000432 injection from lower ELs, and this build option enables lower ELs to use
433 Error Records accessed via System Registers to inject faults. This is
434 applicable only to AArch64 builds.
435
436 This feature is intended for testing purposes only, and is advisable to keep
437 disabled for production images.
438
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100439- ``FIP_NAME``: This is an optional build option which specifies the FIP
440 filename for the ``fip`` target. Default is ``fip.bin``.
441
442- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
443 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
444
445- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
446 tool to create certificates as per the Chain of Trust described in
447 `Trusted Board Boot`_. The build system then calls ``fiptool`` to
448 include the certificates in the FIP and FWU\_FIP. Default value is '0'.
449
450 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
451 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
452 the corresponding certificates, and to include those certificates in the
453 FIP and FWU\_FIP.
454
455 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
456 images will not include support for Trusted Board Boot. The FIP will still
457 include the corresponding certificates. This FIP can be used to verify the
458 Chain of Trust on the host machine through other mechanisms.
459
460 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
461 images will include support for Trusted Board Boot, but the FIP and FWU\_FIP
462 will not include the corresponding certificates, causing a boot failure.
463
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100464- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
465 inherent support for specific EL3 type interrupts. Setting this build option
466 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
467 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
468 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
469 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
470 the Secure Payload interrupts needs to be synchronously handed over to Secure
471 EL1 for handling. The default value of this option is ``0``, which means the
472 Group 0 interrupts are assumed to be handled by Secure EL1.
473
474 .. __: `platform-interrupt-controller-API.rst`
475 .. __: `interrupt-framework-design.rst`
476
Julius Wernerc51a2ec2018-08-28 14:45:43 -0700477- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
478 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
479 ``0`` (default), these exceptions will be trapped in the current exception
480 level (or in EL1 if the current exception level is EL0).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100481
Dan Handley610e7e12018-03-01 18:44:00 +0000482- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100483 software operations are required for CPUs to enter and exit coherency.
484 However, there exists newer systems where CPUs' entry to and exit from
485 coherency is managed in hardware. Such systems require software to only
486 initiate the operations, and the rest is managed in hardware, minimizing
Dan Handley610e7e12018-03-01 18:44:00 +0000487 active software management. In such systems, this boolean option enables
488 TF-A to carry out build and run-time optimizations during boot and power
489 management operations. This option defaults to 0 and if it is enabled,
490 then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100491
Jeenu Viswambharane834ee12018-04-27 15:17:03 +0100492 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
493 translation library (xlat tables v2) must be used; version 1 of translation
494 library is not supported.
495
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100496- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
497 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
498 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
499 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
500 images.
501
Soby Mathew13b16052017-08-31 11:49:32 +0100502- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
503 used for generating the PKCS keys and subsequent signing of the certificate.
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800504 It accepts 3 values viz. ``rsa``, ``rsa_1_5``, ``ecdsa``. The ``rsa_1_5`` is
Soby Mathew2fd70f62017-08-31 11:50:29 +0100505 the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is
506 retained only for compatibility. The default value of this flag is ``rsa``
507 which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
Soby Mathew13b16052017-08-31 11:49:32 +0100508
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800509- ``HASH_ALG``: This build flag enables the user to select the secure hash
510 algorithm. It accepts 3 values viz. ``sha256``, ``sha384``, ``sha512``.
511 The default value of this flag is ``sha256``.
512
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100513- ``LDFLAGS``: Extra user options appended to the linkers' command line in
514 addition to the one set by the build system.
515
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100516- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
517 output compiled into the build. This should be one of the following:
518
519 ::
520
521 0 (LOG_LEVEL_NONE)
Daniel Boulby86c6b072018-06-14 10:07:40 +0100522 10 (LOG_LEVEL_ERROR)
523 20 (LOG_LEVEL_NOTICE)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100524 30 (LOG_LEVEL_WARNING)
525 40 (LOG_LEVEL_INFO)
526 50 (LOG_LEVEL_VERBOSE)
527
John Tsichritzis35006c42018-10-05 12:02:29 +0100528 All log output up to and including the selected log level is compiled into
529 the build. The default value is 40 in debug builds and 20 in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100530
531- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
532 specifies the file that contains the Non-Trusted World private key in PEM
533 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
534
535- ``NS_BL2U``: Path to NS\_BL2U image in the host file system. This image is
536 optional. It is only needed if the platform makefile specifies that it
537 is required in order to build the ``fwu_fip`` target.
538
539- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
540 contents upon world switch. It can take either 0 (don't save and restore) or
541 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
542 wants the timer registers to be saved and restored.
543
544- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
545 the underlying hardware is not a full PL011 UART but a minimally compliant
546 generic UART, which is a subset of the PL011. The driver will not access
547 any register that is not part of the SBSA generic UART specification.
548 Default value is 0 (a full PL011 compliant UART is present).
549
Dan Handley610e7e12018-03-01 18:44:00 +0000550- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
551 must be subdirectory of any depth under ``plat/``, and must contain a
552 platform makefile named ``platform.mk``. For example, to build TF-A for the
553 Arm Juno board, select PLAT=juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100554
555- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
556 instead of the normal boot flow. When defined, it must specify the entry
557 point address for the preloaded BL33 image. This option is incompatible with
558 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
559 over ``PRELOADED_BL33_BASE``.
560
561- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
562 vector address can be programmed or is fixed on the platform. It can take
563 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
564 programmable reset address, it is expected that a CPU will start executing
565 code directly at the right address, both on a cold and warm reset. In this
566 case, there is no need to identify the entrypoint on boot and the boot path
567 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
568 does not need to be implemented in this case.
569
570- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
571 possible for the PSCI power-state parameter viz original and extended
572 State-ID formats. This flag if set to 1, configures the generic PSCI layer
573 to use the extended format. The default value of this flag is 0, which
574 means by default the original power-state format is used by the PSCI
575 implementation. This flag should be specified by the platform makefile
576 and it governs the return value of PSCI\_FEATURES API for CPU\_SUSPEND
Dan Handley610e7e12018-03-01 18:44:00 +0000577 smc function id. When this option is enabled on Arm platforms, the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100578 option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well.
579
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100580- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
581 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
582 or later CPUs.
583
584 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
585 set to ``1``.
586
587 This option is disabled by default.
588
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100589- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
590 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
591 entrypoint) or 1 (CPU reset to BL31 entrypoint).
592 The default value is 0.
593
Dan Handley610e7e12018-03-01 18:44:00 +0000594- ``RESET_TO_SP_MIN``: SP\_MIN is the minimal AArch32 Secure Payload provided
595 in TF-A. This flag configures SP\_MIN entrypoint as the CPU reset vector
596 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
597 entrypoint) or 1 (CPU reset to SP\_MIN entrypoint). The default value is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100598
599- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
600 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
601 file name will be used to save the key.
602
603- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
604 certificate generation tool to save the keys used to establish the Chain of
605 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
606
607- ``SCP_BL2``: Path to SCP\_BL2 image in the host file system. This image is optional.
608 If a SCP\_BL2 image is present then this option must be passed for the ``fip``
609 target.
610
611- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
612 file that contains the SCP\_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
613 this file name will be used to save the key.
614
615- ``SCP_BL2U``: Path to SCP\_BL2U image in the host file system. This image is
616 optional. It is only needed if the platform makefile specifies that it
617 is required in order to build the ``fwu_fip`` target.
618
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100619- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
620 Delegated Exception Interface to BL31 image. This defaults to ``0``.
621
622 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
623 set to ``1``.
624
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100625- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
626 isolated on separate memory pages. This is a trade-off between security and
627 memory usage. See "Isolating code and read-only data on separate memory
628 pages" section in `Firmware Design`_. This flag is disabled by default and
629 affects all BL images.
630
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100631- ``SMCCC_MAJOR_VERSION``: Numeric value that indicates the major version of
632 the SMC Calling Convention that the Trusted Firmware supports. The only two
633 allowed values are 1 and 2, and it defaults to 1. The minor version is
634 determined using this value.
635
Dan Handley610e7e12018-03-01 18:44:00 +0000636- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
637 This build option is only valid if ``ARCH=aarch64``. The value should be
638 the path to the directory containing the SPD source, relative to
639 ``services/spd/``; the directory is expected to contain a makefile called
640 ``<spd-value>.mk``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100641
642- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
643 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
644 execution in BL1 just before handing over to BL31. At this point, all
645 firmware images have been loaded in memory, and the MMU and caches are
646 turned off. Refer to the "Debugging options" section for more details.
647
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100648- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200649 secure interrupts (caught through the FIQ line). Platforms can enable
650 this directive if they need to handle such interruption. When enabled,
651 the FIQ are handled in monitor mode and non secure world is not allowed
652 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
653 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
654
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100655- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
656 Boot feature. When set to '1', BL1 and BL2 images include support to load
657 and verify the certificates and images in a FIP, and BL1 includes support
658 for the Firmware Update. The default value is '0'. Generation and inclusion
659 of certificates in the FIP and FWU\_FIP depends upon the value of the
660 ``GENERATE_COT`` option.
661
662 Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys
663 already exist in disk, they will be overwritten without further notice.
664
665- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
666 specifies the file that contains the Trusted World private key in PEM
667 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
668
669- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
670 synchronous, (see "Initializing a BL32 Image" section in
671 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
672 synchronous method) or 1 (BL32 is initialized using asynchronous method).
673 Default is 0.
674
675- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
676 routing model which routes non-secure interrupts asynchronously from TSP
677 to EL3 causing immediate preemption of TSP. The EL3 is responsible
678 for saving and restoring the TSP context in this routing model. The
679 default routing model (when the value is 0) is to route non-secure
680 interrupts to TSP allowing it to save its context and hand over
681 synchronously to EL3 via an SMC.
682
Jeenu Viswambharan2f40f322018-01-11 14:30:22 +0000683 Note: when ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
684 must also be set to ``1``.
685
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100686- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
687 memory region in the BL memory map or not (see "Use of Coherent memory in
Dan Handley610e7e12018-03-01 18:44:00 +0000688 TF-A" section in `Firmware Design`_). It can take the value 1
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100689 (Coherent memory region is included) or 0 (Coherent memory region is
690 excluded). Default is 1.
691
692- ``V``: Verbose build. If assigned anything other than 0, the build commands
693 are printed. Default is 0.
694
Dan Handley610e7e12018-03-01 18:44:00 +0000695- ``VERSION_STRING``: String used in the log output for each TF-A image.
696 Defaults to a string formed by concatenating the version number, build type
697 and build string.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100698
699- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
700 the CPU after warm boot. This is applicable for platforms which do not
701 require interconnect programming to enable cache coherency (eg: single
702 cluster platforms). If this option is enabled, then warm boot path
703 enables D-caches immediately after enabling MMU. This option defaults to 0.
704
Dan Handley610e7e12018-03-01 18:44:00 +0000705Arm development platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100706^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
707
708- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
709 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
710 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
711 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
712 flag.
713
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100714- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
715 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
716 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
717 match the frame used by the Non-Secure image (normally the Linux kernel).
718 Default is true (access to the frame is allowed).
719
720- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
Dan Handley610e7e12018-03-01 18:44:00 +0000721 By default, Arm platforms use a watchdog to trigger a system reset in case
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100722 an error is encountered during the boot process (for example, when an image
723 could not be loaded or authenticated). The watchdog is enabled in the early
724 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
725 Trusted Watchdog may be disabled at build time for testing or development
726 purposes.
727
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100728- ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
729 have specific values at boot. This boolean option allows the Trusted Firmware
730 to have a Linux kernel image as BL33 by preparing the registers to these
Manish Pandey37c4ec22018-11-02 13:28:25 +0000731 values before jumping to BL33. This option defaults to 0 (disabled). For
732 AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when
733 using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set
734 to the location of a device tree blob (DTB) already loaded in memory. The
735 Linux Image address must be specified using the ``PRELOADED_BL33_BASE``
736 option.
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100737
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100738- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
739 for the construction of composite state-ID in the power-state parameter.
740 The existing PSCI clients currently do not support this encoding of
741 State-ID yet. Hence this flag is used to configure whether to use the
742 recommended State-ID encoding or not. The default value of this flag is 0,
743 in which case the platform is configured to expect NULL in the State-ID
744 field of power-state parameter.
745
746- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
747 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
Dan Handley610e7e12018-03-01 18:44:00 +0000748 for Arm platforms. Depending on the selected option, the proper private key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100749 must be specified using the ``ROT_KEY`` option when building the Trusted
750 Firmware. This private key will be used by the certificate generation tool
751 to sign the BL2 and Trusted Key certificates. Available options for
752 ``ARM_ROTPK_LOCATION`` are:
753
754 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
755 registers. The private key corresponding to this ROTPK hash is not
756 currently available.
757 - ``devel_rsa`` : return a development public key hash embedded in the BL1
758 and BL2 binaries. This hash has been obtained from the RSA public key
759 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
760 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
761 creating the certificates.
Qixiang Xu1c2aef12017-08-24 15:12:20 +0800762 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
763 and BL2 binaries. This hash has been obtained from the ECDSA public key
764 ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
765 this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
766 when creating the certificates.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100767
768- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
769
Qixiang Xuc7b12c52017-10-13 09:04:12 +0800770 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100771 - ``tdram`` : Trusted DRAM (if available)
John Tsichritzisee10e792018-06-06 09:38:10 +0100772 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
773 configured by the TrustZone controller)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100774
Dan Handley610e7e12018-03-01 18:44:00 +0000775- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
776 of the translation tables library instead of version 2. It is set to 0 by
777 default, which selects version 2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100778
Dan Handley610e7e12018-03-01 18:44:00 +0000779- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm®
780 TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm
781 platforms. If this option is specified, then the path to the CryptoCell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100782 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
783
Dan Handley610e7e12018-03-01 18:44:00 +0000784For a better understanding of these options, the Arm development platform memory
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100785map is explained in the `Firmware Design`_.
786
Dan Handley610e7e12018-03-01 18:44:00 +0000787Arm CSS platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100788^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
789
790- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
791 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
792 compatible change to the MTL protocol, used for AP/SCP communication.
Dan Handley610e7e12018-03-01 18:44:00 +0000793 TF-A no longer supports earlier SCP versions. If this option is set to 1
794 then TF-A will detect if an earlier version is in use. Default is 1.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100795
796- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP\_BL2 and
797 SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded
798 during boot. Default is 1.
799
Soby Mathew1ced6b82017-06-12 12:37:10 +0100800- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
801 instead of SCPI/BOM driver for communicating with the SCP during power
802 management operations and for SCP RAM Firmware transfer. If this option
803 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100804
Dan Handley610e7e12018-03-01 18:44:00 +0000805Arm FVP platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100806^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
807
808- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
Dan Handley610e7e12018-03-01 18:44:00 +0000809 build the topology tree within TF-A. By default TF-A is configured for dual
810 cluster topology and this option can be used to override the default value.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100811
812- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
813 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
814 explained in the options below:
815
816 - ``FVP_CCI`` : The CCI driver is selected. This is the default
817 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
818 - ``FVP_CCN`` : The CCN driver is selected. This is the default
819 if ``FVP_CLUSTER_COUNT`` > 2.
820
Jeenu Viswambharan75421132018-01-31 14:52:08 +0000821- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
822 a single cluster. This option defaults to 4.
823
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000824- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
825 in the system. This option defaults to 1. Note that the build option
826 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
827
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100828- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
829
830 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
831 - ``FVP_GICV2`` : The GICv2 only driver is selected
832 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100833
834- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
835 for functions that wait for an arbitrary time length (udelay and mdelay).
836 The default value is 0.
837
Soby Mathewb1bf0442018-02-16 14:52:52 +0000838- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
839 to DTB and packaged in FIP as the HW_CONFIG. See `Firmware Design`_ for
840 details on HW_CONFIG. By default, this is initialized to a sensible DTS
841 file in ``fdts/`` folder depending on other build options. But some cases,
842 like shifted affinity format for MPIDR, cannot be detected at build time
843 and this option is needed to specify the appropriate DTS file.
844
845- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
846 FIP. See `Firmware Design`_ for details on HW_CONFIG. This option is
847 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
848 HW_CONFIG blob instead of the DTS file. This option is useful to override
849 the default HW_CONFIG selected by the build system.
850
Summer Qin13b95c22018-03-02 15:51:14 +0800851ARM JUNO platform specific build options
852^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
853
854- ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
855 Media Protection (TZ-MP1). Default value of this flag is 0.
856
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100857Debugging options
858~~~~~~~~~~~~~~~~~
859
860To compile a debug version and make the build more verbose use
861
862::
863
864 make PLAT=<platform> DEBUG=1 V=1 all
865
866AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
867example DS-5) might not support this and may need an older version of DWARF
868symbols to be emitted by GCC. This can be achieved by using the
869``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
870version to 2 is recommended for DS-5 versions older than 5.16.
871
872When debugging logic problems it might also be useful to disable all compiler
873optimizations by using ``-O0``.
874
875NOTE: Using ``-O0`` could cause output images to be larger and base addresses
Dan Handley610e7e12018-03-01 18:44:00 +0000876might need to be recalculated (see the **Memory layout on Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100877platforms** section in the `Firmware Design`_).
878
879Extra debug options can be passed to the build system by setting ``CFLAGS`` or
880``LDFLAGS``:
881
882.. code:: makefile
883
884 CFLAGS='-O0 -gdwarf-2' \
885 make PLAT=<platform> DEBUG=1 V=1 all
886
887Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
888ignored as the linker is called directly.
889
890It is also possible to introduce an infinite loop to help in debugging the
Dan Handley610e7e12018-03-01 18:44:00 +0000891post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
892``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100893section. In this case, the developer may take control of the target using a
894debugger when indicated by the console output. When using DS-5, the following
895commands can be used:
896
897::
898
899 # Stop target execution
900 interrupt
901
902 #
903 # Prepare your debugging environment, e.g. set breakpoints
904 #
905
906 # Jump over the debug loop
907 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
908
909 # Resume execution
910 continue
911
912Building the Test Secure Payload
913~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
914
915The TSP is coupled with a companion runtime service in the BL31 firmware,
916called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
917must be recompiled as well. For more information on SPs and SPDs, see the
918`Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
919
Dan Handley610e7e12018-03-01 18:44:00 +0000920First clean the TF-A build directory to get rid of any previous BL31 binary.
921Then to build the TSP image use:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100922
923::
924
925 make PLAT=<platform> SPD=tspd all
926
927An additional boot loader binary file is created in the ``build`` directory:
928
929::
930
931 build/<platform>/<build-type>/bl32.bin
932
933Checking source code style
934~~~~~~~~~~~~~~~~~~~~~~~~~~
935
936When making changes to the source for submission to the project, the source
937must be in compliance with the Linux style guide, and to assist with this check
938the project Makefile contains two targets, which both utilise the
939``checkpatch.pl`` script that ships with the Linux source tree.
940
Joel Huttonfe027712018-03-19 11:59:57 +0000941To check the entire source tree, you must first download copies of
942``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
943in the `Linux master tree`_ scripts directory, then set the ``CHECKPATCH``
944environment variable to point to ``checkpatch.pl`` (with the other 2 files in
John Tsichritzisee10e792018-06-06 09:38:10 +0100945the same directory) and build the target checkcodebase:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100946
947::
948
949 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
950
951To just check the style on the files that differ between your local branch and
952the remote master, use:
953
954::
955
956 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
957
958If you wish to check your patch against something other than the remote master,
959set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
960is set to ``origin/master``.
961
962Building and using the FIP tool
963~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
964
Dan Handley610e7e12018-03-01 18:44:00 +0000965Firmware Image Package (FIP) is a packaging format used by TF-A to package
966firmware images in a single binary. The number and type of images that should
967be packed in a FIP is platform specific and may include TF-A images and other
968firmware images required by the platform. For example, most platforms require
969a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or
970U-Boot).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100971
Dan Handley610e7e12018-03-01 18:44:00 +0000972The TF-A build system provides the make target ``fip`` to create a FIP file
973for the specified platform using the FIP creation tool included in the TF-A
974project. Examples below show how to build a FIP file for FVP, packaging TF-A
975and BL33 images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100976
977For AArch64:
978
979::
980
981 make PLAT=fvp BL33=<path/to/bl33.bin> fip
982
983For AArch32:
984
985::
986
987 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path/to/bl33.bin> fip
988
989Note that AArch32 support for Normal world boot loader (BL33), like U-boot or
990UEFI, on FVP is not available upstream. Hence custom solutions are required to
991allow Linux boot on FVP. These instructions assume such a custom boot loader
992(BL33) is available.
993
994The resulting FIP may be found in:
995
996::
997
998 build/fvp/<build-type>/fip.bin
999
1000For advanced operations on FIP files, it is also possible to independently build
1001the tool and create or modify FIPs using this tool. To do this, follow these
1002steps:
1003
1004It is recommended to remove old artifacts before building the tool:
1005
1006::
1007
1008 make -C tools/fiptool clean
1009
1010Build the tool:
1011
1012::
1013
1014 make [DEBUG=1] [V=1] fiptool
1015
1016The tool binary can be located in:
1017
1018::
1019
1020 ./tools/fiptool/fiptool
1021
1022Invoking the tool with ``--help`` will print a help message with all available
1023options.
1024
1025Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
1026
1027::
1028
1029 ./tools/fiptool/fiptool create \
1030 --tb-fw build/<platform>/<build-type>/bl2.bin \
1031 --soc-fw build/<platform>/<build-type>/bl31.bin \
1032 fip.bin
1033
1034Example 2: view the contents of an existing Firmware package:
1035
1036::
1037
1038 ./tools/fiptool/fiptool info <path-to>/fip.bin
1039
1040Example 3: update the entries of an existing Firmware package:
1041
1042::
1043
1044 # Change the BL2 from Debug to Release version
1045 ./tools/fiptool/fiptool update \
1046 --tb-fw build/<platform>/release/bl2.bin \
1047 build/<platform>/debug/fip.bin
1048
1049Example 4: unpack all entries from an existing Firmware package:
1050
1051::
1052
1053 # Images will be unpacked to the working directory
1054 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
1055
1056Example 5: remove an entry from an existing Firmware package:
1057
1058::
1059
1060 ./tools/fiptool/fiptool remove \
1061 --tb-fw build/<platform>/debug/fip.bin
1062
1063Note that if the destination FIP file exists, the create, update and
1064remove operations will automatically overwrite it.
1065
1066The unpack operation will fail if the images already exist at the
1067destination. In that case, use -f or --force to continue.
1068
1069More information about FIP can be found in the `Firmware Design`_ document.
1070
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001071Building FIP images with support for Trusted Board Boot
1072~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1073
1074Trusted Board Boot primarily consists of the following two features:
1075
1076- Image Authentication, described in `Trusted Board Boot`_, and
1077- Firmware Update, described in `Firmware Update`_
1078
1079The following steps should be followed to build FIP and (optionally) FWU\_FIP
1080images with support for these features:
1081
1082#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
1083 modules by checking out a recent version of the `mbed TLS Repository`_. It
Dan Handley610e7e12018-03-01 18:44:00 +00001084 is important to use a version that is compatible with TF-A and fixes any
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001085 known security vulnerabilities. See `mbed TLS Security Center`_ for more
Dan Handley610e7e12018-03-01 18:44:00 +00001086 information. The latest version of TF-A is tested with tag
David Cunado05845bf2017-12-19 16:33:25 +00001087 ``mbedtls-2.12.0``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001088
1089 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
1090 source files the modules depend upon.
1091 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
1092 options required to build the mbed TLS sources.
1093
1094 Note that the mbed TLS library is licensed under the Apache version 2.0
Dan Handley610e7e12018-03-01 18:44:00 +00001095 license. Using mbed TLS source code will affect the licensing of TF-A
1096 binaries that are built using this library.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001097
1098#. To build the FIP image, ensure the following command line variables are set
Dan Handley610e7e12018-03-01 18:44:00 +00001099 while invoking ``make`` to build TF-A:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001100
1101 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
1102 - ``TRUSTED_BOARD_BOOT=1``
1103 - ``GENERATE_COT=1``
1104
Dan Handley610e7e12018-03-01 18:44:00 +00001105 In the case of Arm platforms, the location of the ROTPK hash must also be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001106 specified at build time. Two locations are currently supported (see
1107 ``ARM_ROTPK_LOCATION`` build option):
1108
1109 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1110 root-key storage registers present in the platform. On Juno, this
1111 registers are read-only. On FVP Base and Cortex models, the registers
1112 are read-only, but the value can be specified using the command line
1113 option ``bp.trusted_key_storage.public_key`` when launching the model.
1114 On both Juno and FVP models, the default value corresponds to an
1115 ECDSA-SECP256R1 public key hash, whose private part is not currently
1116 available.
1117
1118 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001119 in the Arm platform port. The private/public RSA key pair may be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001120 found in ``plat/arm/board/common/rotpk``.
1121
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001122 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001123 in the Arm platform port. The private/public ECDSA key pair may be
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001124 found in ``plat/arm/board/common/rotpk``.
1125
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001126 Example of command line using RSA development keys:
1127
1128 ::
1129
1130 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1131 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1132 ARM_ROTPK_LOCATION=devel_rsa \
1133 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1134 BL33=<path-to>/<bl33_image> \
1135 all fip
1136
1137 The result of this build will be the bl1.bin and the fip.bin binaries. This
1138 FIP will include the certificates corresponding to the Chain of Trust
1139 described in the TBBR-client document. These certificates can also be found
1140 in the output build directory.
1141
1142#. The optional FWU\_FIP contains any additional images to be loaded from
1143 Non-Volatile storage during the `Firmware Update`_ process. To build the
1144 FWU\_FIP, any FWU images required by the platform must be specified on the
Dan Handley610e7e12018-03-01 18:44:00 +00001145 command line. On Arm development platforms like Juno, these are:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001146
1147 - NS\_BL2U. The AP non-secure Firmware Updater image.
1148 - SCP\_BL2U. The SCP Firmware Update Configuration image.
1149
1150 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1151 targets using RSA development:
1152
1153 ::
1154
1155 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1156 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1157 ARM_ROTPK_LOCATION=devel_rsa \
1158 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1159 BL33=<path-to>/<bl33_image> \
1160 SCP_BL2=<path-to>/<scp_bl2_image> \
1161 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1162 NS_BL2U=<path-to>/<ns_bl2u_image> \
1163 all fip fwu_fip
1164
1165 Note: The BL2U image will be built by default and added to the FWU\_FIP.
1166 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1167 to the command line above.
1168
1169 Note: Building and installing the non-secure and SCP FWU images (NS\_BL1U,
1170 NS\_BL2U and SCP\_BL2U) is outside the scope of this document.
1171
1172 The result of this build will be bl1.bin, fip.bin and fwu\_fip.bin binaries.
1173 Both the FIP and FWU\_FIP will include the certificates corresponding to the
1174 Chain of Trust described in the TBBR-client document. These certificates
1175 can also be found in the output build directory.
1176
1177Building the Certificate Generation Tool
1178~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1179
Dan Handley610e7e12018-03-01 18:44:00 +00001180The ``cert_create`` tool is built as part of the TF-A build process when the
1181``fip`` make target is specified and TBB is enabled (as described in the
1182previous section), but it can also be built separately with the following
1183command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001184
1185::
1186
1187 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1188
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +01001189For platforms that require their own IDs in certificate files, the generic
1190'cert\_create' tool can be built with the following command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001191
1192::
1193
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +01001194 make USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001195
1196``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1197verbose. The following command should be used to obtain help about the tool:
1198
1199::
1200
1201 ./tools/cert_create/cert_create -h
1202
1203Building a FIP for Juno and FVP
1204-------------------------------
1205
1206This section provides Juno and FVP specific instructions to build Trusted
1207Firmware, obtain the additional required firmware, and pack it all together in
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001208a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001209
David Cunadob2de0992017-06-29 12:01:33 +01001210Note: Pre-built binaries for AArch32 are available from Linaro Release 16.12
1211onwards. Before that release, pre-built binaries are only available for AArch64.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001212
Joel Huttonfe027712018-03-19 11:59:57 +00001213Note: Follow the full instructions for one platform before switching to a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001214different one. Mixing instructions for different platforms may result in
1215corrupted binaries.
1216
Joel Huttonfe027712018-03-19 11:59:57 +00001217Note: The uboot image downloaded by the Linaro workspace script does not always
1218match the uboot image packaged as BL33 in the corresponding fip file. It is
1219recommended to use the version that is packaged in the fip file using the
1220instructions below.
1221
Soby Mathewecd94ad2018-05-09 13:59:29 +01001222Note: For the FVP, the kernel FDT is packaged in FIP during build and loaded
1223by the firmware at runtime. See `Obtaining the Flattened Device Trees`_
1224section for more info on selecting the right FDT to use.
1225
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001226#. Clean the working directory
1227
1228 ::
1229
1230 make realclean
1231
1232#. Obtain SCP\_BL2 (Juno) and BL33 (all platforms)
1233
1234 Use the fiptool to extract the SCP\_BL2 and BL33 images from the FIP
1235 package included in the Linaro release:
1236
1237 ::
1238
1239 # Build the fiptool
1240 make [DEBUG=1] [V=1] fiptool
1241
1242 # Unpack firmware images from Linaro FIP
1243 ./tools/fiptool/fiptool unpack \
1244 <path/to/linaro/release>/fip.bin
1245
1246 The unpack operation will result in a set of binary images extracted to the
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001247 current working directory. The SCP\_BL2 image corresponds to
1248 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001249
Joel Huttonfe027712018-03-19 11:59:57 +00001250 Note: The fiptool will complain if the images to be unpacked already
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001251 exist in the current directory. If that is the case, either delete those
1252 files or use the ``--force`` option to overwrite.
1253
Joel Huttonfe027712018-03-19 11:59:57 +00001254 Note: For AArch32, the instructions below assume that nt-fw.bin is a custom
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001255 Normal world boot loader that supports AArch32.
1256
Dan Handley610e7e12018-03-01 18:44:00 +00001257#. Build TF-A images and create a new FIP for FVP
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001258
1259 ::
1260
1261 # AArch64
1262 make PLAT=fvp BL33=nt-fw.bin all fip
1263
1264 # AArch32
1265 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1266
Dan Handley610e7e12018-03-01 18:44:00 +00001267#. Build TF-A images and create a new FIP for Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001268
1269 For AArch64:
1270
1271 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1272 as a build parameter.
1273
1274 ::
1275
1276 make PLAT=juno all fip \
1277 BL33=<path-to-juno-oe-uboot>/SOFTWARE/bl33-uboot.bin \
1278 SCP_BL2=<path-to-juno-busybox-uboot>/SOFTWARE/scp_bl2.bin
1279
1280 For AArch32:
1281
1282 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1283 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1284 separately for AArch32.
1285
1286 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1287 to the AArch32 Linaro cross compiler.
1288
1289 ::
1290
1291 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
1292
1293 - Build BL32 in AArch32.
1294
1295 ::
1296
1297 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1298 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1299
1300 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1301 must point to the AArch64 Linaro cross compiler.
1302
1303 ::
1304
1305 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1306
1307 - The following parameters should be used to build BL1 and BL2 in AArch64
1308 and point to the BL32 file.
1309
1310 ::
1311
Soby Mathew97b1bff2018-09-27 16:46:41 +01001312 make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001313 BL33=<path-to-juno32-oe-uboot>/SOFTWARE/bl33-uboot.bin \
Soby Mathewbf169232017-11-14 14:10:10 +00001314 SCP_BL2=<path-to-juno32-oe-uboot>/SOFTWARE/scp_bl2.bin \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001315 BL32=<path-to-bl32>/bl32.bin all fip
1316
1317The resulting BL1 and FIP images may be found in:
1318
1319::
1320
1321 # Juno
1322 ./build/juno/release/bl1.bin
1323 ./build/juno/release/fip.bin
1324
1325 # FVP
1326 ./build/fvp/release/bl1.bin
1327 ./build/fvp/release/fip.bin
1328
Roberto Vargas096f3a02017-10-17 10:19:00 +01001329
1330Booting Firmware Update images
1331-------------------------------------
1332
1333When Firmware Update (FWU) is enabled there are at least 2 new images
1334that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1335FWU FIP.
1336
1337Juno
1338~~~~
1339
1340The new images must be programmed in flash memory by adding
1341an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1342on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1343Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1344programming" for more information. User should ensure these do not
1345overlap with any other entries in the file.
1346
1347::
1348
1349 NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1350 NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
1351 NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
1352 NOR10LOAD: 00000000 ;Image Load Address
1353 NOR10ENTRY: 00000000 ;Image Entry Point
1354
1355 NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1356 NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
1357 NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
1358 NOR11LOAD: 00000000 ;Image Load Address
1359
1360The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1361In the same way, the address ns_bl2u_base_address is the value of
1362NS_BL2U_BASE - 0x8000000.
1363
1364FVP
1365~~~
1366
1367The additional fip images must be loaded with:
1368
1369::
1370
1371 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
1372 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
1373
1374The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1375In the same way, the address ns_bl2u_base_address is the value of
1376NS_BL2U_BASE.
1377
1378
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001379EL3 payloads alternative boot flow
1380----------------------------------
1381
1382On a pre-production system, the ability to execute arbitrary, bare-metal code at
1383the highest exception level is required. It allows full, direct access to the
1384hardware, for example to run silicon soak tests.
1385
1386Although it is possible to implement some baremetal secure firmware from
1387scratch, this is a complex task on some platforms, depending on the level of
1388configuration required to put the system in the expected state.
1389
1390Rather than booting a baremetal application, a possible compromise is to boot
Dan Handley610e7e12018-03-01 18:44:00 +00001391``EL3 payloads`` through TF-A instead. This is implemented as an alternative
1392boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
1393other BL images and passing control to BL31. It reduces the complexity of
1394developing EL3 baremetal code by:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001395
1396- putting the system into a known architectural state;
1397- taking care of platform secure world initialization;
1398- loading the SCP\_BL2 image if required by the platform.
1399
Dan Handley610e7e12018-03-01 18:44:00 +00001400When booting an EL3 payload on Arm standard platforms, the configuration of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001401TrustZone controller is simplified such that only region 0 is enabled and is
1402configured to permit secure access only. This gives full access to the whole
1403DRAM to the EL3 payload.
1404
1405The system is left in the same state as when entering BL31 in the default boot
1406flow. In particular:
1407
1408- Running in EL3;
1409- Current state is AArch64;
1410- Little-endian data access;
1411- All exceptions disabled;
1412- MMU disabled;
1413- Caches disabled.
1414
1415Booting an EL3 payload
1416~~~~~~~~~~~~~~~~~~~~~~
1417
1418The EL3 payload image is a standalone image and is not part of the FIP. It is
Dan Handley610e7e12018-03-01 18:44:00 +00001419not loaded by TF-A. Therefore, there are 2 possible scenarios:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001420
1421- The EL3 payload may reside in non-volatile memory (NVM) and execute in
1422 place. In this case, booting it is just a matter of specifying the right
Dan Handley610e7e12018-03-01 18:44:00 +00001423 address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001424
1425- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1426 run-time.
1427
1428To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1429used. The infinite loop that it introduces in BL1 stops execution at the right
1430moment for a debugger to take control of the target and load the payload (for
1431example, over JTAG).
1432
1433It is expected that this loading method will work in most cases, as a debugger
1434connection is usually available in a pre-production system. The user is free to
1435use any other platform-specific mechanism to load the EL3 payload, though.
1436
1437Booting an EL3 payload on FVP
1438^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1439
1440The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1441the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1442is undefined on the FVP platform and the FVP platform code doesn't clear it.
1443Therefore, one must modify the way the model is normally invoked in order to
1444clear the mailbox at start-up.
1445
1446One way to do that is to create an 8-byte file containing all zero bytes using
1447the following command:
1448
1449::
1450
1451 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1452
1453and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1454using the following model parameters:
1455
1456::
1457
1458 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1459 --data=mailbox.dat@0x04000000 [Foundation FVP]
1460
1461To provide the model with the EL3 payload image, the following methods may be
1462used:
1463
1464#. If the EL3 payload is able to execute in place, it may be programmed into
1465 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1466 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1467 used for the FIP):
1468
1469 ::
1470
1471 -C bp.flashloader1.fname="/path/to/el3-payload"
1472
1473 On Foundation FVP, there is no flash loader component and the EL3 payload
1474 may be programmed anywhere in flash using method 3 below.
1475
1476#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1477 command may be used to load the EL3 payload ELF image over JTAG:
1478
1479 ::
1480
1481 load /path/to/el3-payload.elf
1482
1483#. The EL3 payload may be pre-loaded in volatile memory using the following
1484 model parameters:
1485
1486 ::
1487
1488 --data cluster0.cpu0="/path/to/el3-payload"@address [Base FVPs]
1489 --data="/path/to/el3-payload"@address [Foundation FVP]
1490
1491 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
Dan Handley610e7e12018-03-01 18:44:00 +00001492 used when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001493
1494Booting an EL3 payload on Juno
1495^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1496
1497If the EL3 payload is able to execute in place, it may be programmed in flash
1498memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1499on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1500Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1501programming" for more information.
1502
1503Alternatively, the same DS-5 command mentioned in the FVP section above can
1504be used to load the EL3 payload's ELF file over JTAG on Juno.
1505
1506Preloaded BL33 alternative boot flow
1507------------------------------------
1508
1509Some platforms have the ability to preload BL33 into memory instead of relying
Dan Handley610e7e12018-03-01 18:44:00 +00001510on TF-A to load it. This may simplify packaging of the normal world code and
1511improve performance in a development environment. When secure world cold boot
1512is complete, TF-A simply jumps to a BL33 base address provided at build time.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001513
1514For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
Dan Handley610e7e12018-03-01 18:44:00 +00001515used when compiling TF-A. For example, the following command will create a FIP
1516without a BL33 and prepare to jump to a BL33 image loaded at address
15170x80000000:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001518
1519::
1520
1521 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1522
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001523Boot of a preloaded kernel image on Base FVP
1524~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001525
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001526The following example uses a simplified boot flow by directly jumping from the
1527TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
1528useful if both the kernel and the device tree blob (DTB) are already present in
1529memory (like in FVP).
1530
1531For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
1532address ``0x82000000``, the firmware can be built like this:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001533
1534::
1535
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001536 CROSS_COMPILE=aarch64-linux-gnu- \
1537 make PLAT=fvp DEBUG=1 \
1538 RESET_TO_BL31=1 \
1539 ARM_LINUX_KERNEL_AS_BL33=1 \
1540 PRELOADED_BL33_BASE=0x80080000 \
1541 ARM_PRELOADED_DTB_BASE=0x82000000 \
1542 all fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001543
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001544Now, it is needed to modify the DTB so that the kernel knows the address of the
1545ramdisk. The following script generates a patched DTB from the provided one,
1546assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
1547script assumes that the user is using a ramdisk image prepared for U-Boot, like
1548the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
1549offset in ``INITRD_START`` has to be removed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001550
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001551.. code:: bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001552
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001553 #!/bin/bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001554
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001555 # Path to the input DTB
1556 KERNEL_DTB=<path-to>/<fdt>
1557 # Path to the output DTB
1558 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
1559 # Base address of the ramdisk
1560 INITRD_BASE=0x84000000
1561 # Path to the ramdisk
1562 INITRD=<path-to>/<ramdisk.img>
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001563
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001564 # Skip uboot header (64 bytes)
1565 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
1566 INITRD_SIZE=$(stat -Lc %s ${INITRD})
1567 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
1568
1569 CHOSEN_NODE=$(echo \
1570 "/ { \
1571 chosen { \
1572 linux,initrd-start = <${INITRD_START}>; \
1573 linux,initrd-end = <${INITRD_END}>; \
1574 }; \
1575 };")
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001576
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001577 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
1578 dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001579
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001580And the FVP binary can be run with the following command:
1581
1582::
1583
1584 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1585 -C pctl.startup=0.0.0.0 \
1586 -C bp.secure_memory=1 \
1587 -C cluster0.NUM_CORES=4 \
1588 -C cluster1.NUM_CORES=4 \
1589 -C cache_state_modelled=1 \
1590 -C cluster0.cpu0.RVBAR=0x04020000 \
1591 -C cluster0.cpu1.RVBAR=0x04020000 \
1592 -C cluster0.cpu2.RVBAR=0x04020000 \
1593 -C cluster0.cpu3.RVBAR=0x04020000 \
1594 -C cluster1.cpu0.RVBAR=0x04020000 \
1595 -C cluster1.cpu1.RVBAR=0x04020000 \
1596 -C cluster1.cpu2.RVBAR=0x04020000 \
1597 -C cluster1.cpu3.RVBAR=0x04020000 \
1598 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \
1599 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
1600 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1601 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
1602
1603Boot of a preloaded kernel image on Juno
1604~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001605
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001606The Trusted Firmware must be compiled in a similar way as for FVP explained
1607above. The process to load binaries to memory is the one explained in
1608`Booting an EL3 payload on Juno`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001609
1610Running the software on FVP
1611---------------------------
1612
David Cunado7c032642018-03-12 18:47:05 +00001613The latest version of the AArch64 build of TF-A has been tested on the following
1614Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1615(64-bit host machine only).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001616
David Cunado05845bf2017-12-19 16:33:25 +00001617NOTE: Unless otherwise stated, the model version is Version 11.4 Build 37.
David Cunado124415e2017-06-27 17:31:12 +01001618
David Cunado05845bf2017-12-19 16:33:25 +00001619- ``FVP_Base_Aresx4``
1620- ``FVP_Base_AEMv8A-AEMv8A``
1621- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
1622- ``FVP_Base_AEMv8A-AEMv8A``
1623- ``FVP_Base_RevC-2xAEMv8A``
1624- ``FVP_Base_Cortex-A32x4``
David Cunado124415e2017-06-27 17:31:12 +01001625- ``FVP_Base_Cortex-A35x4``
1626- ``FVP_Base_Cortex-A53x4``
David Cunado05845bf2017-12-19 16:33:25 +00001627- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
1628- ``FVP_Base_Cortex-A55x4``
David Cunado124415e2017-06-27 17:31:12 +01001629- ``FVP_Base_Cortex-A57x4-A53x4``
1630- ``FVP_Base_Cortex-A57x4``
1631- ``FVP_Base_Cortex-A72x4-A53x4``
1632- ``FVP_Base_Cortex-A72x4``
1633- ``FVP_Base_Cortex-A73x4-A53x4``
1634- ``FVP_Base_Cortex-A73x4``
David Cunado05845bf2017-12-19 16:33:25 +00001635- ``FVP_Base_Cortex-A75x4``
1636- ``FVP_Base_Cortex-A76x4``
1637- ``FVP_CSS_SGI-575`` (Version 11.3 build 40)
1638- ``Foundation_Platform``
David Cunado7c032642018-03-12 18:47:05 +00001639
1640The latest version of the AArch32 build of TF-A has been tested on the following
1641Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1642(64-bit host machine only).
1643
1644- ``FVP_Base_AEMv8A-AEMv8A``
David Cunado124415e2017-06-27 17:31:12 +01001645- ``FVP_Base_Cortex-A32x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001646
David Cunado7c032642018-03-12 18:47:05 +00001647NOTE: The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
1648is not compatible with legacy GIC configurations. Therefore this FVP does not
1649support these legacy GIC configurations.
1650
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001651NOTE: The build numbers quoted above are those reported by launching the FVP
1652with the ``--version`` parameter.
1653
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001654NOTE: Linaro provides a ramdisk image in prebuilt FVP configurations and full
1655file systems that can be downloaded separately. To run an FVP with a virtio
1656file system image an additional FVP configuration option
1657``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1658used.
1659
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001660NOTE: The software will not work on Version 1.0 of the Foundation FVP.
1661The commands below would report an ``unhandled argument`` error in this case.
1662
1663NOTE: FVPs can be launched with ``--cadi-server`` option such that a
Dan Handley610e7e12018-03-01 18:44:00 +00001664CADI-compliant debugger (for example, Arm DS-5) can connect to and control its
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001665execution.
1666
Eleanor Bonnicie124dc42017-10-04 15:03:33 +01001667NOTE: Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
David Cunado97309462017-07-31 12:24:51 +01001668the internal synchronisation timings changed compared to older versions of the
1669models. The models can be launched with ``-Q 100`` option if they are required
1670to match the run time characteristics of the older versions.
1671
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001672The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
Dan Handley610e7e12018-03-01 18:44:00 +00001673downloaded for free from `Arm's website`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001674
David Cunado124415e2017-06-27 17:31:12 +01001675The Cortex-A models listed above are also available to download from
Dan Handley610e7e12018-03-01 18:44:00 +00001676`Arm's website`_.
David Cunado124415e2017-06-27 17:31:12 +01001677
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001678Please refer to the FVP documentation for a detailed description of the model
Dan Handley610e7e12018-03-01 18:44:00 +00001679parameter options. A brief description of the important ones that affect TF-A
1680and normal world software behavior is provided below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001681
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001682Obtaining the Flattened Device Trees
1683~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1684
1685Depending on the FVP configuration and Linux configuration used, different
Soby Mathewecd94ad2018-05-09 13:59:29 +01001686FDT files are required. FDT source files for the Foundation and Base FVPs can
1687be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
1688a subset of the Base FVP components. For example, the Foundation FVP lacks
1689CLCD and MMC support, and has only one CPU cluster.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001690
1691Note: It is not recommended to use the FDTs built along the kernel because not
1692all FDTs are available from there.
1693
Soby Mathewecd94ad2018-05-09 13:59:29 +01001694The dynamic configuration capability is enabled in the firmware for FVPs.
1695This means that the firmware can authenticate and load the FDT if present in
1696FIP. A default FDT is packaged into FIP during the build based on
1697the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
1698or ``FVP_HW_CONFIG_DTS`` build options (refer to the
1699`Arm FVP platform specific build options`_ section for detail on the options).
1700
1701- ``fvp-base-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001702
David Cunado7c032642018-03-12 18:47:05 +00001703 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1704 affinities and with Base memory map configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001705
Soby Mathewecd94ad2018-05-09 13:59:29 +01001706- ``fvp-base-gicv2-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001707
David Cunado7c032642018-03-12 18:47:05 +00001708 For use with models such as the Cortex-A32 Base FVPs without shifted
1709 affinities and running Linux in AArch32 state with Base memory map
1710 configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001711
Soby Mathewecd94ad2018-05-09 13:59:29 +01001712- ``fvp-base-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001713
David Cunado7c032642018-03-12 18:47:05 +00001714 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1715 affinities and with Base memory map configuration and Linux GICv3 support.
1716
Soby Mathewecd94ad2018-05-09 13:59:29 +01001717- ``fvp-base-gicv3-psci-1t.dts``
David Cunado7c032642018-03-12 18:47:05 +00001718
1719 For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
1720 single threaded CPUs, Base memory map configuration and Linux GICv3 support.
1721
Soby Mathewecd94ad2018-05-09 13:59:29 +01001722- ``fvp-base-gicv3-psci-dynamiq.dts``
David Cunado7c032642018-03-12 18:47:05 +00001723
1724 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
1725 single cluster, single threaded CPUs, Base memory map configuration and Linux
1726 GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001727
Soby Mathewecd94ad2018-05-09 13:59:29 +01001728- ``fvp-base-gicv3-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001729
David Cunado7c032642018-03-12 18:47:05 +00001730 For use with models such as the Cortex-A32 Base FVPs without shifted
1731 affinities and running Linux in AArch32 state with Base memory map
1732 configuration and Linux GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001733
Soby Mathewecd94ad2018-05-09 13:59:29 +01001734- ``fvp-foundation-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001735
1736 For use with Foundation FVP with Base memory map configuration.
1737
Soby Mathewecd94ad2018-05-09 13:59:29 +01001738- ``fvp-foundation-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001739
1740 (Default) For use with Foundation FVP with Base memory map configuration
1741 and Linux GICv3 support.
1742
1743Running on the Foundation FVP with reset to BL1 entrypoint
1744~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1745
1746The following ``Foundation_Platform`` parameters should be used to boot Linux with
Dan Handley610e7e12018-03-01 18:44:00 +000017474 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001748
1749::
1750
1751 <path-to>/Foundation_Platform \
1752 --cores=4 \
Antonio Nino Diazb44eda52018-02-23 11:01:31 +00001753 --arm-v8.0 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001754 --secure-memory \
1755 --visualization \
1756 --gicv3 \
1757 --data="<path-to>/<bl1-binary>"@0x0 \
1758 --data="<path-to>/<FIP-binary>"@0x08000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001759 --data="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001760 --data="<path-to>/<ramdisk-binary>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001761
1762Notes:
1763
1764- BL1 is loaded at the start of the Trusted ROM.
1765- The Firmware Image Package is loaded at the start of NOR FLASH0.
Soby Mathewecd94ad2018-05-09 13:59:29 +01001766- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
1767 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001768- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1769 and enable the GICv3 device in the model. Note that without this option,
1770 the Foundation FVP defaults to legacy (Versatile Express) memory map which
Dan Handley610e7e12018-03-01 18:44:00 +00001771 is not supported by TF-A.
1772- In order for TF-A to run correctly on the Foundation FVP, the architecture
1773 versions must match. The Foundation FVP defaults to the highest v8.x
1774 version it supports but the default build for TF-A is for v8.0. To avoid
1775 issues either start the Foundation FVP to use v8.0 architecture using the
1776 ``--arm-v8.0`` option, or build TF-A with an appropriate value for
1777 ``ARM_ARCH_MINOR``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001778
1779Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1780~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1781
David Cunado7c032642018-03-12 18:47:05 +00001782The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001783with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001784
1785::
1786
David Cunado7c032642018-03-12 18:47:05 +00001787 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001788 -C pctl.startup=0.0.0.0 \
1789 -C bp.secure_memory=1 \
1790 -C bp.tzc_400.diagnostics=1 \
1791 -C cluster0.NUM_CORES=4 \
1792 -C cluster1.NUM_CORES=4 \
1793 -C cache_state_modelled=1 \
1794 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1795 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001796 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001797 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001798
1799Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1800~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1801
1802The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001803with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001804
1805::
1806
1807 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1808 -C pctl.startup=0.0.0.0 \
1809 -C bp.secure_memory=1 \
1810 -C bp.tzc_400.diagnostics=1 \
1811 -C cluster0.NUM_CORES=4 \
1812 -C cluster1.NUM_CORES=4 \
1813 -C cache_state_modelled=1 \
1814 -C cluster0.cpu0.CONFIG64=0 \
1815 -C cluster0.cpu1.CONFIG64=0 \
1816 -C cluster0.cpu2.CONFIG64=0 \
1817 -C cluster0.cpu3.CONFIG64=0 \
1818 -C cluster1.cpu0.CONFIG64=0 \
1819 -C cluster1.cpu1.CONFIG64=0 \
1820 -C cluster1.cpu2.CONFIG64=0 \
1821 -C cluster1.cpu3.CONFIG64=0 \
1822 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1823 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001824 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001825 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001826
1827Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1828~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1829
1830The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001831boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001832
1833::
1834
1835 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1836 -C pctl.startup=0.0.0.0 \
1837 -C bp.secure_memory=1 \
1838 -C bp.tzc_400.diagnostics=1 \
1839 -C cache_state_modelled=1 \
1840 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1841 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001842 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001843 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001844
1845Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1846~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1847
1848The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001849boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001850
1851::
1852
1853 <path-to>/FVP_Base_Cortex-A32x4 \
1854 -C pctl.startup=0.0.0.0 \
1855 -C bp.secure_memory=1 \
1856 -C bp.tzc_400.diagnostics=1 \
1857 -C cache_state_modelled=1 \
1858 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1859 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001860 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001861 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001862
1863Running on the AEMv8 Base FVP with reset to BL31 entrypoint
1864~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1865
David Cunado7c032642018-03-12 18:47:05 +00001866The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001867with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001868
1869::
1870
David Cunado7c032642018-03-12 18:47:05 +00001871 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001872 -C pctl.startup=0.0.0.0 \
1873 -C bp.secure_memory=1 \
1874 -C bp.tzc_400.diagnostics=1 \
1875 -C cluster0.NUM_CORES=4 \
1876 -C cluster1.NUM_CORES=4 \
1877 -C cache_state_modelled=1 \
Soby Mathewba678c32018-12-12 14:54:23 +00001878 -C cluster0.cpu0.RVBAR=0x04010000 \
1879 -C cluster0.cpu1.RVBAR=0x04010000 \
1880 -C cluster0.cpu2.RVBAR=0x04010000 \
1881 -C cluster0.cpu3.RVBAR=0x04010000 \
1882 -C cluster1.cpu0.RVBAR=0x04010000 \
1883 -C cluster1.cpu1.RVBAR=0x04010000 \
1884 -C cluster1.cpu2.RVBAR=0x04010000 \
1885 -C cluster1.cpu3.RVBAR=0x04010000 \
1886 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
1887 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001888 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001889 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001890 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001891 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001892
1893Notes:
1894
Soby Mathewba678c32018-12-12 14:54:23 +00001895- Since Position Independent Executable (PIE) support is enabled for BL31
1896 in this config, it can be loaded at any valid address for execution.
1897
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001898- Since a FIP is not loaded when using BL31 as reset entrypoint, the
1899 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
1900 parameter is needed to load the individual bootloader images in memory.
1901 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
Soby Mathewecd94ad2018-05-09 13:59:29 +01001902 Payload. For the same reason, the FDT needs to be compiled from the DT source
1903 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
1904 parameter.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001905
1906- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
1907 X and Y are the cluster and CPU numbers respectively, is used to set the
1908 reset vector for each core.
1909
1910- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
1911 changing the value of
1912 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
1913 ``BL32_BASE``.
1914
1915Running on the AEMv8 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1916~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1917
1918The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001919with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001920
1921::
1922
1923 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1924 -C pctl.startup=0.0.0.0 \
1925 -C bp.secure_memory=1 \
1926 -C bp.tzc_400.diagnostics=1 \
1927 -C cluster0.NUM_CORES=4 \
1928 -C cluster1.NUM_CORES=4 \
1929 -C cache_state_modelled=1 \
1930 -C cluster0.cpu0.CONFIG64=0 \
1931 -C cluster0.cpu1.CONFIG64=0 \
1932 -C cluster0.cpu2.CONFIG64=0 \
1933 -C cluster0.cpu3.CONFIG64=0 \
1934 -C cluster1.cpu0.CONFIG64=0 \
1935 -C cluster1.cpu1.CONFIG64=0 \
1936 -C cluster1.cpu2.CONFIG64=0 \
1937 -C cluster1.cpu3.CONFIG64=0 \
Soby Mathewba678c32018-12-12 14:54:23 +00001938 -C cluster0.cpu0.RVBAR=0x04002000 \
1939 -C cluster0.cpu1.RVBAR=0x04002000 \
1940 -C cluster0.cpu2.RVBAR=0x04002000 \
1941 -C cluster0.cpu3.RVBAR=0x04002000 \
1942 -C cluster1.cpu0.RVBAR=0x04002000 \
1943 -C cluster1.cpu1.RVBAR=0x04002000 \
1944 -C cluster1.cpu2.RVBAR=0x04002000 \
1945 -C cluster1.cpu3.RVBAR=0x04002000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01001946 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001947 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001948 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001949 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001950 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001951
1952Note: The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
1953It should match the address programmed into the RVBAR register as well.
1954
1955Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
1956~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1957
1958The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001959boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001960
1961::
1962
1963 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1964 -C pctl.startup=0.0.0.0 \
1965 -C bp.secure_memory=1 \
1966 -C bp.tzc_400.diagnostics=1 \
1967 -C cache_state_modelled=1 \
Soby Mathewba678c32018-12-12 14:54:23 +00001968 -C cluster0.cpu0.RVBARADDR=0x04010000 \
1969 -C cluster0.cpu1.RVBARADDR=0x04010000 \
1970 -C cluster0.cpu2.RVBARADDR=0x04010000 \
1971 -C cluster0.cpu3.RVBARADDR=0x04010000 \
1972 -C cluster1.cpu0.RVBARADDR=0x04010000 \
1973 -C cluster1.cpu1.RVBARADDR=0x04010000 \
1974 -C cluster1.cpu2.RVBARADDR=0x04010000 \
1975 -C cluster1.cpu3.RVBARADDR=0x04010000 \
1976 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
1977 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001978 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001979 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001980 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001981 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001982
1983Running on the Cortex-A32 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1984~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1985
1986The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001987boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001988
1989::
1990
1991 <path-to>/FVP_Base_Cortex-A32x4 \
1992 -C pctl.startup=0.0.0.0 \
1993 -C bp.secure_memory=1 \
1994 -C bp.tzc_400.diagnostics=1 \
1995 -C cache_state_modelled=1 \
Soby Mathewba678c32018-12-12 14:54:23 +00001996 -C cluster0.cpu0.RVBARADDR=0x04002000 \
1997 -C cluster0.cpu1.RVBARADDR=0x04002000 \
1998 -C cluster0.cpu2.RVBARADDR=0x04002000 \
1999 -C cluster0.cpu3.RVBARADDR=0x04002000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01002000 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002001 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002002 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002003 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002004 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002005
2006Running the software on Juno
2007----------------------------
2008
Dan Handley610e7e12018-03-01 18:44:00 +00002009This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002010
2011To execute the software stack on Juno, the version of the Juno board recovery
2012image indicated in the `Linaro Release Notes`_ must be installed. If you have an
2013earlier version installed or are unsure which version is installed, please
2014re-install the recovery image by following the
2015`Instructions for using Linaro's deliverables on Juno`_.
2016
Dan Handley610e7e12018-03-01 18:44:00 +00002017Preparing TF-A images
2018~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002019
Dan Handley610e7e12018-03-01 18:44:00 +00002020After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
2021``SOFTWARE/`` directory of the Juno SD card.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002022
2023Other Juno software information
2024~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2025
Dan Handley610e7e12018-03-01 18:44:00 +00002026Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002027software information. Please also refer to the `Juno Getting Started Guide`_ to
Dan Handley610e7e12018-03-01 18:44:00 +00002028get more detailed information about the Juno Arm development platform and how to
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002029configure it.
2030
2031Testing SYSTEM SUSPEND on Juno
2032~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2033
2034The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
2035to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
2036on Juno, at the linux shell prompt, issue the following command:
2037
2038::
2039
2040 echo +10 > /sys/class/rtc/rtc0/wakealarm
2041 echo -n mem > /sys/power/state
2042
2043The Juno board should suspend to RAM and then wakeup after 10 seconds due to
2044wakeup interrupt from RTC.
2045
2046--------------
2047
Dan Handley610e7e12018-03-01 18:44:00 +00002048*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002049
David Cunadob2de0992017-06-29 12:01:33 +01002050.. _Linaro: `Linaro Release Notes`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002051.. _Linaro Release: `Linaro Release Notes`_
David Cunado82509be2017-12-19 16:33:25 +00002052.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-linaro-release-notes
David Cunado82509be2017-12-19 16:33:25 +00002053.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/linaro-software-deliverables
2054.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
Dan Handley610e7e12018-03-01 18:44:00 +00002055.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002056.. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php
Sandrine Bailleux771535b2018-09-20 10:27:13 +02002057.. _Linux master tree: https://github.com/torvalds/linux/tree/master/
Antonio Nino Diazb5d68092017-05-23 11:49:22 +01002058.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002059.. _here: psci-lib-integration-guide.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002060.. _Trusted Board Boot: trusted-board-boot.rst
Soby Mathewecd94ad2018-05-09 13:59:29 +01002061.. _TB_FW_CONFIG for FVP: ../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002062.. _Secure-EL1 Payloads and Dispatchers: firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002063.. _Firmware Update: firmware-update.rst
2064.. _Firmware Design: firmware-design.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002065.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
2066.. _mbed TLS Security Center: https://tls.mbed.org/security
Dan Handley610e7e12018-03-01 18:44:00 +00002067.. _Arm's website: `FVP models`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002068.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002069.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
David Cunadob2de0992017-06-29 12:01:33 +01002070.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
Sandrine Bailleux604f0a42018-09-20 12:44:39 +02002071.. _Secure Partition Manager Design guide: secure-partition-manager-design.rst